Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19531229	1			T1	1588		T3	219		T4	9746
all_values[1]	19531229	1			T1	1588		T3	219		T4	9746
all_values[2]	19531229	1			T1	1588		T3	219		T4	9746

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255992

1

T3

47

T4

3273

T5

2

auto[1]

58337695

1

T1

4764

T3

610

T4

25965

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49988970

1

T1

4216

T3

520

T4

25887

auto[1]

8604717

1

T1

548

T3

137

T4

3351

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	74278	1			T16	42		T24	188		T28	1485
all_values[0]	auto[0]	auto[1]	386	1			T16	2		T24	2		T28	2
all_values[0]	auto[1]	auto[0]	19435356	1			T1	1586		T3	217		T4	9740
all_values[0]	auto[1]	auto[1]	21209	1			T1	2		T3	2		T4	6
all_values[1]	auto[0]	auto[0]	93684	1			T5	2		T25	421		T19	3746
all_values[1]	auto[0]	auto[1]	226	1			T19	3		T8	6		T9	12
all_values[1]	auto[1]	auto[0]	19436946	1			T1	1588		T3	219		T4	9746
all_values[1]	auto[1]	auto[1]	373	1			T6	3		T19	1		T18	1
all_values[2]	auto[0]	auto[0]	47042	1			T3	7		T4	3273		T19	161
all_values[2]	auto[0]	auto[1]	40376	1			T3	40		T19	2		T20	2
all_values[2]	auto[1]	auto[0]	10901664	1			T1	1042		T3	77		T4	3128
all_values[2]	auto[1]	auto[1]	8542147	1			T1	546		T3	95		T4	3345