Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148133

1

T1

1014

T3

2

T4

4

auto[1]

156200

1

T1

488

T4

16

T5

90

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	117704	1			T1	716		T4	10		T5	29
len_1026_2046	8575	1			T1	18		T5	1		T6	93
len_514_1022	5113	1			T1	7		T6	20		T7	24
len_2_510	3700	1			T1	9		T6	13		T7	12
len_2056	208	1			T24	3		T20	2		T40	1
len_2048	360	1			T6	3		T7	2		T26	1
len_2040	258	1			T20	5		T40	4		T84	3
len_1032	187	1			T20	8		T40	1		T84	4
len_1024	1929	1			T6	6		T7	6		T24	3
len_1016	207	1			T40	3		T84	2		T9	14
len_520	193	1			T20	7		T40	1		T84	1
len_512	374	1			T1	1		T6	3		T7	3
len_504	220	1			T24	2		T20	4		T40	3
len_8	1234	1			T5	15		T19	8		T46	1
len_0	11904	1			T3	1		T6	46		T7	404

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

97

1

T7

2

T18

2

T66

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	59451	1			T1	472		T4	2		T6	457
auto[0]	len_1026_2046	4066	1			T1	18		T6	83		T7	16
auto[0]	len_514_1022	2380	1			T1	7		T6	12		T7	12
auto[0]	len_2_510	2208	1			T1	9		T6	11		T7	4
auto[0]	len_2056	104	1			T40	1		T84	1		T8	6
auto[0]	len_2048	198	1			T6	2		T7	1		T26	1
auto[0]	len_2040	108	1			T20	5		T40	4		T84	2
auto[0]	len_1032	80	1			T20	3		T84	1		T8	3
auto[0]	len_1024	311	1			T6	3		T7	5		T24	2
auto[0]	len_1016	127	1			T40	2		T84	2		T9	13
auto[0]	len_520	106	1			T20	2		T40	1		T8	1
auto[0]	len_512	223	1			T1	1		T6	2		T7	1
auto[0]	len_504	110	1			T24	2		T20	4		T40	2
auto[0]	len_8	15	1			T46	1		T132	2		T64	4
auto[0]	len_0	4579	1			T3	1		T7	1		T16	9
auto[1]	len_2050_plus	58253	1			T1	244		T4	8		T5	29
auto[1]	len_1026_2046	4509	1			T5	1		T6	10		T7	19
auto[1]	len_514_1022	2733	1			T6	8		T7	12		T26	1
auto[1]	len_2_510	1492	1			T6	2		T7	8		T16	1
auto[1]	len_2056	104	1			T24	3		T20	2		T84	1
auto[1]	len_2048	162	1			T6	1		T7	1		T18	1
auto[1]	len_2040	150	1			T84	1		T8	3		T133	4
auto[1]	len_1032	107	1			T20	5		T40	1		T84	3
auto[1]	len_1024	1618	1			T6	3		T7	1		T24	1
auto[1]	len_1016	80	1			T40	1		T9	1		T133	1
auto[1]	len_520	87	1			T20	5		T84	1		T9	4
auto[1]	len_512	151	1			T6	1		T7	2		T26	1
auto[1]	len_504	110	1			T40	1		T8	1		T9	3
auto[1]	len_8	1219	1			T5	15		T19	8		T20	12
auto[1]	len_0	7325	1			T6	46		T7	403		T16	67

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

54

1

T7

2

T18

2

T66

1

auto[1]

len_upper

43

1

T134

2

T12

1

T107

1