Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4892159

1

T1

2827

T3

56

T4

2771

auto[1]

3255677

1

T1

223

T3

56

T4

2116

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3129606

1

T1

216

T3

30

T4

2632

auto[1]

5018230

1

T1

2834

T3

82

T4

2255

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3590372

1

T1

2008

T3

56

T4

2671

auto[1]

4557464

1

T1

1042

T3

56

T4

2216

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4918942

1

T1

2020

T4

1749

T5

26095

auto[1]

3228894

1

T1

1030

T3

112

T4

3138

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7330493	1			T1	3030		T3	112		T4	4737
fifo_depth[1]	135115	1			T1	18		T4	104		T5	839
fifo_depth[2]	102621	1			T4	36		T5	443		T6	80
fifo_depth[3]	79601	1			T4	8		T5	128		T6	62
fifo_depth[4]	72800	1			T1	2		T4	1		T5	31
fifo_depth[5]	56514	1			T4	1		T5	4		T6	116
fifo_depth[6]	46215	1			T5	2		T6	213		T7	149
fifo_depth[7]	30000	1			T6	202		T7	235		T17	23

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

817343

1

T1

20

T4

150

T5

1447

auto[1]

7330493

1

T1

3030

T3

112

T4

4737

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8131815

1

T1

3050

T3

112

T4

4887

auto[1]

16021

1

T6

337

T7

920

T18

190

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

41250

1

T6

309

T7

2239

T24

7

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

43161

1

T6

81

T7

807

T26

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

33421

1

T6

270

T7

253

T25

34

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

40261

1

T4

63

T6

296

T7

496

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

156278

1

T1

18

T4

32

T7

543

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

42600

1

T6

490

T7

262

T24

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

38516

1

T1

2

T6

206

T7

342

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

36626

1

T6

790

T7

181

T17

151

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39739

1

T4

23

T5

25

T6

887

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

51058

1

T5

232

T6

258

T7

1177

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42099

1

T5

236

T6

91

T24

20

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

39280

1

T6

2164

T16

57

T17

188

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54136

1

T5

269

T6

174

T7

755

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

47568

1

T5

349

T7

678

T27

78

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

50912

1

T5

78

T6

233

T17

37

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

60438

1

T4

32

T5

258

T6

1874

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

199802

1

T6

8

T7

30

T17

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

219216

1

T4

771

T6

37

T7

56

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

203094

1

T6

331

T7

10

T17

766

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

194441

1

T4

1080

T6

296

T7

85

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1733898

1

T1

1971

T4

474

T6

92

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

200839

1

T4

251

T6

15

T7

47

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

201307

1

T1

17

T6

184

T7

13

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

205662

1

T3

56

T6

206

T7

165

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

490180

1

T1

12

T4

490

T5

1670

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

486626

1

T3

30

T5

6040

T6

200

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

523067

1

T5

11784

T6

127

T7

611

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

482911

1

T1

204

T4

205

T5

9

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

570123

1

T4

730

T5

10566

T6

187

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

515685

1

T1

826

T3

26

T5

8591

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

541120

1

T5

1467

T6

11

T17

453

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

562522

1

T4

736

T5

6890

T6

458

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

240650

1

T6

317

T7

2262

T17

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

260149

1

T4

771

T6

118

T7

841

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

234297

1

T6

601

T7

263

T17

766

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

234396

1

T4

1143

T6

592

T7

581

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1888940

1

T1

1989

T4

506

T6

92

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

242031

1

T4

251

T6

404

T7

299

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

239200

1

T1

19

T6

390

T7

355

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

241122

1

T3

56

T6

916

T7

346

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

529263

1

T1

12

T4

513

T5

1695

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

536708

1

T3

30

T5

6272

T6

458

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

564917

1

T5

12020

T6

218

T7

611

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

521851

1

T1

204

T4

205

T5

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

623256

1

T4

730

T5

10835

T6

361

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

562550

1

T1

826

T3

26

T5

8940

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

591380

1

T5

1545

T6

244

T17

490

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

621105

1

T4

768

T5

7148

T6

2328

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

402

1

T7

7

T18

43

T64

117

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2228

1

T7

22

T18

5

T64

89

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

2218

1

T64

106

T44

17

T135

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

306

1

T18

15

T12

18

T64

15

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1236

1

T7

12

T64

424

T135

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1408

1

T6

101

T7

10

T18

22

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

623

1

T12

67

T64

137

T44

12

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1166

1

T6

80

T18

87

T64

112

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

656

1

T6

17

T7

362

T64

71

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

976

1

T7

506

T18

15

T64

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

249

1

T18

1

T64

40

T31

40

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

340

1

T6

135

T12

4

T64

50

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1003

1

T7

1

T18

2

T64

164

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

703

1

T12

22

T64

364

T136

26

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

652

1

T12

140

T64

169

T44

122

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1855

1

T6

4

T64

20

T44

26

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

199802

1

T6

8

T7

30

T17

2

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

219216

1

T4

771

T6

37

T7

56

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

203094

1

T6

331

T7

10

T17

766

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

194441

1

T4

1080

T6

296

T7

85

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1733898

1

T1

1971

T4

474

T6

92

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

200839

1

T4

251

T6

15

T7

47

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

201307

1

T1

17

T6

184

T7

13

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

205662

1

T3

56

T6

206

T7

165

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

490180

1

T1

12

T4

490

T5

1670

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

486626

1

T3

30

T5

6040

T6

200

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

523067

1

T5

11784

T6

127

T7

611

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

482911

1

T1

204

T4

205

T5

9

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

570123

1

T4

730

T5

10566

T6

187

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

515685

1

T1

826

T3

26

T5

8591

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

541120

1

T5

1467

T6

11

T17

453

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

562522

1

T4

736

T5

6890

T6

458

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

4078

1

T6

2

T7

1

T24

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

4656

1

T6

6

T7

1

T26

2

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

4104

1

T6

2

T7

9

T25

24

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

4522

1

T4

47

T6

24

T7

2

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

43137

1

T1

18

T4

22

T25

7

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

4485

1

T6

3

T24

1

T27

17

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

4584

1

T6

5

T7

2

T26

11

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

4601

1

T6

1

T7

13

T17

37

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5964

1

T4

13

T5

14

T6

3

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

7890

1

T5

132

T6

2

T27

28

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

7323

1

T5

155

T6

2

T24

2

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6583

1

T6

11

T17

27

T27

13

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

9163

1

T5

154

T6

3

T7

17

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

7469

1

T5

197

T7

2

T27

12

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

7748

1

T5

44

T17

13

T26

2

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

8808

1

T4

22

T5

143

T6

7

fifo_depth[2]

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42

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17