Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19531229	1			T1	1588		T3	219		T4	9746
all_pins[1]	19531229	1			T1	1588		T3	219		T4	9746
all_pins[2]	19531229	1			T1	1588		T3	219		T4	9746

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	50029106	1			T1	4216		T3	560		T4	25887
values[0x1]	8564581	1			T1	548		T3	97		T4	3351
transitions[0x0=>0x1]	8564418	1			T1	548		T3	97		T4	3351
transitions[0x1=>0x0]	8564428	1			T1	548		T3	97		T4	3351

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19509208	1			T1	1586		T3	217		T4	9740
all_pins[0]	values[0x1]	22021	1			T1	2		T3	2		T4	6
all_pins[0]	transitions[0x0=>0x1]	21948	1			T1	2		T3	2		T4	6
all_pins[0]	transitions[0x1=>0x0]	8542084	1			T1	546		T3	95		T4	3345
all_pins[1]	values[0x0]	19530816	1			T1	1588		T3	219		T4	9746
all_pins[1]	values[0x1]	413	1			T6	5		T7	4		T19	1
all_pins[1]	transitions[0x0=>0x1]	362	1			T6	5		T7	4		T18	2
all_pins[1]	transitions[0x1=>0x0]	21970	1			T1	2		T3	2		T4	6
all_pins[2]	values[0x0]	10989082	1			T1	1042		T3	124		T4	6401
all_pins[2]	values[0x1]	8542147	1			T1	546		T3	95		T4	3345
all_pins[2]	transitions[0x0=>0x1]	8542108	1			T1	546		T3	95		T4	3345
all_pins[2]	transitions[0x1=>0x0]	374	1			T6	5		T7	4		T19	1