Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1084 1 T19 8 T40 4 T8 28
all_values[1] 1084 1 T19 8 T40 4 T8 28
all_values[2] 1084 1 T19 8 T40 4 T8 28


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1621 1 T19 12 T40 8 T8 32
auto[1] 1631 1 T19 12 T40 4 T8 52


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1222 1 T19 8 T40 5 T8 25
auto[1] 2030 1 T19 16 T40 7 T8 59


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1890 1 T19 13 T40 10 T8 47
auto[1] 1362 1 T19 11 T40 2 T8 37


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 197 1 T19 3 T8 3 T9 9
all_values[0] auto[0] auto[0] auto[1] 113 1 T40 3 T8 5 T9 12
all_values[0] auto[0] auto[1] auto[0] 220 1 T8 5 T9 11 T122 1
all_values[0] auto[0] auto[1] auto[1] 103 1 T19 1 T8 3 T9 10
all_values[0] auto[1] auto[0] auto[1] 234 1 T19 1 T40 1 T8 4
all_values[0] auto[1] auto[1] auto[1] 217 1 T19 3 T8 8 T9 17
all_values[1] auto[0] auto[0] auto[0] 176 1 T40 2 T8 3 T9 11
all_values[1] auto[0] auto[0] auto[1] 119 1 T19 2 T8 4 T9 10
all_values[1] auto[0] auto[1] auto[0] 194 1 T19 1 T40 2 T8 1
all_values[1] auto[0] auto[1] auto[1] 145 1 T19 1 T8 5 T9 9
all_values[1] auto[1] auto[0] auto[1] 229 1 T19 2 T8 4 T9 10
all_values[1] auto[1] auto[1] auto[1] 221 1 T19 2 T8 11 T9 16
all_values[2] auto[0] auto[0] auto[0] 228 1 T19 2 T40 1 T8 8
all_values[2] auto[0] auto[0] auto[1] 95 1 T19 1 T9 4 T122 1
all_values[2] auto[0] auto[1] auto[0] 207 1 T19 2 T8 5 T9 18
all_values[2] auto[0] auto[1] auto[1] 93 1 T40 2 T8 5 T9 6
all_values[2] auto[1] auto[0] auto[1] 230 1 T19 1 T40 1 T8 1
all_values[2] auto[1] auto[1] auto[1] 231 1 T19 2 T8 9 T9 14


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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