Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4723	1			T1	2		T3	1		T4	1
sha2_none	4726	1			T1	1		T3	1		T4	3
sha2_512	8160	1			T1	1		T3	1		T5	9
sha2_384	7843	1			T1	1		T3	1		T4	2
sha2_256	6985	1			T1	1		T4	5		T5	15

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20013

1

T1

3

T3

2

T4

6

auto[1]

12850

1

T1

3

T3

2

T4

5

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12599

1

T1

3

T3

1

T4

4

auto[1]

20264

1

T1

3

T3

3

T4

7

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17089

1

T1

4

T3

2

T4

7

disabled

15774

1

T1

2

T3

2

T4

4

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5086	1			T1	1		T3	1		T4	2
key_none	8110	1			T1	1		T3	1		T4	3
key_1024	4700	1			T1	2		T3	1		T4	3
key_512	4228	1			T5	10		T6	10		T7	4
key_384	3752	1			T5	10		T6	6		T7	8
key_256	3566	1			T1	1		T3	1		T4	3
key_128	3335	1			T1	1		T5	8		T6	7

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20186

1

T1

3

T4

4

T5

32

auto[1]

12677

1

T1

3

T3

4

T4

7

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

32632

1

T1

6

T3

4

T4

11

disabled

231

1

T20

4

T36

2

T38

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1709

1

T1

1

T4

1

T5

8

enabled

auto[0]

auto[0]

auto[1]

1777

1

T3

1

T5

8

T6

2

enabled

auto[0]

auto[1]

auto[0]

1879

1

T5

9

T6

3

T7

3

enabled

auto[0]

auto[1]

auto[1]

1771

1

T1

2

T4

1

T5

5

enabled

auto[1]

auto[0]

auto[0]

4449

1

T4

2

T5

8

T6

5

enabled

auto[1]

auto[0]

auto[1]

1773

1

T1

1

T3

1

T5

8

enabled

auto[1]

auto[1]

auto[0]

1956

1

T5

7

T6

1

T7

1

enabled

auto[1]

auto[1]

auto[1]

1775

1

T4

3

T5

6

T6

4

disabled

auto[0]

auto[0]

auto[0]

1301

1

T6

1

T7

3

T24

2

disabled

auto[0]

auto[0]

auto[1]

1419

1

T4

1

T6

1

T7

7

disabled

auto[0]

auto[1]

auto[0]

1405

1

T6

3

T7

1

T17

3

disabled

auto[0]

auto[1]

auto[1]

1338

1

T4

1

T6

3

T7

3

disabled

auto[1]

auto[0]

auto[0]

6169

1

T1

1

T4

1

T6

3

disabled

auto[1]

auto[0]

auto[1]

1416

1

T4

1

T6

2

T7

3

disabled

auto[1]

auto[1]

auto[0]

1318

1

T1

1

T6

6

T7

1

disabled

auto[1]

auto[1]

auto[1]

1408

1

T3

2

T6

8

T7

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16997

1

T1

4

T3

2

T4

7

enabled

disabled

92

1

T20

3

T38

1

T40

6

disabled

disabled

139

1

T20

1

T36

2

T40

6

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15635

1

T1

2

T3

2

T4

4

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1215	1			T5	4		T6	4		T7	3
key_invalid	sha2_none	915	1			T4	1		T5	2		T6	1
key_invalid	sha2_512	960	1			T3	1		T5	1		T6	2
key_invalid	sha2_384	935	1			T5	1		T6	1		T7	1
key_invalid	sha2_256	948	1			T1	1		T4	1		T6	2
key_none	sha2_invalid	588	1			T5	1		T6	1		T24	1
key_none	sha2_none	581	1			T4	1		T5	1		T6	1
key_none	sha2_512	2596	1			T1	1		T6	3		T7	5
key_none	sha2_384	2602	1			T3	1		T4	1		T5	2
key_none	sha2_256	1694	1			T4	1		T5	2		T7	1
key_1024	sha2_invalid	576	1			T1	1		T4	1		T5	2
key_1024	sha2_none	663	1			T1	1		T3	1		T4	1
key_1024	sha2_512	1780	1			T5	2		T6	5		T7	2
key_1024	sha2_384	979	1			T4	1		T5	2		T16	1
key_512	sha2_invalid	603	1			T5	1		T6	2		T17	1
key_512	sha2_none	624	1			T5	2		T17	2		T27	1
key_512	sha2_512	688	1			T6	3		T7	3		T27	1
key_512	sha2_384	1322	1			T5	2		T6	1		T16	1
key_512	sha2_256	941	1			T5	4		T6	3		T7	1
key_384	sha2_invalid	570	1			T5	1		T26	1		T19	2
key_384	sha2_none	651	1			T5	3		T7	3		T27	1
key_384	sha2_512	701	1			T5	2		T7	4		T27	1
key_384	sha2_384	669	1			T5	2		T6	4		T7	1
key_384	sha2_256	1120	1			T5	2		T6	2		T27	1
key_256	sha2_invalid	573	1			T3	1		T6	2		T17	1
key_256	sha2_none	621	1			T5	1		T6	1		T7	1
key_256	sha2_512	713	1			T5	2		T6	2		T7	2
key_256	sha2_384	675	1			T1	1		T5	3		T7	3
key_256	sha2_256	921	1			T4	3		T5	3		T6	1
key_128	sha2_invalid	580	1			T1	1		T5	1		T24	1
key_128	sha2_none	656	1			T5	1		T6	2		T7	1
key_128	sha2_512	709	1			T5	2		T6	1		T7	4
key_128	sha2_384	639	1			T5	2		T6	4		T7	2
key_128	sha2_256	698	1			T5	2		T7	1		T24	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

649

1

T5

2

T26

1

T25

4

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1215	1			T5	4		T6	4		T7	3
key_invalid	sha2_none	915	1			T4	1		T5	2		T6	1
key_invalid	sha2_512	960	1			T3	1		T5	1		T6	2
key_invalid	sha2_384	935	1			T5	1		T6	1		T7	1
key_invalid	sha2_256	948	1			T1	1		T4	1		T6	2
key_none	sha2_invalid	588	1			T5	1		T6	1		T24	1
key_none	sha2_none	581	1			T4	1		T5	1		T6	1
key_none	sha2_512	2596	1			T1	1		T6	3		T7	5
key_none	sha2_384	2602	1			T3	1		T4	1		T5	2
key_none	sha2_256	1694	1			T4	1		T5	2		T7	1
key_1024	sha2_invalid	576	1			T1	1		T4	1		T5	2
key_1024	sha2_none	663	1			T1	1		T3	1		T4	1
key_1024	sha2_512	1780	1			T5	2		T6	5		T7	2
key_1024	sha2_384	979	1			T4	1		T5	2		T16	1
key_1024	sha2_256	649	1			T5	2		T26	1		T25	4
key_512	sha2_invalid	603	1			T5	1		T6	2		T17	1
key_512	sha2_none	624	1			T5	2		T17	2		T27	1
key_512	sha2_512	688	1			T6	3		T7	3		T27	1
key_512	sha2_384	1322	1			T5	2		T6	1		T16	1
key_512	sha2_256	941	1			T5	4		T6	3		T7	1
key_384	sha2_invalid	570	1			T5	1		T26	1		T19	2
key_384	sha2_none	651	1			T5	3		T7	3		T27	1
key_384	sha2_512	701	1			T5	2		T7	4		T27	1
key_384	sha2_384	669	1			T5	2		T6	4		T7	1
key_384	sha2_256	1120	1			T5	2		T6	2		T27	1
key_256	sha2_invalid	573	1			T3	1		T6	2		T17	1
key_256	sha2_none	621	1			T5	1		T6	1		T7	1
key_256	sha2_512	713	1			T5	2		T6	2		T7	2
key_256	sha2_384	675	1			T1	1		T5	3		T7	3
key_256	sha2_256	921	1			T4	3		T5	3		T6	1
key_128	sha2_invalid	580	1			T1	1		T5	1		T24	1
key_128	sha2_none	656	1			T5	1		T6	2		T7	1
key_128	sha2_512	709	1			T5	2		T6	1		T7	4
key_128	sha2_384	639	1			T5	2		T6	4		T7	2
key_128	sha2_256	698	1			T5	2		T7	1		T24	1