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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.05 95.40 97.27 100.00 97.06 98.27 98.48 99.85


Total test records in report: 660
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T534 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.25859104 Jul 30 05:16:44 PM PDT 24 Jul 30 05:16:48 PM PDT 24 984994414 ps
T61 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1637291980 Jul 30 05:16:30 PM PDT 24 Jul 30 05:16:35 PM PDT 24 493437731 ps
T112 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.962858758 Jul 30 05:16:47 PM PDT 24 Jul 30 05:16:49 PM PDT 24 812272474 ps
T88 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.885193225 Jul 30 05:16:23 PM PDT 24 Jul 30 05:16:24 PM PDT 24 20602124 ps
T535 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1657169993 Jul 30 05:16:31 PM PDT 24 Jul 30 05:16:34 PM PDT 24 423799635 ps
T536 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1999016 Jul 30 05:16:51 PM PDT 24 Jul 30 05:16:51 PM PDT 24 23282905 ps
T113 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2727501604 Jul 30 05:16:39 PM PDT 24 Jul 30 05:16:42 PM PDT 24 162013271 ps
T537 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2979745882 Jul 30 05:16:33 PM PDT 24 Jul 30 05:16:34 PM PDT 24 21304795 ps
T538 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4201045687 Jul 30 05:16:32 PM PDT 24 Jul 30 05:16:33 PM PDT 24 60330241 ps
T539 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1450982717 Jul 30 05:16:57 PM PDT 24 Jul 30 05:16:58 PM PDT 24 82181145 ps
T89 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1807930298 Jul 30 05:16:36 PM PDT 24 Jul 30 05:16:37 PM PDT 24 29849939 ps
T540 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1959982510 Jul 30 05:16:28 PM PDT 24 Jul 30 05:16:29 PM PDT 24 48442406 ps
T62 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.193770478 Jul 30 05:16:52 PM PDT 24 Jul 30 05:16:54 PM PDT 24 682712082 ps
T114 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3219399008 Jul 30 05:16:55 PM PDT 24 Jul 30 05:16:56 PM PDT 24 264477258 ps
T115 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3030082263 Jul 30 05:17:02 PM PDT 24 Jul 30 05:17:03 PM PDT 24 65719728 ps
T541 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1692520898 Jul 30 05:16:49 PM PDT 24 Jul 30 05:16:52 PM PDT 24 285900092 ps
T542 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2403757859 Jul 30 05:16:57 PM PDT 24 Jul 30 05:16:57 PM PDT 24 39363377 ps
T116 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2527037827 Jul 30 05:16:48 PM PDT 24 Jul 30 05:16:49 PM PDT 24 47839373 ps
T543 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2860472118 Jul 30 05:16:55 PM PDT 24 Jul 30 05:16:58 PM PDT 24 493776948 ps
T544 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2683053666 Jul 30 05:16:36 PM PDT 24 Jul 30 05:16:38 PM PDT 24 70310110 ps
T123 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1111622345 Jul 30 05:16:40 PM PDT 24 Jul 30 05:16:44 PM PDT 24 232108400 ps
T545 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2381182993 Jul 30 05:17:03 PM PDT 24 Jul 30 05:17:04 PM PDT 24 16534556 ps
T117 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2694841248 Jul 30 05:16:43 PM PDT 24 Jul 30 05:16:45 PM PDT 24 130550312 ps
T546 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4281263689 Jul 30 05:16:35 PM PDT 24 Jul 30 05:16:37 PM PDT 24 270283442 ps
T547 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4014124400 Jul 30 05:16:36 PM PDT 24 Jul 30 05:16:41 PM PDT 24 115920401 ps
T548 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3902143049 Jul 30 05:16:52 PM PDT 24 Jul 30 05:16:53 PM PDT 24 64586205 ps
T549 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3548982311 Jul 30 05:16:55 PM PDT 24 Jul 30 05:16:55 PM PDT 24 49946526 ps
T550 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1270620863 Jul 30 05:16:56 PM PDT 24 Jul 30 05:16:57 PM PDT 24 44282424 ps
T551 /workspace/coverage/cover_reg_top/44.hmac_intr_test.91646783 Jul 30 05:16:54 PM PDT 24 Jul 30 05:16:55 PM PDT 24 14416124 ps
T552 /workspace/coverage/cover_reg_top/25.hmac_intr_test.78593221 Jul 30 05:16:54 PM PDT 24 Jul 30 05:16:54 PM PDT 24 14363620 ps
T553 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2823600063 Jul 30 05:16:55 PM PDT 24 Jul 30 05:16:55 PM PDT 24 11415514 ps
T554 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2065246065 Jul 30 05:17:00 PM PDT 24 Jul 30 05:17:01 PM PDT 24 19299063 ps
T555 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.106935555 Jul 30 05:16:38 PM PDT 24 Jul 30 05:16:39 PM PDT 24 34538421 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.101129319 Jul 30 05:16:24 PM PDT 24 Jul 30 05:16:32 PM PDT 24 313929315 ps
T118 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.887269943 Jul 30 05:16:23 PM PDT 24 Jul 30 05:16:25 PM PDT 24 519796194 ps
T556 /workspace/coverage/cover_reg_top/26.hmac_intr_test.338375437 Jul 30 05:16:58 PM PDT 24 Jul 30 05:16:59 PM PDT 24 96529951 ps
T557 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3161576620 Jul 30 05:16:44 PM PDT 24 Jul 30 05:16:44 PM PDT 24 122664140 ps
T558 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.575440421 Jul 30 05:16:38 PM PDT 24 Jul 30 05:16:40 PM PDT 24 44019747 ps
T559 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1078542135 Jul 30 05:16:46 PM PDT 24 Jul 30 05:16:47 PM PDT 24 58842091 ps
T560 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1461482339 Jul 30 05:16:35 PM PDT 24 Jul 30 05:16:37 PM PDT 24 578473291 ps
T561 /workspace/coverage/cover_reg_top/33.hmac_intr_test.4273422159 Jul 30 05:16:54 PM PDT 24 Jul 30 05:16:55 PM PDT 24 47991842 ps
T119 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2361139133 Jul 30 05:16:43 PM PDT 24 Jul 30 05:16:45 PM PDT 24 98614582 ps
T562 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2181758116 Jul 30 05:16:44 PM PDT 24 Jul 30 05:16:46 PM PDT 24 86632242 ps
T563 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.91166446 Jul 30 05:16:28 PM PDT 24 Jul 30 05:16:30 PM PDT 24 47687751 ps
T564 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2232001819 Jul 30 05:16:55 PM PDT 24 Jul 30 05:16:56 PM PDT 24 16979619 ps
T91 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3640132410 Jul 30 05:16:44 PM PDT 24 Jul 30 05:16:45 PM PDT 24 55051400 ps
T92 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3381776988 Jul 30 05:16:42 PM PDT 24 Jul 30 05:16:43 PM PDT 24 21248580 ps
T565 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2381158213 Jul 30 05:16:28 PM PDT 24 Jul 30 05:16:29 PM PDT 24 60324582 ps
T93 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2717025382 Jul 30 05:16:50 PM PDT 24 Jul 30 05:16:51 PM PDT 24 15496235 ps
T94 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1438770832 Jul 30 05:16:37 PM PDT 24 Jul 30 05:16:38 PM PDT 24 126987438 ps
T566 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4139973329 Jul 30 05:16:49 PM PDT 24 Jul 30 05:16:51 PM PDT 24 124984679 ps
T567 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2092057004 Jul 30 05:16:36 PM PDT 24 Jul 30 05:16:38 PM PDT 24 545492132 ps
T568 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.191816661 Jul 30 05:16:43 PM PDT 24 Jul 30 05:16:44 PM PDT 24 44234412 ps
T569 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1565754264 Jul 30 05:16:38 PM PDT 24 Jul 30 05:16:39 PM PDT 24 42954408 ps
T570 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1271845243 Jul 30 05:16:53 PM PDT 24 Jul 30 05:16:57 PM PDT 24 156845900 ps
T129 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1837654388 Jul 30 05:16:44 PM PDT 24 Jul 30 05:16:47 PM PDT 24 232297441 ps
T571 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1464713778 Jul 30 05:16:44 PM PDT 24 Jul 30 05:16:46 PM PDT 24 37416940 ps
T572 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1067439162 Jul 30 05:16:30 PM PDT 24 Jul 30 05:31:04 PM PDT 24 1281439220127 ps
T573 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1998668341 Jul 30 05:16:49 PM PDT 24 Jul 30 05:16:51 PM PDT 24 296307277 ps
T95 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4125227287 Jul 30 05:16:43 PM PDT 24 Jul 30 05:16:44 PM PDT 24 53004420 ps
T131 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1224124767 Jul 30 05:16:48 PM PDT 24 Jul 30 05:16:53 PM PDT 24 290369154 ps
T128 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2416189579 Jul 30 05:16:49 PM PDT 24 Jul 30 05:16:54 PM PDT 24 367167794 ps
T574 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3666429217 Jul 30 05:16:51 PM PDT 24 Jul 30 05:16:54 PM PDT 24 142710098 ps
T575 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1186064026 Jul 30 05:16:36 PM PDT 24 Jul 30 05:16:38 PM PDT 24 88187520 ps
T576 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3430543071 Jul 30 05:16:54 PM PDT 24 Jul 30 05:16:55 PM PDT 24 20398253 ps
T109 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4286108605 Jul 30 05:16:47 PM PDT 24 Jul 30 05:16:47 PM PDT 24 36896750 ps
T577 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1346451705 Jul 30 05:16:55 PM PDT 24 Jul 30 05:16:56 PM PDT 24 14337328 ps
T96 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1154971445 Jul 30 05:16:50 PM PDT 24 Jul 30 05:16:50 PM PDT 24 21975360 ps
T578 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2567198397 Jul 30 05:16:25 PM PDT 24 Jul 30 05:16:28 PM PDT 24 181108014 ps
T579 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3091008921 Jul 30 05:16:40 PM PDT 24 Jul 30 05:16:44 PM PDT 24 282124532 ps
T130 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2358203579 Jul 30 05:16:46 PM PDT 24 Jul 30 05:16:48 PM PDT 24 219451602 ps
T580 /workspace/coverage/cover_reg_top/3.hmac_intr_test.217480537 Jul 30 05:16:30 PM PDT 24 Jul 30 05:16:31 PM PDT 24 12797438 ps
T581 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3752694279 Jul 30 05:16:58 PM PDT 24 Jul 30 05:16:58 PM PDT 24 18872614 ps
T582 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1284047186 Jul 30 05:16:57 PM PDT 24 Jul 30 05:16:58 PM PDT 24 44174743 ps
T583 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1049678224 Jul 30 05:16:50 PM PDT 24 Jul 30 05:16:51 PM PDT 24 17100252 ps
T97 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4172166947 Jul 30 05:16:28 PM PDT 24 Jul 30 05:16:34 PM PDT 24 1522894281 ps
T584 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.86583139 Jul 30 05:16:51 PM PDT 24 Jul 30 05:16:53 PM PDT 24 70544022 ps
T585 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3454930423 Jul 30 05:16:49 PM PDT 24 Jul 30 05:16:51 PM PDT 24 134706270 ps
T98 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.451439132 Jul 30 05:16:51 PM PDT 24 Jul 30 05:16:52 PM PDT 24 32616604 ps
T586 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2251138287 Jul 30 05:16:37 PM PDT 24 Jul 30 05:16:39 PM PDT 24 226948680 ps
T587 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.166935979 Jul 30 05:16:29 PM PDT 24 Jul 30 05:16:35 PM PDT 24 607833383 ps
T588 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1837105584 Jul 30 05:16:25 PM PDT 24 Jul 30 05:16:26 PM PDT 24 13753000 ps
T589 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1984746299 Jul 30 05:17:03 PM PDT 24 Jul 30 05:17:04 PM PDT 24 47197095 ps
T590 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2948439375 Jul 30 05:16:47 PM PDT 24 Jul 30 05:16:50 PM PDT 24 61462792 ps
T591 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2832674653 Jul 30 05:16:35 PM PDT 24 Jul 30 05:16:39 PM PDT 24 699464930 ps
T592 /workspace/coverage/cover_reg_top/32.hmac_intr_test.264272674 Jul 30 05:16:54 PM PDT 24 Jul 30 05:16:55 PM PDT 24 14482730 ps
T593 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.916099931 Jul 30 05:16:41 PM PDT 24 Jul 30 05:16:42 PM PDT 24 164505437 ps
T99 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1798366164 Jul 30 05:16:40 PM PDT 24 Jul 30 05:16:41 PM PDT 24 61348831 ps
T594 /workspace/coverage/cover_reg_top/40.hmac_intr_test.698697069 Jul 30 05:16:55 PM PDT 24 Jul 30 05:16:56 PM PDT 24 50084285 ps
T595 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4230255955 Jul 30 05:16:34 PM PDT 24 Jul 30 05:16:42 PM PDT 24 1018368395 ps
T127 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2733873606 Jul 30 05:16:44 PM PDT 24 Jul 30 05:16:48 PM PDT 24 236435828 ps
T596 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2158405667 Jul 30 05:16:26 PM PDT 24 Jul 30 05:16:27 PM PDT 24 37841738 ps
T597 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1444660729 Jul 30 05:16:23 PM PDT 24 Jul 30 05:16:25 PM PDT 24 510236952 ps
T598 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2438188280 Jul 30 05:16:30 PM PDT 24 Jul 30 05:16:32 PM PDT 24 20156338 ps
T599 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.727527765 Jul 30 05:16:47 PM PDT 24 Jul 30 05:16:48 PM PDT 24 28297634 ps
T600 /workspace/coverage/cover_reg_top/18.hmac_intr_test.629363321 Jul 30 05:16:50 PM PDT 24 Jul 30 05:16:51 PM PDT 24 36770643 ps
T601 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2998491030 Jul 30 05:16:47 PM PDT 24 Jul 30 05:16:47 PM PDT 24 13857065 ps
T602 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.107004178 Jul 30 05:16:37 PM PDT 24 Jul 30 05:16:38 PM PDT 24 99658095 ps
T603 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.647434559 Jul 30 05:16:49 PM PDT 24 Jul 30 05:16:50 PM PDT 24 152361071 ps
T604 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1946936832 Jul 30 05:16:54 PM PDT 24 Jul 30 05:16:55 PM PDT 24 11328614 ps
T605 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1077078191 Jul 30 05:16:26 PM PDT 24 Jul 30 05:16:27 PM PDT 24 53066994 ps
T606 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3360573560 Jul 30 05:16:46 PM PDT 24 Jul 30 05:16:48 PM PDT 24 119186864 ps
T607 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2365977168 Jul 30 05:16:38 PM PDT 24 Jul 30 05:16:39 PM PDT 24 44383639 ps
T608 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3031159679 Jul 30 05:16:44 PM PDT 24 Jul 30 05:16:45 PM PDT 24 19018228 ps
T609 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1866596290 Jul 30 05:16:53 PM PDT 24 Jul 30 05:16:53 PM PDT 24 23645570 ps
T610 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3573434365 Jul 30 05:16:49 PM PDT 24 Jul 30 05:16:50 PM PDT 24 11386548 ps
T611 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2879642851 Jul 30 05:16:30 PM PDT 24 Jul 30 05:16:32 PM PDT 24 108533213 ps
T612 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1261679953 Jul 30 05:16:37 PM PDT 24 Jul 30 05:16:38 PM PDT 24 16571284 ps
T613 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3081394285 Jul 30 05:16:50 PM PDT 24 Jul 30 05:16:51 PM PDT 24 39786411 ps
T124 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.438349652 Jul 30 05:16:39 PM PDT 24 Jul 30 05:16:42 PM PDT 24 305322525 ps
T614 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2205435130 Jul 30 05:16:38 PM PDT 24 Jul 30 05:16:39 PM PDT 24 45932664 ps
T615 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.647883951 Jul 30 05:16:25 PM PDT 24 Jul 30 05:16:29 PM PDT 24 203083689 ps
T616 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2445009028 Jul 30 05:16:24 PM PDT 24 Jul 30 05:16:25 PM PDT 24 67830696 ps
T617 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4023875931 Jul 30 05:16:44 PM PDT 24 Jul 30 05:32:10 PM PDT 24 352159938342 ps
T618 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.609412401 Jul 30 05:16:50 PM PDT 24 Jul 30 05:16:51 PM PDT 24 125724828 ps
T619 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.653328654 Jul 30 05:16:48 PM PDT 24 Jul 30 05:16:49 PM PDT 24 23218782 ps
T620 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3035890363 Jul 30 05:16:29 PM PDT 24 Jul 30 05:16:30 PM PDT 24 506342580 ps
T621 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1576254649 Jul 30 05:16:54 PM PDT 24 Jul 30 05:16:56 PM PDT 24 435962709 ps
T622 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3982117755 Jul 30 05:16:36 PM PDT 24 Jul 30 05:16:44 PM PDT 24 609107276 ps
T623 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.570342452 Jul 30 05:16:35 PM PDT 24 Jul 30 05:16:37 PM PDT 24 94966694 ps
T624 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.628591383 Jul 30 05:16:51 PM PDT 24 Jul 30 05:31:29 PM PDT 24 249056974748 ps
T625 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1204920953 Jul 30 05:16:31 PM PDT 24 Jul 30 05:16:32 PM PDT 24 91122685 ps
T626 /workspace/coverage/cover_reg_top/15.hmac_intr_test.433436176 Jul 30 05:16:50 PM PDT 24 Jul 30 05:16:50 PM PDT 24 13198065 ps
T627 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1640464174 Jul 30 05:16:36 PM PDT 24 Jul 30 05:16:45 PM PDT 24 221416468 ps
T628 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2038322426 Jul 30 05:16:57 PM PDT 24 Jul 30 05:16:58 PM PDT 24 20621837 ps
T629 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1899279025 Jul 30 05:16:44 PM PDT 24 Jul 30 05:16:45 PM PDT 24 60299675 ps
T630 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3200800175 Jul 30 05:16:25 PM PDT 24 Jul 30 05:16:36 PM PDT 24 1405708218 ps
T631 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2778276419 Jul 30 05:16:43 PM PDT 24 Jul 30 05:16:46 PM PDT 24 414900301 ps
T632 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2499115764 Jul 30 05:16:56 PM PDT 24 Jul 30 05:16:57 PM PDT 24 23361137 ps
T633 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1895457206 Jul 30 05:16:50 PM PDT 24 Jul 30 05:16:51 PM PDT 24 48038425 ps
T634 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3046656435 Jul 30 05:16:44 PM PDT 24 Jul 30 05:16:46 PM PDT 24 298368753 ps
T635 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1852862029 Jul 30 05:16:51 PM PDT 24 Jul 30 05:16:52 PM PDT 24 42871591 ps
T636 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2109092056 Jul 30 05:16:50 PM PDT 24 Jul 30 05:16:51 PM PDT 24 125996768 ps
T637 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3190299561 Jul 30 05:16:33 PM PDT 24 Jul 30 05:16:34 PM PDT 24 17261849 ps
T125 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2480804901 Jul 30 05:16:34 PM PDT 24 Jul 30 05:16:36 PM PDT 24 398609673 ps
T638 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2243091520 Jul 30 05:16:53 PM PDT 24 Jul 30 05:16:54 PM PDT 24 48294329 ps
T639 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2283207703 Jul 30 05:17:01 PM PDT 24 Jul 30 05:17:02 PM PDT 24 10918305 ps
T640 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1296662299 Jul 30 05:17:02 PM PDT 24 Jul 30 05:17:03 PM PDT 24 49000617 ps
T641 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1380953989 Jul 30 05:16:51 PM PDT 24 Jul 30 05:16:55 PM PDT 24 180087823 ps
T642 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1705582421 Jul 30 05:16:51 PM PDT 24 Jul 30 05:16:52 PM PDT 24 20418948 ps
T643 /workspace/coverage/cover_reg_top/41.hmac_intr_test.481692142 Jul 30 05:16:56 PM PDT 24 Jul 30 05:16:57 PM PDT 24 18309410 ps
T644 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3008574948 Jul 30 05:16:25 PM PDT 24 Jul 30 05:16:35 PM PDT 24 719865509 ps
T645 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1644778691 Jul 30 05:16:47 PM PDT 24 Jul 30 05:16:50 PM PDT 24 85373310 ps
T646 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.828364495 Jul 30 05:16:48 PM PDT 24 Jul 30 05:19:53 PM PDT 24 12293138355 ps
T647 /workspace/coverage/cover_reg_top/39.hmac_intr_test.970350374 Jul 30 05:16:52 PM PDT 24 Jul 30 05:16:53 PM PDT 24 74272523 ps
T648 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4263976183 Jul 30 05:16:51 PM PDT 24 Jul 30 05:16:53 PM PDT 24 85423008 ps
T649 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2406309048 Jul 30 05:16:29 PM PDT 24 Jul 30 05:16:30 PM PDT 24 27546024 ps
T650 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2346187193 Jul 30 05:16:23 PM PDT 24 Jul 30 05:16:27 PM PDT 24 685320444 ps
T651 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4047929641 Jul 30 05:16:36 PM PDT 24 Jul 30 05:16:38 PM PDT 24 196197233 ps
T652 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.611647259 Jul 30 05:16:38 PM PDT 24 Jul 30 05:16:41 PM PDT 24 83672367 ps
T653 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2494826712 Jul 30 05:17:00 PM PDT 24 Jul 30 05:17:01 PM PDT 24 17605913 ps
T654 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.823732831 Jul 30 05:16:42 PM PDT 24 Jul 30 05:16:46 PM PDT 24 568826464 ps
T655 /workspace/coverage/cover_reg_top/16.hmac_intr_test.349947645 Jul 30 05:16:49 PM PDT 24 Jul 30 05:16:49 PM PDT 24 40701331 ps
T656 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1766530305 Jul 30 05:16:23 PM PDT 24 Jul 30 05:17:26 PM PDT 24 8314120002 ps
T657 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1668267478 Jul 30 05:16:55 PM PDT 24 Jul 30 05:16:56 PM PDT 24 11397599 ps
T658 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.81024024 Jul 30 05:17:03 PM PDT 24 Jul 30 05:17:04 PM PDT 24 29198737 ps
T126 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.322348659 Jul 30 05:16:50 PM PDT 24 Jul 30 05:16:55 PM PDT 24 240069268 ps
T659 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.4095337658 Jul 30 05:16:30 PM PDT 24 Jul 30 05:16:33 PM PDT 24 117360735 ps
T660 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1359688049 Jul 30 05:16:24 PM PDT 24 Jul 30 05:16:29 PM PDT 24 235243646 ps
T63 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4289748485 Jul 30 05:16:48 PM PDT 24 Jul 30 05:16:50 PM PDT 24 85311989 ps

Test location /workspace/coverage/default/43.hmac_burst_wr.676333735
Short name T7
Test name
Test status
Simulation time 1247183327 ps
CPU time 62.79 seconds
Started Jul 30 05:19:05 PM PDT 24
Finished Jul 30 05:20:08 PM PDT 24
Peak memory 199948 kb
Host smart-fc81c7f7-0353-4894-b28a-292c7f8dbb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676333735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.676333735
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1115450588
Short name T6
Test name
Test status
Simulation time 993451286 ps
CPU time 54.02 seconds
Started Jul 30 05:17:08 PM PDT 24
Finished Jul 30 05:18:02 PM PDT 24
Peak memory 199928 kb
Host smart-e407e7c9-118a-4615-a731-1bf37bd0d7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115450588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1115450588
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.4076862333
Short name T8
Test name
Test status
Simulation time 68998284915 ps
CPU time 1362.3 seconds
Started Jul 30 05:17:19 PM PDT 24
Finished Jul 30 05:40:02 PM PDT 24
Peak memory 460204 kb
Host smart-7e4dd1cc-72e8-4b0f-b3b6-a203abc41953
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4076862333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.4076862333
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1574405063
Short name T21
Test name
Test status
Simulation time 55867676187 ps
CPU time 1462.69 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:41:47 PM PDT 24
Peak memory 686508 kb
Host smart-e5820cb8-9203-4968-98c1-85788da282d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574405063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1574405063
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1637291980
Short name T61
Test name
Test status
Simulation time 493437731 ps
CPU time 4.3 seconds
Started Jul 30 05:16:30 PM PDT 24
Finished Jul 30 05:16:35 PM PDT 24
Peak memory 200172 kb
Host smart-189c75a1-69a1-4ad4-80ec-f8e19913390a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637291980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1637291980
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1559595180
Short name T12
Test name
Test status
Simulation time 81916183051 ps
CPU time 3586.11 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 06:17:12 PM PDT 24
Peak memory 859088 kb
Host smart-2fb1e650-6cd0-47b1-9baa-0fc404fe85a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559595180 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1559595180
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all.736599502
Short name T20
Test name
Test status
Simulation time 42911691231 ps
CPU time 1375.66 seconds
Started Jul 30 05:19:05 PM PDT 24
Finished Jul 30 05:42:01 PM PDT 24
Peak memory 754188 kb
Host smart-a41e2b53-abe2-4f92-b86c-7083923a5d5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736599502 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.736599502
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3115663938
Short name T47
Test name
Test status
Simulation time 23342745 ps
CPU time 0.61 seconds
Started Jul 30 05:17:31 PM PDT 24
Finished Jul 30 05:17:32 PM PDT 24
Peak memory 195960 kb
Host smart-273be075-c0d7-4eb7-919f-4985320b8bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115663938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3115663938
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3688017982
Short name T50
Test name
Test status
Simulation time 167155203 ps
CPU time 1.2 seconds
Started Jul 30 05:17:01 PM PDT 24
Finished Jul 30 05:17:02 PM PDT 24
Peak memory 219696 kb
Host smart-09b9fc45-2288-4ce5-a2d9-417ceed9a22f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688017982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3688017982
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.101129319
Short name T90
Test name
Test status
Simulation time 313929315 ps
CPU time 8.27 seconds
Started Jul 30 05:16:24 PM PDT 24
Finished Jul 30 05:16:32 PM PDT 24
Peak memory 200132 kb
Host smart-bab50eb5-f229-45aa-b3d6-a09a1cd4d94f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101129319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.101129319
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.322348659
Short name T126
Test name
Test status
Simulation time 240069268 ps
CPU time 4.19 seconds
Started Jul 30 05:16:50 PM PDT 24
Finished Jul 30 05:16:55 PM PDT 24
Peak memory 200172 kb
Host smart-ef50b3d7-239e-42fd-b2e1-160a34b1844c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322348659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.322348659
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3240217320
Short name T18
Test name
Test status
Simulation time 3849945915 ps
CPU time 58.53 seconds
Started Jul 30 05:17:11 PM PDT 24
Finished Jul 30 05:18:10 PM PDT 24
Peak memory 208200 kb
Host smart-679740fa-ade7-424a-9b46-659ccdd5477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240217320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3240217320
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3871462657
Short name T64
Test name
Test status
Simulation time 495591254033 ps
CPU time 9105.43 seconds
Started Jul 30 05:17:19 PM PDT 24
Finished Jul 30 07:49:05 PM PDT 24
Peak memory 854564 kb
Host smart-883d5da8-e345-4cdd-9724-5d35cf737a1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871462657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3871462657
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.887269943
Short name T118
Test name
Test status
Simulation time 519796194 ps
CPU time 2.18 seconds
Started Jul 30 05:16:23 PM PDT 24
Finished Jul 30 05:16:25 PM PDT 24
Peak memory 200128 kb
Host smart-01f7ff2b-d2cc-44e5-80d3-e8d9e4822bb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887269943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.887269943
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2958728646
Short name T9
Test name
Test status
Simulation time 113407177150 ps
CPU time 2839.6 seconds
Started Jul 30 05:17:00 PM PDT 24
Finished Jul 30 06:04:20 PM PDT 24
Peak memory 759904 kb
Host smart-150683dc-49d5-4ee0-866a-c5f0f9774e85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958728646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2958728646
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2166354446
Short name T46
Test name
Test status
Simulation time 93404723984 ps
CPU time 632.43 seconds
Started Jul 30 05:17:00 PM PDT 24
Finished Jul 30 05:27:33 PM PDT 24
Peak memory 199976 kb
Host smart-1f65ad42-9fb6-478f-978b-d83b8e077303
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2166354446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2166354446
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4289748485
Short name T63
Test name
Test status
Simulation time 85311989 ps
CPU time 1.93 seconds
Started Jul 30 05:16:48 PM PDT 24
Finished Jul 30 05:16:50 PM PDT 24
Peak memory 200068 kb
Host smart-b056e0ca-dead-4ac6-b0f4-420790e413ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289748485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4289748485
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.647883951
Short name T615
Test name
Test status
Simulation time 203083689 ps
CPU time 3.35 seconds
Started Jul 30 05:16:25 PM PDT 24
Finished Jul 30 05:16:29 PM PDT 24
Peak memory 200148 kb
Host smart-2edbb56c-9580-40dd-959e-9f829200b774
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647883951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.647883951
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3008574948
Short name T644
Test name
Test status
Simulation time 719865509 ps
CPU time 10.31 seconds
Started Jul 30 05:16:25 PM PDT 24
Finished Jul 30 05:16:35 PM PDT 24
Peak memory 200108 kb
Host smart-ea29aee2-113c-4c23-8f7b-641c8f839dc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008574948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3008574948
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2158405667
Short name T596
Test name
Test status
Simulation time 37841738 ps
CPU time 0.73 seconds
Started Jul 30 05:16:26 PM PDT 24
Finished Jul 30 05:16:27 PM PDT 24
Peak memory 198056 kb
Host smart-37a8866a-24b5-4962-9ed4-28a6bb38f751
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158405667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2158405667
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1766530305
Short name T656
Test name
Test status
Simulation time 8314120002 ps
CPU time 63.1 seconds
Started Jul 30 05:16:23 PM PDT 24
Finished Jul 30 05:17:26 PM PDT 24
Peak memory 216612 kb
Host smart-a04c0399-0ee6-40bb-8471-7631cddc73bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766530305 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1766530305
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1837105584
Short name T588
Test name
Test status
Simulation time 13753000 ps
CPU time 0.68 seconds
Started Jul 30 05:16:25 PM PDT 24
Finished Jul 30 05:16:26 PM PDT 24
Peak memory 198364 kb
Host smart-aa7a2f95-cbcb-435c-9b05-d5f57123d4c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837105584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1837105584
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2381158213
Short name T565
Test name
Test status
Simulation time 60324582 ps
CPU time 0.64 seconds
Started Jul 30 05:16:28 PM PDT 24
Finished Jul 30 05:16:29 PM PDT 24
Peak memory 195064 kb
Host smart-049fc190-6b2d-4e52-a5e6-0a65d3373099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381158213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2381158213
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2346187193
Short name T650
Test name
Test status
Simulation time 685320444 ps
CPU time 3.6 seconds
Started Jul 30 05:16:23 PM PDT 24
Finished Jul 30 05:16:27 PM PDT 24
Peak memory 200188 kb
Host smart-fe585e2b-e8c1-4e57-94d1-c6708b9547b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346187193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2346187193
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2567198397
Short name T578
Test name
Test status
Simulation time 181108014 ps
CPU time 3.11 seconds
Started Jul 30 05:16:25 PM PDT 24
Finished Jul 30 05:16:28 PM PDT 24
Peak memory 200192 kb
Host smart-e5ad4a20-7a66-411a-976a-ede141953ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567198397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2567198397
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3200800175
Short name T630
Test name
Test status
Simulation time 1405708218 ps
CPU time 10.7 seconds
Started Jul 30 05:16:25 PM PDT 24
Finished Jul 30 05:16:36 PM PDT 24
Peak memory 200000 kb
Host smart-b740341a-38a9-49ca-9cba-92c88771f50d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200800175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3200800175
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.885193225
Short name T88
Test name
Test status
Simulation time 20602124 ps
CPU time 0.85 seconds
Started Jul 30 05:16:23 PM PDT 24
Finished Jul 30 05:16:24 PM PDT 24
Peak memory 199680 kb
Host smart-06b1f87d-ec12-4ce8-b621-7338052d003d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885193225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.885193225
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1067439162
Short name T572
Test name
Test status
Simulation time 1281439220127 ps
CPU time 874.05 seconds
Started Jul 30 05:16:30 PM PDT 24
Finished Jul 30 05:31:04 PM PDT 24
Peak memory 213260 kb
Host smart-96fcbeae-c131-420a-bc69-2784fe7705bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067439162 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1067439162
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2445009028
Short name T616
Test name
Test status
Simulation time 67830696 ps
CPU time 0.67 seconds
Started Jul 30 05:16:24 PM PDT 24
Finished Jul 30 05:16:25 PM PDT 24
Peak memory 198096 kb
Host smart-8846d16d-1b3e-4d9b-8bc1-773d3fd8a55d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445009028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2445009028
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1077078191
Short name T605
Test name
Test status
Simulation time 53066994 ps
CPU time 0.59 seconds
Started Jul 30 05:16:26 PM PDT 24
Finished Jul 30 05:16:27 PM PDT 24
Peak memory 195060 kb
Host smart-4a4aeab2-939c-4e4c-be4b-7a121b8b3e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077078191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1077078191
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2879642851
Short name T611
Test name
Test status
Simulation time 108533213 ps
CPU time 1.79 seconds
Started Jul 30 05:16:30 PM PDT 24
Finished Jul 30 05:16:32 PM PDT 24
Peak memory 200144 kb
Host smart-2357afe1-94c5-498e-9f1a-f08194d7ef8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879642851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2879642851
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1444660729
Short name T597
Test name
Test status
Simulation time 510236952 ps
CPU time 1.7 seconds
Started Jul 30 05:16:23 PM PDT 24
Finished Jul 30 05:16:25 PM PDT 24
Peak memory 200088 kb
Host smart-cab29ba4-a559-42d0-acbb-b82dbf89fefe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444660729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1444660729
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1359688049
Short name T660
Test name
Test status
Simulation time 235243646 ps
CPU time 4.54 seconds
Started Jul 30 05:16:24 PM PDT 24
Finished Jul 30 05:16:29 PM PDT 24
Peak memory 200124 kb
Host smart-e48cbf91-695d-4ec5-a17e-3b79d959e20e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359688049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1359688049
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4023875931
Short name T617
Test name
Test status
Simulation time 352159938342 ps
CPU time 925.36 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:32:10 PM PDT 24
Peak memory 224820 kb
Host smart-8240c7d7-b5fa-4175-b21f-0459420e021d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023875931 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4023875931
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3640132410
Short name T91
Test name
Test status
Simulation time 55051400 ps
CPU time 0.84 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:45 PM PDT 24
Peak memory 200012 kb
Host smart-ec14c5b3-d387-4543-9229-97109537be92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640132410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3640132410
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2205435130
Short name T614
Test name
Test status
Simulation time 45932664 ps
CPU time 0.58 seconds
Started Jul 30 05:16:38 PM PDT 24
Finished Jul 30 05:16:39 PM PDT 24
Peak memory 195164 kb
Host smart-08ad1184-bd02-48db-a711-2b0d06c2ea0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205435130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2205435130
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1644778691
Short name T645
Test name
Test status
Simulation time 85373310 ps
CPU time 2.18 seconds
Started Jul 30 05:16:47 PM PDT 24
Finished Jul 30 05:16:50 PM PDT 24
Peak memory 200176 kb
Host smart-52e1694f-d2ef-4046-9b59-431e171ebdad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644778691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1644778691
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3666429217
Short name T574
Test name
Test status
Simulation time 142710098 ps
CPU time 2.88 seconds
Started Jul 30 05:16:51 PM PDT 24
Finished Jul 30 05:16:54 PM PDT 24
Peak memory 200176 kb
Host smart-7a1b7224-0ec4-4623-8eab-a2e74d4fbf57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666429217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3666429217
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.438349652
Short name T124
Test name
Test status
Simulation time 305322525 ps
CPU time 2.9 seconds
Started Jul 30 05:16:39 PM PDT 24
Finished Jul 30 05:16:42 PM PDT 24
Peak memory 200252 kb
Host smart-4910d40b-4e60-4003-abc8-34999c523f95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438349652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.438349652
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1464713778
Short name T571
Test name
Test status
Simulation time 37416940 ps
CPU time 1.29 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:46 PM PDT 24
Peak memory 200084 kb
Host smart-bb39d010-dde2-40fe-8ebb-8359ed5712b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464713778 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1464713778
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3161576620
Short name T557
Test name
Test status
Simulation time 122664140 ps
CPU time 0.72 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:44 PM PDT 24
Peak memory 198028 kb
Host smart-39aecc5d-2920-4859-9d95-3500fea4e0f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161576620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3161576620
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3031159679
Short name T608
Test name
Test status
Simulation time 19018228 ps
CPU time 0.65 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:45 PM PDT 24
Peak memory 194984 kb
Host smart-c6ea2b7c-657b-49b2-bd5c-d7182c510c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031159679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3031159679
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3046656435
Short name T634
Test name
Test status
Simulation time 298368753 ps
CPU time 2.36 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:46 PM PDT 24
Peak memory 200192 kb
Host smart-6be6117b-6299-44af-879d-4a4db0753184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046656435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3046656435
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2181758116
Short name T562
Test name
Test status
Simulation time 86632242 ps
CPU time 1.78 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:46 PM PDT 24
Peak memory 200140 kb
Host smart-cc9633a4-7200-4680-b6d5-c1044fd3beef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181758116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2181758116
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2097763343
Short name T60
Test name
Test status
Simulation time 591952587 ps
CPU time 3.08 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:47 PM PDT 24
Peak memory 200144 kb
Host smart-701421fe-9f56-43c1-b4d0-466a8cc75aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097763343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2097763343
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2778276419
Short name T631
Test name
Test status
Simulation time 414900301 ps
CPU time 2.31 seconds
Started Jul 30 05:16:43 PM PDT 24
Finished Jul 30 05:16:46 PM PDT 24
Peak memory 200164 kb
Host smart-3db3e249-d886-4fb2-bf7d-2e6258df3bff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778276419 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2778276419
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4286108605
Short name T109
Test name
Test status
Simulation time 36896750 ps
CPU time 0.7 seconds
Started Jul 30 05:16:47 PM PDT 24
Finished Jul 30 05:16:47 PM PDT 24
Peak memory 198368 kb
Host smart-97ef4687-648d-4c2d-a8ff-2fcb03fac2c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286108605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4286108605
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1078542135
Short name T559
Test name
Test status
Simulation time 58842091 ps
CPU time 0.63 seconds
Started Jul 30 05:16:46 PM PDT 24
Finished Jul 30 05:16:47 PM PDT 24
Peak memory 195032 kb
Host smart-fa26b43e-d037-4a4a-be55-20bcba3dae06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078542135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1078542135
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.191816661
Short name T568
Test name
Test status
Simulation time 44234412 ps
CPU time 1.13 seconds
Started Jul 30 05:16:43 PM PDT 24
Finished Jul 30 05:16:44 PM PDT 24
Peak memory 200172 kb
Host smart-8ba1ee4c-a1a3-4762-98e3-5c9ce6303632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191816661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.191816661
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2709678925
Short name T532
Test name
Test status
Simulation time 193004206 ps
CPU time 4.14 seconds
Started Jul 30 05:16:45 PM PDT 24
Finished Jul 30 05:16:49 PM PDT 24
Peak memory 200112 kb
Host smart-74492998-9dfa-4152-bf95-023e47b10172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709678925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2709678925
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2733873606
Short name T127
Test name
Test status
Simulation time 236435828 ps
CPU time 3.89 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:48 PM PDT 24
Peak memory 200216 kb
Host smart-c7ec31c4-616f-4583-8f19-be16b932c0b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733873606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2733873606
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3360573560
Short name T606
Test name
Test status
Simulation time 119186864 ps
CPU time 1.8 seconds
Started Jul 30 05:16:46 PM PDT 24
Finished Jul 30 05:16:48 PM PDT 24
Peak memory 200128 kb
Host smart-6d69d71c-2968-4bf9-97b4-f45b16969898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360573560 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3360573560
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4125227287
Short name T95
Test name
Test status
Simulation time 53004420 ps
CPU time 0.68 seconds
Started Jul 30 05:16:43 PM PDT 24
Finished Jul 30 05:16:44 PM PDT 24
Peak memory 198236 kb
Host smart-85b391ba-5dbd-4de2-9ed6-96791bdffeee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125227287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.4125227287
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1899279025
Short name T629
Test name
Test status
Simulation time 60299675 ps
CPU time 0.69 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:45 PM PDT 24
Peak memory 195164 kb
Host smart-9b8b3d4b-b376-47ae-9498-ce13f56de9da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899279025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1899279025
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2694841248
Short name T117
Test name
Test status
Simulation time 130550312 ps
CPU time 1.69 seconds
Started Jul 30 05:16:43 PM PDT 24
Finished Jul 30 05:16:45 PM PDT 24
Peak memory 200036 kb
Host smart-5b53f190-0098-4844-8bc6-b3d52819649a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694841248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2694841248
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.25859104
Short name T534
Test name
Test status
Simulation time 984994414 ps
CPU time 4.35 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:48 PM PDT 24
Peak memory 200124 kb
Host smart-c6c751ea-7243-4693-8480-ba88b4fc7124
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25859104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.25859104
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2358203579
Short name T130
Test name
Test status
Simulation time 219451602 ps
CPU time 1.76 seconds
Started Jul 30 05:16:46 PM PDT 24
Finished Jul 30 05:16:48 PM PDT 24
Peak memory 200196 kb
Host smart-f3783f3e-2517-496a-a16d-9e878a3db4fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358203579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2358203579
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1998668341
Short name T573
Test name
Test status
Simulation time 296307277 ps
CPU time 1.94 seconds
Started Jul 30 05:16:49 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 200184 kb
Host smart-1aec7d62-1b36-46a4-955a-40dba860668a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998668341 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1998668341
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.653328654
Short name T619
Test name
Test status
Simulation time 23218782 ps
CPU time 0.83 seconds
Started Jul 30 05:16:48 PM PDT 24
Finished Jul 30 05:16:49 PM PDT 24
Peak memory 199908 kb
Host smart-6f4873c8-fb8f-4dad-84d2-51bb84007c92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653328654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.653328654
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2283207703
Short name T639
Test name
Test status
Simulation time 10918305 ps
CPU time 0.61 seconds
Started Jul 30 05:17:01 PM PDT 24
Finished Jul 30 05:17:02 PM PDT 24
Peak memory 195060 kb
Host smart-a67daa61-8f5f-4397-9b94-150be7cd9a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283207703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2283207703
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.86583139
Short name T584
Test name
Test status
Simulation time 70544022 ps
CPU time 1.63 seconds
Started Jul 30 05:16:51 PM PDT 24
Finished Jul 30 05:16:53 PM PDT 24
Peak memory 200028 kb
Host smart-ba646226-0422-4714-8a5e-d48d49a0ab01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86583139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_
outstanding.86583139
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.823732831
Short name T654
Test name
Test status
Simulation time 568826464 ps
CPU time 2.93 seconds
Started Jul 30 05:16:42 PM PDT 24
Finished Jul 30 05:16:46 PM PDT 24
Peak memory 200176 kb
Host smart-bef1babf-ef70-45c4-9aaf-63e162f24953
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823732831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.823732831
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2109092056
Short name T636
Test name
Test status
Simulation time 125996768 ps
CPU time 1.64 seconds
Started Jul 30 05:16:50 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 200168 kb
Host smart-eed03caa-8984-44af-9af8-5c4114cbdb92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109092056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2109092056
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.828364495
Short name T646
Test name
Test status
Simulation time 12293138355 ps
CPU time 184.78 seconds
Started Jul 30 05:16:48 PM PDT 24
Finished Jul 30 05:19:53 PM PDT 24
Peak memory 215600 kb
Host smart-535c3479-93a6-4208-8767-4e501a8d9ef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828364495 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.828364495
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1154971445
Short name T96
Test name
Test status
Simulation time 21975360 ps
CPU time 0.7 seconds
Started Jul 30 05:16:50 PM PDT 24
Finished Jul 30 05:16:50 PM PDT 24
Peak memory 198008 kb
Host smart-75dd2805-1caf-4c7f-8f1f-0d52eecb243e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154971445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1154971445
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.433436176
Short name T626
Test name
Test status
Simulation time 13198065 ps
CPU time 0.61 seconds
Started Jul 30 05:16:50 PM PDT 24
Finished Jul 30 05:16:50 PM PDT 24
Peak memory 195068 kb
Host smart-02b4dc4f-9f1f-4005-a8cc-6a70081fa278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433436176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.433436176
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3030082263
Short name T115
Test name
Test status
Simulation time 65719728 ps
CPU time 1.31 seconds
Started Jul 30 05:17:02 PM PDT 24
Finished Jul 30 05:17:03 PM PDT 24
Peak memory 199352 kb
Host smart-4fb25218-2284-4d4f-84ce-9429f8032620
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030082263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3030082263
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4139973329
Short name T566
Test name
Test status
Simulation time 124984679 ps
CPU time 1.89 seconds
Started Jul 30 05:16:49 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 200208 kb
Host smart-bc15bc16-7029-4edd-a9bd-49c0441fd9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139973329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.4139973329
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3081394285
Short name T613
Test name
Test status
Simulation time 39786411 ps
CPU time 1.25 seconds
Started Jul 30 05:16:50 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 200176 kb
Host smart-d57b5dba-51b4-40cb-9afa-c1807042f7a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081394285 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3081394285
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1895457206
Short name T633
Test name
Test status
Simulation time 48038425 ps
CPU time 0.78 seconds
Started Jul 30 05:16:50 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 199512 kb
Host smart-4669fe2c-11fc-4af0-b13e-4bffa4f73bfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895457206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1895457206
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.349947645
Short name T655
Test name
Test status
Simulation time 40701331 ps
CPU time 0.6 seconds
Started Jul 30 05:16:49 PM PDT 24
Finished Jul 30 05:16:49 PM PDT 24
Peak memory 195064 kb
Host smart-71ab1674-fcd6-427d-a969-c331c5274c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349947645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.349947645
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.609412401
Short name T618
Test name
Test status
Simulation time 125724828 ps
CPU time 1.75 seconds
Started Jul 30 05:16:50 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 200200 kb
Host smart-075fe506-265a-4c94-a9e3-851ac320facd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609412401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.609412401
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2948439375
Short name T590
Test name
Test status
Simulation time 61462792 ps
CPU time 2.69 seconds
Started Jul 30 05:16:47 PM PDT 24
Finished Jul 30 05:16:50 PM PDT 24
Peak memory 200196 kb
Host smart-8295ac6f-6801-4af5-9dfc-f241f40473bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948439375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2948439375
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2416189579
Short name T128
Test name
Test status
Simulation time 367167794 ps
CPU time 4.51 seconds
Started Jul 30 05:16:49 PM PDT 24
Finished Jul 30 05:16:54 PM PDT 24
Peak memory 200056 kb
Host smart-c331ed99-4244-4834-a899-b75233c910f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416189579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2416189579
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1576254649
Short name T621
Test name
Test status
Simulation time 435962709 ps
CPU time 1.72 seconds
Started Jul 30 05:16:54 PM PDT 24
Finished Jul 30 05:16:56 PM PDT 24
Peak memory 200196 kb
Host smart-1da77239-5a10-4b30-890f-9363369042b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576254649 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1576254649
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2717025382
Short name T93
Test name
Test status
Simulation time 15496235 ps
CPU time 0.69 seconds
Started Jul 30 05:16:50 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 197740 kb
Host smart-c882f631-b93b-48de-bdb5-923efca5a3bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717025382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2717025382
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3573434365
Short name T610
Test name
Test status
Simulation time 11386548 ps
CPU time 0.57 seconds
Started Jul 30 05:16:49 PM PDT 24
Finished Jul 30 05:16:50 PM PDT 24
Peak memory 194948 kb
Host smart-2f67ec8b-7f5d-47a5-8588-c32e85bab216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573434365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3573434365
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2527037827
Short name T116
Test name
Test status
Simulation time 47839373 ps
CPU time 1.18 seconds
Started Jul 30 05:16:48 PM PDT 24
Finished Jul 30 05:16:49 PM PDT 24
Peak memory 198768 kb
Host smart-5de18380-dd32-4faa-b3e7-b15e697ace25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527037827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2527037827
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.81024024
Short name T658
Test name
Test status
Simulation time 29198737 ps
CPU time 1.44 seconds
Started Jul 30 05:17:03 PM PDT 24
Finished Jul 30 05:17:04 PM PDT 24
Peak memory 200028 kb
Host smart-219c0376-bb2e-4330-b709-8fca322cab79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81024024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.81024024
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1380953989
Short name T641
Test name
Test status
Simulation time 180087823 ps
CPU time 4.12 seconds
Started Jul 30 05:16:51 PM PDT 24
Finished Jul 30 05:16:55 PM PDT 24
Peak memory 200172 kb
Host smart-46cb067d-b604-4f1f-aaaa-9dcd09748992
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380953989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1380953989
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.628591383
Short name T624
Test name
Test status
Simulation time 249056974748 ps
CPU time 876.98 seconds
Started Jul 30 05:16:51 PM PDT 24
Finished Jul 30 05:31:29 PM PDT 24
Peak memory 216564 kb
Host smart-b50f696c-86ee-4280-8bc4-31233826909e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628591383 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.628591383
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.451439132
Short name T98
Test name
Test status
Simulation time 32616604 ps
CPU time 0.7 seconds
Started Jul 30 05:16:51 PM PDT 24
Finished Jul 30 05:16:52 PM PDT 24
Peak memory 198264 kb
Host smart-61e16d47-e9cc-4225-acc4-0826a4c453d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451439132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.451439132
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.629363321
Short name T600
Test name
Test status
Simulation time 36770643 ps
CPU time 0.63 seconds
Started Jul 30 05:16:50 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 195060 kb
Host smart-51b33364-eaf3-4807-b683-f11085dd7861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629363321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.629363321
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.647434559
Short name T603
Test name
Test status
Simulation time 152361071 ps
CPU time 1.05 seconds
Started Jul 30 05:16:49 PM PDT 24
Finished Jul 30 05:16:50 PM PDT 24
Peak memory 200112 kb
Host smart-74d6bcca-8f96-4abd-b2c7-a5bf04371de1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647434559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.647434559
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3454930423
Short name T585
Test name
Test status
Simulation time 134706270 ps
CPU time 1.93 seconds
Started Jul 30 05:16:49 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 200144 kb
Host smart-6953355a-53db-4880-9393-e8b11120718b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454930423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3454930423
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1224124767
Short name T131
Test name
Test status
Simulation time 290369154 ps
CPU time 4.63 seconds
Started Jul 30 05:16:48 PM PDT 24
Finished Jul 30 05:16:53 PM PDT 24
Peak memory 200140 kb
Host smart-82ddd76f-802a-4e49-a737-418bf1547af1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224124767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1224124767
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1692520898
Short name T541
Test name
Test status
Simulation time 285900092 ps
CPU time 2.27 seconds
Started Jul 30 05:16:49 PM PDT 24
Finished Jul 30 05:16:52 PM PDT 24
Peak memory 200128 kb
Host smart-af210c57-afd8-47e0-856b-a22b158af7e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692520898 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1692520898
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3219399008
Short name T114
Test name
Test status
Simulation time 264477258 ps
CPU time 0.81 seconds
Started Jul 30 05:16:55 PM PDT 24
Finished Jul 30 05:16:56 PM PDT 24
Peak memory 199772 kb
Host smart-ca40a901-e18e-4691-84e3-34a115367eaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219399008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3219399008
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1049678224
Short name T583
Test name
Test status
Simulation time 17100252 ps
CPU time 0.59 seconds
Started Jul 30 05:16:50 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 195088 kb
Host smart-07ff23db-c046-4ca2-906e-8a058c765abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049678224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1049678224
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1465179770
Short name T111
Test name
Test status
Simulation time 45859561 ps
CPU time 1.17 seconds
Started Jul 30 05:16:51 PM PDT 24
Finished Jul 30 05:16:53 PM PDT 24
Peak memory 198824 kb
Host smart-4e72b744-dfaf-4984-b74c-4ac56a8b5699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465179770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1465179770
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1271845243
Short name T570
Test name
Test status
Simulation time 156845900 ps
CPU time 3.26 seconds
Started Jul 30 05:16:53 PM PDT 24
Finished Jul 30 05:16:57 PM PDT 24
Peak memory 200088 kb
Host smart-a92fcf00-4861-4fee-81af-91f0c5447d91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271845243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1271845243
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.193770478
Short name T62
Test name
Test status
Simulation time 682712082 ps
CPU time 1.85 seconds
Started Jul 30 05:16:52 PM PDT 24
Finished Jul 30 05:16:54 PM PDT 24
Peak memory 200236 kb
Host smart-5d469b34-f3d5-4108-8f37-b09745ddd1f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193770478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.193770478
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.166935979
Short name T587
Test name
Test status
Simulation time 607833383 ps
CPU time 5.63 seconds
Started Jul 30 05:16:29 PM PDT 24
Finished Jul 30 05:16:35 PM PDT 24
Peak memory 200220 kb
Host smart-cb4cd720-d3a8-46a3-b43f-cf866093e3a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166935979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.166935979
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4172166947
Short name T97
Test name
Test status
Simulation time 1522894281 ps
CPU time 5.68 seconds
Started Jul 30 05:16:28 PM PDT 24
Finished Jul 30 05:16:34 PM PDT 24
Peak memory 200112 kb
Host smart-13fa7b22-18dd-4484-85f8-ab92de7f5e5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172166947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4172166947
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3035890363
Short name T620
Test name
Test status
Simulation time 506342580 ps
CPU time 0.98 seconds
Started Jul 30 05:16:29 PM PDT 24
Finished Jul 30 05:16:30 PM PDT 24
Peak memory 199596 kb
Host smart-8c246f46-f303-41ba-823f-a16d9cd67dc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035890363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3035890363
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4201045687
Short name T538
Test name
Test status
Simulation time 60330241 ps
CPU time 1.78 seconds
Started Jul 30 05:16:32 PM PDT 24
Finished Jul 30 05:16:33 PM PDT 24
Peak memory 200208 kb
Host smart-0d72d697-eb0f-43d7-835b-14e3b55d3958
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201045687 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.4201045687
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2406309048
Short name T649
Test name
Test status
Simulation time 27546024 ps
CPU time 0.82 seconds
Started Jul 30 05:16:29 PM PDT 24
Finished Jul 30 05:16:30 PM PDT 24
Peak memory 199940 kb
Host smart-f3356670-2c41-4702-865f-5b5afd0515c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406309048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2406309048
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1959982510
Short name T540
Test name
Test status
Simulation time 48442406 ps
CPU time 0.62 seconds
Started Jul 30 05:16:28 PM PDT 24
Finished Jul 30 05:16:29 PM PDT 24
Peak memory 195208 kb
Host smart-a6a1a564-ee00-4dec-a3b5-de3d36f258c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959982510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1959982510
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2438188280
Short name T598
Test name
Test status
Simulation time 20156338 ps
CPU time 1.06 seconds
Started Jul 30 05:16:30 PM PDT 24
Finished Jul 30 05:16:32 PM PDT 24
Peak memory 198584 kb
Host smart-ca3f6d54-a2c2-48e3-9ac7-52d0f2252cd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438188280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2438188280
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.4095337658
Short name T659
Test name
Test status
Simulation time 117360735 ps
CPU time 2.33 seconds
Started Jul 30 05:16:30 PM PDT 24
Finished Jul 30 05:16:33 PM PDT 24
Peak memory 200200 kb
Host smart-a93d3101-2c64-43b7-b8d5-9db4e4826263
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095337658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.4095337658
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.91166446
Short name T563
Test name
Test status
Simulation time 47687751 ps
CPU time 1.71 seconds
Started Jul 30 05:16:28 PM PDT 24
Finished Jul 30 05:16:30 PM PDT 24
Peak memory 200200 kb
Host smart-1798e438-3355-4595-9dd1-77c00403099d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91166446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.91166446
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1296662299
Short name T640
Test name
Test status
Simulation time 49000617 ps
CPU time 0.65 seconds
Started Jul 30 05:17:02 PM PDT 24
Finished Jul 30 05:17:03 PM PDT 24
Peak memory 194836 kb
Host smart-6c20773e-797b-4012-9474-94514515fa00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296662299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1296662299
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3902143049
Short name T548
Test name
Test status
Simulation time 64586205 ps
CPU time 0.62 seconds
Started Jul 30 05:16:52 PM PDT 24
Finished Jul 30 05:16:53 PM PDT 24
Peak memory 195044 kb
Host smart-e0ec18d4-6685-4552-82f1-d0e301d006de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902143049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3902143049
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2381182993
Short name T545
Test name
Test status
Simulation time 16534556 ps
CPU time 0.65 seconds
Started Jul 30 05:17:03 PM PDT 24
Finished Jul 30 05:17:04 PM PDT 24
Peak memory 194924 kb
Host smart-33fdfe41-e4ee-4389-af24-bb9f8efd83ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381182993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2381182993
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1984746299
Short name T589
Test name
Test status
Simulation time 47197095 ps
CPU time 0.64 seconds
Started Jul 30 05:17:03 PM PDT 24
Finished Jul 30 05:17:04 PM PDT 24
Peak memory 194996 kb
Host smart-f1cb2276-1b51-43f4-8a7b-52b12a562184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984746299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1984746299
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1346451705
Short name T577
Test name
Test status
Simulation time 14337328 ps
CPU time 0.59 seconds
Started Jul 30 05:16:55 PM PDT 24
Finished Jul 30 05:16:56 PM PDT 24
Peak memory 194996 kb
Host smart-c00cc535-5a13-4938-b34f-fb4ef5e5a028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346451705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1346451705
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.78593221
Short name T552
Test name
Test status
Simulation time 14363620 ps
CPU time 0.61 seconds
Started Jul 30 05:16:54 PM PDT 24
Finished Jul 30 05:16:54 PM PDT 24
Peak memory 195012 kb
Host smart-2bf3255e-9233-4d21-809d-6c0bae9f7d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78593221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.78593221
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.338375437
Short name T556
Test name
Test status
Simulation time 96529951 ps
CPU time 0.57 seconds
Started Jul 30 05:16:58 PM PDT 24
Finished Jul 30 05:16:59 PM PDT 24
Peak memory 194972 kb
Host smart-94651440-813f-4742-ba4a-985911c2c58e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338375437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.338375437
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1450982717
Short name T539
Test name
Test status
Simulation time 82181145 ps
CPU time 0.57 seconds
Started Jul 30 05:16:57 PM PDT 24
Finished Jul 30 05:16:58 PM PDT 24
Peak memory 194996 kb
Host smart-37b1a835-74ef-4cba-973e-2fc3b3b49564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450982717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1450982717
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2232001819
Short name T564
Test name
Test status
Simulation time 16979619 ps
CPU time 0.63 seconds
Started Jul 30 05:16:55 PM PDT 24
Finished Jul 30 05:16:56 PM PDT 24
Peak memory 195068 kb
Host smart-9a78d5e5-2603-4df5-bd9c-7cb6146940a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232001819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2232001819
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2494826712
Short name T653
Test name
Test status
Simulation time 17605913 ps
CPU time 0.64 seconds
Started Jul 30 05:17:00 PM PDT 24
Finished Jul 30 05:17:01 PM PDT 24
Peak memory 195076 kb
Host smart-08aa0b28-5dd7-4f52-873a-51754c78798b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494826712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2494826712
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4230255955
Short name T595
Test name
Test status
Simulation time 1018368395 ps
CPU time 8.6 seconds
Started Jul 30 05:16:34 PM PDT 24
Finished Jul 30 05:16:42 PM PDT 24
Peak memory 200124 kb
Host smart-ea23eb09-b09f-483e-b444-5e42067fb388
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230255955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4230255955
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1640464174
Short name T627
Test name
Test status
Simulation time 221416468 ps
CPU time 9.58 seconds
Started Jul 30 05:16:36 PM PDT 24
Finished Jul 30 05:16:45 PM PDT 24
Peak memory 200112 kb
Host smart-937ca818-e103-4333-af1d-8da1c9c3c5de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640464174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1640464174
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1204920953
Short name T625
Test name
Test status
Simulation time 91122685 ps
CPU time 0.9 seconds
Started Jul 30 05:16:31 PM PDT 24
Finished Jul 30 05:16:32 PM PDT 24
Peak memory 199532 kb
Host smart-9e216d1c-7b3c-4bb1-b4f7-f83e4bb32815
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204920953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1204920953
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2683053666
Short name T544
Test name
Test status
Simulation time 70310110 ps
CPU time 1.86 seconds
Started Jul 30 05:16:36 PM PDT 24
Finished Jul 30 05:16:38 PM PDT 24
Peak memory 199984 kb
Host smart-6137e83b-7d33-4f5e-8aa2-a3f8d7bf1e64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683053666 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2683053666
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1807930298
Short name T89
Test name
Test status
Simulation time 29849939 ps
CPU time 0.86 seconds
Started Jul 30 05:16:36 PM PDT 24
Finished Jul 30 05:16:37 PM PDT 24
Peak memory 199940 kb
Host smart-5a4e59ff-d687-41e5-a8d8-332125850242
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807930298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1807930298
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.217480537
Short name T580
Test name
Test status
Simulation time 12797438 ps
CPU time 0.61 seconds
Started Jul 30 05:16:30 PM PDT 24
Finished Jul 30 05:16:31 PM PDT 24
Peak memory 195124 kb
Host smart-e53d0149-bdcb-49e3-9151-6901a03584b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217480537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.217480537
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.570342452
Short name T623
Test name
Test status
Simulation time 94966694 ps
CPU time 1.84 seconds
Started Jul 30 05:16:35 PM PDT 24
Finished Jul 30 05:16:37 PM PDT 24
Peak memory 200092 kb
Host smart-98fbc790-3521-4548-ab5f-16521d5be6ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570342452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.570342452
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1657169993
Short name T535
Test name
Test status
Simulation time 423799635 ps
CPU time 2.8 seconds
Started Jul 30 05:16:31 PM PDT 24
Finished Jul 30 05:16:34 PM PDT 24
Peak memory 200032 kb
Host smart-e0bfdbef-83ac-4ea1-b975-42c34ed9d24c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657169993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1657169993
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1668267478
Short name T657
Test name
Test status
Simulation time 11397599 ps
CPU time 0.6 seconds
Started Jul 30 05:16:55 PM PDT 24
Finished Jul 30 05:16:56 PM PDT 24
Peak memory 194980 kb
Host smart-cd697fba-d8d8-4b70-9860-3c6a0ba67b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668267478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1668267478
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3752694279
Short name T581
Test name
Test status
Simulation time 18872614 ps
CPU time 0.58 seconds
Started Jul 30 05:16:58 PM PDT 24
Finished Jul 30 05:16:58 PM PDT 24
Peak memory 195064 kb
Host smart-0d46668f-767f-46aa-b2f3-cb7e810765c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752694279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3752694279
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.264272674
Short name T592
Test name
Test status
Simulation time 14482730 ps
CPU time 0.57 seconds
Started Jul 30 05:16:54 PM PDT 24
Finished Jul 30 05:16:55 PM PDT 24
Peak memory 194972 kb
Host smart-6a4566c9-90ed-4535-8c2a-cf70f40e7c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264272674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.264272674
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.4273422159
Short name T561
Test name
Test status
Simulation time 47991842 ps
CPU time 0.61 seconds
Started Jul 30 05:16:54 PM PDT 24
Finished Jul 30 05:16:55 PM PDT 24
Peak memory 195072 kb
Host smart-4eee5f44-33ac-4602-a2f6-ddafd2876b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273422159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.4273422159
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1284047186
Short name T582
Test name
Test status
Simulation time 44174743 ps
CPU time 0.62 seconds
Started Jul 30 05:16:57 PM PDT 24
Finished Jul 30 05:16:58 PM PDT 24
Peak memory 195084 kb
Host smart-b071a7d8-6098-4693-8f01-45617a8a7a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284047186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1284047186
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2038322426
Short name T628
Test name
Test status
Simulation time 20621837 ps
CPU time 0.63 seconds
Started Jul 30 05:16:57 PM PDT 24
Finished Jul 30 05:16:58 PM PDT 24
Peak memory 195132 kb
Host smart-d5949deb-30e1-4653-9f31-c3f45cc63544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038322426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2038322426
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1946936832
Short name T604
Test name
Test status
Simulation time 11328614 ps
CPU time 0.62 seconds
Started Jul 30 05:16:54 PM PDT 24
Finished Jul 30 05:16:55 PM PDT 24
Peak memory 195020 kb
Host smart-5d3eec7d-709e-462f-bce9-3fad5f4d97ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946936832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1946936832
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2823600063
Short name T553
Test name
Test status
Simulation time 11415514 ps
CPU time 0.6 seconds
Started Jul 30 05:16:55 PM PDT 24
Finished Jul 30 05:16:55 PM PDT 24
Peak memory 194988 kb
Host smart-3fee775a-2a84-4e8e-a6d7-c37552595a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823600063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2823600063
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2243091520
Short name T638
Test name
Test status
Simulation time 48294329 ps
CPU time 0.63 seconds
Started Jul 30 05:16:53 PM PDT 24
Finished Jul 30 05:16:54 PM PDT 24
Peak memory 194988 kb
Host smart-8797f7ed-191e-4c42-904a-d0da63b93ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243091520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2243091520
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.970350374
Short name T647
Test name
Test status
Simulation time 74272523 ps
CPU time 0.56 seconds
Started Jul 30 05:16:52 PM PDT 24
Finished Jul 30 05:16:53 PM PDT 24
Peak memory 195008 kb
Host smart-c6301b6c-f2c6-4bec-9d4c-7751c866c626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970350374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.970350374
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3982117755
Short name T622
Test name
Test status
Simulation time 609107276 ps
CPU time 8.12 seconds
Started Jul 30 05:16:36 PM PDT 24
Finished Jul 30 05:16:44 PM PDT 24
Peak memory 199840 kb
Host smart-650815f7-20c1-4b97-8a7e-e0d84b0e045e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982117755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3982117755
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4014124400
Short name T547
Test name
Test status
Simulation time 115920401 ps
CPU time 5.13 seconds
Started Jul 30 05:16:36 PM PDT 24
Finished Jul 30 05:16:41 PM PDT 24
Peak memory 199192 kb
Host smart-03cfc769-9a25-433e-af15-2790f51718f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014124400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4014124400
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1438770832
Short name T94
Test name
Test status
Simulation time 126987438 ps
CPU time 0.95 seconds
Started Jul 30 05:16:37 PM PDT 24
Finished Jul 30 05:16:38 PM PDT 24
Peak memory 199692 kb
Host smart-32e1d108-3da6-4ed4-b497-6efd27078234
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438770832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1438770832
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.106935555
Short name T555
Test name
Test status
Simulation time 34538421 ps
CPU time 1.16 seconds
Started Jul 30 05:16:38 PM PDT 24
Finished Jul 30 05:16:39 PM PDT 24
Peak memory 200008 kb
Host smart-83b48432-1877-4807-a3b3-b70b9616e1e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106935555 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.106935555
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.107004178
Short name T602
Test name
Test status
Simulation time 99658095 ps
CPU time 0.81 seconds
Started Jul 30 05:16:37 PM PDT 24
Finished Jul 30 05:16:38 PM PDT 24
Peak memory 199884 kb
Host smart-fb8aa70c-0374-432f-aa2b-eba6d0063586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107004178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.107004178
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3190299561
Short name T637
Test name
Test status
Simulation time 17261849 ps
CPU time 0.56 seconds
Started Jul 30 05:16:33 PM PDT 24
Finished Jul 30 05:16:34 PM PDT 24
Peak memory 195104 kb
Host smart-2c2c86e1-da58-436f-bb94-a650b048efa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190299561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3190299561
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1186064026
Short name T575
Test name
Test status
Simulation time 88187520 ps
CPU time 1.86 seconds
Started Jul 30 05:16:36 PM PDT 24
Finished Jul 30 05:16:38 PM PDT 24
Peak memory 200152 kb
Host smart-63e21aaf-6b0b-4f3d-9aa1-441d44213ddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186064026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1186064026
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2832674653
Short name T591
Test name
Test status
Simulation time 699464930 ps
CPU time 4.01 seconds
Started Jul 30 05:16:35 PM PDT 24
Finished Jul 30 05:16:39 PM PDT 24
Peak memory 200068 kb
Host smart-a1784f17-41bf-4704-8ed3-8f645389faf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832674653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2832674653
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4281263689
Short name T546
Test name
Test status
Simulation time 270283442 ps
CPU time 1.71 seconds
Started Jul 30 05:16:35 PM PDT 24
Finished Jul 30 05:16:37 PM PDT 24
Peak memory 200244 kb
Host smart-c19d576f-237f-48bf-a882-f6acfbbde7c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281263689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4281263689
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.698697069
Short name T594
Test name
Test status
Simulation time 50084285 ps
CPU time 0.59 seconds
Started Jul 30 05:16:55 PM PDT 24
Finished Jul 30 05:16:56 PM PDT 24
Peak memory 195016 kb
Host smart-cf648202-2bbc-41c2-9205-8c1828a833f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698697069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.698697069
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.481692142
Short name T643
Test name
Test status
Simulation time 18309410 ps
CPU time 0.61 seconds
Started Jul 30 05:16:56 PM PDT 24
Finished Jul 30 05:16:57 PM PDT 24
Peak memory 195064 kb
Host smart-f76fb6fe-7cba-4bbf-ac1f-401799ed89e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481692142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.481692142
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2499115764
Short name T632
Test name
Test status
Simulation time 23361137 ps
CPU time 0.62 seconds
Started Jul 30 05:16:56 PM PDT 24
Finished Jul 30 05:16:57 PM PDT 24
Peak memory 195028 kb
Host smart-f1f1dc23-0473-4bb8-8713-8feea8745f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499115764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2499115764
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3548982311
Short name T549
Test name
Test status
Simulation time 49946526 ps
CPU time 0.61 seconds
Started Jul 30 05:16:55 PM PDT 24
Finished Jul 30 05:16:55 PM PDT 24
Peak memory 195120 kb
Host smart-c45ee8df-a076-4470-a263-77b3e090ccd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548982311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3548982311
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.91646783
Short name T551
Test name
Test status
Simulation time 14416124 ps
CPU time 0.58 seconds
Started Jul 30 05:16:54 PM PDT 24
Finished Jul 30 05:16:55 PM PDT 24
Peak memory 195092 kb
Host smart-4b26affb-97f3-44e6-929c-85a9045a0b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91646783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.91646783
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1866596290
Short name T609
Test name
Test status
Simulation time 23645570 ps
CPU time 0.63 seconds
Started Jul 30 05:16:53 PM PDT 24
Finished Jul 30 05:16:53 PM PDT 24
Peak memory 195044 kb
Host smart-43c7585d-1b72-4de2-960f-ade1d6dcc8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866596290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1866596290
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3430543071
Short name T576
Test name
Test status
Simulation time 20398253 ps
CPU time 0.65 seconds
Started Jul 30 05:16:54 PM PDT 24
Finished Jul 30 05:16:55 PM PDT 24
Peak memory 195036 kb
Host smart-935cfd6b-81d2-435c-8e6f-3d7c6a6630e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430543071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3430543071
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2403757859
Short name T542
Test name
Test status
Simulation time 39363377 ps
CPU time 0.59 seconds
Started Jul 30 05:16:57 PM PDT 24
Finished Jul 30 05:16:57 PM PDT 24
Peak memory 195016 kb
Host smart-001df159-b0e1-4981-a150-15ad68de38c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403757859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2403757859
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2065246065
Short name T554
Test name
Test status
Simulation time 19299063 ps
CPU time 0.6 seconds
Started Jul 30 05:17:00 PM PDT 24
Finished Jul 30 05:17:01 PM PDT 24
Peak memory 195196 kb
Host smart-23d58d07-ef9b-4a78-9aa5-6b44af120abf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065246065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2065246065
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1270620863
Short name T550
Test name
Test status
Simulation time 44282424 ps
CPU time 0.6 seconds
Started Jul 30 05:16:56 PM PDT 24
Finished Jul 30 05:16:57 PM PDT 24
Peak memory 195036 kb
Host smart-1cfe2c71-e038-4554-8e3d-4b078a31015c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270620863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1270620863
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1565754264
Short name T569
Test name
Test status
Simulation time 42954408 ps
CPU time 1.27 seconds
Started Jul 30 05:16:38 PM PDT 24
Finished Jul 30 05:16:39 PM PDT 24
Peak memory 199988 kb
Host smart-0deac5b4-cbc0-4d59-9ee0-fcac225b267d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565754264 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1565754264
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1055654562
Short name T110
Test name
Test status
Simulation time 14617089 ps
CPU time 0.7 seconds
Started Jul 30 05:16:37 PM PDT 24
Finished Jul 30 05:16:37 PM PDT 24
Peak memory 198540 kb
Host smart-a45a4f64-11ce-4e34-8da0-e133f01a4229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055654562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1055654562
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2979745882
Short name T537
Test name
Test status
Simulation time 21304795 ps
CPU time 0.58 seconds
Started Jul 30 05:16:33 PM PDT 24
Finished Jul 30 05:16:34 PM PDT 24
Peak memory 194972 kb
Host smart-b336e9e7-2f8a-4522-aed7-1cf47f59092e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979745882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2979745882
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2092057004
Short name T567
Test name
Test status
Simulation time 545492132 ps
CPU time 1.77 seconds
Started Jul 30 05:16:36 PM PDT 24
Finished Jul 30 05:16:38 PM PDT 24
Peak memory 199860 kb
Host smart-ab0fed6f-4fe3-4afc-ab7e-c49c6a136e13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092057004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2092057004
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1461482339
Short name T560
Test name
Test status
Simulation time 578473291 ps
CPU time 1.46 seconds
Started Jul 30 05:16:35 PM PDT 24
Finished Jul 30 05:16:37 PM PDT 24
Peak memory 200100 kb
Host smart-97bd4715-0d21-4329-a95d-8ffe11ca694c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461482339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1461482339
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2480804901
Short name T125
Test name
Test status
Simulation time 398609673 ps
CPU time 1.92 seconds
Started Jul 30 05:16:34 PM PDT 24
Finished Jul 30 05:16:36 PM PDT 24
Peak memory 200120 kb
Host smart-11d94f1c-a278-4d64-88a2-c6ab3183db73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480804901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2480804901
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2860472118
Short name T543
Test name
Test status
Simulation time 493776948 ps
CPU time 2.49 seconds
Started Jul 30 05:16:55 PM PDT 24
Finished Jul 30 05:16:58 PM PDT 24
Peak memory 200216 kb
Host smart-c1dd7005-c54b-4e4c-b18b-aac51c99397d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860472118 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2860472118
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1798366164
Short name T99
Test name
Test status
Simulation time 61348831 ps
CPU time 0.92 seconds
Started Jul 30 05:16:40 PM PDT 24
Finished Jul 30 05:16:41 PM PDT 24
Peak memory 199792 kb
Host smart-13b0281b-0802-4659-b706-276554e1782c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798366164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1798366164
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2365977168
Short name T607
Test name
Test status
Simulation time 44383639 ps
CPU time 0.57 seconds
Started Jul 30 05:16:38 PM PDT 24
Finished Jul 30 05:16:39 PM PDT 24
Peak memory 194916 kb
Host smart-f3a4014a-3da0-4c3f-aea1-ac01cd8000c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365977168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2365977168
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.962858758
Short name T112
Test name
Test status
Simulation time 812272474 ps
CPU time 1.91 seconds
Started Jul 30 05:16:47 PM PDT 24
Finished Jul 30 05:16:49 PM PDT 24
Peak memory 199960 kb
Host smart-1002df29-3f81-4b06-abc5-b3e1d217104c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962858758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.962858758
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4047929641
Short name T651
Test name
Test status
Simulation time 196197233 ps
CPU time 1.2 seconds
Started Jul 30 05:16:36 PM PDT 24
Finished Jul 30 05:16:38 PM PDT 24
Peak memory 200000 kb
Host smart-497b6778-6b9f-43f7-abef-99732d29c292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047929641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.4047929641
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1111622345
Short name T123
Test name
Test status
Simulation time 232108400 ps
CPU time 4.02 seconds
Started Jul 30 05:16:40 PM PDT 24
Finished Jul 30 05:16:44 PM PDT 24
Peak memory 200168 kb
Host smart-9c66500a-cea1-4e2c-9fb5-219349624eef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111622345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1111622345
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.916099931
Short name T593
Test name
Test status
Simulation time 164505437 ps
CPU time 1.4 seconds
Started Jul 30 05:16:41 PM PDT 24
Finished Jul 30 05:16:42 PM PDT 24
Peak memory 200184 kb
Host smart-beb68623-d754-4520-bfe6-a1ac91345d26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916099931 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.916099931
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3381776988
Short name T92
Test name
Test status
Simulation time 21248580 ps
CPU time 0.69 seconds
Started Jul 30 05:16:42 PM PDT 24
Finished Jul 30 05:16:43 PM PDT 24
Peak memory 197912 kb
Host smart-aa9bc068-2523-44cd-b78e-15d77bbab3a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381776988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3381776988
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2998491030
Short name T601
Test name
Test status
Simulation time 13857065 ps
CPU time 0.69 seconds
Started Jul 30 05:16:47 PM PDT 24
Finished Jul 30 05:16:47 PM PDT 24
Peak memory 194640 kb
Host smart-d2a21f62-faed-42e2-a65a-d393c511b834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998491030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2998491030
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2251138287
Short name T586
Test name
Test status
Simulation time 226948680 ps
CPU time 1.14 seconds
Started Jul 30 05:16:37 PM PDT 24
Finished Jul 30 05:16:39 PM PDT 24
Peak memory 200100 kb
Host smart-c6c5ee40-913a-4532-886f-cb867f880eb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251138287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2251138287
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.575440421
Short name T558
Test name
Test status
Simulation time 44019747 ps
CPU time 2.26 seconds
Started Jul 30 05:16:38 PM PDT 24
Finished Jul 30 05:16:40 PM PDT 24
Peak memory 200196 kb
Host smart-365de585-b6d6-463c-959f-ad481862ef78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575440421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.575440421
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3091008921
Short name T579
Test name
Test status
Simulation time 282124532 ps
CPU time 4.32 seconds
Started Jul 30 05:16:40 PM PDT 24
Finished Jul 30 05:16:44 PM PDT 24
Peak memory 200136 kb
Host smart-5dfdbf93-a840-4216-821d-046508a9c77e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091008921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3091008921
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4263976183
Short name T648
Test name
Test status
Simulation time 85423008 ps
CPU time 2.46 seconds
Started Jul 30 05:16:51 PM PDT 24
Finished Jul 30 05:16:53 PM PDT 24
Peak memory 200212 kb
Host smart-ef16d3b7-034f-4da3-b19b-3cfc536048df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263976183 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.4263976183
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1705582421
Short name T642
Test name
Test status
Simulation time 20418948 ps
CPU time 0.94 seconds
Started Jul 30 05:16:51 PM PDT 24
Finished Jul 30 05:16:52 PM PDT 24
Peak memory 200000 kb
Host smart-b4ecc399-0022-4700-87d9-daa7760ffad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705582421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1705582421
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1261679953
Short name T612
Test name
Test status
Simulation time 16571284 ps
CPU time 0.57 seconds
Started Jul 30 05:16:37 PM PDT 24
Finished Jul 30 05:16:38 PM PDT 24
Peak memory 194804 kb
Host smart-46d330ae-2e83-49a6-abb9-9f68ac16780a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261679953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1261679953
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2361139133
Short name T119
Test name
Test status
Simulation time 98614582 ps
CPU time 1.77 seconds
Started Jul 30 05:16:43 PM PDT 24
Finished Jul 30 05:16:45 PM PDT 24
Peak memory 200176 kb
Host smart-93a5ca1b-89a9-4705-9d29-74eb2a958a00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361139133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2361139133
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.611647259
Short name T652
Test name
Test status
Simulation time 83672367 ps
CPU time 2.16 seconds
Started Jul 30 05:16:38 PM PDT 24
Finished Jul 30 05:16:41 PM PDT 24
Peak memory 200132 kb
Host smart-41d0f808-5777-4044-a3b9-934022a909a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611647259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.611647259
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1837654388
Short name T129
Test name
Test status
Simulation time 232297441 ps
CPU time 2.89 seconds
Started Jul 30 05:16:44 PM PDT 24
Finished Jul 30 05:16:47 PM PDT 24
Peak memory 200204 kb
Host smart-ad4dbec5-5f5f-4900-a5ee-48e938962bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837654388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1837654388
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1852862029
Short name T635
Test name
Test status
Simulation time 42871591 ps
CPU time 1.28 seconds
Started Jul 30 05:16:51 PM PDT 24
Finished Jul 30 05:16:52 PM PDT 24
Peak memory 199996 kb
Host smart-537572cd-d04e-4547-8c17-e542b7c3ba49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852862029 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1852862029
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.727527765
Short name T599
Test name
Test status
Simulation time 28297634 ps
CPU time 0.9 seconds
Started Jul 30 05:16:47 PM PDT 24
Finished Jul 30 05:16:48 PM PDT 24
Peak memory 199660 kb
Host smart-8340f8eb-ceff-475c-8028-6b7b79e88453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727527765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.727527765
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1999016
Short name T536
Test name
Test status
Simulation time 23282905 ps
CPU time 0.62 seconds
Started Jul 30 05:16:51 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 195096 kb
Host smart-d9a45b65-8266-4d07-abac-34c1326eae1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1999016
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2727501604
Short name T113
Test name
Test status
Simulation time 162013271 ps
CPU time 2 seconds
Started Jul 30 05:16:39 PM PDT 24
Finished Jul 30 05:16:42 PM PDT 24
Peak memory 200096 kb
Host smart-baf8dd1d-61c1-49b5-ab60-e9753d8491aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727501604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2727501604
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3802987407
Short name T533
Test name
Test status
Simulation time 70468702 ps
CPU time 3.69 seconds
Started Jul 30 05:16:38 PM PDT 24
Finished Jul 30 05:16:42 PM PDT 24
Peak memory 200140 kb
Host smart-5d49dbe7-c912-4243-845a-893b590d2525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802987407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3802987407
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.944173502
Short name T341
Test name
Test status
Simulation time 15889999 ps
CPU time 0.62 seconds
Started Jul 30 05:17:03 PM PDT 24
Finished Jul 30 05:17:03 PM PDT 24
Peak memory 196680 kb
Host smart-45fcfe27-41e2-48f1-baaf-1e8bf6bd0998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944173502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.944173502
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3748970071
Short name T487
Test name
Test status
Simulation time 1480501520 ps
CPU time 74.02 seconds
Started Jul 30 05:17:02 PM PDT 24
Finished Jul 30 05:18:16 PM PDT 24
Peak memory 199700 kb
Host smart-fd612560-0fdc-4418-b36a-b2e83df15ab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748970071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3748970071
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3690726374
Short name T336
Test name
Test status
Simulation time 481255955 ps
CPU time 13.14 seconds
Started Jul 30 05:16:56 PM PDT 24
Finished Jul 30 05:17:09 PM PDT 24
Peak memory 199896 kb
Host smart-8f2f0822-bc88-4219-acc5-a6a3a48737fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690726374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3690726374
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1191907072
Short name T176
Test name
Test status
Simulation time 5846389011 ps
CPU time 997.88 seconds
Started Jul 30 05:16:54 PM PDT 24
Finished Jul 30 05:33:32 PM PDT 24
Peak memory 717508 kb
Host smart-f2c003ae-bf79-4764-8491-f81aacbdf738
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191907072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1191907072
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.14798648
Short name T57
Test name
Test status
Simulation time 3706430695 ps
CPU time 17.5 seconds
Started Jul 30 05:16:59 PM PDT 24
Finished Jul 30 05:17:17 PM PDT 24
Peak memory 199936 kb
Host smart-70f862c3-e2fb-4e60-8d26-a0becab7f416
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14798648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.14798648
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1825581996
Short name T435
Test name
Test status
Simulation time 41848371971 ps
CPU time 141.51 seconds
Started Jul 30 05:16:55 PM PDT 24
Finished Jul 30 05:19:17 PM PDT 24
Peak memory 208248 kb
Host smart-89d6a1e8-ca37-4313-8f9d-596d5e1f5e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825581996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1825581996
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2600993144
Short name T369
Test name
Test status
Simulation time 97270576 ps
CPU time 1.86 seconds
Started Jul 30 05:16:56 PM PDT 24
Finished Jul 30 05:16:58 PM PDT 24
Peak memory 199940 kb
Host smart-95a9a432-5503-4b83-a6f8-40498ff549c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600993144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2600993144
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2649073734
Short name T252
Test name
Test status
Simulation time 55282600060 ps
CPU time 1809.81 seconds
Started Jul 30 05:17:05 PM PDT 24
Finished Jul 30 05:47:15 PM PDT 24
Peak memory 779256 kb
Host smart-474fe969-0a9f-4be4-9f47-555bcaa05c9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649073734 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2649073734
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.1262274817
Short name T438
Test name
Test status
Simulation time 3999649516 ps
CPU time 48.36 seconds
Started Jul 30 05:17:00 PM PDT 24
Finished Jul 30 05:17:48 PM PDT 24
Peak memory 199984 kb
Host smart-977f6220-2951-40cf-9117-04d4502d6ba1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1262274817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.1262274817
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1917646417
Short name T258
Test name
Test status
Simulation time 17245577071 ps
CPU time 66.5 seconds
Started Jul 30 05:17:02 PM PDT 24
Finished Jul 30 05:18:09 PM PDT 24
Peak memory 199960 kb
Host smart-842bb393-f017-4fd4-871c-afd47f05f55c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1917646417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1917646417
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1536775204
Short name T154
Test name
Test status
Simulation time 96352006859 ps
CPU time 121.08 seconds
Started Jul 30 05:17:02 PM PDT 24
Finished Jul 30 05:19:04 PM PDT 24
Peak memory 200008 kb
Host smart-208ce676-a3a3-46fa-b3bf-54e98befe07a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1536775204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1536775204
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3322512895
Short name T307
Test name
Test status
Simulation time 408258639729 ps
CPU time 2389.74 seconds
Started Jul 30 05:17:01 PM PDT 24
Finished Jul 30 05:56:51 PM PDT 24
Peak memory 216200 kb
Host smart-0f0e64ba-0fbb-4fe1-ad18-7c7a03d2d090
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3322512895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3322512895
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.493427008
Short name T406
Test name
Test status
Simulation time 1726091560440 ps
CPU time 2673.28 seconds
Started Jul 30 05:17:05 PM PDT 24
Finished Jul 30 06:01:38 PM PDT 24
Peak memory 215348 kb
Host smart-6e336057-0166-4be8-86b3-e9a3f4b2ad9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=493427008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.493427008
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3358874955
Short name T524
Test name
Test status
Simulation time 1792165801 ps
CPU time 92.35 seconds
Started Jul 30 05:16:59 PM PDT 24
Finished Jul 30 05:18:32 PM PDT 24
Peak memory 199876 kb
Host smart-096e0a82-d6f8-42cd-a728-ccaca12da644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358874955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3358874955
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3176583945
Short name T503
Test name
Test status
Simulation time 32063011 ps
CPU time 0.62 seconds
Started Jul 30 05:17:06 PM PDT 24
Finished Jul 30 05:17:06 PM PDT 24
Peak memory 195932 kb
Host smart-473a5829-9f6a-43f9-8631-225e68c31f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176583945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3176583945
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1525637553
Short name T226
Test name
Test status
Simulation time 3852225445 ps
CPU time 115.67 seconds
Started Jul 30 05:17:00 PM PDT 24
Finished Jul 30 05:18:56 PM PDT 24
Peak memory 199944 kb
Host smart-3d6ab83e-2c64-4357-ac37-bda674530ae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525637553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1525637553
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1308554136
Short name T350
Test name
Test status
Simulation time 3769548888 ps
CPU time 65.76 seconds
Started Jul 30 05:16:58 PM PDT 24
Finished Jul 30 05:18:04 PM PDT 24
Peak memory 200052 kb
Host smart-26b8bfc1-58cc-4dea-8cac-78d55c6cc8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308554136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1308554136
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.193304628
Short name T431
Test name
Test status
Simulation time 2390083017 ps
CPU time 559.12 seconds
Started Jul 30 05:17:00 PM PDT 24
Finished Jul 30 05:26:20 PM PDT 24
Peak memory 730680 kb
Host smart-68e24c42-1122-4099-aebe-d18ef06203bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193304628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.193304628
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2125511415
Short name T253
Test name
Test status
Simulation time 94681653905 ps
CPU time 88.04 seconds
Started Jul 30 05:16:59 PM PDT 24
Finished Jul 30 05:18:27 PM PDT 24
Peak memory 199976 kb
Host smart-26e88e34-c104-4297-95da-0600e3f2ea2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125511415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2125511415
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3014833119
Short name T35
Test name
Test status
Simulation time 1080297040 ps
CPU time 14.89 seconds
Started Jul 30 05:17:00 PM PDT 24
Finished Jul 30 05:17:15 PM PDT 24
Peak memory 199828 kb
Host smart-06d0994a-9304-468c-8fef-94e05f660569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014833119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3014833119
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.216293852
Short name T48
Test name
Test status
Simulation time 55972479 ps
CPU time 0.86 seconds
Started Jul 30 05:17:05 PM PDT 24
Finished Jul 30 05:17:06 PM PDT 24
Peak memory 218600 kb
Host smart-559549fa-22e1-42d6-a947-a9d42cad764d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216293852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.216293852
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1129389030
Short name T456
Test name
Test status
Simulation time 225541931 ps
CPU time 10.45 seconds
Started Jul 30 05:17:02 PM PDT 24
Finished Jul 30 05:17:12 PM PDT 24
Peak memory 199856 kb
Host smart-e9fdfe35-91cd-405c-9a5d-99601fcc8e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129389030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1129389030
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2758074169
Short name T450
Test name
Test status
Simulation time 129364889730 ps
CPU time 3061.89 seconds
Started Jul 30 05:16:57 PM PDT 24
Finished Jul 30 06:08:00 PM PDT 24
Peak memory 804224 kb
Host smart-1750e1d9-868e-4f95-8f43-188ff2ad3a9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758074169 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2758074169
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.115971240
Short name T31
Test name
Test status
Simulation time 40942746693 ps
CPU time 3825.97 seconds
Started Jul 30 05:17:04 PM PDT 24
Finished Jul 30 06:20:50 PM PDT 24
Peak memory 812436 kb
Host smart-4a15135b-4102-431c-9bc0-5944d4e15df1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115971240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.115971240
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1886774643
Short name T256
Test name
Test status
Simulation time 3416029979 ps
CPU time 43.53 seconds
Started Jul 30 05:17:01 PM PDT 24
Finished Jul 30 05:17:44 PM PDT 24
Peak memory 199996 kb
Host smart-072bae69-861f-4606-a0d8-1233bf89d03f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1886774643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1886774643
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2825250178
Short name T437
Test name
Test status
Simulation time 2313272065 ps
CPU time 82.47 seconds
Started Jul 30 05:16:58 PM PDT 24
Finished Jul 30 05:18:20 PM PDT 24
Peak memory 200032 kb
Host smart-179a49b4-53f5-4caf-ab00-1702fe225f75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2825250178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2825250178
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.4223706144
Short name T268
Test name
Test status
Simulation time 10123909484 ps
CPU time 125.47 seconds
Started Jul 30 05:17:02 PM PDT 24
Finished Jul 30 05:19:07 PM PDT 24
Peak memory 200020 kb
Host smart-7a15d64c-36f9-4e27-bb79-3cc7d969447a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4223706144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.4223706144
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1286260208
Short name T494
Test name
Test status
Simulation time 45529437107 ps
CPU time 594.29 seconds
Started Jul 30 05:17:01 PM PDT 24
Finished Jul 30 05:26:55 PM PDT 24
Peak memory 199952 kb
Host smart-91575365-65c3-48ee-bc49-9d02d694e933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1286260208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1286260208
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2811292735
Short name T417
Test name
Test status
Simulation time 41163320132 ps
CPU time 2467.75 seconds
Started Jul 30 05:17:02 PM PDT 24
Finished Jul 30 05:58:10 PM PDT 24
Peak memory 215572 kb
Host smart-ad04e667-75ef-4ac1-8a52-86a159ef3531
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2811292735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2811292735
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2586822933
Short name T324
Test name
Test status
Simulation time 1802763040054 ps
CPU time 2433.96 seconds
Started Jul 30 05:17:00 PM PDT 24
Finished Jul 30 05:57:34 PM PDT 24
Peak memory 216388 kb
Host smart-e68ddb3f-879f-41c4-a9c7-6d0ca9572f1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2586822933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2586822933
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.483867319
Short name T27
Test name
Test status
Simulation time 868002032 ps
CPU time 30.36 seconds
Started Jul 30 05:17:02 PM PDT 24
Finished Jul 30 05:17:32 PM PDT 24
Peak memory 199936 kb
Host smart-374471df-dfb6-4522-ac98-f5f20b06beab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483867319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.483867319
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3009082401
Short name T288
Test name
Test status
Simulation time 27068550 ps
CPU time 0.57 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 05:17:26 PM PDT 24
Peak memory 194932 kb
Host smart-0195a4f0-1c7f-4f75-b475-79a3d0b3cce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009082401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3009082401
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1400592298
Short name T396
Test name
Test status
Simulation time 2302776926 ps
CPU time 97.04 seconds
Started Jul 30 05:17:28 PM PDT 24
Finished Jul 30 05:19:05 PM PDT 24
Peak memory 200012 kb
Host smart-7d5e9bfa-e2e5-4bfc-b81f-85f47b80b025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400592298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1400592298
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3653422843
Short name T26
Test name
Test status
Simulation time 1280841467 ps
CPU time 23.76 seconds
Started Jul 30 05:17:27 PM PDT 24
Finished Jul 30 05:17:51 PM PDT 24
Peak memory 199892 kb
Host smart-e8a21571-8ab7-4c8d-bc22-79d32a5e66e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653422843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3653422843
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2861202163
Short name T482
Test name
Test status
Simulation time 469855866 ps
CPU time 64.06 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:18:33 PM PDT 24
Peak memory 331060 kb
Host smart-75a4539f-cdd7-4ed8-b6fc-b4e3bccccc00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861202163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2861202163
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.479692495
Short name T42
Test name
Test status
Simulation time 5731647573 ps
CPU time 17.97 seconds
Started Jul 30 05:17:26 PM PDT 24
Finished Jul 30 05:17:44 PM PDT 24
Peak memory 199944 kb
Host smart-42d1ee6f-d4d1-41ce-8d79-31890e55e86b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479692495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.479692495
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1314328694
Short name T73
Test name
Test status
Simulation time 18419643760 ps
CPU time 162.11 seconds
Started Jul 30 05:17:27 PM PDT 24
Finished Jul 30 05:20:09 PM PDT 24
Peak memory 216364 kb
Host smart-57b95212-07df-47e5-b512-4e53056e0c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314328694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1314328694
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1532736701
Short name T326
Test name
Test status
Simulation time 123106337 ps
CPU time 3.13 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:17:27 PM PDT 24
Peak memory 199836 kb
Host smart-d48dd18d-07a6-4545-bc9e-5d642c116963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532736701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1532736701
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2884983371
Short name T345
Test name
Test status
Simulation time 22609163328 ps
CPU time 1939.98 seconds
Started Jul 30 05:17:23 PM PDT 24
Finished Jul 30 05:49:44 PM PDT 24
Peak memory 736936 kb
Host smart-a809e6d0-94f2-40ea-9a00-27f2a2b5a979
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884983371 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2884983371
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3785878940
Short name T468
Test name
Test status
Simulation time 13129954486 ps
CPU time 37.98 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 05:18:03 PM PDT 24
Peak memory 199992 kb
Host smart-a59d9df5-73d1-41d2-a0f4-8272136fbc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785878940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3785878940
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2530078769
Short name T300
Test name
Test status
Simulation time 12490428 ps
CPU time 0.68 seconds
Started Jul 30 05:17:27 PM PDT 24
Finished Jul 30 05:17:28 PM PDT 24
Peak memory 194936 kb
Host smart-7802e286-3676-4040-8e08-3c84a0f19da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530078769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2530078769
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3769499856
Short name T315
Test name
Test status
Simulation time 883124543 ps
CPU time 51.59 seconds
Started Jul 30 05:17:22 PM PDT 24
Finished Jul 30 05:18:14 PM PDT 24
Peak memory 199940 kb
Host smart-35ea8fee-8cc1-40d1-b8c5-cd8ce328438d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769499856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3769499856
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2434613068
Short name T135
Test name
Test status
Simulation time 1212036207 ps
CPU time 65.89 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 05:18:31 PM PDT 24
Peak memory 199900 kb
Host smart-09f2de3e-648d-4734-8aca-aae0844b49fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434613068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2434613068
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3531474120
Short name T510
Test name
Test status
Simulation time 2009955830 ps
CPU time 377.98 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 05:23:43 PM PDT 24
Peak memory 644396 kb
Host smart-f44ab8d8-3d05-4f9b-8a5f-41f62d3d90f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531474120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3531474120
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3611256168
Short name T179
Test name
Test status
Simulation time 49731725118 ps
CPU time 193.24 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:20:38 PM PDT 24
Peak memory 199988 kb
Host smart-b2b2168c-6eef-433d-8078-6fe93ca9d649
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611256168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3611256168
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.4145443966
Short name T356
Test name
Test status
Simulation time 13567928929 ps
CPU time 123.9 seconds
Started Jul 30 05:17:22 PM PDT 24
Finished Jul 30 05:19:26 PM PDT 24
Peak memory 199940 kb
Host smart-e6880429-8bc2-40f0-a53a-0cdd770505ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145443966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.4145443966
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1068271829
Short name T140
Test name
Test status
Simulation time 504939468 ps
CPU time 8.54 seconds
Started Jul 30 05:17:23 PM PDT 24
Finished Jul 30 05:17:32 PM PDT 24
Peak memory 199840 kb
Host smart-6ea4b3c7-a2ec-491e-9986-d862b7758e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068271829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1068271829
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1411327566
Short name T121
Test name
Test status
Simulation time 1483077371 ps
CPU time 60.87 seconds
Started Jul 30 05:17:23 PM PDT 24
Finished Jul 30 05:18:24 PM PDT 24
Peak memory 199844 kb
Host smart-d80297c6-2e22-42d7-95ba-5b38e974c57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411327566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1411327566
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2843651141
Short name T314
Test name
Test status
Simulation time 4250718775 ps
CPU time 57.81 seconds
Started Jul 30 05:17:26 PM PDT 24
Finished Jul 30 05:18:24 PM PDT 24
Peak memory 200208 kb
Host smart-8850f020-1cbc-4a59-a566-97b8a88f005d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843651141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2843651141
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1161070524
Short name T483
Test name
Test status
Simulation time 20494887200 ps
CPU time 31.99 seconds
Started Jul 30 05:17:23 PM PDT 24
Finished Jul 30 05:17:55 PM PDT 24
Peak memory 208168 kb
Host smart-8bc2124b-4b20-4b02-b384-2636b9e22d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161070524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1161070524
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1371860704
Short name T459
Test name
Test status
Simulation time 4332948328 ps
CPU time 417.66 seconds
Started Jul 30 05:17:26 PM PDT 24
Finished Jul 30 05:24:24 PM PDT 24
Peak memory 682964 kb
Host smart-d3992da2-c3f4-4b84-918e-670c86662a57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1371860704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1371860704
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1737823707
Short name T287
Test name
Test status
Simulation time 10665659451 ps
CPU time 221.7 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:21:06 PM PDT 24
Peak memory 200084 kb
Host smart-6841d90b-5d33-4423-b4ad-240ba22d9411
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737823707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1737823707
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.594411880
Short name T238
Test name
Test status
Simulation time 19801109880 ps
CPU time 84.12 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:18:48 PM PDT 24
Peak memory 199996 kb
Host smart-47b59c75-ecb9-4bf8-a743-95e30ae57da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594411880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.594411880
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1585499014
Short name T250
Test name
Test status
Simulation time 49208310 ps
CPU time 2.13 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 05:17:27 PM PDT 24
Peak memory 199908 kb
Host smart-5d7ef28d-eb66-4714-9054-17706f8cfabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585499014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1585499014
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1144917135
Short name T147
Test name
Test status
Simulation time 35867010448 ps
CPU time 920.58 seconds
Started Jul 30 05:17:28 PM PDT 24
Finished Jul 30 05:32:49 PM PDT 24
Peak memory 200024 kb
Host smart-ed38870f-55d1-457f-8d78-a9e3569de8b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144917135 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1144917135
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1910232038
Short name T337
Test name
Test status
Simulation time 4599383039 ps
CPU time 66.37 seconds
Started Jul 30 05:17:28 PM PDT 24
Finished Jul 30 05:18:35 PM PDT 24
Peak memory 200040 kb
Host smart-45db5607-1ebb-484b-ba6c-43a0831e0217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910232038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1910232038
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.971236973
Short name T519
Test name
Test status
Simulation time 15673282 ps
CPU time 0.62 seconds
Started Jul 30 05:17:34 PM PDT 24
Finished Jul 30 05:17:34 PM PDT 24
Peak memory 196020 kb
Host smart-170956c2-8400-4c3d-8e5b-abd032594a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971236973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.971236973
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3927006231
Short name T527
Test name
Test status
Simulation time 4442469103 ps
CPU time 69.69 seconds
Started Jul 30 05:17:30 PM PDT 24
Finished Jul 30 05:18:40 PM PDT 24
Peak memory 200040 kb
Host smart-7d3158bf-3558-4dde-bcdb-1a7a1e212f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927006231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3927006231
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.633259887
Short name T255
Test name
Test status
Simulation time 5414233167 ps
CPU time 58.89 seconds
Started Jul 30 05:17:28 PM PDT 24
Finished Jul 30 05:18:27 PM PDT 24
Peak memory 208244 kb
Host smart-799c4b36-6f01-46e7-9456-13945c72fb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633259887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.633259887
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1036710437
Short name T180
Test name
Test status
Simulation time 5912702452 ps
CPU time 1048.89 seconds
Started Jul 30 05:17:30 PM PDT 24
Finished Jul 30 05:34:59 PM PDT 24
Peak memory 747888 kb
Host smart-e079c1a5-7ef1-4e7c-a7d1-5b8fb302f2bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1036710437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1036710437
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2053007804
Short name T195
Test name
Test status
Simulation time 8727367997 ps
CPU time 24.83 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:17:54 PM PDT 24
Peak memory 199972 kb
Host smart-3e9c2d86-1a50-4d55-a531-449a0bafef8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053007804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2053007804
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1870293526
Short name T441
Test name
Test status
Simulation time 671994557 ps
CPU time 37.51 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:18:07 PM PDT 24
Peak memory 199872 kb
Host smart-9ff1eb2f-87c4-4a6f-8565-ded06eed188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870293526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1870293526
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.488730785
Short name T461
Test name
Test status
Simulation time 3000835212 ps
CPU time 12.21 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:17:41 PM PDT 24
Peak memory 199976 kb
Host smart-27f65188-b1c4-4394-8fe3-bf341b2f407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488730785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.488730785
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2051251400
Short name T76
Test name
Test status
Simulation time 400250449011 ps
CPU time 2102.4 seconds
Started Jul 30 05:17:31 PM PDT 24
Finished Jul 30 05:52:34 PM PDT 24
Peak memory 692580 kb
Host smart-e34c1b06-fd5d-4536-a20e-f8f6f0dc7857
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051251400 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2051251400
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3936594363
Short name T189
Test name
Test status
Simulation time 23943730256 ps
CPU time 99.41 seconds
Started Jul 30 05:17:27 PM PDT 24
Finished Jul 30 05:19:06 PM PDT 24
Peak memory 200032 kb
Host smart-f6a43e5b-6be9-4be7-bc50-e24eaab5bbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936594363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3936594363
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2096257084
Short name T313
Test name
Test status
Simulation time 20205525 ps
CPU time 0.64 seconds
Started Jul 30 05:17:35 PM PDT 24
Finished Jul 30 05:17:36 PM PDT 24
Peak memory 196016 kb
Host smart-937899ad-2707-4383-ae89-f84dc1898648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096257084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2096257084
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3573473181
Short name T196
Test name
Test status
Simulation time 2245843530 ps
CPU time 29.26 seconds
Started Jul 30 05:17:33 PM PDT 24
Finished Jul 30 05:18:02 PM PDT 24
Peak memory 199984 kb
Host smart-205fba15-e2ce-4220-b400-b822b6bd4735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573473181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3573473181
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2342714800
Short name T514
Test name
Test status
Simulation time 1768306975 ps
CPU time 24.13 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:17:53 PM PDT 24
Peak memory 199864 kb
Host smart-e93350f7-737d-4cbe-bbd5-e8d52df7c5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342714800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2342714800
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2407228754
Short name T365
Test name
Test status
Simulation time 3358414977 ps
CPU time 301.16 seconds
Started Jul 30 05:17:31 PM PDT 24
Finished Jul 30 05:22:32 PM PDT 24
Peak memory 674216 kb
Host smart-a8077529-4837-46fb-a067-84bb45e4ddc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407228754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2407228754
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1880806829
Short name T153
Test name
Test status
Simulation time 168648443 ps
CPU time 9.61 seconds
Started Jul 30 05:17:34 PM PDT 24
Finished Jul 30 05:17:44 PM PDT 24
Peak memory 199940 kb
Host smart-1860b213-124f-4aeb-9faf-e575c8f3db87
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880806829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1880806829
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.456021243
Short name T233
Test name
Test status
Simulation time 2567307338 ps
CPU time 35.5 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:18:04 PM PDT 24
Peak memory 200048 kb
Host smart-2c069cad-967e-4432-90f0-4597b21d4fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456021243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.456021243
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.556304609
Short name T374
Test name
Test status
Simulation time 1772238814 ps
CPU time 10.53 seconds
Started Jul 30 05:17:33 PM PDT 24
Finished Jul 30 05:17:44 PM PDT 24
Peak memory 199992 kb
Host smart-9a0d0364-1801-4f4f-be9c-d1e277745318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556304609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.556304609
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2266399088
Short name T267
Test name
Test status
Simulation time 267106717208 ps
CPU time 745.13 seconds
Started Jul 30 05:17:31 PM PDT 24
Finished Jul 30 05:29:56 PM PDT 24
Peak memory 254764 kb
Host smart-37b8f4a1-a7ce-4b2d-96ae-e4b82d54302b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266399088 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2266399088
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4079037523
Short name T465
Test name
Test status
Simulation time 7957749416 ps
CPU time 97.09 seconds
Started Jul 30 05:17:28 PM PDT 24
Finished Jul 30 05:19:06 PM PDT 24
Peak memory 200028 kb
Host smart-74ecb23d-702a-4b88-b172-73b31286c6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079037523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4079037523
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.938819795
Short name T177
Test name
Test status
Simulation time 13655560 ps
CPU time 0.59 seconds
Started Jul 30 05:17:28 PM PDT 24
Finished Jul 30 05:17:28 PM PDT 24
Peak memory 195932 kb
Host smart-558174cb-6b6f-44cb-b249-72b36378dc96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938819795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.938819795
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.4146091798
Short name T241
Test name
Test status
Simulation time 1231607648 ps
CPU time 69.49 seconds
Started Jul 30 05:17:34 PM PDT 24
Finished Jul 30 05:18:44 PM PDT 24
Peak memory 199952 kb
Host smart-e07ec8b3-ad37-4305-a0ca-e4e0d859e360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146091798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.4146091798
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1509304058
Short name T526
Test name
Test status
Simulation time 776764652 ps
CPU time 41.23 seconds
Started Jul 30 05:17:27 PM PDT 24
Finished Jul 30 05:18:08 PM PDT 24
Peak memory 199880 kb
Host smart-d3613411-bbb1-4622-860f-ca55e6dbfadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509304058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1509304058
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2206890061
Short name T467
Test name
Test status
Simulation time 4259448890 ps
CPU time 931.27 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:33:01 PM PDT 24
Peak memory 730488 kb
Host smart-8d4d1448-5cef-45d1-a555-c58b00468b85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206890061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2206890061
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1564808576
Short name T228
Test name
Test status
Simulation time 21905356839 ps
CPU time 89.06 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:18:58 PM PDT 24
Peak memory 199960 kb
Host smart-3fd1cbca-cfec-40e4-8a77-543ddf6c0f38
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564808576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1564808576
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.887134444
Short name T70
Test name
Test status
Simulation time 44078245244 ps
CPU time 140.15 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:19:50 PM PDT 24
Peak memory 208268 kb
Host smart-f1e7efb1-8a98-4702-b7af-19df925c38c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887134444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.887134444
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.280579650
Short name T82
Test name
Test status
Simulation time 250688134 ps
CPU time 1.21 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:17:31 PM PDT 24
Peak memory 199776 kb
Host smart-1f276c11-fcfc-425b-8c1e-9dee44da73dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280579650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.280579650
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1540159684
Short name T74
Test name
Test status
Simulation time 38046676391 ps
CPU time 499.33 seconds
Started Jul 30 05:17:28 PM PDT 24
Finished Jul 30 05:25:47 PM PDT 24
Peak memory 199972 kb
Host smart-9138fba8-8195-4324-a8d0-d8c36927692d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540159684 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1540159684
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.575790274
Short name T318
Test name
Test status
Simulation time 3177792617 ps
CPU time 56.21 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:18:25 PM PDT 24
Peak memory 200032 kb
Host smart-415dba2c-a28f-4ed4-ac24-791ac37f33b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575790274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.575790274
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2904252471
Short name T272
Test name
Test status
Simulation time 14125817 ps
CPU time 0.58 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:17:30 PM PDT 24
Peak memory 196628 kb
Host smart-4c5707b5-8a63-4967-be27-18cc8e592631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904252471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2904252471
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1808249647
Short name T273
Test name
Test status
Simulation time 2497513132 ps
CPU time 66.47 seconds
Started Jul 30 05:17:28 PM PDT 24
Finished Jul 30 05:18:34 PM PDT 24
Peak memory 200044 kb
Host smart-fd814873-e82a-450f-b5e6-44c7ba5bedff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808249647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1808249647
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2069396537
Short name T146
Test name
Test status
Simulation time 2828509698 ps
CPU time 25.4 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:17:55 PM PDT 24
Peak memory 200004 kb
Host smart-2133a234-1224-4038-bcec-31867dbdd662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069396537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2069396537
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4204553902
Short name T158
Test name
Test status
Simulation time 3273258996 ps
CPU time 683.66 seconds
Started Jul 30 05:17:29 PM PDT 24
Finished Jul 30 05:28:53 PM PDT 24
Peak memory 715280 kb
Host smart-5047a694-7cef-4ba3-8282-2d9eb211eede
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204553902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4204553902
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3923308951
Short name T38
Test name
Test status
Simulation time 24297928841 ps
CPU time 208.24 seconds
Started Jul 30 05:17:32 PM PDT 24
Finished Jul 30 05:21:00 PM PDT 24
Peak memory 199984 kb
Host smart-c2543681-94ca-489a-9438-1d92955249c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923308951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3923308951
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3355535704
Short name T58
Test name
Test status
Simulation time 11332739554 ps
CPU time 150.68 seconds
Started Jul 30 05:17:31 PM PDT 24
Finished Jul 30 05:20:02 PM PDT 24
Peak memory 200152 kb
Host smart-f7cc5d39-7ade-42fd-b8bc-2d780f740a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355535704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3355535704
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.420142029
Short name T513
Test name
Test status
Simulation time 173185744 ps
CPU time 2.43 seconds
Started Jul 30 05:17:31 PM PDT 24
Finished Jul 30 05:17:34 PM PDT 24
Peak memory 199876 kb
Host smart-dffba399-32cb-405c-9bfe-631ae9b593f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420142029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.420142029
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1101239561
Short name T78
Test name
Test status
Simulation time 99137672811 ps
CPU time 2896.79 seconds
Started Jul 30 05:17:30 PM PDT 24
Finished Jul 30 06:05:47 PM PDT 24
Peak memory 749560 kb
Host smart-89265574-c51c-46bc-a5ad-bd779f2d8a78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101239561 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1101239561
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.4047034190
Short name T386
Test name
Test status
Simulation time 58303826167 ps
CPU time 77.9 seconds
Started Jul 30 05:17:28 PM PDT 24
Finished Jul 30 05:18:46 PM PDT 24
Peak memory 199960 kb
Host smart-eecf7d34-7b9d-4255-b01d-174998a0fa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047034190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.4047034190
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.4167448973
Short name T101
Test name
Test status
Simulation time 34773192 ps
CPU time 0.61 seconds
Started Jul 30 05:17:38 PM PDT 24
Finished Jul 30 05:17:39 PM PDT 24
Peak memory 195948 kb
Host smart-2753de52-ea27-45fc-94dc-84a7e6daf9f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167448973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4167448973
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2187296085
Short name T413
Test name
Test status
Simulation time 743046910 ps
CPU time 21.51 seconds
Started Jul 30 05:17:36 PM PDT 24
Finished Jul 30 05:17:57 PM PDT 24
Peak memory 199868 kb
Host smart-f7befd31-da2f-4bf1-9337-0d0f79ab5649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187296085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2187296085
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2809835037
Short name T269
Test name
Test status
Simulation time 3231778257 ps
CPU time 38.52 seconds
Started Jul 30 05:17:32 PM PDT 24
Finished Jul 30 05:18:11 PM PDT 24
Peak memory 200020 kb
Host smart-2bb5891a-9cc6-4403-8513-30debd39bd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809835037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2809835037
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1811582163
Short name T171
Test name
Test status
Simulation time 12614271883 ps
CPU time 600.57 seconds
Started Jul 30 05:17:37 PM PDT 24
Finished Jul 30 05:27:38 PM PDT 24
Peak memory 701572 kb
Host smart-1d0e8f07-c773-499e-9104-ae1715e9ac1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811582163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1811582163
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2077424489
Short name T274
Test name
Test status
Simulation time 4229774020 ps
CPU time 111.27 seconds
Started Jul 30 05:17:33 PM PDT 24
Finished Jul 30 05:19:24 PM PDT 24
Peak memory 199936 kb
Host smart-24de41a8-0461-42e0-97c4-7b2880497e52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077424489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2077424489
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.345199768
Short name T280
Test name
Test status
Simulation time 5690835043 ps
CPU time 27.38 seconds
Started Jul 30 05:17:33 PM PDT 24
Finished Jul 30 05:18:01 PM PDT 24
Peak memory 200056 kb
Host smart-0d658222-cb78-4df2-8165-e4d3f889638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345199768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.345199768
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.130692905
Short name T192
Test name
Test status
Simulation time 1097118287 ps
CPU time 13.7 seconds
Started Jul 30 05:17:34 PM PDT 24
Finished Jul 30 05:17:48 PM PDT 24
Peak memory 199880 kb
Host smart-57f38842-0786-4b4a-b20a-9baed945b855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130692905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.130692905
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2255326343
Short name T13
Test name
Test status
Simulation time 83960985757 ps
CPU time 1629.89 seconds
Started Jul 30 05:17:33 PM PDT 24
Finished Jul 30 05:44:44 PM PDT 24
Peak memory 697220 kb
Host smart-c4c22cf1-b2e4-4a27-9f64-5ce72042d4a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255326343 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2255326343
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.602250763
Short name T169
Test name
Test status
Simulation time 10930247169 ps
CPU time 140.65 seconds
Started Jul 30 05:17:33 PM PDT 24
Finished Jul 30 05:19:54 PM PDT 24
Peak memory 199984 kb
Host smart-4df5e03c-7b75-4fe4-bb71-c7e20c5cca11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602250763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.602250763
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2757466185
Short name T104
Test name
Test status
Simulation time 41720535 ps
CPU time 0.6 seconds
Started Jul 30 05:17:34 PM PDT 24
Finished Jul 30 05:17:34 PM PDT 24
Peak memory 194880 kb
Host smart-2a2cbdc8-ebf4-44c9-a04d-964ac25a054f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757466185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2757466185
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2792831330
Short name T222
Test name
Test status
Simulation time 887007870 ps
CPU time 51.94 seconds
Started Jul 30 05:17:39 PM PDT 24
Finished Jul 30 05:18:31 PM PDT 24
Peak memory 199824 kb
Host smart-a44b71ce-296c-4e97-bfe0-ed283ef49142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792831330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2792831330
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.473128617
Short name T297
Test name
Test status
Simulation time 859542692 ps
CPU time 10.68 seconds
Started Jul 30 05:17:33 PM PDT 24
Finished Jul 30 05:17:44 PM PDT 24
Peak memory 199828 kb
Host smart-f9ba7b87-9b15-4ffe-b856-0472611f964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473128617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.473128617
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.882873986
Short name T407
Test name
Test status
Simulation time 8301537746 ps
CPU time 764.42 seconds
Started Jul 30 05:17:32 PM PDT 24
Finished Jul 30 05:30:17 PM PDT 24
Peak memory 685180 kb
Host smart-f337ec7c-cfbc-48db-a79f-e75d15144103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=882873986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.882873986
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2947239948
Short name T423
Test name
Test status
Simulation time 12226183552 ps
CPU time 158.06 seconds
Started Jul 30 05:17:37 PM PDT 24
Finished Jul 30 05:20:15 PM PDT 24
Peak memory 200040 kb
Host smart-c6bf5318-57ee-45da-907e-ca4c2cc6a544
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947239948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2947239948
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3923772597
Short name T402
Test name
Test status
Simulation time 62127592 ps
CPU time 0.67 seconds
Started Jul 30 05:17:32 PM PDT 24
Finished Jul 30 05:17:33 PM PDT 24
Peak memory 196504 kb
Host smart-abae099a-b839-45c6-a12d-8f55482cb7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923772597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3923772597
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.4138815388
Short name T166
Test name
Test status
Simulation time 1554932268 ps
CPU time 9.44 seconds
Started Jul 30 05:17:33 PM PDT 24
Finished Jul 30 05:17:43 PM PDT 24
Peak memory 199824 kb
Host smart-89564f5f-d67e-4850-b34a-86b557f98da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138815388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.4138815388
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1058076619
Short name T319
Test name
Test status
Simulation time 231657194254 ps
CPU time 1621.61 seconds
Started Jul 30 05:17:34 PM PDT 24
Finished Jul 30 05:44:36 PM PDT 24
Peak memory 689592 kb
Host smart-53c9b7f9-ad39-419e-8d2f-1b928ace1ce1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058076619 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1058076619
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3960073959
Short name T327
Test name
Test status
Simulation time 13923347648 ps
CPU time 69.43 seconds
Started Jul 30 05:17:34 PM PDT 24
Finished Jul 30 05:18:44 PM PDT 24
Peak memory 199928 kb
Host smart-9daef317-1c72-4536-8500-0667387c7a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960073959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3960073959
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3352575450
Short name T291
Test name
Test status
Simulation time 16000599 ps
CPU time 0.58 seconds
Started Jul 30 05:17:40 PM PDT 24
Finished Jul 30 05:17:40 PM PDT 24
Peak memory 195592 kb
Host smart-5bf61b03-ba3b-48e9-87d9-9d8b09c1d7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352575450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3352575450
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2137078720
Short name T66
Test name
Test status
Simulation time 1122974626 ps
CPU time 67 seconds
Started Jul 30 05:17:34 PM PDT 24
Finished Jul 30 05:18:41 PM PDT 24
Peak memory 199928 kb
Host smart-3bae3d27-04c2-42fa-9f58-508586f6986b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137078720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2137078720
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.527804973
Short name T439
Test name
Test status
Simulation time 16153703782 ps
CPU time 54.96 seconds
Started Jul 30 05:17:39 PM PDT 24
Finished Jul 30 05:18:34 PM PDT 24
Peak memory 208172 kb
Host smart-788c43f4-6e6d-4bfc-a1f0-298c6ab27c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527804973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.527804973
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1057202486
Short name T359
Test name
Test status
Simulation time 988354753 ps
CPU time 171.88 seconds
Started Jul 30 05:17:32 PM PDT 24
Finished Jul 30 05:20:24 PM PDT 24
Peak memory 622720 kb
Host smart-a75edef1-9233-48c9-84be-50d466dacc36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057202486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1057202486
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2651820110
Short name T399
Test name
Test status
Simulation time 1107637089 ps
CPU time 25.3 seconds
Started Jul 30 05:17:33 PM PDT 24
Finished Jul 30 05:17:59 PM PDT 24
Peak memory 199816 kb
Host smart-8346a1c9-3373-4af7-9754-81711c80bd6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651820110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2651820110
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.922540084
Short name T149
Test name
Test status
Simulation time 10487878944 ps
CPU time 122.62 seconds
Started Jul 30 05:17:34 PM PDT 24
Finished Jul 30 05:19:36 PM PDT 24
Peak memory 200000 kb
Host smart-f26ca130-c366-4c9b-aab5-42a14822b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922540084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.922540084
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1413385861
Short name T375
Test name
Test status
Simulation time 1350797032 ps
CPU time 4.8 seconds
Started Jul 30 05:17:32 PM PDT 24
Finished Jul 30 05:17:37 PM PDT 24
Peak memory 199888 kb
Host smart-09b78556-9c9d-49d1-92f2-77f49860fe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413385861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1413385861
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3680662284
Short name T19
Test name
Test status
Simulation time 130178593546 ps
CPU time 1417.32 seconds
Started Jul 30 05:17:37 PM PDT 24
Finished Jul 30 05:41:15 PM PDT 24
Peak memory 768312 kb
Host smart-1bd0bb53-65a9-4782-9345-da6cb01c21ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680662284 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3680662284
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.744288609
Short name T41
Test name
Test status
Simulation time 2133823016 ps
CPU time 45.95 seconds
Started Jul 30 05:17:35 PM PDT 24
Finished Jul 30 05:18:21 PM PDT 24
Peak memory 199848 kb
Host smart-35335a39-8d97-49f8-817a-5c59e362bed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744288609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.744288609
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3426199723
Short name T183
Test name
Test status
Simulation time 49431866 ps
CPU time 0.61 seconds
Started Jul 30 05:17:07 PM PDT 24
Finished Jul 30 05:17:08 PM PDT 24
Peak memory 195892 kb
Host smart-10154936-4c41-4d95-98e9-32e5b5127913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426199723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3426199723
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3015034034
Short name T187
Test name
Test status
Simulation time 1754909032 ps
CPU time 81.67 seconds
Started Jul 30 05:17:04 PM PDT 24
Finished Jul 30 05:18:26 PM PDT 24
Peak memory 199884 kb
Host smart-b89db321-833f-461e-a128-2a0d97fe9d69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015034034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3015034034
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1216498788
Short name T505
Test name
Test status
Simulation time 921354827 ps
CPU time 10.13 seconds
Started Jul 30 05:17:04 PM PDT 24
Finished Jul 30 05:17:14 PM PDT 24
Peak memory 199844 kb
Host smart-e0f14fc4-9d4a-4f55-b7a8-6664a9cceb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216498788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1216498788
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2882267729
Short name T430
Test name
Test status
Simulation time 63728333075 ps
CPU time 930.17 seconds
Started Jul 30 05:17:05 PM PDT 24
Finished Jul 30 05:32:35 PM PDT 24
Peak memory 726344 kb
Host smart-cd519ea2-7fa7-4716-bc03-ee4cba1340dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2882267729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2882267729
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.121555288
Short name T45
Test name
Test status
Simulation time 16474194612 ps
CPU time 141.3 seconds
Started Jul 30 05:17:05 PM PDT 24
Finished Jul 30 05:19:26 PM PDT 24
Peak memory 200076 kb
Host smart-dc70ec46-a686-4964-9ab4-2720a09d6348
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121555288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.121555288
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2468851375
Short name T83
Test name
Test status
Simulation time 337122861 ps
CPU time 19.73 seconds
Started Jul 30 05:17:04 PM PDT 24
Finished Jul 30 05:17:23 PM PDT 24
Peak memory 199912 kb
Host smart-97db89c3-17dc-41df-bca9-af41bbd8150a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468851375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2468851375
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3657249816
Short name T52
Test name
Test status
Simulation time 131811689 ps
CPU time 0.85 seconds
Started Jul 30 05:17:07 PM PDT 24
Finished Jul 30 05:17:08 PM PDT 24
Peak memory 218664 kb
Host smart-bd5660cb-578d-4a3b-a18e-ce212bacd8e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657249816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3657249816
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2733934022
Short name T463
Test name
Test status
Simulation time 287264468 ps
CPU time 4.13 seconds
Started Jul 30 05:17:03 PM PDT 24
Finished Jul 30 05:17:07 PM PDT 24
Peak memory 199900 kb
Host smart-1df75b20-e126-46a8-907b-372176803803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733934022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2733934022
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2729058405
Short name T172
Test name
Test status
Simulation time 13078194700 ps
CPU time 353.03 seconds
Started Jul 30 05:17:06 PM PDT 24
Finished Jul 30 05:22:59 PM PDT 24
Peak memory 200076 kb
Host smart-0442c0f2-dd44-466e-8516-19d2bce633b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729058405 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2729058405
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2813763932
Short name T14
Test name
Test status
Simulation time 128353915191 ps
CPU time 1212.13 seconds
Started Jul 30 05:17:03 PM PDT 24
Finished Jul 30 05:37:16 PM PDT 24
Peak memory 595516 kb
Host smart-d867d993-8a58-4502-afc2-d6fc24870fdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813763932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2813763932
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3544688459
Short name T509
Test name
Test status
Simulation time 28690429101 ps
CPU time 72.39 seconds
Started Jul 30 05:17:08 PM PDT 24
Finished Jul 30 05:18:20 PM PDT 24
Peak memory 199916 kb
Host smart-b0471528-3bd8-41e8-a0d0-0181c4f58847
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3544688459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3544688459
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.946722249
Short name T411
Test name
Test status
Simulation time 17141471768 ps
CPU time 67.38 seconds
Started Jul 30 05:17:05 PM PDT 24
Finished Jul 30 05:18:13 PM PDT 24
Peak memory 200028 kb
Host smart-555f5a98-7a4e-4c0f-a89b-4b7f544303a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=946722249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.946722249
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3595258964
Short name T215
Test name
Test status
Simulation time 2850437627 ps
CPU time 109.75 seconds
Started Jul 30 05:17:03 PM PDT 24
Finished Jul 30 05:18:53 PM PDT 24
Peak memory 199932 kb
Host smart-54fe0ff6-5bee-4d13-aebb-c1c20c847324
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3595258964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3595258964
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2252641045
Short name T340
Test name
Test status
Simulation time 137094786029 ps
CPU time 625.01 seconds
Started Jul 30 05:17:04 PM PDT 24
Finished Jul 30 05:27:29 PM PDT 24
Peak memory 199984 kb
Host smart-150641b8-46f0-4d59-a342-834a665c634f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2252641045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2252641045
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.577916864
Short name T499
Test name
Test status
Simulation time 290860367400 ps
CPU time 2550.6 seconds
Started Jul 30 05:17:03 PM PDT 24
Finished Jul 30 05:59:34 PM PDT 24
Peak memory 215676 kb
Host smart-0df1000f-4b69-4819-93e3-93769240e4a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=577916864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.577916864
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2855810369
Short name T328
Test name
Test status
Simulation time 514873054983 ps
CPU time 2297.04 seconds
Started Jul 30 05:17:05 PM PDT 24
Finished Jul 30 05:55:22 PM PDT 24
Peak memory 216032 kb
Host smart-1e33e4cf-46cd-4b7f-b70c-65714b5260db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2855810369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2855810369
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1782710835
Short name T156
Test name
Test status
Simulation time 3357852905 ps
CPU time 14.59 seconds
Started Jul 30 05:17:08 PM PDT 24
Finished Jul 30 05:17:22 PM PDT 24
Peak memory 199984 kb
Host smart-2b1b8b78-396a-4f16-88c7-49360847c304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782710835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1782710835
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2782098753
Short name T210
Test name
Test status
Simulation time 117558057 ps
CPU time 0.62 seconds
Started Jul 30 05:17:40 PM PDT 24
Finished Jul 30 05:17:41 PM PDT 24
Peak memory 195964 kb
Host smart-1f5d6db5-947f-446f-9dab-227a0c40469f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782098753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2782098753
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4094210596
Short name T11
Test name
Test status
Simulation time 1970316494 ps
CPU time 37.96 seconds
Started Jul 30 05:17:38 PM PDT 24
Finished Jul 30 05:18:17 PM PDT 24
Peak memory 199836 kb
Host smart-83a1889a-c7a7-4f43-842b-89007e06d2b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094210596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4094210596
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2592360907
Short name T231
Test name
Test status
Simulation time 197127019 ps
CPU time 3.91 seconds
Started Jul 30 05:17:40 PM PDT 24
Finished Jul 30 05:17:44 PM PDT 24
Peak memory 199808 kb
Host smart-e5ac1816-a8aa-477f-abc6-06196c9c3df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592360907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2592360907
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1171004054
Short name T292
Test name
Test status
Simulation time 6471979638 ps
CPU time 268.55 seconds
Started Jul 30 05:17:38 PM PDT 24
Finished Jul 30 05:22:07 PM PDT 24
Peak memory 606796 kb
Host smart-6bad55a2-199b-490d-b1ae-d87b29864195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171004054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1171004054
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2057851111
Short name T244
Test name
Test status
Simulation time 11007848461 ps
CPU time 151.15 seconds
Started Jul 30 05:17:40 PM PDT 24
Finished Jul 30 05:20:11 PM PDT 24
Peak memory 199944 kb
Host smart-6149f090-c5bc-4731-9b08-f70e87c8e000
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057851111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2057851111
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3173729129
Short name T293
Test name
Test status
Simulation time 4986558168 ps
CPU time 17.18 seconds
Started Jul 30 05:17:41 PM PDT 24
Finished Jul 30 05:17:58 PM PDT 24
Peak memory 200004 kb
Host smart-f5c4542b-00c4-42f1-aee4-001412135314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173729129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3173729129
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2567859431
Short name T296
Test name
Test status
Simulation time 3172242295 ps
CPU time 7.6 seconds
Started Jul 30 05:17:37 PM PDT 24
Finished Jul 30 05:17:45 PM PDT 24
Peak memory 200024 kb
Host smart-c5d74d41-7134-4921-8540-83cfa2baa0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567859431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2567859431
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3463715095
Short name T86
Test name
Test status
Simulation time 36991240315 ps
CPU time 2142.05 seconds
Started Jul 30 05:17:39 PM PDT 24
Finished Jul 30 05:53:22 PM PDT 24
Peak memory 695052 kb
Host smart-850c5444-786e-47d6-b437-e7dfebc2ae9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463715095 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3463715095
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1085700809
Short name T508
Test name
Test status
Simulation time 4526738727 ps
CPU time 74.28 seconds
Started Jul 30 05:17:38 PM PDT 24
Finished Jul 30 05:18:52 PM PDT 24
Peak memory 199972 kb
Host smart-875d3f03-856e-4413-9993-405d7186406a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085700809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1085700809
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.611149023
Short name T325
Test name
Test status
Simulation time 42272836 ps
CPU time 0.66 seconds
Started Jul 30 05:17:47 PM PDT 24
Finished Jul 30 05:17:48 PM PDT 24
Peak memory 195932 kb
Host smart-3cc5f6b9-f13d-47bb-998b-5fe60e244e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611149023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.611149023
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3114830398
Short name T298
Test name
Test status
Simulation time 685097341 ps
CPU time 39.65 seconds
Started Jul 30 05:17:46 PM PDT 24
Finished Jul 30 05:18:26 PM PDT 24
Peak memory 199880 kb
Host smart-6c7959fc-825b-439d-bf64-6bbcd37dfcb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114830398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3114830398
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1078756125
Short name T72
Test name
Test status
Simulation time 9422772243 ps
CPU time 59.82 seconds
Started Jul 30 05:17:47 PM PDT 24
Finished Jul 30 05:18:47 PM PDT 24
Peak memory 208248 kb
Host smart-21cd5198-666b-4ecb-8b94-41509b70c61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078756125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1078756125
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.785574316
Short name T181
Test name
Test status
Simulation time 7204080763 ps
CPU time 678.7 seconds
Started Jul 30 05:17:47 PM PDT 24
Finished Jul 30 05:29:05 PM PDT 24
Peak memory 699124 kb
Host smart-4c2ec888-6e17-4bff-89ee-2784684972bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=785574316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.785574316
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3572890858
Short name T449
Test name
Test status
Simulation time 2555005970 ps
CPU time 47.17 seconds
Started Jul 30 05:17:42 PM PDT 24
Finished Jul 30 05:18:30 PM PDT 24
Peak memory 200016 kb
Host smart-e50e327e-9acb-4625-917a-d996540a8d02
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572890858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3572890858
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3729976366
Short name T230
Test name
Test status
Simulation time 1824615720 ps
CPU time 105.54 seconds
Started Jul 30 05:17:46 PM PDT 24
Finished Jul 30 05:19:31 PM PDT 24
Peak memory 199948 kb
Host smart-369109a1-17a4-4ec0-bd5b-1f50163dcc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729976366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3729976366
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1696113801
Short name T168
Test name
Test status
Simulation time 400142198 ps
CPU time 5.53 seconds
Started Jul 30 05:17:38 PM PDT 24
Finished Jul 30 05:17:44 PM PDT 24
Peak memory 199684 kb
Host smart-071e88eb-a171-4a11-80b0-128773831dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696113801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1696113801
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.4249388695
Short name T53
Test name
Test status
Simulation time 120857545732 ps
CPU time 3160.82 seconds
Started Jul 30 05:17:45 PM PDT 24
Finished Jul 30 06:10:26 PM PDT 24
Peak memory 750612 kb
Host smart-408ac96d-d80b-4a7c-83d6-3cafe8f4b312
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249388695 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.4249388695
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1788839787
Short name T160
Test name
Test status
Simulation time 4029613678 ps
CPU time 77.37 seconds
Started Jul 30 05:17:46 PM PDT 24
Finished Jul 30 05:19:03 PM PDT 24
Peak memory 200016 kb
Host smart-1c633ee3-4fc7-4e7e-9af8-e5ab1b7d0eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788839787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1788839787
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.4124890850
Short name T506
Test name
Test status
Simulation time 13585689 ps
CPU time 0.56 seconds
Started Jul 30 05:17:47 PM PDT 24
Finished Jul 30 05:17:47 PM PDT 24
Peak memory 194920 kb
Host smart-159cb9ba-d52c-4402-b8c4-52e113438eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124890850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.4124890850
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2973368872
Short name T372
Test name
Test status
Simulation time 788417652 ps
CPU time 21.85 seconds
Started Jul 30 05:17:45 PM PDT 24
Finished Jul 30 05:18:07 PM PDT 24
Peak memory 199924 kb
Host smart-d16ed68c-f543-4189-90fc-0ba0394e348e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973368872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2973368872
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.86798217
Short name T44
Test name
Test status
Simulation time 3833785541 ps
CPU time 50.91 seconds
Started Jul 30 05:17:44 PM PDT 24
Finished Jul 30 05:18:35 PM PDT 24
Peak memory 199936 kb
Host smart-12d1918b-1fdb-432c-ad8a-85cc11527196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86798217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.86798217
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1882664142
Short name T498
Test name
Test status
Simulation time 537991696 ps
CPU time 21.39 seconds
Started Jul 30 05:17:43 PM PDT 24
Finished Jul 30 05:18:05 PM PDT 24
Peak memory 205880 kb
Host smart-15ce0d81-69f5-4327-855d-7e42ef4b56a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882664142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1882664142
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2647157469
Short name T412
Test name
Test status
Simulation time 63836766058 ps
CPU time 216.65 seconds
Started Jul 30 05:17:47 PM PDT 24
Finished Jul 30 05:21:23 PM PDT 24
Peak memory 200000 kb
Host smart-b13dc11b-2e03-4ec7-9e1a-a5a133dd913e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647157469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2647157469
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.4222143601
Short name T193
Test name
Test status
Simulation time 18280693227 ps
CPU time 81.83 seconds
Started Jul 30 05:17:46 PM PDT 24
Finished Jul 30 05:19:08 PM PDT 24
Peak memory 200028 kb
Host smart-ab0b2be1-d6ed-49eb-a19b-b642e6da4f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222143601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.4222143601
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.693785668
Short name T493
Test name
Test status
Simulation time 63692441 ps
CPU time 2.81 seconds
Started Jul 30 05:17:44 PM PDT 24
Finished Jul 30 05:17:46 PM PDT 24
Peak memory 199916 kb
Host smart-18bdd001-f519-4b3b-8e5c-5d21a56f7693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693785668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.693785668
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3760582718
Short name T136
Test name
Test status
Simulation time 9098859914 ps
CPU time 134.46 seconds
Started Jul 30 05:17:47 PM PDT 24
Finished Jul 30 05:20:02 PM PDT 24
Peak memory 216420 kb
Host smart-46c980c5-29f3-4a29-9ca2-b29b976f6f84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760582718 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3760582718
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2684044448
Short name T317
Test name
Test status
Simulation time 37779648323 ps
CPU time 93.34 seconds
Started Jul 30 05:17:46 PM PDT 24
Finished Jul 30 05:19:19 PM PDT 24
Peak memory 200024 kb
Host smart-4bd4e5ee-da14-4978-8bc8-e971bd826c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684044448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2684044448
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3611924619
Short name T102
Test name
Test status
Simulation time 43293106 ps
CPU time 0.63 seconds
Started Jul 30 05:17:56 PM PDT 24
Finished Jul 30 05:17:57 PM PDT 24
Peak memory 196656 kb
Host smart-d8d655ed-4a35-4a71-81d8-2407d3a674ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611924619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3611924619
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2945257302
Short name T30
Test name
Test status
Simulation time 18696836122 ps
CPU time 62.92 seconds
Started Jul 30 05:17:51 PM PDT 24
Finished Jul 30 05:18:54 PM PDT 24
Peak memory 199956 kb
Host smart-6a4399f5-6b10-40dc-9dc7-747c6e3f4824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2945257302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2945257302
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.4336203
Short name T270
Test name
Test status
Simulation time 11111442659 ps
CPU time 40.66 seconds
Started Jul 30 05:17:57 PM PDT 24
Finished Jul 30 05:18:38 PM PDT 24
Peak memory 200020 kb
Host smart-131e156e-f239-4b80-96cc-a782908df187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4336203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.4336203
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3777749960
Short name T100
Test name
Test status
Simulation time 3960412292 ps
CPU time 619.15 seconds
Started Jul 30 05:17:51 PM PDT 24
Finished Jul 30 05:28:10 PM PDT 24
Peak memory 680096 kb
Host smart-6fa6b038-fb83-4a00-99b5-95ed476b2ea3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777749960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3777749960
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.997415822
Short name T79
Test name
Test status
Simulation time 3384851345 ps
CPU time 183.5 seconds
Started Jul 30 05:17:53 PM PDT 24
Finished Jul 30 05:20:57 PM PDT 24
Peak memory 200056 kb
Host smart-1231d879-9a2b-4151-89e2-37d6690f2cb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997415822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.997415822
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2730517195
Short name T306
Test name
Test status
Simulation time 1543821702 ps
CPU time 44.92 seconds
Started Jul 30 05:17:47 PM PDT 24
Finished Jul 30 05:18:32 PM PDT 24
Peak memory 199908 kb
Host smart-c964e68c-062d-4dd1-b27a-7b56d7850028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730517195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2730517195
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1254844680
Short name T512
Test name
Test status
Simulation time 774937444 ps
CPU time 8.76 seconds
Started Jul 30 05:17:47 PM PDT 24
Finished Jul 30 05:17:56 PM PDT 24
Peak memory 199936 kb
Host smart-af97c069-084d-45da-8ba9-0f9eb70ce7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254844680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1254844680
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1883097735
Short name T444
Test name
Test status
Simulation time 35247926170 ps
CPU time 327.18 seconds
Started Jul 30 05:17:52 PM PDT 24
Finished Jul 30 05:23:20 PM PDT 24
Peak memory 208220 kb
Host smart-9ac2ce11-bf93-49cf-b52a-4d6c9331bae8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883097735 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1883097735
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.4267290269
Short name T303
Test name
Test status
Simulation time 7684999874 ps
CPU time 58.72 seconds
Started Jul 30 05:17:56 PM PDT 24
Finished Jul 30 05:18:55 PM PDT 24
Peak memory 200020 kb
Host smart-3277da12-984f-4c7c-ae98-39de9a1f4618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267290269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.4267290269
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2976776700
Short name T220
Test name
Test status
Simulation time 12156488 ps
CPU time 0.59 seconds
Started Jul 30 05:17:57 PM PDT 24
Finished Jul 30 05:17:58 PM PDT 24
Peak memory 195580 kb
Host smart-f3b30be9-5f5e-4c22-8018-53c68c2d8320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976776700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2976776700
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.517168214
Short name T32
Test name
Test status
Simulation time 1026658737 ps
CPU time 54.44 seconds
Started Jul 30 05:17:52 PM PDT 24
Finished Jul 30 05:18:46 PM PDT 24
Peak memory 199828 kb
Host smart-41db34c0-daf6-4bf0-b7f0-69b835ce65b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=517168214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.517168214
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.294613458
Short name T367
Test name
Test status
Simulation time 8913673756 ps
CPU time 51.64 seconds
Started Jul 30 05:17:56 PM PDT 24
Finished Jul 30 05:18:47 PM PDT 24
Peak memory 199992 kb
Host smart-06dd6b29-a352-499e-9eea-7e0f7bca1f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294613458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.294613458
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3806043033
Short name T261
Test name
Test status
Simulation time 3668507620 ps
CPU time 689.09 seconds
Started Jul 30 05:17:56 PM PDT 24
Finished Jul 30 05:29:25 PM PDT 24
Peak memory 715712 kb
Host smart-0ad1cbc2-214b-40c2-a6c7-a702c05413b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806043033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3806043033
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.789627107
Short name T426
Test name
Test status
Simulation time 44167436107 ps
CPU time 131.86 seconds
Started Jul 30 05:17:57 PM PDT 24
Finished Jul 30 05:20:09 PM PDT 24
Peak memory 200004 kb
Host smart-22b7ab08-9f30-479c-bc4a-6b616ef6951b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789627107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.789627107
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4201384282
Short name T490
Test name
Test status
Simulation time 30911156910 ps
CPU time 124.38 seconds
Started Jul 30 05:17:53 PM PDT 24
Finished Jul 30 05:19:58 PM PDT 24
Peak memory 216164 kb
Host smart-cff152ab-bb5d-4d2b-a51b-c2d4eeede642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201384282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4201384282
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3517462390
Short name T470
Test name
Test status
Simulation time 1536088553 ps
CPU time 14.23 seconds
Started Jul 30 05:17:57 PM PDT 24
Finished Jul 30 05:18:12 PM PDT 24
Peak memory 199880 kb
Host smart-f653d636-548f-4fe3-acf9-b104f923c47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517462390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3517462390
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3328001945
Short name T122
Test name
Test status
Simulation time 44128299595 ps
CPU time 705.49 seconds
Started Jul 30 05:17:55 PM PDT 24
Finished Jul 30 05:29:41 PM PDT 24
Peak memory 489104 kb
Host smart-824149cf-2a39-4a6c-9783-f70f1896c4f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328001945 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3328001945
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2299362321
Short name T518
Test name
Test status
Simulation time 296157500 ps
CPU time 5.2 seconds
Started Jul 30 05:17:57 PM PDT 24
Finished Jul 30 05:18:02 PM PDT 24
Peak memory 199928 kb
Host smart-d07ff5f1-aef7-4cf0-b406-406d7ada2603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299362321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2299362321
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4262958006
Short name T236
Test name
Test status
Simulation time 39715392 ps
CPU time 0.6 seconds
Started Jul 30 05:18:01 PM PDT 24
Finished Jul 30 05:18:01 PM PDT 24
Peak memory 195956 kb
Host smart-567ad400-bbe6-49df-a9f0-68da9ca2f8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262958006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4262958006
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1579141492
Short name T278
Test name
Test status
Simulation time 1492352871 ps
CPU time 63.17 seconds
Started Jul 30 05:17:57 PM PDT 24
Finished Jul 30 05:19:00 PM PDT 24
Peak memory 199900 kb
Host smart-8fd86bd2-669a-4a82-87fb-6b59f040f67f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579141492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1579141492
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.997174228
Short name T201
Test name
Test status
Simulation time 728964973 ps
CPU time 2.76 seconds
Started Jul 30 05:18:00 PM PDT 24
Finished Jul 30 05:18:03 PM PDT 24
Peak memory 199916 kb
Host smart-3b1621ac-a6c6-4c38-9b57-470f402a54bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997174228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.997174228
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3217019370
Short name T457
Test name
Test status
Simulation time 55110498752 ps
CPU time 1121.84 seconds
Started Jul 30 05:18:01 PM PDT 24
Finished Jul 30 05:36:43 PM PDT 24
Peak memory 697272 kb
Host smart-9d3d0215-038c-4940-9833-92d7678c27da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3217019370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3217019370
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.4174936212
Short name T148
Test name
Test status
Simulation time 46922396801 ps
CPU time 214.75 seconds
Started Jul 30 05:18:05 PM PDT 24
Finished Jul 30 05:21:40 PM PDT 24
Peak memory 199972 kb
Host smart-35fd59b9-4081-4994-a400-0043c7c836d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174936212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4174936212
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3756237769
Short name T163
Test name
Test status
Simulation time 2974581969 ps
CPU time 162.35 seconds
Started Jul 30 05:17:56 PM PDT 24
Finished Jul 30 05:20:39 PM PDT 24
Peak memory 199932 kb
Host smart-970504ff-c66c-40aa-b631-5e3419a483ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756237769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3756237769
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1281492856
Short name T343
Test name
Test status
Simulation time 118703781 ps
CPU time 4.97 seconds
Started Jul 30 05:17:56 PM PDT 24
Finished Jul 30 05:18:01 PM PDT 24
Peak memory 199912 kb
Host smart-8c89c40e-97d9-48b3-872a-95f2a1be6873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281492856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1281492856
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3460143704
Short name T290
Test name
Test status
Simulation time 298450052145 ps
CPU time 1176.75 seconds
Started Jul 30 05:18:00 PM PDT 24
Finished Jul 30 05:37:37 PM PDT 24
Peak memory 715916 kb
Host smart-21082682-0887-4c34-9554-8cf40e549c77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460143704 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3460143704
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.626487475
Short name T142
Test name
Test status
Simulation time 330982009 ps
CPU time 18.51 seconds
Started Jul 30 05:17:59 PM PDT 24
Finished Jul 30 05:18:17 PM PDT 24
Peak memory 199888 kb
Host smart-11cba698-ead5-43d9-bb71-ce9244839b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626487475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.626487475
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2773656490
Short name T352
Test name
Test status
Simulation time 164823524 ps
CPU time 0.59 seconds
Started Jul 30 05:18:06 PM PDT 24
Finished Jul 30 05:18:07 PM PDT 24
Peak memory 194920 kb
Host smart-089e8577-a16d-46e0-84b6-e418509e93e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773656490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2773656490
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.822275450
Short name T452
Test name
Test status
Simulation time 314769599 ps
CPU time 17.14 seconds
Started Jul 30 05:18:00 PM PDT 24
Finished Jul 30 05:18:17 PM PDT 24
Peak memory 199800 kb
Host smart-75cff7f2-d070-49aa-9d26-7e31ec656a23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822275450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.822275450
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.720998229
Short name T245
Test name
Test status
Simulation time 750924207 ps
CPU time 39.65 seconds
Started Jul 30 05:18:02 PM PDT 24
Finished Jul 30 05:18:42 PM PDT 24
Peak memory 199904 kb
Host smart-774aa6ac-2feb-4035-a2cc-c54ee7957ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720998229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.720998229
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1149326465
Short name T54
Test name
Test status
Simulation time 3175044461 ps
CPU time 127.64 seconds
Started Jul 30 05:18:00 PM PDT 24
Finished Jul 30 05:20:07 PM PDT 24
Peak memory 398024 kb
Host smart-31154c9a-c186-4033-b172-4d000ff53b20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149326465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1149326465
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2394963260
Short name T489
Test name
Test status
Simulation time 11400195077 ps
CPU time 112.74 seconds
Started Jul 30 05:18:01 PM PDT 24
Finished Jul 30 05:19:54 PM PDT 24
Peak memory 200036 kb
Host smart-0415e018-fb41-4a81-b237-2bf5d4b31309
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394963260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2394963260
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2357839255
Short name T395
Test name
Test status
Simulation time 13975372504 ps
CPU time 189.84 seconds
Started Jul 30 05:18:01 PM PDT 24
Finished Jul 30 05:21:10 PM PDT 24
Peak memory 208208 kb
Host smart-e3370436-b961-436b-8ab5-c6e75c26914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357839255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2357839255
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2752015448
Short name T248
Test name
Test status
Simulation time 1239034645 ps
CPU time 4.95 seconds
Started Jul 30 05:18:00 PM PDT 24
Finished Jul 30 05:18:06 PM PDT 24
Peak memory 199832 kb
Host smart-36c87676-baca-4cdf-b6d7-83a679bf1e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752015448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2752015448
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.856820180
Short name T525
Test name
Test status
Simulation time 374581113054 ps
CPU time 1402.49 seconds
Started Jul 30 05:18:05 PM PDT 24
Finished Jul 30 05:41:28 PM PDT 24
Peak memory 739920 kb
Host smart-08321a1a-2c81-4deb-a847-28b3387a2b31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856820180 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.856820180
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3068553208
Short name T87
Test name
Test status
Simulation time 9396744135 ps
CPU time 130.3 seconds
Started Jul 30 05:18:05 PM PDT 24
Finished Jul 30 05:20:15 PM PDT 24
Peak memory 200024 kb
Host smart-e3d3a97c-a6cb-4401-aba2-f2984742669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068553208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3068553208
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3158304582
Short name T214
Test name
Test status
Simulation time 37355769 ps
CPU time 0.58 seconds
Started Jul 30 05:18:08 PM PDT 24
Finished Jul 30 05:18:09 PM PDT 24
Peak memory 194948 kb
Host smart-1a9e7212-7daf-40e9-8b85-b67fd6b601bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158304582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3158304582
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2179258000
Short name T283
Test name
Test status
Simulation time 1393044177 ps
CPU time 22.1 seconds
Started Jul 30 05:18:05 PM PDT 24
Finished Jul 30 05:18:27 PM PDT 24
Peak memory 199812 kb
Host smart-3da83aa3-ca67-4961-a110-353128873723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2179258000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2179258000
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3860508033
Short name T316
Test name
Test status
Simulation time 4287920606 ps
CPU time 18.67 seconds
Started Jul 30 05:18:05 PM PDT 24
Finished Jul 30 05:18:24 PM PDT 24
Peak memory 199904 kb
Host smart-831de3c1-b83d-43e4-944a-a4d54eaf2e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860508033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3860508033
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3229372591
Short name T397
Test name
Test status
Simulation time 3472836381 ps
CPU time 623.88 seconds
Started Jul 30 05:18:04 PM PDT 24
Finished Jul 30 05:28:28 PM PDT 24
Peak memory 649056 kb
Host smart-64921a36-fc32-487e-be99-39c75c45da00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229372591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3229372591
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1668474973
Short name T472
Test name
Test status
Simulation time 11507653128 ps
CPU time 179.79 seconds
Started Jul 30 05:18:05 PM PDT 24
Finished Jul 30 05:21:05 PM PDT 24
Peak memory 199992 kb
Host smart-7c4599b5-b2a3-44d2-bd06-174636a32b04
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668474973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1668474973
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.895576845
Short name T443
Test name
Test status
Simulation time 2834554971 ps
CPU time 49.17 seconds
Started Jul 30 05:18:05 PM PDT 24
Finished Jul 30 05:18:55 PM PDT 24
Peak memory 200000 kb
Host smart-8043a001-df02-4fe1-a157-05de6777e725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895576845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.895576845
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1135114202
Short name T338
Test name
Test status
Simulation time 378290132 ps
CPU time 4.92 seconds
Started Jul 30 05:18:05 PM PDT 24
Finished Jul 30 05:18:10 PM PDT 24
Peak memory 199880 kb
Host smart-9973c792-6c94-4408-ac2a-38aad8f6aa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135114202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1135114202
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1808834374
Short name T77
Test name
Test status
Simulation time 33960472275 ps
CPU time 195.57 seconds
Started Jul 30 05:18:06 PM PDT 24
Finished Jul 30 05:21:22 PM PDT 24
Peak memory 605812 kb
Host smart-bb6d224a-7446-4bd9-9d14-6c31bdc7cfa3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808834374 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1808834374
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.985772278
Short name T56
Test name
Test status
Simulation time 5671728872 ps
CPU time 111.64 seconds
Started Jul 30 05:18:06 PM PDT 24
Finished Jul 30 05:19:58 PM PDT 24
Peak memory 199968 kb
Host smart-1d4b44c2-4e51-482c-94c4-64565f50d548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985772278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.985772278
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3399193468
Short name T377
Test name
Test status
Simulation time 13612194 ps
CPU time 0.61 seconds
Started Jul 30 05:18:13 PM PDT 24
Finished Jul 30 05:18:14 PM PDT 24
Peak memory 195940 kb
Host smart-6103aa15-7692-4dbb-b272-c3baf8cba6ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399193468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3399193468
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2038006517
Short name T434
Test name
Test status
Simulation time 74114117 ps
CPU time 4.15 seconds
Started Jul 30 05:18:11 PM PDT 24
Finished Jul 30 05:18:15 PM PDT 24
Peak memory 199924 kb
Host smart-312555e0-cc3d-4588-8338-f2ec7f1e0b23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038006517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2038006517
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2516883834
Short name T410
Test name
Test status
Simulation time 1555095183 ps
CPU time 16.23 seconds
Started Jul 30 05:18:11 PM PDT 24
Finished Jul 30 05:18:28 PM PDT 24
Peak memory 199844 kb
Host smart-fdf9f97b-f1bf-4b6e-8ebc-e85076279fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516883834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2516883834
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.107874848
Short name T138
Test name
Test status
Simulation time 6921308374 ps
CPU time 376.11 seconds
Started Jul 30 05:18:09 PM PDT 24
Finished Jul 30 05:24:25 PM PDT 24
Peak memory 688476 kb
Host smart-87420f93-d514-44cc-9c3a-36ec0fe3c057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107874848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.107874848
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3450155656
Short name T186
Test name
Test status
Simulation time 7854725260 ps
CPU time 143.67 seconds
Started Jul 30 05:18:10 PM PDT 24
Finished Jul 30 05:20:34 PM PDT 24
Peak memory 200040 kb
Host smart-fa78f901-ac4a-41f9-9f6f-fb2fcb011bcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450155656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3450155656
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3280933092
Short name T312
Test name
Test status
Simulation time 88668056 ps
CPU time 4.6 seconds
Started Jul 30 05:18:09 PM PDT 24
Finished Jul 30 05:18:14 PM PDT 24
Peak memory 199908 kb
Host smart-6d143fec-a3d7-464b-bed9-b2b2c21c98da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280933092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3280933092
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2075725568
Short name T425
Test name
Test status
Simulation time 1102676177 ps
CPU time 11.16 seconds
Started Jul 30 05:18:10 PM PDT 24
Finished Jul 30 05:18:21 PM PDT 24
Peak memory 199912 kb
Host smart-5d84b39c-c56a-47db-a259-82e22a029965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075725568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2075725568
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3136240209
Short name T320
Test name
Test status
Simulation time 21548496777 ps
CPU time 592.94 seconds
Started Jul 30 05:18:14 PM PDT 24
Finished Jul 30 05:28:07 PM PDT 24
Peak memory 200016 kb
Host smart-6e2748a7-99e9-47f8-a309-e892c7d69576
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136240209 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3136240209
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3054508791
Short name T515
Test name
Test status
Simulation time 9337702313 ps
CPU time 132.76 seconds
Started Jul 30 05:18:13 PM PDT 24
Finished Jul 30 05:20:26 PM PDT 24
Peak memory 200088 kb
Host smart-c8b5e3fd-a68c-4fa0-8ad8-8b4155a5c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054508791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3054508791
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4132399729
Short name T2
Test name
Test status
Simulation time 40153221 ps
CPU time 0.6 seconds
Started Jul 30 05:18:19 PM PDT 24
Finished Jul 30 05:18:20 PM PDT 24
Peak memory 196616 kb
Host smart-18a45070-6b1b-44a9-bff4-ecd312dc6252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132399729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4132399729
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.369880415
Short name T432
Test name
Test status
Simulation time 11137812303 ps
CPU time 80.43 seconds
Started Jul 30 05:18:15 PM PDT 24
Finished Jul 30 05:19:35 PM PDT 24
Peak memory 199936 kb
Host smart-12265d5d-cbb0-4d8c-b083-011ca231cd71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369880415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.369880415
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.612974683
Short name T401
Test name
Test status
Simulation time 6893606038 ps
CPU time 60.01 seconds
Started Jul 30 05:18:14 PM PDT 24
Finished Jul 30 05:19:15 PM PDT 24
Peak memory 200000 kb
Host smart-93210304-65ce-43c5-850d-a9a1a6ebc7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612974683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.612974683
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2474544725
Short name T473
Test name
Test status
Simulation time 31502283831 ps
CPU time 1024.04 seconds
Started Jul 30 05:18:14 PM PDT 24
Finished Jul 30 05:35:19 PM PDT 24
Peak memory 694288 kb
Host smart-1c0afa07-0fd5-4bf0-8e37-2bd2e5f1977b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2474544725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2474544725
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1094590430
Short name T208
Test name
Test status
Simulation time 1913644539 ps
CPU time 36.75 seconds
Started Jul 30 05:18:15 PM PDT 24
Finished Jul 30 05:18:52 PM PDT 24
Peak memory 199924 kb
Host smart-ab13d1a4-d398-49c6-a54d-462efef25f63
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094590430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1094590430
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3411622187
Short name T448
Test name
Test status
Simulation time 6688162709 ps
CPU time 118.13 seconds
Started Jul 30 05:18:14 PM PDT 24
Finished Jul 30 05:20:12 PM PDT 24
Peak memory 200044 kb
Host smart-d08a15f2-3174-4628-b685-ddf06e0c033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411622187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3411622187
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3528482895
Short name T105
Test name
Test status
Simulation time 275269485 ps
CPU time 12.45 seconds
Started Jul 30 05:18:14 PM PDT 24
Finished Jul 30 05:18:27 PM PDT 24
Peak memory 199864 kb
Host smart-0da3a4a7-2b31-43a3-8eb4-2fc7b12a3df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528482895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3528482895
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.4082546927
Short name T75
Test name
Test status
Simulation time 54400743854 ps
CPU time 697.52 seconds
Started Jul 30 05:18:20 PM PDT 24
Finished Jul 30 05:29:58 PM PDT 24
Peak memory 216400 kb
Host smart-832be3e5-c23c-4e51-a148-3f3b55c3505d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082546927 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.4082546927
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.852544747
Short name T251
Test name
Test status
Simulation time 871729253 ps
CPU time 13.04 seconds
Started Jul 30 05:18:17 PM PDT 24
Finished Jul 30 05:18:30 PM PDT 24
Peak memory 199900 kb
Host smart-cca0dc2b-282a-4712-bd87-965c294c0a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852544747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.852544747
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2855915085
Short name T15
Test name
Test status
Simulation time 19138869 ps
CPU time 0.6 seconds
Started Jul 30 05:17:09 PM PDT 24
Finished Jul 30 05:17:09 PM PDT 24
Peak memory 196656 kb
Host smart-684440e3-9739-4f18-9dee-898daf236716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855915085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2855915085
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.226771199
Short name T376
Test name
Test status
Simulation time 82384826 ps
CPU time 4.45 seconds
Started Jul 30 05:17:05 PM PDT 24
Finished Jul 30 05:17:10 PM PDT 24
Peak memory 199864 kb
Host smart-48c9cbef-a42e-48d2-ba70-d64d06b8f9a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=226771199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.226771199
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.556125327
Short name T360
Test name
Test status
Simulation time 14463918026 ps
CPU time 514.7 seconds
Started Jul 30 05:17:05 PM PDT 24
Finished Jul 30 05:25:40 PM PDT 24
Peak memory 689024 kb
Host smart-e9c70959-087d-4345-909e-3bf1059703a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556125327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.556125327
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2349985624
Short name T282
Test name
Test status
Simulation time 24044548035 ps
CPU time 108 seconds
Started Jul 30 05:17:07 PM PDT 24
Finished Jul 30 05:18:55 PM PDT 24
Peak memory 200048 kb
Host smart-089cbd1f-4408-4e7a-9804-a494c2547d65
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349985624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2349985624
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3943500607
Short name T335
Test name
Test status
Simulation time 22550941272 ps
CPU time 39.56 seconds
Started Jul 30 05:17:05 PM PDT 24
Finished Jul 30 05:17:44 PM PDT 24
Peak memory 200008 kb
Host smart-b91bc8f8-156c-42d7-af1f-5121e5e2eace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943500607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3943500607
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2070178120
Short name T51
Test name
Test status
Simulation time 126269685 ps
CPU time 0.83 seconds
Started Jul 30 05:17:08 PM PDT 24
Finished Jul 30 05:17:09 PM PDT 24
Peak memory 218596 kb
Host smart-42a3934b-db17-46cb-b458-79b4898db1c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070178120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2070178120
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2445822240
Short name T24
Test name
Test status
Simulation time 204999628 ps
CPU time 5.77 seconds
Started Jul 30 05:17:02 PM PDT 24
Finished Jul 30 05:17:08 PM PDT 24
Peak memory 199900 kb
Host smart-3d63be48-f086-4d67-a790-a2747197d766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445822240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2445822240
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1688269132
Short name T224
Test name
Test status
Simulation time 357465459626 ps
CPU time 2215.44 seconds
Started Jul 30 05:17:09 PM PDT 24
Finished Jul 30 05:54:04 PM PDT 24
Peak memory 722216 kb
Host smart-173b6dca-09e5-4be2-bbfe-14496b0d0ad8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688269132 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1688269132
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1459745618
Short name T65
Test name
Test status
Simulation time 24980404364 ps
CPU time 396.7 seconds
Started Jul 30 05:17:09 PM PDT 24
Finished Jul 30 05:23:46 PM PDT 24
Peak memory 209900 kb
Host smart-9cd64d3d-1b3b-40bb-9646-3a0e165688ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459745618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1459745618
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3625885054
Short name T37
Test name
Test status
Simulation time 4262892343 ps
CPU time 41.08 seconds
Started Jul 30 05:17:12 PM PDT 24
Finished Jul 30 05:17:53 PM PDT 24
Peak memory 200064 kb
Host smart-43174981-ee8a-4a1f-9d95-6ca8fabf2c7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3625885054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3625885054
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.2542174479
Short name T454
Test name
Test status
Simulation time 2240662057 ps
CPU time 85.3 seconds
Started Jul 30 05:17:10 PM PDT 24
Finished Jul 30 05:18:36 PM PDT 24
Peak memory 199956 kb
Host smart-37373fdb-c8ef-4ea8-b972-84b785021f3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2542174479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2542174479
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2928774747
Short name T55
Test name
Test status
Simulation time 18066898510 ps
CPU time 73.06 seconds
Started Jul 30 05:17:08 PM PDT 24
Finished Jul 30 05:18:22 PM PDT 24
Peak memory 200008 kb
Host smart-36577421-f857-414b-82ce-f33e45f9964e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2928774747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2928774747
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.137862348
Short name T485
Test name
Test status
Simulation time 41800593487 ps
CPU time 591.38 seconds
Started Jul 30 05:17:10 PM PDT 24
Finished Jul 30 05:27:02 PM PDT 24
Peak memory 200052 kb
Host smart-ad8e3bdc-ea69-42b9-9b62-ad836a3771ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=137862348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.137862348
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3427809158
Short name T333
Test name
Test status
Simulation time 133256165024 ps
CPU time 2310.81 seconds
Started Jul 30 05:17:09 PM PDT 24
Finished Jul 30 05:55:40 PM PDT 24
Peak memory 216028 kb
Host smart-bae6e338-92f0-4d1c-b17f-c8e4b4fc59d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3427809158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3427809158
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2273256632
Short name T517
Test name
Test status
Simulation time 278914601492 ps
CPU time 2436.78 seconds
Started Jul 30 05:17:09 PM PDT 24
Finished Jul 30 05:57:47 PM PDT 24
Peak memory 215724 kb
Host smart-b084de80-d92c-4027-9a31-7294f1b3026a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2273256632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2273256632
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1941961449
Short name T28
Test name
Test status
Simulation time 6819520727 ps
CPU time 14.8 seconds
Started Jul 30 05:17:11 PM PDT 24
Finished Jul 30 05:17:25 PM PDT 24
Peak memory 200012 kb
Host smart-30ebeb1a-77b4-4bf2-877c-cbc32f5824dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941961449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1941961449
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2509914880
Short name T152
Test name
Test status
Simulation time 13358519 ps
CPU time 0.57 seconds
Started Jul 30 05:18:21 PM PDT 24
Finished Jul 30 05:18:21 PM PDT 24
Peak memory 194908 kb
Host smart-c973c63e-20fe-4865-aebc-530991212d09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509914880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2509914880
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3548786102
Short name T528
Test name
Test status
Simulation time 1532252112 ps
CPU time 83.89 seconds
Started Jul 30 05:18:20 PM PDT 24
Finished Jul 30 05:19:44 PM PDT 24
Peak memory 199892 kb
Host smart-97eb9b9f-7382-4a91-80a7-94ae56b4395a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548786102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3548786102
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.276269050
Short name T197
Test name
Test status
Simulation time 485661310 ps
CPU time 7.77 seconds
Started Jul 30 05:18:19 PM PDT 24
Finished Jul 30 05:18:27 PM PDT 24
Peak memory 199848 kb
Host smart-b4f4acb5-237d-4115-b18b-e7bf17821ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276269050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.276269050
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3194063109
Short name T103
Test name
Test status
Simulation time 10238596218 ps
CPU time 464.99 seconds
Started Jul 30 05:18:19 PM PDT 24
Finished Jul 30 05:26:04 PM PDT 24
Peak memory 603320 kb
Host smart-6ea5b452-0118-4fc6-a69b-28ec71740247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194063109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3194063109
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1865283954
Short name T206
Test name
Test status
Simulation time 27393636122 ps
CPU time 169.64 seconds
Started Jul 30 05:18:46 PM PDT 24
Finished Jul 30 05:21:35 PM PDT 24
Peak memory 199964 kb
Host smart-e3aee06e-6fa0-40d5-a50a-495e25dc658b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865283954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1865283954
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3547912933
Short name T500
Test name
Test status
Simulation time 2416968096 ps
CPU time 30.35 seconds
Started Jul 30 05:18:19 PM PDT 24
Finished Jul 30 05:18:50 PM PDT 24
Peak memory 199948 kb
Host smart-3df4e8c2-d4b7-4c26-aaba-45047e67f6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547912933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3547912933
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1312765567
Short name T305
Test name
Test status
Simulation time 91188232 ps
CPU time 4.27 seconds
Started Jul 30 05:18:19 PM PDT 24
Finished Jul 30 05:18:23 PM PDT 24
Peak memory 199860 kb
Host smart-f0608534-605a-450c-93d7-6768bc20ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312765567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1312765567
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.622201906
Short name T440
Test name
Test status
Simulation time 2514477900 ps
CPU time 143.5 seconds
Started Jul 30 05:18:19 PM PDT 24
Finished Jul 30 05:20:43 PM PDT 24
Peak memory 199936 kb
Host smart-be9d8617-7c1e-49c9-b92e-f89b439a6984
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622201906 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.622201906
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2531351560
Short name T458
Test name
Test status
Simulation time 6137222231 ps
CPU time 70.12 seconds
Started Jul 30 05:18:22 PM PDT 24
Finished Jul 30 05:19:32 PM PDT 24
Peak memory 200008 kb
Host smart-05061923-78c9-4844-9f44-140109fafa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531351560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2531351560
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3282572938
Short name T271
Test name
Test status
Simulation time 14373721 ps
CPU time 0.59 seconds
Started Jul 30 05:18:26 PM PDT 24
Finished Jul 30 05:18:27 PM PDT 24
Peak memory 196700 kb
Host smart-7f3227f0-a020-4b35-a210-d8e4203aa3ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282572938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3282572938
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.609798653
Short name T531
Test name
Test status
Simulation time 9951225326 ps
CPU time 85.53 seconds
Started Jul 30 05:18:27 PM PDT 24
Finished Jul 30 05:19:53 PM PDT 24
Peak memory 216380 kb
Host smart-07e77499-8049-4202-ae13-5c1a28608838
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609798653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.609798653
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3914226374
Short name T373
Test name
Test status
Simulation time 1347195869 ps
CPU time 31.96 seconds
Started Jul 30 05:18:26 PM PDT 24
Finished Jul 30 05:18:58 PM PDT 24
Peak memory 199880 kb
Host smart-56273bc1-06e7-4d8d-8804-58928d23730d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914226374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3914226374
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1219733640
Short name T211
Test name
Test status
Simulation time 14472765398 ps
CPU time 681.41 seconds
Started Jul 30 05:18:24 PM PDT 24
Finished Jul 30 05:29:46 PM PDT 24
Peak memory 641812 kb
Host smart-2faa7e8c-a1b4-4d4a-b539-27322b837daa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219733640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1219733640
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2019409343
Short name T392
Test name
Test status
Simulation time 4140288239 ps
CPU time 64.62 seconds
Started Jul 30 05:18:24 PM PDT 24
Finished Jul 30 05:19:29 PM PDT 24
Peak memory 200024 kb
Host smart-d57e7c31-8a68-4339-87fa-85ef42c45ef7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019409343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2019409343
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.115425858
Short name T408
Test name
Test status
Simulation time 59809042085 ps
CPU time 208.69 seconds
Started Jul 30 05:18:22 PM PDT 24
Finished Jul 30 05:21:51 PM PDT 24
Peak memory 216380 kb
Host smart-6cff036c-117c-4d38-8f19-9b8b83be2768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115425858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.115425858
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.710858240
Short name T405
Test name
Test status
Simulation time 165900654 ps
CPU time 7.55 seconds
Started Jul 30 05:18:19 PM PDT 24
Finished Jul 30 05:18:27 PM PDT 24
Peak memory 199856 kb
Host smart-b4c2a8f1-ceba-4ff6-815e-4ae79eff8aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710858240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.710858240
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3024695935
Short name T481
Test name
Test status
Simulation time 109863702157 ps
CPU time 2774.51 seconds
Started Jul 30 05:18:23 PM PDT 24
Finished Jul 30 06:04:38 PM PDT 24
Peak memory 767516 kb
Host smart-ac1eafd6-433b-470a-9b53-02a21bada65e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024695935 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3024695935
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.941328478
Short name T331
Test name
Test status
Simulation time 1187670457 ps
CPU time 34.07 seconds
Started Jul 30 05:18:25 PM PDT 24
Finished Jul 30 05:18:59 PM PDT 24
Peak memory 199904 kb
Host smart-27341159-4c63-4e43-820b-4385a578ef42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941328478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.941328478
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3743437637
Short name T347
Test name
Test status
Simulation time 40218099 ps
CPU time 0.6 seconds
Started Jul 30 05:18:34 PM PDT 24
Finished Jul 30 05:18:35 PM PDT 24
Peak memory 195940 kb
Host smart-69ec5e74-e98b-47dd-b357-2115f96ed2e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743437637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3743437637
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1762668591
Short name T143
Test name
Test status
Simulation time 3177250729 ps
CPU time 50.18 seconds
Started Jul 30 05:18:29 PM PDT 24
Finished Jul 30 05:19:20 PM PDT 24
Peak memory 200008 kb
Host smart-45425bd6-9179-49f4-8d6e-e58a0e811109
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762668591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1762668591
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3786377
Short name T358
Test name
Test status
Simulation time 1604531053 ps
CPU time 8.28 seconds
Started Jul 30 05:18:35 PM PDT 24
Finished Jul 30 05:18:43 PM PDT 24
Peak memory 199948 kb
Host smart-c3e8c67d-2f63-4a62-8182-750f5dc3cd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3786377
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4205304676
Short name T394
Test name
Test status
Simulation time 6589580855 ps
CPU time 1106.5 seconds
Started Jul 30 05:18:31 PM PDT 24
Finished Jul 30 05:36:57 PM PDT 24
Peak memory 780568 kb
Host smart-c5db8fb0-6efc-4296-91ba-a022088e48a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205304676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4205304676
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.485762886
Short name T237
Test name
Test status
Simulation time 2554683122 ps
CPU time 35 seconds
Started Jul 30 05:18:30 PM PDT 24
Finished Jul 30 05:19:05 PM PDT 24
Peak memory 199948 kb
Host smart-845845d4-94b5-45cf-b992-f53c884d1520
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485762886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.485762886
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2232107545
Short name T516
Test name
Test status
Simulation time 2560582818 ps
CPU time 139.28 seconds
Started Jul 30 05:18:30 PM PDT 24
Finished Jul 30 05:20:49 PM PDT 24
Peak memory 200052 kb
Host smart-f9fdad55-70c6-4711-9a56-14345b7ab3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232107545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2232107545
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4210637360
Short name T383
Test name
Test status
Simulation time 526863764 ps
CPU time 11.6 seconds
Started Jul 30 05:18:29 PM PDT 24
Finished Jul 30 05:18:41 PM PDT 24
Peak memory 199856 kb
Host smart-e87155a1-8fa6-4c2e-95e4-3d464d780612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210637360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4210637360
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2306257861
Short name T466
Test name
Test status
Simulation time 55988541051 ps
CPU time 1633.9 seconds
Started Jul 30 05:18:31 PM PDT 24
Finished Jul 30 05:45:45 PM PDT 24
Peak memory 621264 kb
Host smart-a20d2b44-fd39-40aa-be3b-279f0dfae193
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306257861 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2306257861
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2463133003
Short name T311
Test name
Test status
Simulation time 3138348787 ps
CPU time 11.53 seconds
Started Jul 30 05:18:35 PM PDT 24
Finished Jul 30 05:18:46 PM PDT 24
Peak memory 200004 kb
Host smart-60837ff8-be32-4a60-aa2c-fe7fd4e919a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463133003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2463133003
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.710166951
Short name T247
Test name
Test status
Simulation time 40540984 ps
CPU time 0.59 seconds
Started Jul 30 05:18:33 PM PDT 24
Finished Jul 30 05:18:34 PM PDT 24
Peak memory 194940 kb
Host smart-2c6ad375-6fbf-4e51-b355-066fcc0d32bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710166951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.710166951
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1574366558
Short name T355
Test name
Test status
Simulation time 972127577 ps
CPU time 29.05 seconds
Started Jul 30 05:18:35 PM PDT 24
Finished Jul 30 05:19:05 PM PDT 24
Peak memory 199876 kb
Host smart-ef3c844d-6b15-45ad-95b2-96f432e4df3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574366558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1574366558
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.16795563
Short name T207
Test name
Test status
Simulation time 745713266 ps
CPU time 10.67 seconds
Started Jul 30 05:18:34 PM PDT 24
Finished Jul 30 05:18:44 PM PDT 24
Peak memory 199880 kb
Host smart-6c92e1f1-e0a3-4530-aaa2-6a03dd8c4878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16795563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.16795563
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2312127858
Short name T488
Test name
Test status
Simulation time 3295891290 ps
CPU time 640.44 seconds
Started Jul 30 05:18:33 PM PDT 24
Finished Jul 30 05:29:14 PM PDT 24
Peak memory 659532 kb
Host smart-3a25e3f2-df24-4178-b4a5-f6040d84b0ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2312127858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2312127858
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2541076944
Short name T348
Test name
Test status
Simulation time 12681473112 ps
CPU time 161.17 seconds
Started Jul 30 05:18:33 PM PDT 24
Finished Jul 30 05:21:14 PM PDT 24
Peak memory 199988 kb
Host smart-8bd262f0-ec5f-44f9-8d4a-e3ef8dd88e94
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541076944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2541076944
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3793674639
Short name T436
Test name
Test status
Simulation time 9821964385 ps
CPU time 39.74 seconds
Started Jul 30 05:18:35 PM PDT 24
Finished Jul 30 05:19:15 PM PDT 24
Peak memory 200016 kb
Host smart-1ea5cd84-be87-4773-91d1-d7f0a160915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793674639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3793674639
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1517979280
Short name T203
Test name
Test status
Simulation time 2264010725 ps
CPU time 12.47 seconds
Started Jul 30 05:18:29 PM PDT 24
Finished Jul 30 05:18:41 PM PDT 24
Peak memory 199924 kb
Host smart-665bbac1-a880-4501-b09d-1d4b483ca99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517979280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1517979280
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1225442265
Short name T294
Test name
Test status
Simulation time 3838225081 ps
CPU time 257.1 seconds
Started Jul 30 05:18:32 PM PDT 24
Finished Jul 30 05:22:49 PM PDT 24
Peak memory 620264 kb
Host smart-f8984041-3878-4b5c-ad78-10f6f8dcb512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225442265 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1225442265
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1866348220
Short name T497
Test name
Test status
Simulation time 2272079431 ps
CPU time 35.26 seconds
Started Jul 30 05:18:33 PM PDT 24
Finished Jul 30 05:19:08 PM PDT 24
Peak memory 199952 kb
Host smart-8cea5f1f-5f01-4f21-9d7b-1fb9196c8bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866348220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1866348220
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.23828241
Short name T167
Test name
Test status
Simulation time 30783757 ps
CPU time 0.63 seconds
Started Jul 30 05:18:39 PM PDT 24
Finished Jul 30 05:18:40 PM PDT 24
Peak memory 196128 kb
Host smart-cc0a9761-ec5f-41fb-8152-d55fcc2e1a02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23828241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.23828241
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2004955372
Short name T221
Test name
Test status
Simulation time 1237013810 ps
CPU time 58.44 seconds
Started Jul 30 05:18:34 PM PDT 24
Finished Jul 30 05:19:32 PM PDT 24
Peak memory 199908 kb
Host smart-a7132cd3-9373-44ef-8ab2-94dcf7b1bf0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004955372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2004955372
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2595634333
Short name T462
Test name
Test status
Simulation time 898945961 ps
CPU time 47.11 seconds
Started Jul 30 05:18:34 PM PDT 24
Finished Jul 30 05:19:21 PM PDT 24
Peak memory 199896 kb
Host smart-267af92c-81f9-4787-92e0-a8b4b544556d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595634333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2595634333
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3491910027
Short name T67
Test name
Test status
Simulation time 5375734226 ps
CPU time 944.16 seconds
Started Jul 30 05:18:34 PM PDT 24
Finished Jul 30 05:34:19 PM PDT 24
Peak memory 682388 kb
Host smart-5c32e0fe-f5af-445e-8ffe-b3eb0d7f9a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491910027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3491910027
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1033944793
Short name T388
Test name
Test status
Simulation time 2495704109 ps
CPU time 106.3 seconds
Started Jul 30 05:18:32 PM PDT 24
Finished Jul 30 05:20:19 PM PDT 24
Peak memory 200052 kb
Host smart-9a431539-eade-4c24-8154-17d9ecc96f08
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033944793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1033944793
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1802785821
Short name T191
Test name
Test status
Simulation time 5495155042 ps
CPU time 38.77 seconds
Started Jul 30 05:18:33 PM PDT 24
Finished Jul 30 05:19:11 PM PDT 24
Peak memory 199996 kb
Host smart-af675cd7-bbff-44dd-b685-724355ef3656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802785821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1802785821
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3526885909
Short name T276
Test name
Test status
Simulation time 908012936 ps
CPU time 6.18 seconds
Started Jul 30 05:18:33 PM PDT 24
Finished Jul 30 05:18:39 PM PDT 24
Peak memory 199884 kb
Host smart-e4463f13-17d3-49d5-937a-ce7c0369c92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526885909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3526885909
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2475168496
Short name T5
Test name
Test status
Simulation time 28670917398 ps
CPU time 1678.19 seconds
Started Jul 30 05:18:36 PM PDT 24
Finished Jul 30 05:46:35 PM PDT 24
Peak memory 765124 kb
Host smart-1b8ff309-0b5a-4ab8-8584-464b6eec6a35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475168496 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2475168496
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.553521225
Short name T385
Test name
Test status
Simulation time 34133982569 ps
CPU time 126.28 seconds
Started Jul 30 05:18:37 PM PDT 24
Finished Jul 30 05:20:43 PM PDT 24
Peak memory 200088 kb
Host smart-8d0a30d0-5e1c-40ff-82c8-f66dbef5e753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553521225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.553521225
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.141784619
Short name T71
Test name
Test status
Simulation time 39874569 ps
CPU time 0.56 seconds
Started Jul 30 05:18:37 PM PDT 24
Finished Jul 30 05:18:38 PM PDT 24
Peak memory 194904 kb
Host smart-450e0b66-01c9-4147-9cf2-e01790d823f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141784619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.141784619
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.975732043
Short name T33
Test name
Test status
Simulation time 2476958558 ps
CPU time 72.89 seconds
Started Jul 30 05:18:39 PM PDT 24
Finished Jul 30 05:19:52 PM PDT 24
Peak memory 200044 kb
Host smart-6299ef67-281b-4986-abee-a5d691d9b4e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975732043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.975732043
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3796414175
Short name T357
Test name
Test status
Simulation time 4052489118 ps
CPU time 13.08 seconds
Started Jul 30 05:18:38 PM PDT 24
Finished Jul 30 05:18:51 PM PDT 24
Peak memory 199996 kb
Host smart-e4a10df9-bcbb-4ba6-a365-249572fc0a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796414175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3796414175
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2483098369
Short name T496
Test name
Test status
Simulation time 2389840851 ps
CPU time 263.28 seconds
Started Jul 30 05:18:38 PM PDT 24
Finished Jul 30 05:23:01 PM PDT 24
Peak memory 630472 kb
Host smart-1b6f9cbe-60fc-4e93-837e-65d79ba1b32d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483098369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2483098369
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3643691169
Short name T36
Test name
Test status
Simulation time 3698607927 ps
CPU time 60.29 seconds
Started Jul 30 05:18:37 PM PDT 24
Finished Jul 30 05:19:38 PM PDT 24
Peak memory 199968 kb
Host smart-d34f911b-141e-4242-b17b-b4dfe42905fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643691169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3643691169
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1026396755
Short name T157
Test name
Test status
Simulation time 9735611724 ps
CPU time 106.63 seconds
Started Jul 30 05:18:39 PM PDT 24
Finished Jul 30 05:20:26 PM PDT 24
Peak memory 200020 kb
Host smart-d3453b45-0adb-4408-babc-0449699008c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026396755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1026396755
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.346110612
Short name T304
Test name
Test status
Simulation time 109822358 ps
CPU time 4.9 seconds
Started Jul 30 05:18:38 PM PDT 24
Finished Jul 30 05:18:43 PM PDT 24
Peak memory 199892 kb
Host smart-91a9ad01-4f03-40e2-93a1-3f2c43e0949c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346110612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.346110612
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2764175498
Short name T381
Test name
Test status
Simulation time 12483376937 ps
CPU time 56.07 seconds
Started Jul 30 05:18:37 PM PDT 24
Finished Jul 30 05:19:33 PM PDT 24
Peak memory 200028 kb
Host smart-c53aee04-5e98-4df6-983d-80eed4a4ea58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764175498 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2764175498
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.4222648923
Short name T235
Test name
Test status
Simulation time 6097991663 ps
CPU time 116.44 seconds
Started Jul 30 05:18:38 PM PDT 24
Finished Jul 30 05:20:34 PM PDT 24
Peak memory 200004 kb
Host smart-a518b15e-137a-4fdb-bea1-99a411443dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222648923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4222648923
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2016702858
Short name T476
Test name
Test status
Simulation time 17605723 ps
CPU time 0.61 seconds
Started Jul 30 05:18:43 PM PDT 24
Finished Jul 30 05:18:44 PM PDT 24
Peak memory 195960 kb
Host smart-5e928745-8261-4bc7-b116-7a8e49601ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016702858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2016702858
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3540309414
Short name T379
Test name
Test status
Simulation time 1442768080 ps
CPU time 55.31 seconds
Started Jul 30 05:18:41 PM PDT 24
Finished Jul 30 05:19:36 PM PDT 24
Peak memory 199872 kb
Host smart-62f5cffa-657c-4d5d-9c12-21901fbe3482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3540309414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3540309414
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.512858908
Short name T420
Test name
Test status
Simulation time 1352842307 ps
CPU time 24.64 seconds
Started Jul 30 05:18:44 PM PDT 24
Finished Jul 30 05:19:09 PM PDT 24
Peak memory 199880 kb
Host smart-0aab24a9-d464-44f4-8b0b-307784ef559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512858908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.512858908
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2891702127
Short name T391
Test name
Test status
Simulation time 4755559801 ps
CPU time 827.09 seconds
Started Jul 30 05:18:40 PM PDT 24
Finished Jul 30 05:32:28 PM PDT 24
Peak memory 695316 kb
Host smart-2dfdbdf7-0385-43ad-9c08-1a6996d11917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2891702127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2891702127
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2375200507
Short name T155
Test name
Test status
Simulation time 5316388474 ps
CPU time 68.78 seconds
Started Jul 30 05:18:44 PM PDT 24
Finished Jul 30 05:19:53 PM PDT 24
Peak memory 200012 kb
Host smart-e9674dbe-a610-44b7-96f6-dbf46db9f386
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375200507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2375200507
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2044723235
Short name T520
Test name
Test status
Simulation time 6795317376 ps
CPU time 44.71 seconds
Started Jul 30 05:18:42 PM PDT 24
Finished Jul 30 05:19:27 PM PDT 24
Peak memory 200076 kb
Host smart-d4eb313d-962a-428e-b37e-c19c64ed18c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044723235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2044723235
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1735848162
Short name T378
Test name
Test status
Simulation time 644831785 ps
CPU time 6.22 seconds
Started Jul 30 05:18:44 PM PDT 24
Finished Jul 30 05:18:50 PM PDT 24
Peak memory 199888 kb
Host smart-d447ef70-c574-4639-b7ad-0918e13459ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735848162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1735848162
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.428800022
Short name T529
Test name
Test status
Simulation time 140454974624 ps
CPU time 789.13 seconds
Started Jul 30 05:18:42 PM PDT 24
Finished Jul 30 05:31:51 PM PDT 24
Peak memory 635684 kb
Host smart-f68c0edd-8a11-465e-bb75-98d9c9105763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428800022 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.428800022
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2894105023
Short name T464
Test name
Test status
Simulation time 4373991872 ps
CPU time 78.8 seconds
Started Jul 30 05:18:43 PM PDT 24
Finished Jul 30 05:20:02 PM PDT 24
Peak memory 199984 kb
Host smart-ec242317-a750-4ce3-84e9-756fd734709e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894105023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2894105023
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.614158705
Short name T254
Test name
Test status
Simulation time 43417385 ps
CPU time 0.57 seconds
Started Jul 30 05:18:48 PM PDT 24
Finished Jul 30 05:18:48 PM PDT 24
Peak memory 194920 kb
Host smart-0bbab7c0-61a2-4723-a3d0-2afa1508dae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614158705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.614158705
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1235671300
Short name T43
Test name
Test status
Simulation time 2696241313 ps
CPU time 36.42 seconds
Started Jul 30 05:18:44 PM PDT 24
Finished Jul 30 05:19:20 PM PDT 24
Peak memory 199992 kb
Host smart-b0e3fd21-6a00-48e7-bf7a-7041c570b728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235671300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1235671300
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.612115706
Short name T232
Test name
Test status
Simulation time 427688236 ps
CPU time 23.6 seconds
Started Jul 30 05:18:43 PM PDT 24
Finished Jul 30 05:19:07 PM PDT 24
Peak memory 199876 kb
Host smart-97ece44a-6b9f-48cd-a0d9-4b391ca8f205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612115706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.612115706
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2448923533
Short name T174
Test name
Test status
Simulation time 24465682141 ps
CPU time 550.32 seconds
Started Jul 30 05:18:42 PM PDT 24
Finished Jul 30 05:27:52 PM PDT 24
Peak memory 649620 kb
Host smart-c04a36cf-91fe-4def-8a2a-ed9eab112177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2448923533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2448923533
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.493291696
Short name T17
Test name
Test status
Simulation time 9367640435 ps
CPU time 137.12 seconds
Started Jul 30 05:18:48 PM PDT 24
Finished Jul 30 05:21:05 PM PDT 24
Peak memory 200004 kb
Host smart-b543fd33-dc85-47a4-8b06-843b5d29bd5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493291696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.493291696
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1248090996
Short name T4
Test name
Test status
Simulation time 23326168977 ps
CPU time 52.22 seconds
Started Jul 30 05:18:40 PM PDT 24
Finished Jul 30 05:19:33 PM PDT 24
Peak memory 199992 kb
Host smart-78e27a33-5781-49cf-a416-e6c2cfd7c305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248090996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1248090996
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2310525402
Short name T84
Test name
Test status
Simulation time 1618274948 ps
CPU time 11.32 seconds
Started Jul 30 05:18:41 PM PDT 24
Finished Jul 30 05:18:52 PM PDT 24
Peak memory 199808 kb
Host smart-48c4eb65-c99c-4689-9801-0b5ff87a95f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310525402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2310525402
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1657454367
Short name T363
Test name
Test status
Simulation time 274596506331 ps
CPU time 2957.89 seconds
Started Jul 30 05:18:48 PM PDT 24
Finished Jul 30 06:08:07 PM PDT 24
Peak memory 776460 kb
Host smart-8ddd2b29-d1de-4dd4-8381-7538dcf7a21a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657454367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1657454367
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2394021112
Short name T286
Test name
Test status
Simulation time 5203549066 ps
CPU time 47.28 seconds
Started Jul 30 05:18:46 PM PDT 24
Finished Jul 30 05:19:33 PM PDT 24
Peak memory 199996 kb
Host smart-c65c393b-cc30-4b24-ae2c-c119ff16399f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394021112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2394021112
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3864424410
Short name T223
Test name
Test status
Simulation time 21886126 ps
CPU time 0.59 seconds
Started Jul 30 05:18:50 PM PDT 24
Finished Jul 30 05:18:51 PM PDT 24
Peak memory 195968 kb
Host smart-0cc08ba5-de83-426a-aff8-2c2757d62fb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864424410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3864424410
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.160744542
Short name T371
Test name
Test status
Simulation time 5006334950 ps
CPU time 79.95 seconds
Started Jul 30 05:18:46 PM PDT 24
Finished Jul 30 05:20:06 PM PDT 24
Peak memory 200152 kb
Host smart-7fafa9dc-0840-4fa1-ad6b-bfa7fe6284bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160744542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.160744542
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1020667972
Short name T16
Test name
Test status
Simulation time 463416216 ps
CPU time 9.6 seconds
Started Jul 30 05:18:47 PM PDT 24
Finished Jul 30 05:18:57 PM PDT 24
Peak memory 199804 kb
Host smart-d9fcafd1-83d9-463a-9b4d-01f95f300458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020667972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1020667972
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2742145814
Short name T477
Test name
Test status
Simulation time 5263699365 ps
CPU time 158.26 seconds
Started Jul 30 05:18:46 PM PDT 24
Finished Jul 30 05:21:25 PM PDT 24
Peak memory 341964 kb
Host smart-5c927bef-2196-42a6-8514-c1e53223ed79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742145814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2742145814
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.121092715
Short name T139
Test name
Test status
Simulation time 32560138707 ps
CPU time 202.98 seconds
Started Jul 30 05:18:50 PM PDT 24
Finished Jul 30 05:22:13 PM PDT 24
Peak memory 199972 kb
Host smart-72709567-d9ba-4b8a-9421-cc143125d212
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121092715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.121092715
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3512807704
Short name T246
Test name
Test status
Simulation time 21280671354 ps
CPU time 92.11 seconds
Started Jul 30 05:18:47 PM PDT 24
Finished Jul 30 05:20:19 PM PDT 24
Peak memory 200052 kb
Host smart-0a6bf9b7-338a-4ed2-bf04-ea8b031e7d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512807704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3512807704
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1168430368
Short name T204
Test name
Test status
Simulation time 663944958 ps
CPU time 11.38 seconds
Started Jul 30 05:18:46 PM PDT 24
Finished Jul 30 05:18:57 PM PDT 24
Peak memory 199944 kb
Host smart-a12f4fce-b40d-4161-9212-f984f0482817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168430368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1168430368
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1816478158
Short name T455
Test name
Test status
Simulation time 69954452655 ps
CPU time 1748.58 seconds
Started Jul 30 05:18:49 PM PDT 24
Finished Jul 30 05:47:58 PM PDT 24
Peak memory 719656 kb
Host smart-8de17e8e-aad2-456c-9fc1-2df360b8e4b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816478158 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1816478158
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.505900153
Short name T308
Test name
Test status
Simulation time 4063846045 ps
CPU time 111.68 seconds
Started Jul 30 05:18:50 PM PDT 24
Finished Jul 30 05:20:42 PM PDT 24
Peak memory 199948 kb
Host smart-1574dc47-58cb-43c4-853a-595da4db10e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505900153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.505900153
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3807288663
Short name T409
Test name
Test status
Simulation time 20933662 ps
CPU time 0.59 seconds
Started Jul 30 05:18:58 PM PDT 24
Finished Jul 30 05:18:58 PM PDT 24
Peak memory 195960 kb
Host smart-6822ddbd-aa99-4974-a2b8-61ae200e7ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807288663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3807288663
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1130962649
Short name T218
Test name
Test status
Simulation time 293573683 ps
CPU time 18.41 seconds
Started Jul 30 05:18:51 PM PDT 24
Finished Jul 30 05:19:09 PM PDT 24
Peak memory 199924 kb
Host smart-e5bb4642-8744-4cc7-8824-ef6b9d334e76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1130962649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1130962649
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3906530355
Short name T1
Test name
Test status
Simulation time 5935661537 ps
CPU time 19.51 seconds
Started Jul 30 05:18:58 PM PDT 24
Finished Jul 30 05:19:17 PM PDT 24
Peak memory 200064 kb
Host smart-7703a48e-8984-49ff-91d0-205683836ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906530355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3906530355
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3167217986
Short name T185
Test name
Test status
Simulation time 19610587625 ps
CPU time 837.5 seconds
Started Jul 30 05:18:51 PM PDT 24
Finished Jul 30 05:32:49 PM PDT 24
Peak memory 701196 kb
Host smart-209c6877-eaf5-41d7-82b3-b6f9a50ef501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167217986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3167217986
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1560553484
Short name T398
Test name
Test status
Simulation time 37294911339 ps
CPU time 141.94 seconds
Started Jul 30 05:18:57 PM PDT 24
Finished Jul 30 05:21:19 PM PDT 24
Peak memory 200064 kb
Host smart-d73d741c-9b8a-47f6-ae76-a4751f40ea80
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560553484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1560553484
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.669509440
Short name T216
Test name
Test status
Simulation time 23397274586 ps
CPU time 157.35 seconds
Started Jul 30 05:18:52 PM PDT 24
Finished Jul 30 05:21:29 PM PDT 24
Peak memory 200060 kb
Host smart-91ff2cdb-18ae-4f76-8811-b4c7a77ad531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669509440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.669509440
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2492721303
Short name T428
Test name
Test status
Simulation time 1646985796 ps
CPU time 13.74 seconds
Started Jul 30 05:18:49 PM PDT 24
Finished Jul 30 05:19:03 PM PDT 24
Peak memory 199896 kb
Host smart-334ab56b-0eb9-439b-bb00-c87aeddd2460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492721303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2492721303
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1790423263
Short name T134
Test name
Test status
Simulation time 63337158052 ps
CPU time 1176.43 seconds
Started Jul 30 05:18:58 PM PDT 24
Finished Jul 30 05:38:34 PM PDT 24
Peak memory 732420 kb
Host smart-8740e056-2c7a-4dcf-932b-55e138dcfb1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790423263 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1790423263
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2490501721
Short name T309
Test name
Test status
Simulation time 3839948031 ps
CPU time 71.1 seconds
Started Jul 30 05:18:58 PM PDT 24
Finished Jul 30 05:20:09 PM PDT 24
Peak memory 200016 kb
Host smart-57836807-7513-422d-a2da-180be6b218cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490501721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2490501721
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2369769457
Short name T59
Test name
Test status
Simulation time 10603867 ps
CPU time 0.55 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:17:18 PM PDT 24
Peak memory 194900 kb
Host smart-1d1ac4e3-7481-42c2-a55f-c4434e872b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369769457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2369769457
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.303765983
Short name T34
Test name
Test status
Simulation time 1991021446 ps
CPU time 56.34 seconds
Started Jul 30 05:17:07 PM PDT 24
Finished Jul 30 05:18:04 PM PDT 24
Peak memory 199868 kb
Host smart-71e3c49b-5f55-46a7-b668-a85f02e5d1eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303765983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.303765983
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.786805137
Short name T289
Test name
Test status
Simulation time 2390949659 ps
CPU time 384.04 seconds
Started Jul 30 05:17:10 PM PDT 24
Finished Jul 30 05:23:34 PM PDT 24
Peak memory 450944 kb
Host smart-108cfafc-ffeb-4851-b28a-281c189ccba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786805137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.786805137
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1768989644
Short name T453
Test name
Test status
Simulation time 46830688 ps
CPU time 2.62 seconds
Started Jul 30 05:17:11 PM PDT 24
Finished Jul 30 05:17:13 PM PDT 24
Peak memory 199820 kb
Host smart-9d4a42d1-81aa-4196-b474-54f61fded18d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768989644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1768989644
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1554006051
Short name T366
Test name
Test status
Simulation time 6927550157 ps
CPU time 166.64 seconds
Started Jul 30 05:17:09 PM PDT 24
Finished Jul 30 05:19:55 PM PDT 24
Peak memory 199968 kb
Host smart-83727ce0-534a-4300-a011-f6e3d08429ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554006051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1554006051
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1727162459
Short name T49
Test name
Test status
Simulation time 89020448 ps
CPU time 0.96 seconds
Started Jul 30 05:17:17 PM PDT 24
Finished Jul 30 05:17:18 PM PDT 24
Peak memory 219512 kb
Host smart-0092c8c4-9209-4d0c-b2a5-67c0efc4bbfd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727162459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1727162459
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1470714064
Short name T198
Test name
Test status
Simulation time 723240126 ps
CPU time 7.4 seconds
Started Jul 30 05:17:09 PM PDT 24
Finished Jul 30 05:17:17 PM PDT 24
Peak memory 199860 kb
Host smart-01f5042b-34ba-4372-8d51-1b3ae08f5fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470714064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1470714064
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.4007332220
Short name T242
Test name
Test status
Simulation time 49425012987 ps
CPU time 541.15 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:26:20 PM PDT 24
Peak memory 570916 kb
Host smart-1ce43610-b775-46a3-bc7f-b7da599f7a63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007332220 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.4007332220
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1402787548
Short name T199
Test name
Test status
Simulation time 4333918590 ps
CPU time 73.57 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:18:32 PM PDT 24
Peak memory 199996 kb
Host smart-d8f289de-0e0a-4fd2-9de8-851570ce18c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1402787548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1402787548
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.3815600126
Short name T259
Test name
Test status
Simulation time 3734706876 ps
CPU time 58.11 seconds
Started Jul 30 05:17:21 PM PDT 24
Finished Jul 30 05:18:19 PM PDT 24
Peak memory 200036 kb
Host smart-b1f4cfed-4078-4d8c-bfa8-196344ab1d5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3815600126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3815600126
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3153520101
Short name T39
Test name
Test status
Simulation time 7907450762 ps
CPU time 119.31 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:19:17 PM PDT 24
Peak memory 200012 kb
Host smart-16c12bf9-2182-4561-ae93-89a867d717d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3153520101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3153520101
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3103198127
Short name T164
Test name
Test status
Simulation time 108911177428 ps
CPU time 713.63 seconds
Started Jul 30 05:17:19 PM PDT 24
Finished Jul 30 05:29:13 PM PDT 24
Peak memory 199996 kb
Host smart-2088e2ef-a090-4fe4-ac62-d35f455192ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3103198127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3103198127
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2393741824
Short name T182
Test name
Test status
Simulation time 250801822838 ps
CPU time 2324.4 seconds
Started Jul 30 05:17:17 PM PDT 24
Finished Jul 30 05:56:02 PM PDT 24
Peak memory 215568 kb
Host smart-8daab1b4-cf7a-45e8-846d-3a85b637a6d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2393741824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2393741824
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3776480064
Short name T132
Test name
Test status
Simulation time 39263071282 ps
CPU time 1992.11 seconds
Started Jul 30 05:17:20 PM PDT 24
Finished Jul 30 05:50:33 PM PDT 24
Peak memory 215796 kb
Host smart-1f8a75e4-ea0a-4928-a783-392393ee8f3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3776480064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3776480064
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3645243278
Short name T310
Test name
Test status
Simulation time 41448665775 ps
CPU time 107.74 seconds
Started Jul 30 05:17:17 PM PDT 24
Finished Jul 30 05:19:05 PM PDT 24
Peak memory 199952 kb
Host smart-47623420-3f2b-4477-89b4-7679d20a9d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645243278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3645243278
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2828703241
Short name T507
Test name
Test status
Simulation time 131293377 ps
CPU time 0.57 seconds
Started Jul 30 05:19:03 PM PDT 24
Finished Jul 30 05:19:03 PM PDT 24
Peak memory 194964 kb
Host smart-8d12f235-9a6f-49be-b2a7-8b7a9afc048a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828703241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2828703241
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3558081120
Short name T368
Test name
Test status
Simulation time 3038873011 ps
CPU time 38.36 seconds
Started Jul 30 05:18:56 PM PDT 24
Finished Jul 30 05:19:34 PM PDT 24
Peak memory 199972 kb
Host smart-b6c43fa4-cbba-4241-9601-5c48c91fdce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3558081120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3558081120
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3728188823
Short name T387
Test name
Test status
Simulation time 801598462 ps
CPU time 42.51 seconds
Started Jul 30 05:19:00 PM PDT 24
Finished Jul 30 05:19:43 PM PDT 24
Peak memory 199808 kb
Host smart-c3185765-4a89-41ea-9cb1-3b717b81746e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728188823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3728188823
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3910970934
Short name T202
Test name
Test status
Simulation time 4490007194 ps
CPU time 371.33 seconds
Started Jul 30 05:18:56 PM PDT 24
Finished Jul 30 05:25:08 PM PDT 24
Peak memory 679916 kb
Host smart-b43b128e-b4d2-45ce-bade-6cca3fd16d78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910970934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3910970934
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1611472266
Short name T190
Test name
Test status
Simulation time 9174338020 ps
CPU time 167.46 seconds
Started Jul 30 05:18:56 PM PDT 24
Finished Jul 30 05:21:44 PM PDT 24
Peak memory 200016 kb
Host smart-02341bf4-e2f9-48ea-b964-c588d7ececad
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611472266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1611472266
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3666501142
Short name T301
Test name
Test status
Simulation time 1438478652 ps
CPU time 75.91 seconds
Started Jul 30 05:18:56 PM PDT 24
Finished Jul 30 05:20:12 PM PDT 24
Peak memory 199860 kb
Host smart-8f43da48-3806-42f9-b40a-3bc74a2a6631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666501142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3666501142
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3003724887
Short name T339
Test name
Test status
Simulation time 16886237414 ps
CPU time 14.28 seconds
Started Jul 30 05:18:58 PM PDT 24
Finished Jul 30 05:19:12 PM PDT 24
Peak memory 200164 kb
Host smart-07deeb91-4c71-4df6-b13a-08bed517313a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003724887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3003724887
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.531580626
Short name T370
Test name
Test status
Simulation time 7866083921 ps
CPU time 47.83 seconds
Started Jul 30 05:19:02 PM PDT 24
Finished Jul 30 05:19:50 PM PDT 24
Peak memory 199972 kb
Host smart-05519fc5-a5c4-4a35-9621-49e9fe9d2d28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531580626 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.531580626
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2090149062
Short name T418
Test name
Test status
Simulation time 12187452436 ps
CPU time 164.77 seconds
Started Jul 30 05:19:00 PM PDT 24
Finished Jul 30 05:21:45 PM PDT 24
Peak memory 200144 kb
Host smart-824a24ca-f288-4174-b110-a9876153f6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090149062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2090149062
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2611976764
Short name T213
Test name
Test status
Simulation time 14320095 ps
CPU time 0.57 seconds
Started Jul 30 05:19:00 PM PDT 24
Finished Jul 30 05:19:00 PM PDT 24
Peak memory 194900 kb
Host smart-ad1f522a-c3bf-4600-8d66-a8f897a7a9eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611976764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2611976764
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4115206808
Short name T205
Test name
Test status
Simulation time 1917940670 ps
CPU time 66.14 seconds
Started Jul 30 05:19:00 PM PDT 24
Finished Jul 30 05:20:06 PM PDT 24
Peak memory 199928 kb
Host smart-c47712e1-f20d-4548-adbc-11e52379b35d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115206808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4115206808
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1341194508
Short name T194
Test name
Test status
Simulation time 11782621101 ps
CPU time 40.05 seconds
Started Jul 30 05:19:00 PM PDT 24
Finished Jul 30 05:19:40 PM PDT 24
Peak memory 216404 kb
Host smart-2f64eb4b-9ea5-4385-b007-674bb869f253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341194508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1341194508
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2583481852
Short name T403
Test name
Test status
Simulation time 1451189014 ps
CPU time 300.98 seconds
Started Jul 30 05:19:00 PM PDT 24
Finished Jul 30 05:24:02 PM PDT 24
Peak memory 459224 kb
Host smart-da70d119-c043-4625-99fd-679e0ef48341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583481852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2583481852
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3824476218
Short name T469
Test name
Test status
Simulation time 1631247571 ps
CPU time 86.5 seconds
Started Jul 30 05:19:06 PM PDT 24
Finished Jul 30 05:20:32 PM PDT 24
Peak memory 199952 kb
Host smart-27755105-9a01-47fd-8941-014f33d26277
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824476218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3824476218
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3287813936
Short name T460
Test name
Test status
Simulation time 7851664277 ps
CPU time 101.25 seconds
Started Jul 30 05:19:04 PM PDT 24
Finished Jul 30 05:20:46 PM PDT 24
Peak memory 200040 kb
Host smart-2b1771e8-2b84-4cd2-bbae-be0bf6b0aff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287813936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3287813936
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.529996665
Short name T3
Test name
Test status
Simulation time 185457924 ps
CPU time 2.33 seconds
Started Jul 30 05:18:59 PM PDT 24
Finished Jul 30 05:19:02 PM PDT 24
Peak memory 199872 kb
Host smart-5dcc61be-0daa-4eaf-810f-d49e6531b075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529996665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.529996665
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.962528106
Short name T85
Test name
Test status
Simulation time 66635770406 ps
CPU time 4859.51 seconds
Started Jul 30 05:19:00 PM PDT 24
Finished Jul 30 06:40:00 PM PDT 24
Peak memory 861392 kb
Host smart-d8a54718-d56b-4ac5-9e89-355a1cb03c9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962528106 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.962528106
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.463705284
Short name T346
Test name
Test status
Simulation time 454733002 ps
CPU time 19.59 seconds
Started Jul 30 05:18:59 PM PDT 24
Finished Jul 30 05:19:19 PM PDT 24
Peak memory 199924 kb
Host smart-394ac79b-0a25-403f-a144-355f930291ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463705284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.463705284
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2096669758
Short name T446
Test name
Test status
Simulation time 16893505 ps
CPU time 0.63 seconds
Started Jul 30 05:19:04 PM PDT 24
Finished Jul 30 05:19:05 PM PDT 24
Peak memory 196612 kb
Host smart-55dc43ef-2524-4a41-807c-aefd64869494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096669758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2096669758
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3327955610
Short name T299
Test name
Test status
Simulation time 172222313 ps
CPU time 5.08 seconds
Started Jul 30 05:19:05 PM PDT 24
Finished Jul 30 05:19:11 PM PDT 24
Peak memory 199908 kb
Host smart-f25fc81f-155b-49cc-a2c9-0302750e2182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327955610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3327955610
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1832825428
Short name T330
Test name
Test status
Simulation time 14470557280 ps
CPU time 61.23 seconds
Started Jul 30 05:19:01 PM PDT 24
Finished Jul 30 05:20:02 PM PDT 24
Peak memory 199968 kb
Host smart-45761b92-90db-432a-95a1-b1afc93b27da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832825428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1832825428
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2138803213
Short name T170
Test name
Test status
Simulation time 9574891273 ps
CPU time 933.28 seconds
Started Jul 30 05:18:58 PM PDT 24
Finished Jul 30 05:34:32 PM PDT 24
Peak memory 752076 kb
Host smart-a8396ddd-4ceb-4c1c-bb12-ebe5b72503a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138803213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2138803213
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3401301246
Short name T302
Test name
Test status
Simulation time 24423711836 ps
CPU time 155.97 seconds
Started Jul 30 05:19:04 PM PDT 24
Finished Jul 30 05:21:40 PM PDT 24
Peak memory 200004 kb
Host smart-2f3b71fb-b4f6-4b0c-a7b4-a461c1323bc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401301246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3401301246
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2847696002
Short name T107
Test name
Test status
Simulation time 6286155811 ps
CPU time 181.33 seconds
Started Jul 30 05:19:02 PM PDT 24
Finished Jul 30 05:22:03 PM PDT 24
Peak memory 216400 kb
Host smart-0d3ebb52-8a67-4e53-bbd7-93281f94b64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847696002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2847696002
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.307333950
Short name T243
Test name
Test status
Simulation time 32408909 ps
CPU time 1.53 seconds
Started Jul 30 05:19:03 PM PDT 24
Finished Jul 30 05:19:04 PM PDT 24
Peak memory 199856 kb
Host smart-687508e4-42ff-4c8d-b45f-6069be466546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307333950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.307333950
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2493442949
Short name T200
Test name
Test status
Simulation time 23846886374 ps
CPU time 89.14 seconds
Started Jul 30 05:19:04 PM PDT 24
Finished Jul 30 05:20:33 PM PDT 24
Peak memory 199984 kb
Host smart-c4227848-3890-401c-b6de-c5f68729ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493442949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2493442949
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.4029424878
Short name T173
Test name
Test status
Simulation time 63785765 ps
CPU time 0.55 seconds
Started Jul 30 05:19:09 PM PDT 24
Finished Jul 30 05:19:10 PM PDT 24
Peak memory 194900 kb
Host smart-8797bab0-f7cc-402d-b715-4941f4c30002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029424878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.4029424878
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2873223403
Short name T281
Test name
Test status
Simulation time 897013510 ps
CPU time 49.18 seconds
Started Jul 30 05:19:04 PM PDT 24
Finished Jul 30 05:19:53 PM PDT 24
Peak memory 199880 kb
Host smart-0bf28b29-84a3-45aa-8b2d-0724b95ee921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873223403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2873223403
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.99493361
Short name T484
Test name
Test status
Simulation time 3450334436 ps
CPU time 304.24 seconds
Started Jul 30 05:19:04 PM PDT 24
Finished Jul 30 05:24:09 PM PDT 24
Peak memory 480292 kb
Host smart-248b9b2a-1101-4c71-992f-27c23ae8c64d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99493361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.99493361
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3753369634
Short name T159
Test name
Test status
Simulation time 3872076772 ps
CPU time 121.89 seconds
Started Jul 30 05:19:10 PM PDT 24
Finished Jul 30 05:21:12 PM PDT 24
Peak memory 199980 kb
Host smart-afd49a31-0454-4143-bb04-641b5dec3540
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753369634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3753369634
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.570551177
Short name T260
Test name
Test status
Simulation time 10312010394 ps
CPU time 120.42 seconds
Started Jul 30 05:19:03 PM PDT 24
Finished Jul 30 05:21:04 PM PDT 24
Peak memory 199964 kb
Host smart-b923c7f2-daa6-4c24-805f-463ca25b7e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570551177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.570551177
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2376056248
Short name T295
Test name
Test status
Simulation time 791812507 ps
CPU time 13.85 seconds
Started Jul 30 05:19:05 PM PDT 24
Finished Jul 30 05:19:19 PM PDT 24
Peak memory 199868 kb
Host smart-8f9709c2-8056-432e-9d4e-cdc34b949a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376056248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2376056248
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3971771733
Short name T523
Test name
Test status
Simulation time 173470628121 ps
CPU time 1696.19 seconds
Started Jul 30 05:19:08 PM PDT 24
Finished Jul 30 05:47:25 PM PDT 24
Peak memory 710260 kb
Host smart-6fa11b7a-744a-4e16-ae3a-fd5d26b01bfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971771733 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3971771733
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1043225715
Short name T323
Test name
Test status
Simulation time 5722394105 ps
CPU time 72.9 seconds
Started Jul 30 05:19:08 PM PDT 24
Finished Jul 30 05:20:21 PM PDT 24
Peak memory 200064 kb
Host smart-20ac8f31-0ea0-40d0-8f5e-52edbc3d2f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043225715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1043225715
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.144422247
Short name T279
Test name
Test status
Simulation time 44458398 ps
CPU time 0.59 seconds
Started Jul 30 05:19:12 PM PDT 24
Finished Jul 30 05:19:13 PM PDT 24
Peak memory 195616 kb
Host smart-324779d3-030e-44bb-8e99-a17acfcae20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144422247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.144422247
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.544340711
Short name T471
Test name
Test status
Simulation time 836741324 ps
CPU time 32.41 seconds
Started Jul 30 05:19:11 PM PDT 24
Finished Jul 30 05:19:44 PM PDT 24
Peak memory 199880 kb
Host smart-4541e42b-9bb8-4c92-ac01-651a5e94e314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544340711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.544340711
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2114480876
Short name T212
Test name
Test status
Simulation time 305202392 ps
CPU time 4.43 seconds
Started Jul 30 05:19:12 PM PDT 24
Finished Jul 30 05:19:17 PM PDT 24
Peak memory 199840 kb
Host smart-f7a013ce-c8a2-4836-af7a-9e705e00f12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114480876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2114480876
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1648391405
Short name T225
Test name
Test status
Simulation time 13666748400 ps
CPU time 581.94 seconds
Started Jul 30 05:19:08 PM PDT 24
Finished Jul 30 05:28:50 PM PDT 24
Peak memory 672408 kb
Host smart-cf5e94bf-d9bb-4d9f-9127-3ba3e873589c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1648391405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1648391405
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3792667601
Short name T416
Test name
Test status
Simulation time 8930637118 ps
CPU time 127.39 seconds
Started Jul 30 05:19:09 PM PDT 24
Finished Jul 30 05:21:16 PM PDT 24
Peak memory 199992 kb
Host smart-466f3d13-f42e-4500-bfa9-0c34ae3ad724
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792667601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3792667601
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1267252644
Short name T141
Test name
Test status
Simulation time 4018073341 ps
CPU time 18.89 seconds
Started Jul 30 05:19:11 PM PDT 24
Finished Jul 30 05:19:30 PM PDT 24
Peak memory 200016 kb
Host smart-5e89f26f-5ea8-4280-afd3-a056738a679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267252644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1267252644
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.438843813
Short name T209
Test name
Test status
Simulation time 1520262661 ps
CPU time 7.14 seconds
Started Jul 30 05:19:10 PM PDT 24
Finished Jul 30 05:19:17 PM PDT 24
Peak memory 200048 kb
Host smart-997934b0-fbce-4ec5-966d-951c7625a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438843813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.438843813
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1901358717
Short name T265
Test name
Test status
Simulation time 30141114748 ps
CPU time 2513.27 seconds
Started Jul 30 05:19:13 PM PDT 24
Finished Jul 30 06:01:07 PM PDT 24
Peak memory 800956 kb
Host smart-5cf621ad-2763-4220-8c41-c3be916464a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901358717 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1901358717
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.519513826
Short name T422
Test name
Test status
Simulation time 14447098065 ps
CPU time 60.98 seconds
Started Jul 30 05:19:12 PM PDT 24
Finished Jul 30 05:20:13 PM PDT 24
Peak memory 199984 kb
Host smart-1855c9d0-f984-48d5-b297-b3dde128d614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519513826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.519513826
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.781303251
Short name T404
Test name
Test status
Simulation time 43165545 ps
CPU time 0.61 seconds
Started Jul 30 05:19:19 PM PDT 24
Finished Jul 30 05:19:19 PM PDT 24
Peak memory 195936 kb
Host smart-5309f788-3c5e-4736-b3a5-35aa43f61372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781303251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.781303251
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.560588428
Short name T240
Test name
Test status
Simulation time 6004330704 ps
CPU time 77.2 seconds
Started Jul 30 05:19:13 PM PDT 24
Finished Jul 30 05:20:30 PM PDT 24
Peak memory 200172 kb
Host smart-e4be4a45-55a3-4ebd-9842-314c800a1acf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=560588428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.560588428
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3966989673
Short name T249
Test name
Test status
Simulation time 48644180054 ps
CPU time 55.28 seconds
Started Jul 30 05:19:15 PM PDT 24
Finished Jul 30 05:20:10 PM PDT 24
Peak memory 200056 kb
Host smart-580c2e8c-81d4-4254-ab49-e83604d19b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966989673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3966989673
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1497774780
Short name T429
Test name
Test status
Simulation time 816672293 ps
CPU time 160.09 seconds
Started Jul 30 05:19:14 PM PDT 24
Finished Jul 30 05:21:54 PM PDT 24
Peak memory 439356 kb
Host smart-e089081d-4651-4b50-8282-3cd0a20af4e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497774780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1497774780
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3390286070
Short name T229
Test name
Test status
Simulation time 41507751180 ps
CPU time 198.61 seconds
Started Jul 30 05:19:12 PM PDT 24
Finished Jul 30 05:22:31 PM PDT 24
Peak memory 200060 kb
Host smart-abc84175-ee14-452e-83a2-4fd04624e07c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390286070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3390286070
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1422511212
Short name T501
Test name
Test status
Simulation time 54258489862 ps
CPU time 182.73 seconds
Started Jul 30 05:19:15 PM PDT 24
Finished Jul 30 05:22:17 PM PDT 24
Peak memory 200016 kb
Host smart-20340a0a-679e-4487-b26e-d5e6dab4552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422511212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1422511212
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3170711685
Short name T188
Test name
Test status
Simulation time 219697776 ps
CPU time 2.88 seconds
Started Jul 30 05:19:14 PM PDT 24
Finished Jul 30 05:19:17 PM PDT 24
Peak memory 199900 kb
Host smart-8a17ac1b-dc31-4867-8a94-84c843452745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170711685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3170711685
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.4054893876
Short name T390
Test name
Test status
Simulation time 49519931006 ps
CPU time 1721.36 seconds
Started Jul 30 05:19:13 PM PDT 24
Finished Jul 30 05:47:55 PM PDT 24
Peak memory 727980 kb
Host smart-5d9f9522-767e-406b-8f9b-79f0d118f913
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054893876 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.4054893876
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1062807026
Short name T502
Test name
Test status
Simulation time 8276515491 ps
CPU time 119.29 seconds
Started Jul 30 05:19:14 PM PDT 24
Finished Jul 30 05:21:14 PM PDT 24
Peak memory 199976 kb
Host smart-a5267f75-b95d-47d4-a776-7a31e27392ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062807026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1062807026
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1987133830
Short name T262
Test name
Test status
Simulation time 10690646 ps
CPU time 0.59 seconds
Started Jul 30 05:19:19 PM PDT 24
Finished Jul 30 05:19:20 PM PDT 24
Peak memory 194964 kb
Host smart-5988ebba-28b2-4445-8240-2db61da35be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987133830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1987133830
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.148407288
Short name T414
Test name
Test status
Simulation time 310417759 ps
CPU time 8.21 seconds
Started Jul 30 05:19:19 PM PDT 24
Finished Jul 30 05:19:28 PM PDT 24
Peak memory 199872 kb
Host smart-618a6cee-4cc3-48f4-95ad-959752a30a2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=148407288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.148407288
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1038217708
Short name T474
Test name
Test status
Simulation time 1193875040 ps
CPU time 29.92 seconds
Started Jul 30 05:19:18 PM PDT 24
Finished Jul 30 05:19:48 PM PDT 24
Peak memory 199876 kb
Host smart-02ea17b5-0823-4b89-8112-262aa313241a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038217708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1038217708
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.206969299
Short name T415
Test name
Test status
Simulation time 2395555604 ps
CPU time 456.26 seconds
Started Jul 30 05:19:20 PM PDT 24
Finished Jul 30 05:26:56 PM PDT 24
Peak memory 658904 kb
Host smart-c19c0ee8-6666-4b5b-aeba-061f12194c5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=206969299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.206969299
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.4058634004
Short name T165
Test name
Test status
Simulation time 11843734589 ps
CPU time 141.91 seconds
Started Jul 30 05:19:19 PM PDT 24
Finished Jul 30 05:21:41 PM PDT 24
Peak memory 199972 kb
Host smart-a3ad8172-8b7a-4f99-9c30-fe88f2830225
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058634004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.4058634004
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.579263338
Short name T480
Test name
Test status
Simulation time 1107396383 ps
CPU time 15.66 seconds
Started Jul 30 05:19:19 PM PDT 24
Finished Jul 30 05:19:35 PM PDT 24
Peak memory 199880 kb
Host smart-b59f0489-8b0c-4236-b473-daf049c63fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579263338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.579263338
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2083360811
Short name T81
Test name
Test status
Simulation time 233675342 ps
CPU time 1.42 seconds
Started Jul 30 05:19:21 PM PDT 24
Finished Jul 30 05:19:22 PM PDT 24
Peak memory 199884 kb
Host smart-e1cd7382-fbbf-435f-ae0e-17576b001fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083360811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2083360811
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3691892920
Short name T145
Test name
Test status
Simulation time 55666464166 ps
CPU time 1790.72 seconds
Started Jul 30 05:19:18 PM PDT 24
Finished Jul 30 05:49:09 PM PDT 24
Peak memory 766892 kb
Host smart-d45242e0-67fe-4891-a555-1f2928f3d158
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691892920 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3691892920
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2557665421
Short name T69
Test name
Test status
Simulation time 7943192396 ps
CPU time 150.12 seconds
Started Jul 30 05:19:18 PM PDT 24
Finished Jul 30 05:21:48 PM PDT 24
Peak memory 199928 kb
Host smart-db734c3a-dd21-48bb-a79e-627c5917c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557665421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2557665421
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2307391320
Short name T364
Test name
Test status
Simulation time 91874963 ps
CPU time 0.63 seconds
Started Jul 30 05:19:21 PM PDT 24
Finished Jul 30 05:19:22 PM PDT 24
Peak memory 195988 kb
Host smart-02ef0567-8397-49b3-8832-5aec5289cc01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307391320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2307391320
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2568901760
Short name T380
Test name
Test status
Simulation time 623348435 ps
CPU time 35.94 seconds
Started Jul 30 05:19:23 PM PDT 24
Finished Jul 30 05:19:59 PM PDT 24
Peak memory 200048 kb
Host smart-28e4ec70-2b5b-4349-a11a-b357f2a42425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568901760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2568901760
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1168933878
Short name T362
Test name
Test status
Simulation time 2798916360 ps
CPU time 32.06 seconds
Started Jul 30 05:19:21 PM PDT 24
Finished Jul 30 05:19:54 PM PDT 24
Peak memory 200016 kb
Host smart-6c9e2d31-ad84-490d-ae2f-0b464c7a37ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168933878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1168933878
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.529679904
Short name T353
Test name
Test status
Simulation time 22022655376 ps
CPU time 964.15 seconds
Started Jul 30 05:19:23 PM PDT 24
Finished Jul 30 05:35:27 PM PDT 24
Peak memory 736672 kb
Host smart-dc9d06cf-3c41-42e5-87c5-bc9afd651d71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529679904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.529679904
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1685257409
Short name T266
Test name
Test status
Simulation time 12054683105 ps
CPU time 174.87 seconds
Started Jul 30 05:19:21 PM PDT 24
Finished Jul 30 05:22:16 PM PDT 24
Peak memory 199936 kb
Host smart-b9935265-699b-435f-8470-3d385398d677
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685257409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1685257409
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1652811248
Short name T433
Test name
Test status
Simulation time 26819383484 ps
CPU time 42.06 seconds
Started Jul 30 05:19:23 PM PDT 24
Finished Jul 30 05:20:05 PM PDT 24
Peak memory 200024 kb
Host smart-2b9b9087-fb47-45d3-a9ab-5de8daafa297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652811248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1652811248
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.16249406
Short name T219
Test name
Test status
Simulation time 1151403021 ps
CPU time 13.41 seconds
Started Jul 30 05:19:23 PM PDT 24
Finished Jul 30 05:19:37 PM PDT 24
Peak memory 199876 kb
Host smart-78d292b6-3a63-415f-b593-f49b5b1c8822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16249406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.16249406
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.637980517
Short name T334
Test name
Test status
Simulation time 198786999725 ps
CPU time 609.44 seconds
Started Jul 30 05:19:23 PM PDT 24
Finished Jul 30 05:29:33 PM PDT 24
Peak memory 216272 kb
Host smart-c5d4c32a-ebba-4617-a508-0ad9b755fcf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637980517 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.637980517
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1146758049
Short name T257
Test name
Test status
Simulation time 35846992 ps
CPU time 0.73 seconds
Started Jul 30 05:19:22 PM PDT 24
Finished Jul 30 05:19:23 PM PDT 24
Peak memory 196424 kb
Host smart-88735db0-f4bd-43ab-9f16-647886ce27f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146758049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1146758049
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.260378304
Short name T361
Test name
Test status
Simulation time 16748555 ps
CPU time 0.64 seconds
Started Jul 30 05:19:28 PM PDT 24
Finished Jul 30 05:19:29 PM PDT 24
Peak memory 195976 kb
Host smart-f58eb9ac-4284-4b37-80a3-0dbd409ecc69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260378304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.260378304
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3870784558
Short name T495
Test name
Test status
Simulation time 1874979006 ps
CPU time 55.36 seconds
Started Jul 30 05:19:30 PM PDT 24
Finished Jul 30 05:20:25 PM PDT 24
Peak memory 199924 kb
Host smart-fcd3c263-4c26-4aeb-b387-9eda209d203b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870784558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3870784558
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1593944738
Short name T264
Test name
Test status
Simulation time 1776427238 ps
CPU time 5.08 seconds
Started Jul 30 05:19:30 PM PDT 24
Finished Jul 30 05:19:36 PM PDT 24
Peak memory 199880 kb
Host smart-d3bda493-79c2-4896-81a4-4ef21f4c5460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593944738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1593944738
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2893373845
Short name T277
Test name
Test status
Simulation time 4438065426 ps
CPU time 168.34 seconds
Started Jul 30 05:19:29 PM PDT 24
Finished Jul 30 05:22:17 PM PDT 24
Peak memory 487580 kb
Host smart-1f8fba68-be9c-4105-bd73-4985a719cd8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893373845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2893373845
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1891258107
Short name T263
Test name
Test status
Simulation time 21852652491 ps
CPU time 134.11 seconds
Started Jul 30 05:19:30 PM PDT 24
Finished Jul 30 05:21:44 PM PDT 24
Peak memory 199988 kb
Host smart-eae34f7c-1578-4db4-9471-dade5d31aebe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891258107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1891258107
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1571574221
Short name T521
Test name
Test status
Simulation time 2862236714 ps
CPU time 156.99 seconds
Started Jul 30 05:19:23 PM PDT 24
Finished Jul 30 05:22:00 PM PDT 24
Peak memory 200020 kb
Host smart-8a39b5a9-8388-47a7-85cf-7e421fab8b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571574221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1571574221
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2883140943
Short name T275
Test name
Test status
Simulation time 541371186 ps
CPU time 9.44 seconds
Started Jul 30 05:19:23 PM PDT 24
Finished Jul 30 05:19:33 PM PDT 24
Peak memory 199960 kb
Host smart-8f8c2784-7d7c-461a-827c-6c4c1428f01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883140943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2883140943
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3938100832
Short name T475
Test name
Test status
Simulation time 5708961803 ps
CPU time 41.03 seconds
Started Jul 30 05:19:29 PM PDT 24
Finished Jul 30 05:20:10 PM PDT 24
Peak memory 200064 kb
Host smart-8d80926c-1c1a-4ddc-b9ee-2ae19586c14a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938100832 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3938100832
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1227482267
Short name T120
Test name
Test status
Simulation time 15069563132 ps
CPU time 100.31 seconds
Started Jul 30 05:19:29 PM PDT 24
Finished Jul 30 05:21:09 PM PDT 24
Peak memory 199968 kb
Host smart-16219ac2-4ead-437c-bcd6-fbd5be706c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227482267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1227482267
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1686322295
Short name T178
Test name
Test status
Simulation time 25889576 ps
CPU time 0.6 seconds
Started Jul 30 05:19:31 PM PDT 24
Finished Jul 30 05:19:31 PM PDT 24
Peak memory 195880 kb
Host smart-a5c580a5-fd86-417a-a7ca-3efd86039253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686322295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1686322295
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3314763637
Short name T424
Test name
Test status
Simulation time 1901671454 ps
CPU time 110.1 seconds
Started Jul 30 05:19:30 PM PDT 24
Finished Jul 30 05:21:20 PM PDT 24
Peak memory 199876 kb
Host smart-297bd91c-7372-4851-9bca-214072647459
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314763637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3314763637
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2641956570
Short name T285
Test name
Test status
Simulation time 3629566718 ps
CPU time 11.53 seconds
Started Jul 30 05:19:29 PM PDT 24
Finished Jul 30 05:19:41 PM PDT 24
Peak memory 199928 kb
Host smart-7bd6b903-8ee9-44cb-94b9-de6320d7cdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641956570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2641956570
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1006674954
Short name T342
Test name
Test status
Simulation time 1843477200 ps
CPU time 92 seconds
Started Jul 30 05:19:28 PM PDT 24
Finished Jul 30 05:21:00 PM PDT 24
Peak memory 465624 kb
Host smart-9c99db38-c9b8-461e-8471-64589f64e912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1006674954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1006674954
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2684640766
Short name T491
Test name
Test status
Simulation time 3410401069 ps
CPU time 188.74 seconds
Started Jul 30 05:19:27 PM PDT 24
Finished Jul 30 05:22:36 PM PDT 24
Peak memory 199988 kb
Host smart-83cb7779-2f93-4d37-8900-d7258240f359
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684640766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2684640766
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.953759522
Short name T25
Test name
Test status
Simulation time 37933796754 ps
CPU time 173.2 seconds
Started Jul 30 05:19:28 PM PDT 24
Finished Jul 30 05:22:22 PM PDT 24
Peak memory 199968 kb
Host smart-772d80d4-ef2c-484e-b8de-80213c919f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953759522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.953759522
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3242915867
Short name T137
Test name
Test status
Simulation time 310555621 ps
CPU time 10.77 seconds
Started Jul 30 05:19:28 PM PDT 24
Finished Jul 30 05:19:39 PM PDT 24
Peak memory 199860 kb
Host smart-2c49cb91-a502-4295-b4f2-5ab3c20c8065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242915867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3242915867
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.383331233
Short name T442
Test name
Test status
Simulation time 116299224385 ps
CPU time 243.24 seconds
Started Jul 30 05:19:31 PM PDT 24
Finished Jul 30 05:23:34 PM PDT 24
Peak memory 200004 kb
Host smart-8204805c-8ede-42f9-85aa-564f067f4c11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383331233 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.383331233
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.356444401
Short name T419
Test name
Test status
Simulation time 52481264190 ps
CPU time 131.04 seconds
Started Jul 30 05:19:31 PM PDT 24
Finished Jul 30 05:21:42 PM PDT 24
Peak memory 199968 kb
Host smart-8861ffab-74c0-4bbb-a136-2c2b0374a2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356444401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.356444401
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1573308166
Short name T329
Test name
Test status
Simulation time 33686657 ps
CPU time 0.56 seconds
Started Jul 30 05:17:16 PM PDT 24
Finished Jul 30 05:17:17 PM PDT 24
Peak memory 195968 kb
Host smart-087a9e1a-5a3e-42f5-a0ff-9b3a0830f3eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573308166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1573308166
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.656415852
Short name T161
Test name
Test status
Simulation time 1481853636 ps
CPU time 88.51 seconds
Started Jul 30 05:17:16 PM PDT 24
Finished Jul 30 05:18:45 PM PDT 24
Peak memory 199844 kb
Host smart-e2d35648-5fa0-4ab3-ace2-a38729fe9773
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=656415852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.656415852
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.407917409
Short name T427
Test name
Test status
Simulation time 496831963 ps
CPU time 25.42 seconds
Started Jul 30 05:17:16 PM PDT 24
Finished Jul 30 05:17:41 PM PDT 24
Peak memory 199828 kb
Host smart-f5cbe38e-1ca3-4451-9128-6c7b340b4931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407917409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.407917409
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2363256480
Short name T80
Test name
Test status
Simulation time 12370315027 ps
CPU time 486.26 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:25:25 PM PDT 24
Peak memory 640716 kb
Host smart-dd7c89b7-2b17-4430-82df-02cffe1cdc7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2363256480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2363256480
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1578108916
Short name T322
Test name
Test status
Simulation time 127019980315 ps
CPU time 180.13 seconds
Started Jul 30 05:17:20 PM PDT 24
Finished Jul 30 05:20:21 PM PDT 24
Peak memory 199984 kb
Host smart-70ef7096-2823-491a-944e-969d21012f90
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578108916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1578108916
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1479911835
Short name T175
Test name
Test status
Simulation time 75813886995 ps
CPU time 194.53 seconds
Started Jul 30 05:17:17 PM PDT 24
Finished Jul 30 05:20:31 PM PDT 24
Peak memory 216380 kb
Host smart-8a836fba-8f99-4965-adba-cbd43d68325a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479911835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1479911835
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2476228456
Short name T332
Test name
Test status
Simulation time 3282023153 ps
CPU time 10.65 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:17:28 PM PDT 24
Peak memory 199992 kb
Host smart-35c27277-1b51-4232-9470-df0cfb88002e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476228456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2476228456
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2392065942
Short name T29
Test name
Test status
Simulation time 37118703849 ps
CPU time 801.95 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:30:40 PM PDT 24
Peak memory 511392 kb
Host smart-8b3c79b1-b595-474d-8262-cfbfc9dbb26a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392065942 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2392065942
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.649038620
Short name T511
Test name
Test status
Simulation time 2444173099 ps
CPU time 31.44 seconds
Started Jul 30 05:17:17 PM PDT 24
Finished Jul 30 05:17:48 PM PDT 24
Peak memory 200016 kb
Host smart-4468339e-78ed-42a7-92af-67202bdc14ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649038620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.649038620
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.842251605
Short name T445
Test name
Test status
Simulation time 71411578 ps
CPU time 0.57 seconds
Started Jul 30 05:17:20 PM PDT 24
Finished Jul 30 05:17:21 PM PDT 24
Peak memory 195924 kb
Host smart-a4c0e721-bcc5-494a-8c8f-eaab8475750c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842251605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.842251605
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3986387908
Short name T447
Test name
Test status
Simulation time 1591485524 ps
CPU time 42.23 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:18:00 PM PDT 24
Peak memory 199900 kb
Host smart-20dfb098-8119-48f9-a33c-f7b5dab3c273
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986387908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3986387908
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1549448991
Short name T227
Test name
Test status
Simulation time 673554849 ps
CPU time 11.09 seconds
Started Jul 30 05:17:17 PM PDT 24
Finished Jul 30 05:17:29 PM PDT 24
Peak memory 199924 kb
Host smart-55acdea6-c5d0-4bfe-9c0b-a103ee660286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549448991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1549448991
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2913918309
Short name T451
Test name
Test status
Simulation time 1129525327 ps
CPU time 198.82 seconds
Started Jul 30 05:17:21 PM PDT 24
Finished Jul 30 05:20:40 PM PDT 24
Peak memory 470984 kb
Host smart-e58b26f0-8028-4455-93f6-5728524a5c76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2913918309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2913918309
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3548738525
Short name T393
Test name
Test status
Simulation time 2633497549 ps
CPU time 23.53 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:17:42 PM PDT 24
Peak memory 199928 kb
Host smart-f11fb6f1-5fc4-434e-879a-b3153f9f6777
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548738525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3548738525
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1076286825
Short name T492
Test name
Test status
Simulation time 6965454431 ps
CPU time 96.87 seconds
Started Jul 30 05:17:16 PM PDT 24
Finished Jul 30 05:18:53 PM PDT 24
Peak memory 216228 kb
Host smart-81bc5a60-b9c1-40c6-bd6a-d863f8a9e9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076286825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1076286825
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2432371372
Short name T234
Test name
Test status
Simulation time 711091563 ps
CPU time 3.64 seconds
Started Jul 30 05:17:17 PM PDT 24
Finished Jul 30 05:17:21 PM PDT 24
Peak memory 199844 kb
Host smart-7f682984-f2b2-42c0-a048-00405e17dc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432371372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2432371372
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3314385353
Short name T504
Test name
Test status
Simulation time 47820814979 ps
CPU time 297.6 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 05:22:22 PM PDT 24
Peak memory 447624 kb
Host smart-f11912f9-a531-49c3-8ec9-55ae05e26c45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314385353 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3314385353
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.606183687
Short name T23
Test name
Test status
Simulation time 7924049896 ps
CPU time 76.82 seconds
Started Jul 30 05:17:19 PM PDT 24
Finished Jul 30 05:18:35 PM PDT 24
Peak memory 216488 kb
Host smart-9d4c4236-b9dd-4d7c-93d0-50edb30b7f25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=606183687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.606183687
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2893095535
Short name T389
Test name
Test status
Simulation time 795350210 ps
CPU time 39.36 seconds
Started Jul 30 05:17:20 PM PDT 24
Finished Jul 30 05:17:59 PM PDT 24
Peak memory 200036 kb
Host smart-7752adc5-2733-4bab-b057-2901d7523383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893095535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2893095535
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3948920937
Short name T150
Test name
Test status
Simulation time 12610620 ps
CPU time 0.57 seconds
Started Jul 30 05:17:17 PM PDT 24
Finished Jul 30 05:17:18 PM PDT 24
Peak memory 196616 kb
Host smart-7257cfef-6fe9-4475-8557-1d56cafd4d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948920937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3948920937
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3812082617
Short name T239
Test name
Test status
Simulation time 685871015 ps
CPU time 10.84 seconds
Started Jul 30 05:17:20 PM PDT 24
Finished Jul 30 05:17:30 PM PDT 24
Peak memory 199752 kb
Host smart-9c4fa694-7309-4947-8a3a-1d9e85d470c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812082617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3812082617
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3493871380
Short name T382
Test name
Test status
Simulation time 1205335324 ps
CPU time 64.12 seconds
Started Jul 30 05:17:21 PM PDT 24
Finished Jul 30 05:18:25 PM PDT 24
Peak memory 199864 kb
Host smart-c44de802-36ad-437b-b5b6-fa2bb2ed80c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493871380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3493871380
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2751907289
Short name T68
Test name
Test status
Simulation time 10441124890 ps
CPU time 775.22 seconds
Started Jul 30 05:17:22 PM PDT 24
Finished Jul 30 05:30:17 PM PDT 24
Peak memory 728124 kb
Host smart-f2a0e65b-22f1-4db3-9897-ab3a3edfaf62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751907289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2751907289
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2598834510
Short name T284
Test name
Test status
Simulation time 2268862783 ps
CPU time 28.57 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:17:52 PM PDT 24
Peak memory 199952 kb
Host smart-2f606e78-5b82-42f4-9e1e-4a8414ad254d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598834510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2598834510
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2814741312
Short name T530
Test name
Test status
Simulation time 3143216792 ps
CPU time 41.11 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 05:18:06 PM PDT 24
Peak memory 200152 kb
Host smart-3c568d28-397e-4540-8d85-8a2b8943a032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814741312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2814741312
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1691635390
Short name T184
Test name
Test status
Simulation time 145128936 ps
CPU time 6.44 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:17:24 PM PDT 24
Peak memory 199928 kb
Host smart-e9ee70da-1071-477a-b3ca-5d093ff46b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691635390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1691635390
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3530210019
Short name T40
Test name
Test status
Simulation time 132271095671 ps
CPU time 2878.44 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 06:05:23 PM PDT 24
Peak memory 785252 kb
Host smart-c86ce2b6-169e-4a56-aafd-15dfc7e13a00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530210019 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3530210019
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.38038374
Short name T10
Test name
Test status
Simulation time 180744249516 ps
CPU time 1727.92 seconds
Started Jul 30 05:17:18 PM PDT 24
Finished Jul 30 05:46:06 PM PDT 24
Peak memory 771736 kb
Host smart-5d275404-b33c-46bc-88ce-bd4d4dd45e13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38038374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.38038374
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2369110700
Short name T384
Test name
Test status
Simulation time 2370072719 ps
CPU time 61.06 seconds
Started Jul 30 05:17:21 PM PDT 24
Finished Jul 30 05:18:22 PM PDT 24
Peak memory 199936 kb
Host smart-700efb8d-f40a-4237-bcca-009381b253db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369110700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2369110700
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1234336839
Short name T106
Test name
Test status
Simulation time 21377363 ps
CPU time 0.55 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:17:25 PM PDT 24
Peak memory 195948 kb
Host smart-61a49e9c-e38c-49bb-9c90-0d92a6f1f6bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234336839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1234336839
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.676671864
Short name T400
Test name
Test status
Simulation time 4919895221 ps
CPU time 48 seconds
Started Jul 30 05:17:20 PM PDT 24
Finished Jul 30 05:18:08 PM PDT 24
Peak memory 199984 kb
Host smart-3e06b57c-336b-4630-865f-cb38752f20da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676671864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.676671864
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.568913768
Short name T351
Test name
Test status
Simulation time 2990202831 ps
CPU time 51.29 seconds
Started Jul 30 05:17:21 PM PDT 24
Finished Jul 30 05:18:12 PM PDT 24
Peak memory 199928 kb
Host smart-d691e820-627a-41de-b67b-bc8447321388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568913768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.568913768
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3399683503
Short name T479
Test name
Test status
Simulation time 80829316517 ps
CPU time 1072.33 seconds
Started Jul 30 05:17:21 PM PDT 24
Finished Jul 30 05:35:14 PM PDT 24
Peak memory 694632 kb
Host smart-0852b816-609d-4ba0-9f4e-8db6383bc90a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3399683503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3399683503
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1537405791
Short name T144
Test name
Test status
Simulation time 3194527416 ps
CPU time 98.69 seconds
Started Jul 30 05:17:22 PM PDT 24
Finished Jul 30 05:19:01 PM PDT 24
Peak memory 199976 kb
Host smart-3674b74a-20b4-4c7d-9117-65e189a8f430
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537405791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1537405791
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1975408381
Short name T486
Test name
Test status
Simulation time 14930163871 ps
CPU time 129.28 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:19:33 PM PDT 24
Peak memory 200036 kb
Host smart-8665e542-d4a8-4a69-903e-4f69ddc6b3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975408381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1975408381
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3771636543
Short name T522
Test name
Test status
Simulation time 327650921 ps
CPU time 7.36 seconds
Started Jul 30 05:17:23 PM PDT 24
Finished Jul 30 05:17:31 PM PDT 24
Peak memory 199924 kb
Host smart-900d41d3-c749-4164-8ff8-72ae938b0e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771636543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3771636543
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2394605884
Short name T133
Test name
Test status
Simulation time 45506508770 ps
CPU time 1637.51 seconds
Started Jul 30 05:17:17 PM PDT 24
Finished Jul 30 05:44:35 PM PDT 24
Peak memory 772940 kb
Host smart-8dc02e6a-7d6f-4246-98b4-ed8dace5cc6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394605884 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2394605884
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1769172452
Short name T22
Test name
Test status
Simulation time 268699851978 ps
CPU time 3996.37 seconds
Started Jul 30 05:17:22 PM PDT 24
Finished Jul 30 06:23:58 PM PDT 24
Peak memory 802652 kb
Host smart-5f5e5e9f-6411-46be-be58-9cf8d3639ef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769172452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1769172452
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2548287654
Short name T421
Test name
Test status
Simulation time 3930781782 ps
CPU time 45.78 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:18:09 PM PDT 24
Peak memory 200016 kb
Host smart-b1b5887b-85d9-4dcc-89df-4f62c5589c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548287654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2548287654
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2720837298
Short name T349
Test name
Test status
Simulation time 15418943 ps
CPU time 0.59 seconds
Started Jul 30 05:17:26 PM PDT 24
Finished Jul 30 05:17:27 PM PDT 24
Peak memory 195948 kb
Host smart-1634beb3-948a-43c4-91f5-0b77a1fc7bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720837298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2720837298
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1574260521
Short name T162
Test name
Test status
Simulation time 2127329635 ps
CPU time 30.85 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 05:17:56 PM PDT 24
Peak memory 199836 kb
Host smart-0d8266de-151f-4dd2-b214-ad5d72c87954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574260521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1574260521
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3673842068
Short name T344
Test name
Test status
Simulation time 8159553865 ps
CPU time 43.13 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:18:07 PM PDT 24
Peak memory 200140 kb
Host smart-88b1b230-3854-4144-a779-5c51e78a27e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673842068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3673842068
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1595799933
Short name T478
Test name
Test status
Simulation time 13368609037 ps
CPU time 534.37 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 05:26:19 PM PDT 24
Peak memory 678620 kb
Host smart-5fe49562-0044-48d5-9b50-92307706307a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595799933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1595799933
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3157169390
Short name T108
Test name
Test status
Simulation time 1465209419 ps
CPU time 13.86 seconds
Started Jul 30 05:17:23 PM PDT 24
Finished Jul 30 05:17:37 PM PDT 24
Peak memory 199812 kb
Host smart-866e09b6-f16d-4573-a56b-d3c82e754524
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157169390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3157169390
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2290095319
Short name T217
Test name
Test status
Simulation time 11020248000 ps
CPU time 129.98 seconds
Started Jul 30 05:17:25 PM PDT 24
Finished Jul 30 05:19:35 PM PDT 24
Peak memory 200000 kb
Host smart-e6119838-e05d-4286-8291-d70af185aeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290095319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2290095319
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.4121425248
Short name T151
Test name
Test status
Simulation time 115051602 ps
CPU time 5.12 seconds
Started Jul 30 05:17:22 PM PDT 24
Finished Jul 30 05:17:27 PM PDT 24
Peak memory 199856 kb
Host smart-d2a4b7c3-b299-46fa-bdc0-314c8b09d770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121425248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.4121425248
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2870709957
Short name T354
Test name
Test status
Simulation time 246376212528 ps
CPU time 1073.38 seconds
Started Jul 30 05:17:24 PM PDT 24
Finished Jul 30 05:35:18 PM PDT 24
Peak memory 249748 kb
Host smart-c3b96575-b7ee-4323-ad94-746e52dbee6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870709957 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2870709957
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3082793095
Short name T321
Test name
Test status
Simulation time 3748885064 ps
CPU time 101.25 seconds
Started Jul 30 05:17:22 PM PDT 24
Finished Jul 30 05:19:03 PM PDT 24
Peak memory 199988 kb
Host smart-3b2e5c0e-38f0-4497-9872-2e51aa3c7c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082793095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3082793095
Directory /workspace/9.hmac_wipe_secret/latest
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