Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18578707	1			T1	29719		T2	1203		T3	8489
all_values[1]	18578707	1			T1	29719		T2	1203		T3	8489
all_values[2]	18578707	1			T1	29719		T2	1203		T3	8489

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249333

1

T4

807

T5

3

T7

2040

auto[1]

55486788

1

T1

89157

T2

3609

T3

25467

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47422043

1

T1

77905

T2

3001

T3

25287

auto[1]

8314078

1

T1

11252

T2

608

T3

180

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	94967	1			T4	807		T5	1		T6	1
all_values[0]	auto[0]	auto[1]	412	1			T18	12		T79	2		T122	4
all_values[0]	auto[1]	auto[0]	18462883	1			T1	29685		T2	1187		T3	8309
all_values[0]	auto[1]	auto[1]	20445	1			T1	34		T2	16		T3	180
all_values[1]	auto[0]	auto[0]	79954	1			T5	1		T7	2040		T6	1
all_values[1]	auto[0]	auto[1]	216	1			T18	6		T8	5		T10	4
all_values[1]	auto[1]	auto[0]	18498174	1			T1	29719		T2	1203		T3	8489
all_values[1]	auto[1]	auto[1]	363	1			T18	9		T21	2		T15	2
all_values[2]	auto[0]	auto[0]	37334	1			T5	1		T6	1		T14	226
all_values[2]	auto[0]	auto[1]	36450	1			T14	712		T18	5		T9	450
all_values[2]	auto[1]	auto[0]	10248731	1			T1	18501		T2	611		T3	8489
all_values[2]	auto[1]	auto[1]	8256192	1			T1	11218		T2	592		T4	9616