Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130251

1

T1

42

T2

26

T4

34

auto[1]

126444

1

T1

26

T2

16

T3

174

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	95600	1			T1	26		T4	20		T5	370
len_1026_2046	7160	1			T1	3		T2	2		T5	110
len_514_1022	3772	1			T1	1		T4	1		T5	10
len_2_510	2962	1			T2	2		T4	2		T5	11
len_2056	557	1			T2	2		T6	4		T18	1
len_2048	366	1			T4	1		T5	1		T6	3
len_2040	192	1			T6	8		T18	1		T122	3
len_1032	198	1			T6	4		T18	2		T122	1
len_1024	1884	1			T3	87		T4	1		T5	4
len_1016	212	1			T2	4		T5	1		T6	6
len_520	230	1			T2	4		T6	28		T122	5
len_512	385	1			T5	1		T6	7		T122	6
len_504	250	1			T2	5		T6	12		T18	7
len_8	1528	1			T5	3		T6	8		T18	2
len_0	13052	1			T1	4		T2	2		T4	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

123

1

T5

3

T13

2

T74

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	50641	1			T1	14		T4	14		T5	160
auto[0]	len_1026_2046	3962	1			T1	2		T2	2		T5	65
auto[0]	len_514_1022	2041	1			T1	1		T5	3		T6	9
auto[0]	len_2_510	2135	1			T2	2		T4	1		T5	4
auto[0]	len_2056	135	1			T6	3		T122	2		T138	5
auto[0]	len_2048	215	1			T4	1		T6	3		T74	1
auto[0]	len_2040	111	1			T6	4		T18	1		T122	1
auto[0]	len_1032	87	1			T6	2		T138	2		T139	1
auto[0]	len_1024	297	1			T5	1		T6	3		T13	1
auto[0]	len_1016	119	1			T2	2		T6	4		T18	1
auto[0]	len_520	124	1			T2	4		T6	17		T122	1
auto[0]	len_512	226	1			T5	1		T6	5		T122	4
auto[0]	len_504	148	1			T2	2		T6	5		T18	4
auto[0]	len_8	35	1			T61	2		T140	1		T141	1
auto[0]	len_0	4850	1			T1	4		T2	1		T4	1
auto[1]	len_2050_plus	44959	1			T1	12		T4	6		T5	210
auto[1]	len_1026_2046	3198	1			T1	1		T5	45		T6	112
auto[1]	len_514_1022	1731	1			T4	1		T5	7		T6	10
auto[1]	len_2_510	827	1			T4	1		T5	7		T6	3
auto[1]	len_2056	422	1			T2	2		T6	1		T18	1
auto[1]	len_2048	151	1			T5	1		T122	3		T15	1
auto[1]	len_2040	81	1			T6	4		T122	2		T127	1
auto[1]	len_1032	111	1			T6	2		T18	2		T122	1
auto[1]	len_1024	1587	1			T3	87		T4	1		T5	3
auto[1]	len_1016	93	1			T2	2		T5	1		T6	2
auto[1]	len_520	106	1			T6	11		T122	4		T142	2
auto[1]	len_512	159	1			T6	2		T122	2		T15	2
auto[1]	len_504	102	1			T2	3		T6	7		T18	3
auto[1]	len_8	1493	1			T5	3		T6	8		T18	2
auto[1]	len_0	8202	1			T2	1		T5	1		T6	65

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

76

1

T13

2

T74

2

T122

1

auto[1]

len_upper

47

1

T5

3

T47

3

T122

1