Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4618844 1 T1 7511 T2 243 T3 4299
auto[1] 2873401 1 T1 7386 T2 360 T4 3825


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2961613 1 T1 5301 T2 402 T4 8136
auto[1] 4530632 1 T1 9596 T2 201 T3 4299


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3344300 1 T1 10101 T2 202 T4 7757
auto[1] 4147945 1 T1 4796 T2 401 T3 4299


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4653899 1 T1 5397 T2 381 T3 4299
auto[1] 2838346 1 T1 9500 T2 222 T4 4672


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6822471 1 T1 14608 T2 549 T3 2946
fifo_depth[1] 118737 1 T1 214 T2 8 T3 152
fifo_depth[2] 88185 1 T1 67 T2 6 T3 151
fifo_depth[3] 69254 1 T1 7 T2 5 T3 139
fifo_depth[4] 62685 1 T2 10 T3 133 T4 296
fifo_depth[5] 49286 1 T1 1 T2 8 T3 144
fifo_depth[6] 39527 1 T2 4 T3 129 T4 172
fifo_depth[7] 26083 1 T2 4 T3 127 T4 94


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 669774 1 T1 289 T2 54 T3 1353
auto[1] 6822471 1 T1 14608 T2 549 T3 2946


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7481842 1 T1 14897 T2 603 T3 4299
auto[1] 10403 1 T21 66 T15 572 T16 81


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 38018 1 T1 25 T2 9 T4 789
auto[0] auto[0] auto[0] auto[0] auto[1] 34159 1 T1 54 T4 62 T5 16
auto[0] auto[0] auto[0] auto[1] auto[0] 31736 1 T1 10 T6 16 T13 293
auto[0] auto[0] auto[0] auto[1] auto[1] 23653 1 T12 44 T6 40 T14 22
auto[0] auto[0] auto[1] auto[0] auto[0] 131924 1 T1 12 T6 47 T74 1
auto[0] auto[0] auto[1] auto[0] auto[1] 30262 1 T1 54 T4 116 T6 20
auto[0] auto[0] auto[1] auto[1] auto[0] 27634 1 T1 18 T4 61 T5 10
auto[0] auto[0] auto[1] auto[1] auto[1] 31607 1 T1 19 T4 339 T5 1
auto[0] auto[1] auto[0] auto[0] auto[0] 38158 1 T1 37 T4 112 T5 14
auto[0] auto[1] auto[0] auto[0] auto[1] 38564 1 T1 5 T4 7 T7 158
auto[0] auto[1] auto[0] auto[1] auto[0] 44363 1 T2 15 T4 59 T6 74
auto[0] auto[1] auto[0] auto[1] auto[1] 34379 1 T1 29 T2 14 T6 40
auto[0] auto[1] auto[1] auto[0] auto[0] 48994 1 T3 1353 T7 251 T6 33
auto[0] auto[1] auto[1] auto[0] auto[1] 39194 1 T5 60 T6 4 T13 11
auto[0] auto[1] auto[1] auto[1] auto[0] 42211 1 T1 26 T5 4 T6 34
auto[0] auto[1] auto[1] auto[1] auto[1] 34918 1 T2 16 T4 134 T5 9
auto[1] auto[0] auto[0] auto[0] auto[0] 176357 1 T1 611 T2 77 T4 2111
auto[1] auto[0] auto[0] auto[0] auto[1] 191259 1 T1 1662 T4 1193 T5 170
auto[1] auto[0] auto[0] auto[1] auto[0] 187591 1 T1 849 T2 50 T4 1087
auto[1] auto[0] auto[0] auto[1] auto[1] 176181 1 T1 208 T2 15 T5 74
auto[1] auto[0] auto[1] auto[0] auto[0] 1729791 1 T1 1271 T4 402 T5 73
auto[1] auto[0] auto[1] auto[0] auto[1] 184916 1 T1 2702 T2 15 T4 372
auto[1] auto[0] auto[1] auto[1] auto[0] 180971 1 T1 473 T2 1 T4 116
auto[1] auto[0] auto[1] auto[1] auto[1] 168241 1 T1 2133 T2 35 T4 1109
auto[1] auto[1] auto[0] auto[0] auto[0] 509251 1 T1 922 T2 39 T4 2110
auto[1] auto[1] auto[0] auto[0] auto[1] 467791 1 T1 156 T2 75 T4 269
auto[1] auto[1] auto[0] auto[1] auto[0] 502391 1 T1 29 T2 102 T4 337
auto[1] auto[1] auto[0] auto[1] auto[1] 467762 1 T1 704 T2 6 T5 1339
auto[1] auto[1] auto[1] auto[0] auto[0] 503959 1 T2 16 T3 2946 T4 235
auto[1] auto[1] auto[1] auto[0] auto[1] 456247 1 T2 12 T4 859 T5 2369
auto[1] auto[1] auto[1] auto[1] auto[0] 460550 1 T1 1114 T2 72 T4 371
auto[1] auto[1] auto[1] auto[1] auto[1] 459213 1 T1 1774 T2 34 T4 212


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 213728 1 T1 636 T2 86 T4 2900
auto[0] auto[0] auto[0] auto[0] auto[1] 224928 1 T1 1716 T4 1255 T5 186
auto[0] auto[0] auto[0] auto[1] auto[0] 218471 1 T1 859 T2 50 T4 1087
auto[0] auto[0] auto[0] auto[1] auto[1] 199485 1 T1 208 T2 15 T5 74
auto[0] auto[0] auto[1] auto[0] auto[0] 1860873 1 T1 1283 T4 402 T5 73
auto[0] auto[0] auto[1] auto[0] auto[1] 214672 1 T1 2756 T2 15 T4 488
auto[0] auto[0] auto[1] auto[1] auto[0] 208084 1 T1 491 T2 1 T4 177
auto[0] auto[0] auto[1] auto[1] auto[1] 198142 1 T1 2152 T2 35 T4 1448
auto[0] auto[1] auto[0] auto[0] auto[0] 547087 1 T1 959 T2 39 T4 2222
auto[0] auto[1] auto[0] auto[0] auto[1] 505191 1 T1 161 T2 75 T4 276
auto[0] auto[1] auto[0] auto[1] auto[0] 546431 1 T1 29 T2 117 T4 396
auto[0] auto[1] auto[0] auto[1] auto[1] 501805 1 T1 733 T2 20 T5 1339
auto[0] auto[1] auto[1] auto[0] auto[0] 552661 1 T2 16 T3 4299 T4 235
auto[0] auto[1] auto[1] auto[0] auto[1] 495068 1 T2 12 T4 859 T5 2429
auto[0] auto[1] auto[1] auto[1] auto[0] 501565 1 T1 1140 T2 72 T4 371
auto[0] auto[1] auto[1] auto[1] auto[1] 493651 1 T1 1774 T2 50 T4 346
auto[1] auto[0] auto[0] auto[0] auto[0] 647 1 T15 49 T10 2 T125 174
auto[1] auto[0] auto[0] auto[0] auto[1] 490 1 T15 34 T10 40 T145 7
auto[1] auto[0] auto[0] auto[1] auto[0] 856 1 T10 30 T125 20 T140 15
auto[1] auto[0] auto[0] auto[1] auto[1] 349 1 T15 1 T125 73 T146 1
auto[1] auto[0] auto[1] auto[0] auto[0] 842 1 T21 66 T125 4 T140 89
auto[1] auto[0] auto[1] auto[0] auto[1] 506 1 T15 16 T125 130 T140 194
auto[1] auto[0] auto[1] auto[1] auto[0] 521 1 T58 5 T140 32 T145 14
auto[1] auto[0] auto[1] auto[1] auto[1] 1706 1 T16 75 T10 154 T58 19
auto[1] auto[1] auto[0] auto[0] auto[0] 322 1 T58 58 T125 3 T140 2
auto[1] auto[1] auto[0] auto[0] auto[1] 1164 1 T125 8 T45 220 T147 735
auto[1] auto[1] auto[0] auto[1] auto[0] 323 1 T15 96 T16 3 T10 8
auto[1] auto[1] auto[0] auto[1] auto[1] 336 1 T15 1 T10 6 T125 3
auto[1] auto[1] auto[1] auto[0] auto[0] 292 1 T58 10 T146 11 T148 102
auto[1] auto[1] auto[1] auto[0] auto[1] 373 1 T125 1 T140 58 T145 84
auto[1] auto[1] auto[1] auto[1] auto[0] 1196 1 T10 1 T146 3 T45 6
auto[1] auto[1] auto[1] auto[1] auto[1] 480 1 T15 375 T16 3 T140 48


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 176357 1 T1 611 T2 77 T4 2111
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 191259 1 T1 1662 T4 1193 T5 170
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 187591 1 T1 849 T2 50 T4 1087
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 176181 1 T1 208 T2 15 T5 74
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1729791 1 T1 1271 T4 402 T5 73
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 184916 1 T1 2702 T2 15 T4 372
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 180971 1 T1 473 T2 1 T4 116
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 168241 1 T1 2133 T2 35 T4 1109
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 509251 1 T1 922 T2 39 T4 2110
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 467791 1 T1 156 T2 75 T4 269
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 502391 1 T1 29 T2 102 T4 337
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 467762 1 T1 704 T2 6 T5 1339
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 503959 1 T2 16 T3 2946 T4 235
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 456247 1 T2 12 T4 859 T5 2369
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 460550 1 T1 1114 T2 72 T4 371
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 459213 1 T1 1774 T2 34 T4 212
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3789 1 T1 23 T2 1 T4 125
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 4174 1 T1 38 T4 7 T5 2
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3804 1 T1 7 T6 9 T13 50
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3548 1 T12 14 T6 20 T14 18
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 41650 1 T1 9 T6 38 T18 11
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3669 1 T1 43 T4 20 T6 14
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 4044 1 T1 14 T4 14 T5 3
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3213 1 T1 14 T4 43 T6 7
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6511 1 T1 23 T4 16 T5 10
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6032 1 T1 5 T7 33 T6 45
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6497 1 T2 3 T4 11 T6 60
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 5427 1 T1 20 T2 2 T6 14
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8416 1 T3 152 T7 39 T6 20
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 5944 1 T5 46 T6 2 T14 12
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 6125 1 T1 18 T5 3 T6 9
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5894 1 T2 2 T4 20 T5 3
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3039 1 T1 2 T2 1 T4 127
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3197 1 T1 14 T4 4 T5 6
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3073 1 T1 3 T6 2 T13 47
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2706 1 T12 22 T6 6 T14 4
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 25984 1 T1 3 T6 5 T18 3
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2779 1 T1 9 T4 18 T6 6
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3174 1 T1 4 T4 13 T5 2
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2450 1 T1 4 T4 51 T13 1
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 5384 1 T1 13 T4 20 T5 2
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 4824 1 T4 2 T7 25 T6 8
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5434 1 T2 2 T4 10 T6 12
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4502 1 T1 7 T2 1 T6 10
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6717 1 T3 151 T7 39 T6 10
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5267 1 T5 10 T6 1 T13 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4973 1 T1 8 T5 1 T6 24
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4682 1 T2 2 T4 21 T5 4
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2403 1 T2 1 T4 163 T13 17
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2451 1 T1 2 T4 12 T5 3
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2419 1 T6 1 T13 48 T22 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2055 1 T12 7 T6 6 T22 1
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 17247 1 T6 3 T18 1 T21 1
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2123 1 T1 2 T4 10 T13 26
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2405 1 T4 13 T5 2 T6 3
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 1977 1 T1 1 T4 52 T5 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 4594 1 T4 14 T5 1 T6 2
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4085 1 T7 24 T6 3 T47 36
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4797 1 T2 2 T4 13 T6 1
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 3863 1 T1 2 T2 1 T6 2
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5658 1 T3 139 T7 42 T6 3
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 4651 1 T5 3 T13 2 T79 39
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4577 1 T6 1 T13 30 T18 4
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3949 1 T2 1 T4 35 T6 3
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2614 1 T2 3 T4 150 T13 20
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2366 1 T4 10 T5 4 T6 4
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2337 1 T6 3 T13 31 T79 9
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2183 1 T12 1 T6 2 T23 1
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 12285 1 T74 1 T21 1 T79 5
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2126 1 T4 18 T13 22 T79 28
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2415 1 T4 8 T5 2 T6 4
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2160 1 T4 56 T13 2 T79 35
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4448 1 T4 18 T6 1 T13 3
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 3750 1 T7 18 T18 1 T47 50
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4488 1 T2 3 T4 11 T13 8
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3664 1 T2 2 T6 7 T79 9
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5215 1 T3 133 T7 34 T13 20
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4570 1 T13 3 T79 43 T15 7
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 4201 1 T13 29 T18 1 T122 12
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3863 1 T2 2 T4 25 T5 2
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1913 1 T2 1 T4 103 T13 19
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1721 1 T4 11 T13 5 T15 2
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1640 1 T13 37 T79 8 T122 2
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1561 1 T6 3 T142 2 T15 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 8429 1 T6 1 T79 5 T15 5
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1571 1 T4 13 T13 27 T79 30
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1786 1 T4 6 T15 159 T8 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1649 1 T4 42 T13 1 T79 27
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3748 1 T1 1 T4 14 T5 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3189 1 T4 1 T7 17 T47 40
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3980 1 T2 1 T4 9 T6 1
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3143 1 T79 9 T121 1 T122 1
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4335 1 T3 144 T7 34 T13 21
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3756 1 T5 1 T79 36 T15 10
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3796 1 T13 31 T122 1 T15 3
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3069 1 T2 6 T4 13 T47 55
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1765 1 T4 67 T13 22 T79 22
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1515 1 T4 6 T5 1 T6 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1317 1 T13 34 T79 10 T122 2
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1396 1 T6 2 T122 4 T142 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 6125 1 T79 6 T15 8 T16 38
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1305 1 T4 18 T13 14 T79 24
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1523 1 T4 5 T5 1 T15 117
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1464 1 T4 49 T13 2 T79 22
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2882 1 T4 13 T13 2 T47 34
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2525 1 T4 1 T7 18 T47 26
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3272 1 T4 4 T13 5 T79 27
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2369 1 T2 2 T6 6 T79 12
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3415 1 T3 129 T7 30 T13 21
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3186 1 T79 24 T15 10 T139 2
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2993 1 T13 35 T74 1 T122 4
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2475 1 T2 2 T4 9 T47 56
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1280 1 T2 2 T4 38 T13 9
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 920 1 T4 3 T13 8 T15 2
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 801 1 T13 18 T79 5 T122 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 789 1 T10 55 T123 22 T58 7
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 3529 1 T21 6 T79 4 T15 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 896 1 T4 9 T13 17 T79 13
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 793 1 T15 11 T10 45 T123 3
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 999 1 T4 23 T13 1 T79 11
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2015 1 T4 10 T13 2 T47 21
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1864 1 T4 1 T7 11 T47 16
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2316 1 T2 1 T4 1 T13 3
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1635 1 T2 1 T79 4 T15 15
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2377 1 T3 127 T7 16 T13 15
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2110 1 T79 13 T15 9 T139 1
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2122 1 T13 19 T15 2 T16 8
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1637 1 T4 9 T47 35 T122 2

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