Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18578707	1			T1	29719		T2	1203		T3	8489
all_pins[1]	18578707	1			T1	29719		T2	1203		T3	8489
all_pins[2]	18578707	1			T1	29719		T2	1203		T3	8489

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47458191	1			T1	77901		T2	3001		T3	25287
values[0x1]	8277930	1			T1	11256		T2	608		T3	180
transitions[0x0=>0x1]	8277725	1			T1	11256		T2	608		T3	180
transitions[0x1=>0x0]	8277743	1			T1	11256		T2	608		T3	180

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18557358	1			T1	29681		T2	1187		T3	8309
all_pins[0]	values[0x1]	21349	1			T1	38		T2	16		T3	180
all_pins[0]	transitions[0x0=>0x1]	21262	1			T1	38		T2	16		T3	180
all_pins[0]	transitions[0x1=>0x0]	8256123	1			T1	11218		T2	592		T4	9616
all_pins[1]	values[0x0]	18578318	1			T1	29719		T2	1203		T3	8489
all_pins[1]	values[0x1]	389	1			T18	9		T21	2		T15	3
all_pins[1]	transitions[0x0=>0x1]	329	1			T18	4		T21	2		T15	3
all_pins[1]	transitions[0x1=>0x0]	21289	1			T1	38		T2	16		T3	180
all_pins[2]	values[0x0]	10322515	1			T1	18501		T2	611		T3	8489
all_pins[2]	values[0x1]	8256192	1			T1	11218		T2	592		T4	9616
all_pins[2]	transitions[0x0=>0x1]	8256134	1			T1	11218		T2	592		T4	9616
all_pins[2]	transitions[0x1=>0x0]	331	1			T18	4		T21	2		T15	3