Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1057 1 T18 37 T8 11 T10 7
all_values[1] 1057 1 T18 37 T8 11 T10 7
all_values[2] 1057 1 T18 37 T8 11 T10 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1576 1 T18 52 T8 19 T10 17
auto[1] 1595 1 T18 59 T8 14 T10 4


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1156 1 T18 49 T8 11 T10 7
auto[1] 2015 1 T18 62 T8 22 T10 14


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1818 1 T18 68 T8 17 T10 13
auto[1] 1353 1 T18 43 T8 16 T10 8


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 195 1 T18 3 T8 5 T10 2
all_values[0] auto[0] auto[0] auto[1] 103 1 T18 4 T8 1 T10 2
all_values[0] auto[0] auto[1] auto[0] 199 1 T18 9 T8 2 T127 1
all_values[0] auto[0] auto[1] auto[1] 101 1 T18 3 T127 1 T75 4
all_values[0] auto[1] auto[0] auto[1] 238 1 T18 8 T8 2 T10 2
all_values[0] auto[1] auto[1] auto[1] 221 1 T18 10 T8 1 T10 1
all_values[1] auto[0] auto[0] auto[0] 174 1 T18 10 T8 1 T10 1
all_values[1] auto[0] auto[0] auto[1] 125 1 T18 5 T8 3 T10 2
all_values[1] auto[0] auto[1] auto[0] 172 1 T18 4 T8 2 T127 2
all_values[1] auto[0] auto[1] auto[1] 132 1 T18 3 T127 1 T75 4
all_values[1] auto[1] auto[0] auto[1] 214 1 T18 5 T8 3 T10 4
all_values[1] auto[1] auto[1] auto[1] 240 1 T18 10 T8 2 T75 2
all_values[2] auto[0] auto[0] auto[0] 209 1 T18 14 T10 3 T127 4
all_values[2] auto[0] auto[0] auto[1] 105 1 T18 1 T8 1 T127 1
all_values[2] auto[0] auto[1] auto[0] 207 1 T18 9 T8 1 T10 1
all_values[2] auto[0] auto[1] auto[1] 96 1 T18 3 T8 1 T10 2
all_values[2] auto[1] auto[0] auto[1] 213 1 T18 2 T8 3 T10 1
all_values[2] auto[1] auto[1] auto[1] 227 1 T18 8 T8 5 T127 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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