Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4539	1			T1	9		T2	5		T4	9
sha2_none	4630	1			T1	7		T2	9		T4	2
sha2_512	7941	1			T1	9		T2	5		T4	4
sha2_384	7566	1			T1	7		T2	5		T3	180
sha2_256	6527	1			T1	9		T2	7		T4	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19422

1

T1

22

T2

11

T3

180

auto[1]

12193

1

T1

19

T2

20

T4

12

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12020

1

T1

20

T2

19

T4

23

auto[1]

19595

1

T1

21

T2

12

T3

180

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16351

1

T1

13

T2

19

T3

180

disabled

15264

1

T1

28

T2

12

T4

18

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4959	1			T1	5		T2	8		T4	3
key_none	7961	1			T1	5		T2	5		T4	10
key_1024	4543	1			T1	7		T2	3		T3	60
key_512	3946	1			T1	2		T2	4		T3	120
key_384	3572	1			T1	6		T2	4		T4	6
key_256	3370	1			T1	9		T2	3		T4	3
key_128	3171	1			T1	7		T2	4		T4	7

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19709

1

T1

23

T2

19

T3

180

auto[1]

11906

1

T1

18

T2

12

T4

11

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

31436

1

T1

41

T2

31

T3

180

disabled

179

1

T6

2

T18

1

T48

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1698

1

T1

3

T2

2

T4

6

enabled

auto[0]

auto[0]

auto[1]

1628

1

T1

1

T2

2

T4

2

enabled

auto[0]

auto[1]

auto[0]

1751

1

T1

1

T2

5

T4

3

enabled

auto[0]

auto[1]

auto[1]

1721

1

T1

2

T2

2

T5

2

enabled

auto[1]

auto[0]

auto[0]

4381

1

T2

1

T3

180

T4

1

enabled

auto[1]

auto[0]

auto[1]

1662

1

T2

1

T4

1

T5

3

enabled

auto[1]

auto[1]

auto[0]

1810

1

T1

4

T2

3

T4

1

enabled

auto[1]

auto[1]

auto[1]

1700

1

T1

2

T2

3

T4

1

disabled

auto[0]

auto[0]

auto[0]

1339

1

T1

5

T2

4

T4

6

disabled

auto[0]

auto[0]

auto[1]

1242

1

T1

4

T4

3

T5

3

disabled

auto[0]

auto[1]

auto[0]

1337

1

T1

2

T2

3

T4

3

disabled

auto[0]

auto[1]

auto[1]

1304

1

T1

2

T2

1

T5

1

disabled

auto[1]

auto[0]

auto[0]

6125

1

T1

6

T4

1

T5

4

disabled

auto[1]

auto[0]

auto[1]

1347

1

T1

3

T2

1

T4

1

disabled

auto[1]

auto[1]

auto[0]

1268

1

T1

2

T2

1

T4

1

disabled

auto[1]

auto[1]

auto[1]

1302

1

T1

4

T2

2

T4

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16284

1

T1

13

T2

19

T3

180

enabled

disabled

67

1

T127

1

T75

1

T137

1

disabled

disabled

112

1

T6

2

T18

1

T48

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15152

1

T1

28

T2

12

T4

18

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1152	1			T2	2		T4	1		T5	5
key_invalid	sha2_none	970	1			T1	2		T2	1		T5	1
key_invalid	sha2_512	965	1			T1	2		T2	2		T5	2
key_invalid	sha2_384	902	1			T2	1		T4	2		T5	1
key_invalid	sha2_256	873	1			T1	1		T2	2		T5	2
key_none	sha2_invalid	537	1			T1	1		T2	1		T4	1
key_none	sha2_none	585	1			T1	1		T2	1		T6	16
key_none	sha2_512	2597	1			T1	1		T2	1		T4	3
key_none	sha2_384	2586	1			T1	1		T2	1		T4	5
key_none	sha2_256	1604	1			T1	1		T2	1		T4	1
key_1024	sha2_invalid	571	1			T1	3		T6	6		T13	3
key_1024	sha2_none	589	1			T1	1		T2	2		T4	1
key_1024	sha2_512	1755	1			T1	1		T6	10		T14	2
key_1024	sha2_384	950	1			T1	1		T2	1		T3	60
key_512	sha2_invalid	554	1			T2	1		T6	11		T18	3
key_512	sha2_none	595	1			T5	1		T12	1		T6	7
key_512	sha2_512	652	1			T1	1		T6	14		T13	3
key_512	sha2_384	1248	1			T2	2		T3	120		T7	1
key_512	sha2_256	839	1			T1	1		T2	1		T4	1
key_384	sha2_invalid	580	1			T2	1		T4	3		T5	3
key_384	sha2_none	606	1			T1	1		T2	2		T5	3
key_384	sha2_512	660	1			T1	2		T2	1		T5	5
key_384	sha2_384	590	1			T1	3		T4	2		T5	1
key_384	sha2_256	1074	1			T5	1		T12	1		T6	4
key_256	sha2_invalid	573	1			T1	2		T4	2		T6	8
key_256	sha2_none	624	1			T1	2		T2	2		T5	2
key_256	sha2_512	645	1			T1	1		T5	5		T6	12
key_256	sha2_384	629	1			T1	1		T6	5		T13	4
key_256	sha2_256	864	1			T1	3		T2	1		T4	1
key_128	sha2_invalid	548	1			T1	3		T4	2		T7	1
key_128	sha2_none	644	1			T2	1		T4	1		T5	1
key_128	sha2_512	656	1			T1	1		T2	1		T4	1
key_128	sha2_384	642	1			T1	1		T4	1		T5	2
key_128	sha2_256	622	1			T1	2		T2	2		T4	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

630

1

T1

1

T4

2

T5

4

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1152	1			T2	2		T4	1		T5	5
key_invalid	sha2_none	970	1			T1	2		T2	1		T5	1
key_invalid	sha2_512	965	1			T1	2		T2	2		T5	2
key_invalid	sha2_384	902	1			T2	1		T4	2		T5	1
key_invalid	sha2_256	873	1			T1	1		T2	2		T5	2
key_none	sha2_invalid	537	1			T1	1		T2	1		T4	1
key_none	sha2_none	585	1			T1	1		T2	1		T6	16
key_none	sha2_512	2597	1			T1	1		T2	1		T4	3
key_none	sha2_384	2586	1			T1	1		T2	1		T4	5
key_none	sha2_256	1604	1			T1	1		T2	1		T4	1
key_1024	sha2_invalid	571	1			T1	3		T6	6		T13	3
key_1024	sha2_none	589	1			T1	1		T2	2		T4	1
key_1024	sha2_512	1755	1			T1	1		T6	10		T14	2
key_1024	sha2_384	950	1			T1	1		T2	1		T3	60
key_1024	sha2_256	630	1			T1	1		T4	2		T5	4
key_512	sha2_invalid	554	1			T2	1		T6	11		T18	3
key_512	sha2_none	595	1			T5	1		T12	1		T6	7
key_512	sha2_512	652	1			T1	1		T6	14		T13	3
key_512	sha2_384	1248	1			T2	2		T3	120		T7	1
key_512	sha2_256	839	1			T1	1		T2	1		T4	1
key_384	sha2_invalid	580	1			T2	1		T4	3		T5	3
key_384	sha2_none	606	1			T1	1		T2	2		T5	3
key_384	sha2_512	660	1			T1	2		T2	1		T5	5
key_384	sha2_384	590	1			T1	3		T4	2		T5	1
key_384	sha2_256	1074	1			T5	1		T12	1		T6	4
key_256	sha2_invalid	573	1			T1	2		T4	2		T6	8
key_256	sha2_none	624	1			T1	2		T2	2		T5	2
key_256	sha2_512	645	1			T1	1		T5	5		T6	12
key_256	sha2_384	629	1			T1	1		T6	5		T13	4
key_256	sha2_256	864	1			T1	3		T2	1		T4	1
key_128	sha2_invalid	548	1			T1	3		T4	2		T7	1
key_128	sha2_none	644	1			T2	1		T4	1		T5	1
key_128	sha2_512	656	1			T1	1		T2	1		T4	1
key_128	sha2_384	642	1			T1	1		T4	1		T5	2
key_128	sha2_256	622	1			T1	2		T2	2		T4	2