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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.04 95.40 97.22 100.00 97.06 98.27 98.48 99.85


Total test records in report: 660
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T112 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3175363353 Jul 31 05:08:42 PM PDT 24 Jul 31 05:08:44 PM PDT 24 79793588 ps
T537 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2144212375 Jul 31 05:09:01 PM PDT 24 Jul 31 05:09:03 PM PDT 24 29040388 ps
T538 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2392045335 Jul 31 05:08:42 PM PDT 24 Jul 31 05:08:42 PM PDT 24 27074059 ps
T113 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1051256662 Jul 31 05:08:56 PM PDT 24 Jul 31 05:08:58 PM PDT 24 310910743 ps
T539 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4255023037 Jul 31 05:08:39 PM PDT 24 Jul 31 05:08:44 PM PDT 24 451376071 ps
T540 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.173613549 Jul 31 05:08:39 PM PDT 24 Jul 31 05:08:42 PM PDT 24 205016403 ps
T541 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1563490562 Jul 31 05:08:43 PM PDT 24 Jul 31 05:08:45 PM PDT 24 139653403 ps
T114 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1794545448 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:53 PM PDT 24 184212149 ps
T542 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2394347719 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:55 PM PDT 24 101132058 ps
T543 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3530692308 Jul 31 05:08:55 PM PDT 24 Jul 31 05:08:55 PM PDT 24 30081187 ps
T544 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1641166516 Jul 31 05:09:04 PM PDT 24 Jul 31 05:09:05 PM PDT 24 73931677 ps
T67 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3693849283 Jul 31 05:08:45 PM PDT 24 Jul 31 05:08:46 PM PDT 24 424869142 ps
T115 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2774470208 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:53 PM PDT 24 33031671 ps
T545 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3965807935 Jul 31 05:09:08 PM PDT 24 Jul 31 05:09:09 PM PDT 24 98068493 ps
T68 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.839652720 Jul 31 05:08:56 PM PDT 24 Jul 31 05:09:00 PM PDT 24 539494530 ps
T116 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.201148882 Jul 31 05:08:45 PM PDT 24 Jul 31 05:08:48 PM PDT 24 110616041 ps
T546 /workspace/coverage/cover_reg_top/49.hmac_intr_test.93704125 Jul 31 05:09:15 PM PDT 24 Jul 31 05:09:15 PM PDT 24 13665796 ps
T117 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2517498709 Jul 31 05:08:43 PM PDT 24 Jul 31 05:08:44 PM PDT 24 52849522 ps
T547 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2574050840 Jul 31 05:09:13 PM PDT 24 Jul 31 05:09:14 PM PDT 24 12881884 ps
T69 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.449805278 Jul 31 05:08:54 PM PDT 24 Jul 31 05:08:56 PM PDT 24 956481500 ps
T128 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2941055543 Jul 31 05:08:34 PM PDT 24 Jul 31 05:08:38 PM PDT 24 331533064 ps
T548 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2792718818 Jul 31 05:09:10 PM PDT 24 Jul 31 05:09:11 PM PDT 24 23964301 ps
T549 /workspace/coverage/cover_reg_top/3.hmac_intr_test.4225479357 Jul 31 05:08:44 PM PDT 24 Jul 31 05:08:44 PM PDT 24 31977414 ps
T550 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1871204455 Jul 31 05:08:46 PM PDT 24 Jul 31 05:08:48 PM PDT 24 77572469 ps
T551 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2565237273 Jul 31 05:08:38 PM PDT 24 Jul 31 05:08:39 PM PDT 24 13000247 ps
T129 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.658471063 Jul 31 05:08:55 PM PDT 24 Jul 31 05:08:58 PM PDT 24 200701727 ps
T118 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3100441505 Jul 31 05:08:43 PM PDT 24 Jul 31 05:08:44 PM PDT 24 68678511 ps
T97 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3820755899 Jul 31 05:08:34 PM PDT 24 Jul 31 05:08:35 PM PDT 24 110390372 ps
T552 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1525211197 Jul 31 05:09:08 PM PDT 24 Jul 31 05:09:08 PM PDT 24 14337108 ps
T119 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.515209716 Jul 31 05:09:02 PM PDT 24 Jul 31 05:09:03 PM PDT 24 14448335 ps
T553 /workspace/coverage/cover_reg_top/29.hmac_intr_test.636371106 Jul 31 05:09:07 PM PDT 24 Jul 31 05:09:08 PM PDT 24 22299592 ps
T554 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2270092381 Jul 31 05:08:35 PM PDT 24 Jul 31 05:08:37 PM PDT 24 222761696 ps
T555 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3227571348 Jul 31 05:09:09 PM PDT 24 Jul 31 05:09:10 PM PDT 24 365660017 ps
T556 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3412383013 Jul 31 05:09:13 PM PDT 24 Jul 31 05:09:13 PM PDT 24 85845471 ps
T557 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2019704876 Jul 31 05:09:10 PM PDT 24 Jul 31 05:09:10 PM PDT 24 16745105 ps
T98 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1862916030 Jul 31 05:08:41 PM PDT 24 Jul 31 05:08:47 PM PDT 24 998484434 ps
T558 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3801129941 Jul 31 05:08:50 PM PDT 24 Jul 31 05:08:51 PM PDT 24 41638957 ps
T559 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2993033182 Jul 31 05:08:41 PM PDT 24 Jul 31 05:08:42 PM PDT 24 20736384 ps
T560 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1618100394 Jul 31 05:08:43 PM PDT 24 Jul 31 05:08:44 PM PDT 24 14891771 ps
T561 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3020111468 Jul 31 05:09:06 PM PDT 24 Jul 31 05:09:06 PM PDT 24 37221421 ps
T562 /workspace/coverage/cover_reg_top/17.hmac_intr_test.782100508 Jul 31 05:09:03 PM PDT 24 Jul 31 05:09:04 PM PDT 24 36425869 ps
T120 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.823081184 Jul 31 05:08:57 PM PDT 24 Jul 31 05:08:59 PM PDT 24 77250895 ps
T134 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.124066673 Jul 31 05:08:39 PM PDT 24 Jul 31 05:08:41 PM PDT 24 167767754 ps
T135 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2210272524 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:54 PM PDT 24 110274124 ps
T563 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.182210688 Jul 31 05:08:44 PM PDT 24 Jul 31 05:08:45 PM PDT 24 57697034 ps
T564 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1468204998 Jul 31 05:09:14 PM PDT 24 Jul 31 05:09:14 PM PDT 24 39205050 ps
T565 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2224469306 Jul 31 05:09:00 PM PDT 24 Jul 31 05:09:01 PM PDT 24 23894848 ps
T566 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.22284202 Jul 31 05:08:58 PM PDT 24 Jul 31 05:09:00 PM PDT 24 711879531 ps
T567 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3091384998 Jul 31 05:09:12 PM PDT 24 Jul 31 05:09:13 PM PDT 24 39054933 ps
T568 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1712632733 Jul 31 05:08:55 PM PDT 24 Jul 31 05:08:58 PM PDT 24 115127384 ps
T569 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1461825792 Jul 31 05:09:04 PM PDT 24 Jul 31 05:09:06 PM PDT 24 80841203 ps
T570 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2885569809 Jul 31 05:09:12 PM PDT 24 Jul 31 05:09:12 PM PDT 24 18758289 ps
T571 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2097470918 Jul 31 05:08:57 PM PDT 24 Jul 31 05:08:59 PM PDT 24 87142785 ps
T572 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1227747754 Jul 31 05:08:45 PM PDT 24 Jul 31 05:08:45 PM PDT 24 21114370 ps
T573 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2751259634 Jul 31 05:08:56 PM PDT 24 Jul 31 05:08:57 PM PDT 24 120952550 ps
T574 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1899604131 Jul 31 05:08:36 PM PDT 24 Jul 31 05:08:36 PM PDT 24 16977152 ps
T99 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1316977444 Jul 31 05:08:47 PM PDT 24 Jul 31 05:08:56 PM PDT 24 1855404615 ps
T130 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.348433074 Jul 31 05:08:57 PM PDT 24 Jul 31 05:09:01 PM PDT 24 249101589 ps
T575 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2877983026 Jul 31 05:08:53 PM PDT 24 Jul 31 05:08:56 PM PDT 24 167226940 ps
T576 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1012983289 Jul 31 05:09:01 PM PDT 24 Jul 31 05:09:03 PM PDT 24 35258772 ps
T577 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.243980655 Jul 31 05:08:56 PM PDT 24 Jul 31 05:08:57 PM PDT 24 14976579 ps
T578 /workspace/coverage/cover_reg_top/19.hmac_intr_test.476009798 Jul 31 05:09:08 PM PDT 24 Jul 31 05:09:09 PM PDT 24 14549125 ps
T579 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1837417387 Jul 31 05:08:53 PM PDT 24 Jul 31 05:08:55 PM PDT 24 50911550 ps
T100 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3391344276 Jul 31 05:08:46 PM PDT 24 Jul 31 05:08:47 PM PDT 24 17396289 ps
T101 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3332222802 Jul 31 05:09:06 PM PDT 24 Jul 31 05:09:07 PM PDT 24 58993785 ps
T580 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2065466192 Jul 31 05:09:09 PM PDT 24 Jul 31 05:09:10 PM PDT 24 41198410 ps
T581 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1268364551 Jul 31 05:08:44 PM PDT 24 Jul 31 05:08:54 PM PDT 24 2817489468 ps
T582 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3395267282 Jul 31 05:08:39 PM PDT 24 Jul 31 05:08:40 PM PDT 24 28938045 ps
T583 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3235853194 Jul 31 05:09:07 PM PDT 24 Jul 31 05:09:09 PM PDT 24 32852065 ps
T584 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1252296064 Jul 31 05:09:09 PM PDT 24 Jul 31 05:09:10 PM PDT 24 31414200 ps
T585 /workspace/coverage/cover_reg_top/14.hmac_intr_test.614962055 Jul 31 05:09:04 PM PDT 24 Jul 31 05:09:04 PM PDT 24 11381440 ps
T586 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2322123357 Jul 31 05:09:09 PM PDT 24 Jul 31 05:09:11 PM PDT 24 185490603 ps
T102 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3242912222 Jul 31 05:08:56 PM PDT 24 Jul 31 05:08:57 PM PDT 24 48608933 ps
T131 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3052662280 Jul 31 05:09:01 PM PDT 24 Jul 31 05:09:04 PM PDT 24 169585199 ps
T587 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.535121087 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:54 PM PDT 24 179627017 ps
T105 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4103046684 Jul 31 05:08:38 PM PDT 24 Jul 31 05:08:49 PM PDT 24 426079032 ps
T588 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1802087404 Jul 31 05:09:07 PM PDT 24 Jul 31 05:09:08 PM PDT 24 243449417 ps
T589 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4091956331 Jul 31 05:08:45 PM PDT 24 Jul 31 05:08:47 PM PDT 24 74840218 ps
T590 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3456198685 Jul 31 05:08:57 PM PDT 24 Jul 31 05:08:58 PM PDT 24 45872449 ps
T591 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2656057820 Jul 31 05:09:09 PM PDT 24 Jul 31 05:09:11 PM PDT 24 83202005 ps
T592 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4185766524 Jul 31 05:09:06 PM PDT 24 Jul 31 05:09:07 PM PDT 24 40414038 ps
T593 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4108644157 Jul 31 05:09:03 PM PDT 24 Jul 31 05:09:04 PM PDT 24 75039955 ps
T594 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.565904924 Jul 31 05:08:43 PM PDT 24 Jul 31 05:08:49 PM PDT 24 111691020 ps
T595 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1534758154 Jul 31 05:08:56 PM PDT 24 Jul 31 05:08:59 PM PDT 24 134788477 ps
T70 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.659704479 Jul 31 05:08:45 PM PDT 24 Jul 31 05:08:47 PM PDT 24 48261730 ps
T596 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2488971132 Jul 31 05:09:07 PM PDT 24 Jul 31 05:09:08 PM PDT 24 14499230 ps
T597 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3100533929 Jul 31 05:08:55 PM PDT 24 Jul 31 05:08:55 PM PDT 24 53638677 ps
T598 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1308422278 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:54 PM PDT 24 179854849 ps
T599 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1209246812 Jul 31 05:09:09 PM PDT 24 Jul 31 05:09:10 PM PDT 24 108676622 ps
T600 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1163792185 Jul 31 05:08:51 PM PDT 24 Jul 31 05:08:53 PM PDT 24 330230581 ps
T136 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3619620196 Jul 31 05:08:39 PM PDT 24 Jul 31 05:08:42 PM PDT 24 491386581 ps
T601 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3988990103 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:53 PM PDT 24 36562061 ps
T602 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3977753447 Jul 31 05:08:39 PM PDT 24 Jul 31 05:08:41 PM PDT 24 148947443 ps
T603 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1230303872 Jul 31 05:09:08 PM PDT 24 Jul 31 05:09:09 PM PDT 24 13487878 ps
T604 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3890695726 Jul 31 05:08:51 PM PDT 24 Jul 31 05:08:52 PM PDT 24 27064336 ps
T605 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2119872795 Jul 31 05:09:09 PM PDT 24 Jul 31 05:09:11 PM PDT 24 130398295 ps
T606 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2822486925 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:56 PM PDT 24 58960075 ps
T607 /workspace/coverage/cover_reg_top/11.hmac_intr_test.859970807 Jul 31 05:08:57 PM PDT 24 Jul 31 05:08:58 PM PDT 24 30150766 ps
T103 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.684880261 Jul 31 05:08:51 PM PDT 24 Jul 31 05:08:52 PM PDT 24 77991103 ps
T104 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3831009138 Jul 31 05:08:42 PM PDT 24 Jul 31 05:08:54 PM PDT 24 1053159802 ps
T608 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1552395936 Jul 31 05:09:07 PM PDT 24 Jul 31 05:09:08 PM PDT 24 38554681 ps
T609 /workspace/coverage/cover_reg_top/36.hmac_intr_test.352502825 Jul 31 05:09:12 PM PDT 24 Jul 31 05:09:13 PM PDT 24 119675469 ps
T610 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4029619947 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:53 PM PDT 24 120900132 ps
T611 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3654090154 Jul 31 05:09:07 PM PDT 24 Jul 31 05:09:08 PM PDT 24 31771974 ps
T612 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2530218098 Jul 31 05:09:12 PM PDT 24 Jul 31 05:09:13 PM PDT 24 22039816 ps
T613 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2915243653 Jul 31 05:08:56 PM PDT 24 Jul 31 05:23:27 PM PDT 24 168689568001 ps
T614 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1699333114 Jul 31 05:09:01 PM PDT 24 Jul 31 05:09:03 PM PDT 24 128164443 ps
T615 /workspace/coverage/cover_reg_top/7.hmac_intr_test.982926651 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:53 PM PDT 24 17597309 ps
T132 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2104782835 Jul 31 05:08:58 PM PDT 24 Jul 31 05:09:03 PM PDT 24 952426180 ps
T616 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3586870084 Jul 31 05:09:10 PM PDT 24 Jul 31 05:09:11 PM PDT 24 26844090 ps
T106 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3494336308 Jul 31 05:08:55 PM PDT 24 Jul 31 05:08:56 PM PDT 24 93081719 ps
T617 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1771165039 Jul 31 05:08:56 PM PDT 24 Jul 31 05:08:57 PM PDT 24 17871299 ps
T618 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3976882695 Jul 31 05:09:02 PM PDT 24 Jul 31 05:09:04 PM PDT 24 99374575 ps
T619 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3821934976 Jul 31 05:09:05 PM PDT 24 Jul 31 05:09:06 PM PDT 24 58749335 ps
T620 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1989750788 Jul 31 05:08:42 PM PDT 24 Jul 31 05:08:44 PM PDT 24 144159617 ps
T621 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3326436711 Jul 31 05:08:43 PM PDT 24 Jul 31 05:08:59 PM PDT 24 1052191804 ps
T622 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.303760467 Jul 31 05:09:01 PM PDT 24 Jul 31 05:09:02 PM PDT 24 34299606 ps
T623 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.961533232 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:53 PM PDT 24 97435997 ps
T624 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3195492549 Jul 31 05:08:43 PM PDT 24 Jul 31 05:08:47 PM PDT 24 182870588 ps
T625 /workspace/coverage/cover_reg_top/22.hmac_intr_test.946074547 Jul 31 05:09:08 PM PDT 24 Jul 31 05:09:09 PM PDT 24 12611541 ps
T626 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1366996091 Jul 31 05:08:45 PM PDT 24 Jul 31 05:08:46 PM PDT 24 26673311 ps
T627 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1065943394 Jul 31 05:08:58 PM PDT 24 Jul 31 05:08:59 PM PDT 24 154936737 ps
T628 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.855769723 Jul 31 05:09:01 PM PDT 24 Jul 31 05:09:03 PM PDT 24 254605972 ps
T629 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1190504223 Jul 31 05:08:45 PM PDT 24 Jul 31 05:08:46 PM PDT 24 69402451 ps
T630 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3748537229 Jul 31 05:08:56 PM PDT 24 Jul 31 05:08:58 PM PDT 24 83558040 ps
T631 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4018787995 Jul 31 05:08:56 PM PDT 24 Jul 31 05:08:58 PM PDT 24 91640211 ps
T632 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1052369212 Jul 31 05:08:54 PM PDT 24 Jul 31 05:08:55 PM PDT 24 15290071 ps
T110 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2190782200 Jul 31 05:08:44 PM PDT 24 Jul 31 05:08:45 PM PDT 24 68583833 ps
T633 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2715783984 Jul 31 05:08:47 PM PDT 24 Jul 31 05:08:48 PM PDT 24 94776730 ps
T634 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1506090310 Jul 31 05:08:54 PM PDT 24 Jul 31 05:08:55 PM PDT 24 47057673 ps
T107 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.6091654 Jul 31 05:08:45 PM PDT 24 Jul 31 05:08:48 PM PDT 24 218649621 ps
T635 /workspace/coverage/cover_reg_top/21.hmac_intr_test.509801239 Jul 31 05:09:08 PM PDT 24 Jul 31 05:09:09 PM PDT 24 44663860 ps
T636 /workspace/coverage/cover_reg_top/46.hmac_intr_test.4132762686 Jul 31 05:09:11 PM PDT 24 Jul 31 05:09:12 PM PDT 24 15208538 ps
T637 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.702534918 Jul 31 05:09:04 PM PDT 24 Jul 31 05:09:06 PM PDT 24 92797581 ps
T133 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1691370211 Jul 31 05:09:04 PM PDT 24 Jul 31 05:09:08 PM PDT 24 871186011 ps
T638 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.936691559 Jul 31 05:08:47 PM PDT 24 Jul 31 05:08:48 PM PDT 24 58284510 ps
T639 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3897421891 Jul 31 05:09:04 PM PDT 24 Jul 31 05:09:06 PM PDT 24 89475820 ps
T640 /workspace/coverage/cover_reg_top/45.hmac_intr_test.4240407695 Jul 31 05:09:12 PM PDT 24 Jul 31 05:09:13 PM PDT 24 18218955 ps
T641 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3204024409 Jul 31 05:08:43 PM PDT 24 Jul 31 05:08:44 PM PDT 24 98927146 ps
T642 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2146144344 Jul 31 05:09:09 PM PDT 24 Jul 31 05:09:10 PM PDT 24 41626065 ps
T643 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1797941986 Jul 31 05:08:57 PM PDT 24 Jul 31 05:08:58 PM PDT 24 48205036 ps
T644 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.418850347 Jul 31 05:09:00 PM PDT 24 Jul 31 05:09:02 PM PDT 24 247093713 ps
T645 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2182661596 Jul 31 05:09:00 PM PDT 24 Jul 31 05:09:00 PM PDT 24 13859352 ps
T646 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1572849572 Jul 31 05:09:09 PM PDT 24 Jul 31 05:09:10 PM PDT 24 124226724 ps
T647 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3892592160 Jul 31 05:08:51 PM PDT 24 Jul 31 05:08:54 PM PDT 24 137357152 ps
T108 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3295001971 Jul 31 05:08:40 PM PDT 24 Jul 31 05:08:41 PM PDT 24 21702434 ps
T648 /workspace/coverage/cover_reg_top/44.hmac_intr_test.356587018 Jul 31 05:09:12 PM PDT 24 Jul 31 05:09:13 PM PDT 24 53660103 ps
T109 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1198171539 Jul 31 05:09:03 PM PDT 24 Jul 31 05:09:03 PM PDT 24 19513870 ps
T649 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2378982355 Jul 31 05:08:56 PM PDT 24 Jul 31 05:09:00 PM PDT 24 299955875 ps
T650 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4144976797 Jul 31 05:09:08 PM PDT 24 Jul 31 05:09:10 PM PDT 24 134440251 ps
T651 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3551896816 Jul 31 05:08:54 PM PDT 24 Jul 31 05:08:57 PM PDT 24 76150820 ps
T652 /workspace/coverage/cover_reg_top/27.hmac_intr_test.833790170 Jul 31 05:09:08 PM PDT 24 Jul 31 05:09:09 PM PDT 24 17257636 ps
T653 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3025734737 Jul 31 05:09:08 PM PDT 24 Jul 31 05:09:09 PM PDT 24 24545484 ps
T654 /workspace/coverage/cover_reg_top/16.hmac_intr_test.192129207 Jul 31 05:09:04 PM PDT 24 Jul 31 05:09:04 PM PDT 24 34767328 ps
T655 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3932552354 Jul 31 05:09:08 PM PDT 24 Jul 31 05:09:09 PM PDT 24 24160263 ps
T656 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1006954711 Jul 31 05:08:52 PM PDT 24 Jul 31 05:08:53 PM PDT 24 47142076 ps
T657 /workspace/coverage/cover_reg_top/10.hmac_intr_test.47187751 Jul 31 05:08:56 PM PDT 24 Jul 31 05:08:57 PM PDT 24 60152210 ps
T658 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2346129179 Jul 31 05:08:54 PM PDT 24 Jul 31 05:08:56 PM PDT 24 595693655 ps
T659 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3039400989 Jul 31 05:09:09 PM PDT 24 Jul 31 05:09:12 PM PDT 24 257883803 ps
T660 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1032649449 Jul 31 05:08:44 PM PDT 24 Jul 31 05:08:49 PM PDT 24 1433960447 ps

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1129001625
Short name T6
Test name
Test status
Simulation time 514214034683 ps
CPU time 1171.14 seconds
Started Jul 31 07:07:59 PM PDT 24
Finished Jul 31 07:27:30 PM PDT 24
Peak memory 680476 kb
Host smart-a0838fe3-3533-45d4-ad54-f95094bcbe2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129001625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1129001625
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2087389517
Short name T10
Test name
Test status
Simulation time 18515722873 ps
CPU time 1124.35 seconds
Started Jul 31 07:07:59 PM PDT 24
Finished Jul 31 07:26:43 PM PDT 24
Peak memory 366056 kb
Host smart-4fe0e16f-5d52-44b6-9c5e-ce2630ff3620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087389517 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2087389517
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1935503828
Short name T5
Test name
Test status
Simulation time 11063016132 ps
CPU time 249 seconds
Started Jul 31 07:06:36 PM PDT 24
Finished Jul 31 07:10:45 PM PDT 24
Peak memory 449256 kb
Host smart-dad4de8c-19b1-4d7a-8891-9ac3a3dd533c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935503828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1935503828
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.839652720
Short name T68
Test name
Test status
Simulation time 539494530 ps
CPU time 3.93 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:09:00 PM PDT 24
Peak memory 200060 kb
Host smart-d7ea83b4-4289-4d91-b227-c51a1efebbb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839652720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.839652720
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3645867382
Short name T50
Test name
Test status
Simulation time 18149081 ps
CPU time 0.59 seconds
Started Jul 31 07:12:21 PM PDT 24
Finished Jul 31 07:12:22 PM PDT 24
Peak memory 194992 kb
Host smart-6089b90b-e1d7-4c37-a1f5-bad95d2c0fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645867382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3645867382
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1320986535
Short name T140
Test name
Test status
Simulation time 10892253639 ps
CPU time 625.04 seconds
Started Jul 31 07:12:30 PM PDT 24
Finished Jul 31 07:22:56 PM PDT 24
Peak memory 213308 kb
Host smart-d7c746ed-d014-48c9-9d39-0365f0eb991b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320986535 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1320986535
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3820755899
Short name T97
Test name
Test status
Simulation time 110390372 ps
CPU time 1.01 seconds
Started Jul 31 05:08:34 PM PDT 24
Finished Jul 31 05:08:35 PM PDT 24
Peak memory 199912 kb
Host smart-c421ac81-8de9-4f22-8e1d-abdea0b3ed68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820755899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3820755899
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3316061208
Short name T4
Test name
Test status
Simulation time 2165711516 ps
CPU time 116.1 seconds
Started Jul 31 07:12:59 PM PDT 24
Finished Jul 31 07:14:55 PM PDT 24
Peak memory 199976 kb
Host smart-60ca1b82-d4d4-48c3-806a-8ac84815ca06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316061208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3316061208
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.4266946988
Short name T24
Test name
Test status
Simulation time 71370939748 ps
CPU time 6135.85 seconds
Started Jul 31 07:08:12 PM PDT 24
Finished Jul 31 08:50:29 PM PDT 24
Peak memory 847864 kb
Host smart-213d5005-f26e-43d7-bb59-43baee90de3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266946988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.4266946988
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3442522400
Short name T54
Test name
Test status
Simulation time 80895137 ps
CPU time 0.98 seconds
Started Jul 31 07:06:40 PM PDT 24
Finished Jul 31 07:06:41 PM PDT 24
Peak memory 219664 kb
Host smart-f9ea15f9-bc56-49c2-a941-6930cc1c0227
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442522400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3442522400
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.348433074
Short name T130
Test name
Test status
Simulation time 249101589 ps
CPU time 4.03 seconds
Started Jul 31 05:08:57 PM PDT 24
Finished Jul 31 05:09:01 PM PDT 24
Peak memory 200144 kb
Host smart-cc14b091-2641-4d0e-aa14-b2d1092f589e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348433074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.348433074
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4054283596
Short name T44
Test name
Test status
Simulation time 1341150617 ps
CPU time 76.13 seconds
Started Jul 31 07:06:36 PM PDT 24
Finished Jul 31 07:07:52 PM PDT 24
Peak memory 199868 kb
Host smart-21c061b0-91e7-48c5-a5c2-99720cdbd36c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054283596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4054283596
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3175363353
Short name T112
Test name
Test status
Simulation time 79793588 ps
CPU time 1.1 seconds
Started Jul 31 05:08:42 PM PDT 24
Finished Jul 31 05:08:44 PM PDT 24
Peak memory 200068 kb
Host smart-34cf8378-8436-4a41-8889-8b5fcbd0d274
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175363353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3175363353
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.658471063
Short name T129
Test name
Test status
Simulation time 200701727 ps
CPU time 2.81 seconds
Started Jul 31 05:08:55 PM PDT 24
Finished Jul 31 05:08:58 PM PDT 24
Peak memory 200148 kb
Host smart-70cf5033-fae5-4975-bc38-eac22de59638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658471063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.658471063
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3553928398
Short name T75
Test name
Test status
Simulation time 1234162638432 ps
CPU time 1777.07 seconds
Started Jul 31 07:06:35 PM PDT 24
Finished Jul 31 07:36:12 PM PDT 24
Peak memory 692948 kb
Host smart-74eb0bba-8820-4be9-9e09-dbee2de9fe55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553928398 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3553928398
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.659704479
Short name T70
Test name
Test status
Simulation time 48261730 ps
CPU time 1.74 seconds
Started Jul 31 05:08:45 PM PDT 24
Finished Jul 31 05:08:47 PM PDT 24
Peak memory 200100 kb
Host smart-4eecce8e-0fca-4017-a1f9-fe77b0b52e18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659704479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.659704479
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.173613549
Short name T540
Test name
Test status
Simulation time 205016403 ps
CPU time 3.53 seconds
Started Jul 31 05:08:39 PM PDT 24
Finished Jul 31 05:08:42 PM PDT 24
Peak memory 200032 kb
Host smart-780b5fe1-db86-463c-8840-1b31c29e3e01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173613549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.173613549
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4103046684
Short name T105
Test name
Test status
Simulation time 426079032 ps
CPU time 10.22 seconds
Started Jul 31 05:08:38 PM PDT 24
Finished Jul 31 05:08:49 PM PDT 24
Peak memory 200104 kb
Host smart-83317fb9-a3d2-4ec9-a65a-db7f9fb353d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103046684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4103046684
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2993033182
Short name T559
Test name
Test status
Simulation time 20736384 ps
CPU time 1.08 seconds
Started Jul 31 05:08:41 PM PDT 24
Finished Jul 31 05:08:42 PM PDT 24
Peak memory 199948 kb
Host smart-4c44599e-fcbb-4150-a356-b59df4f95df0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993033182 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2993033182
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3512729319
Short name T534
Test name
Test status
Simulation time 28060015 ps
CPU time 0.72 seconds
Started Jul 31 05:08:40 PM PDT 24
Finished Jul 31 05:08:41 PM PDT 24
Peak memory 198136 kb
Host smart-c594c49c-fb2f-49cf-a8fa-360cc4447837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512729319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3512729319
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1899604131
Short name T574
Test name
Test status
Simulation time 16977152 ps
CPU time 0.59 seconds
Started Jul 31 05:08:36 PM PDT 24
Finished Jul 31 05:08:36 PM PDT 24
Peak memory 194988 kb
Host smart-936d72dc-104c-4a37-9f9d-441e7aeaaab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899604131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1899604131
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2270092381
Short name T554
Test name
Test status
Simulation time 222761696 ps
CPU time 1.52 seconds
Started Jul 31 05:08:35 PM PDT 24
Finished Jul 31 05:08:37 PM PDT 24
Peak memory 200124 kb
Host smart-9a781960-8d9a-481c-8cfd-dc8830ae6c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270092381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2270092381
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2941055543
Short name T128
Test name
Test status
Simulation time 331533064 ps
CPU time 4.64 seconds
Started Jul 31 05:08:34 PM PDT 24
Finished Jul 31 05:08:38 PM PDT 24
Peak memory 200072 kb
Host smart-7c5d1120-2068-408c-b098-b1cb7890f4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941055543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2941055543
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1862916030
Short name T98
Test name
Test status
Simulation time 998484434 ps
CPU time 5.55 seconds
Started Jul 31 05:08:41 PM PDT 24
Finished Jul 31 05:08:47 PM PDT 24
Peak memory 200036 kb
Host smart-0f874e55-6fcd-4e12-914c-9655f4a44f06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862916030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1862916030
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3831009138
Short name T104
Test name
Test status
Simulation time 1053159802 ps
CPU time 11.9 seconds
Started Jul 31 05:08:42 PM PDT 24
Finished Jul 31 05:08:54 PM PDT 24
Peak memory 200056 kb
Host smart-23ce1e57-7a23-474b-a876-cea5f9b4df24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831009138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3831009138
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3295001971
Short name T108
Test name
Test status
Simulation time 21702434 ps
CPU time 0.97 seconds
Started Jul 31 05:08:40 PM PDT 24
Finished Jul 31 05:08:41 PM PDT 24
Peak memory 199648 kb
Host smart-f92abf3c-0e86-45ca-a893-1fb54c66c694
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295001971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3295001971
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3977753447
Short name T602
Test name
Test status
Simulation time 148947443 ps
CPU time 2.54 seconds
Started Jul 31 05:08:39 PM PDT 24
Finished Jul 31 05:08:41 PM PDT 24
Peak memory 200112 kb
Host smart-d1c7229b-139a-47ff-a986-f9c215602929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977753447 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3977753447
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3391344276
Short name T100
Test name
Test status
Simulation time 17396289 ps
CPU time 0.79 seconds
Started Jul 31 05:08:46 PM PDT 24
Finished Jul 31 05:08:47 PM PDT 24
Peak memory 199948 kb
Host smart-84c6188f-c22b-4760-96a7-d1c5efe8d92c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391344276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3391344276
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2392045335
Short name T538
Test name
Test status
Simulation time 27074059 ps
CPU time 0.57 seconds
Started Jul 31 05:08:42 PM PDT 24
Finished Jul 31 05:08:42 PM PDT 24
Peak memory 195080 kb
Host smart-0c4966bd-24fd-4b2a-8cf9-6e235f48d54a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392045335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2392045335
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3204024409
Short name T641
Test name
Test status
Simulation time 98927146 ps
CPU time 1.78 seconds
Started Jul 31 05:08:43 PM PDT 24
Finished Jul 31 05:08:44 PM PDT 24
Peak memory 200092 kb
Host smart-43b28b03-95e2-4cb8-bbcd-06793b8921d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204024409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3204024409
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1871204455
Short name T550
Test name
Test status
Simulation time 77572469 ps
CPU time 1.54 seconds
Started Jul 31 05:08:46 PM PDT 24
Finished Jul 31 05:08:48 PM PDT 24
Peak memory 200104 kb
Host smart-8e69dc82-7f7c-4f6e-80eb-1153f4a68d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871204455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1871204455
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3619620196
Short name T136
Test name
Test status
Simulation time 491386581 ps
CPU time 3.15 seconds
Started Jul 31 05:08:39 PM PDT 24
Finished Jul 31 05:08:42 PM PDT 24
Peak memory 200064 kb
Host smart-b6d46448-c859-429c-9725-a301f6a7bc33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619620196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3619620196
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2751259634
Short name T573
Test name
Test status
Simulation time 120952550 ps
CPU time 1.14 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:08:57 PM PDT 24
Peak memory 199944 kb
Host smart-c02c4e40-f6ab-4a30-9c3a-288e1c6d7736
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751259634 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2751259634
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3494336308
Short name T106
Test name
Test status
Simulation time 93081719 ps
CPU time 0.82 seconds
Started Jul 31 05:08:55 PM PDT 24
Finished Jul 31 05:08:56 PM PDT 24
Peak memory 199832 kb
Host smart-1aa52612-3070-4e5c-94db-ca2fe9eaf655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494336308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3494336308
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.47187751
Short name T657
Test name
Test status
Simulation time 60152210 ps
CPU time 0.59 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:08:57 PM PDT 24
Peak memory 195020 kb
Host smart-7eecc7b5-f378-4e72-91b0-0a1291a9435e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47187751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.47187751
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1164184921
Short name T111
Test name
Test status
Simulation time 45530995 ps
CPU time 2.16 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:08:58 PM PDT 24
Peak memory 200052 kb
Host smart-ddb8787f-8fb5-463f-8e97-44c584280dec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164184921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1164184921
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3748537229
Short name T630
Test name
Test status
Simulation time 83558040 ps
CPU time 1.89 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:08:58 PM PDT 24
Peak memory 200100 kb
Host smart-eed3ca60-4ca5-4dee-a5e8-d48c1607d69a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748537229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3748537229
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1065943394
Short name T627
Test name
Test status
Simulation time 154936737 ps
CPU time 1.2 seconds
Started Jul 31 05:08:58 PM PDT 24
Finished Jul 31 05:08:59 PM PDT 24
Peak memory 199136 kb
Host smart-456575bd-070b-484f-b3a6-994ee4859145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065943394 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1065943394
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1052369212
Short name T632
Test name
Test status
Simulation time 15290071 ps
CPU time 0.78 seconds
Started Jul 31 05:08:54 PM PDT 24
Finished Jul 31 05:08:55 PM PDT 24
Peak memory 199972 kb
Host smart-c0a8376d-1690-4827-ab14-e4bb2c86d42e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052369212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1052369212
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.859970807
Short name T607
Test name
Test status
Simulation time 30150766 ps
CPU time 0.62 seconds
Started Jul 31 05:08:57 PM PDT 24
Finished Jul 31 05:08:58 PM PDT 24
Peak memory 195040 kb
Host smart-337ba366-2e2c-4185-9551-8664571e3a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859970807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.859970807
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.823081184
Short name T120
Test name
Test status
Simulation time 77250895 ps
CPU time 1.71 seconds
Started Jul 31 05:08:57 PM PDT 24
Finished Jul 31 05:08:59 PM PDT 24
Peak memory 200104 kb
Host smart-734ec59a-9d8c-4e0f-aaa8-12a4e38ac515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823081184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.823081184
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1712632733
Short name T568
Test name
Test status
Simulation time 115127384 ps
CPU time 3.12 seconds
Started Jul 31 05:08:55 PM PDT 24
Finished Jul 31 05:08:58 PM PDT 24
Peak memory 200084 kb
Host smart-fc9897a8-62b1-4fe1-bce1-4b79a027a7c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712632733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1712632733
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2915243653
Short name T613
Test name
Test status
Simulation time 168689568001 ps
CPU time 870.88 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:23:27 PM PDT 24
Peak memory 216640 kb
Host smart-446bc40a-6db3-4dc0-9752-87092deec6fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915243653 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2915243653
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.243980655
Short name T577
Test name
Test status
Simulation time 14976579 ps
CPU time 0.8 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:08:57 PM PDT 24
Peak memory 199860 kb
Host smart-89ab68fb-8f83-462e-ad8d-920a7d7289a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243980655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.243980655
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3530692308
Short name T543
Test name
Test status
Simulation time 30081187 ps
CPU time 0.61 seconds
Started Jul 31 05:08:55 PM PDT 24
Finished Jul 31 05:08:55 PM PDT 24
Peak memory 195004 kb
Host smart-34ddd20a-8a4a-442d-aa91-c1f910f42f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530692308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3530692308
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1051256662
Short name T113
Test name
Test status
Simulation time 310910743 ps
CPU time 2.39 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:08:58 PM PDT 24
Peak memory 199888 kb
Host smart-360a301a-ebeb-4073-9ee7-8f2e53308ca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051256662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1051256662
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2097470918
Short name T571
Test name
Test status
Simulation time 87142785 ps
CPU time 1.64 seconds
Started Jul 31 05:08:57 PM PDT 24
Finished Jul 31 05:08:59 PM PDT 24
Peak memory 200088 kb
Host smart-6a7c8e48-576f-4939-a15b-c24892b7d938
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097470918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2097470918
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2104782835
Short name T132
Test name
Test status
Simulation time 952426180 ps
CPU time 4.58 seconds
Started Jul 31 05:08:58 PM PDT 24
Finished Jul 31 05:09:03 PM PDT 24
Peak memory 199560 kb
Host smart-b01fa585-f25d-4ebf-bc34-b27f6ba2c7dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104782835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2104782835
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2144212375
Short name T537
Test name
Test status
Simulation time 29040388 ps
CPU time 1.59 seconds
Started Jul 31 05:09:01 PM PDT 24
Finished Jul 31 05:09:03 PM PDT 24
Peak memory 200080 kb
Host smart-dffec2aa-43a4-40b9-a900-a866f9b45fc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144212375 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2144212375
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3242912222
Short name T102
Test name
Test status
Simulation time 48608933 ps
CPU time 0.8 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:08:57 PM PDT 24
Peak memory 199824 kb
Host smart-672ab261-62eb-49fb-93b6-d4d75fe68a41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242912222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3242912222
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1797941986
Short name T643
Test name
Test status
Simulation time 48205036 ps
CPU time 0.63 seconds
Started Jul 31 05:08:57 PM PDT 24
Finished Jul 31 05:08:58 PM PDT 24
Peak memory 195108 kb
Host smart-c904267d-6b8e-4ae8-af9c-bb343cbc6370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797941986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1797941986
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3456198685
Short name T590
Test name
Test status
Simulation time 45872449 ps
CPU time 1.2 seconds
Started Jul 31 05:08:57 PM PDT 24
Finished Jul 31 05:08:58 PM PDT 24
Peak memory 200108 kb
Host smart-30fc6ddd-2996-450e-a3ef-862f88fe89e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456198685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3456198685
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1534758154
Short name T595
Test name
Test status
Simulation time 134788477 ps
CPU time 2.76 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:08:59 PM PDT 24
Peak memory 200072 kb
Host smart-5c5dc98f-e349-42ad-93af-eb4a63235d7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534758154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1534758154
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1802087404
Short name T588
Test name
Test status
Simulation time 243449417 ps
CPU time 1.85 seconds
Started Jul 31 05:09:07 PM PDT 24
Finished Jul 31 05:09:08 PM PDT 24
Peak memory 200104 kb
Host smart-e346f68f-1525-4798-a6d2-7d0cde0e3635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802087404 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1802087404
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2224469306
Short name T565
Test name
Test status
Simulation time 23894848 ps
CPU time 0.84 seconds
Started Jul 31 05:09:00 PM PDT 24
Finished Jul 31 05:09:01 PM PDT 24
Peak memory 199748 kb
Host smart-27e7f06c-2e04-4f27-a72b-3c250da91e64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224469306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2224469306
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.614962055
Short name T585
Test name
Test status
Simulation time 11381440 ps
CPU time 0.64 seconds
Started Jul 31 05:09:04 PM PDT 24
Finished Jul 31 05:09:04 PM PDT 24
Peak memory 195072 kb
Host smart-fbd07531-f99a-4604-b38a-336097bbe18f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614962055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.614962055
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1012983289
Short name T576
Test name
Test status
Simulation time 35258772 ps
CPU time 1.69 seconds
Started Jul 31 05:09:01 PM PDT 24
Finished Jul 31 05:09:03 PM PDT 24
Peak memory 200064 kb
Host smart-280ea55e-5ae0-4005-a83a-66adb82943fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012983289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1012983289
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3897421891
Short name T639
Test name
Test status
Simulation time 89475820 ps
CPU time 1.97 seconds
Started Jul 31 05:09:04 PM PDT 24
Finished Jul 31 05:09:06 PM PDT 24
Peak memory 200084 kb
Host smart-e1d36851-b02b-4039-9ef7-b644aa61db38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897421891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3897421891
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.855769723
Short name T628
Test name
Test status
Simulation time 254605972 ps
CPU time 1.84 seconds
Started Jul 31 05:09:01 PM PDT 24
Finished Jul 31 05:09:03 PM PDT 24
Peak memory 200196 kb
Host smart-816df04b-287d-4035-8c8c-35ed07bac55a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855769723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.855769723
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1641166516
Short name T544
Test name
Test status
Simulation time 73931677 ps
CPU time 1.74 seconds
Started Jul 31 05:09:04 PM PDT 24
Finished Jul 31 05:09:05 PM PDT 24
Peak memory 200152 kb
Host smart-9301f245-24fe-4673-84bb-abf32a021e5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641166516 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1641166516
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.515209716
Short name T119
Test name
Test status
Simulation time 14448335 ps
CPU time 0.74 seconds
Started Jul 31 05:09:02 PM PDT 24
Finished Jul 31 05:09:03 PM PDT 24
Peak memory 198096 kb
Host smart-ab6a68fd-47f9-4e60-bd31-2f2434db39c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515209716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.515209716
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2182661596
Short name T645
Test name
Test status
Simulation time 13859352 ps
CPU time 0.58 seconds
Started Jul 31 05:09:00 PM PDT 24
Finished Jul 31 05:09:00 PM PDT 24
Peak memory 195156 kb
Host smart-074a7a1b-9d4d-4c59-bb9c-d59e388369df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182661596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2182661596
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1699333114
Short name T614
Test name
Test status
Simulation time 128164443 ps
CPU time 2.22 seconds
Started Jul 31 05:09:01 PM PDT 24
Finished Jul 31 05:09:03 PM PDT 24
Peak memory 200060 kb
Host smart-e28f49cb-db6a-4363-9bf1-339ab923f998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699333114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1699333114
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3537162446
Short name T536
Test name
Test status
Simulation time 112041307 ps
CPU time 1.58 seconds
Started Jul 31 05:09:02 PM PDT 24
Finished Jul 31 05:09:04 PM PDT 24
Peak memory 200120 kb
Host smart-90cf482c-ac24-46c5-96ec-beb0c477f287
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537162446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3537162446
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1691370211
Short name T133
Test name
Test status
Simulation time 871186011 ps
CPU time 4.49 seconds
Started Jul 31 05:09:04 PM PDT 24
Finished Jul 31 05:09:08 PM PDT 24
Peak memory 200040 kb
Host smart-fe02394d-832e-4f8c-a8b0-bb49fbc75c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691370211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1691370211
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4108644157
Short name T593
Test name
Test status
Simulation time 75039955 ps
CPU time 1.14 seconds
Started Jul 31 05:09:03 PM PDT 24
Finished Jul 31 05:09:04 PM PDT 24
Peak memory 200128 kb
Host smart-b9e07c23-f294-472c-a128-3ede446b9301
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108644157 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4108644157
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.303760467
Short name T622
Test name
Test status
Simulation time 34299606 ps
CPU time 0.82 seconds
Started Jul 31 05:09:01 PM PDT 24
Finished Jul 31 05:09:02 PM PDT 24
Peak memory 199932 kb
Host smart-13adcbe1-56f4-488f-beb9-ecb2e5e87431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303760467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.303760467
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.192129207
Short name T654
Test name
Test status
Simulation time 34767328 ps
CPU time 0.63 seconds
Started Jul 31 05:09:04 PM PDT 24
Finished Jul 31 05:09:04 PM PDT 24
Peak memory 195108 kb
Host smart-9275193e-02ee-4de8-bcc5-e8cbfe586d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192129207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.192129207
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1461825792
Short name T569
Test name
Test status
Simulation time 80841203 ps
CPU time 1.65 seconds
Started Jul 31 05:09:04 PM PDT 24
Finished Jul 31 05:09:06 PM PDT 24
Peak memory 200124 kb
Host smart-1501f0c8-fe44-489b-8bbc-2e1da0d127f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461825792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1461825792
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3976882695
Short name T618
Test name
Test status
Simulation time 99374575 ps
CPU time 1.45 seconds
Started Jul 31 05:09:02 PM PDT 24
Finished Jul 31 05:09:04 PM PDT 24
Peak memory 200112 kb
Host smart-9e0ae5c7-cccb-477f-a3bd-53f0f5b9065a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976882695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3976882695
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.702534918
Short name T637
Test name
Test status
Simulation time 92797581 ps
CPU time 1.84 seconds
Started Jul 31 05:09:04 PM PDT 24
Finished Jul 31 05:09:06 PM PDT 24
Peak memory 200172 kb
Host smart-9b776702-6891-46cf-8636-52ca772275e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702534918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.702534918
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3235853194
Short name T583
Test name
Test status
Simulation time 32852065 ps
CPU time 1.06 seconds
Started Jul 31 05:09:07 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 199904 kb
Host smart-63839147-9d54-49ba-a59e-8aa58c17f718
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235853194 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3235853194
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1198171539
Short name T109
Test name
Test status
Simulation time 19513870 ps
CPU time 0.74 seconds
Started Jul 31 05:09:03 PM PDT 24
Finished Jul 31 05:09:03 PM PDT 24
Peak memory 198520 kb
Host smart-1719bf95-3033-4823-be35-5531eee7af7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198171539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1198171539
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.782100508
Short name T562
Test name
Test status
Simulation time 36425869 ps
CPU time 0.6 seconds
Started Jul 31 05:09:03 PM PDT 24
Finished Jul 31 05:09:04 PM PDT 24
Peak memory 195052 kb
Host smart-710b3a57-819c-4ea6-bba4-156b567f2afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782100508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.782100508
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3821934976
Short name T619
Test name
Test status
Simulation time 58749335 ps
CPU time 1.19 seconds
Started Jul 31 05:09:05 PM PDT 24
Finished Jul 31 05:09:06 PM PDT 24
Peak memory 200072 kb
Host smart-a5ceb8d3-d34e-4a5d-97d2-bd4fe70451b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821934976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3821934976
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.418850347
Short name T644
Test name
Test status
Simulation time 247093713 ps
CPU time 1.46 seconds
Started Jul 31 05:09:00 PM PDT 24
Finished Jul 31 05:09:02 PM PDT 24
Peak memory 200060 kb
Host smart-cd76399a-2ad7-4376-b7ae-ef7b6b9cd363
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418850347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.418850347
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3052662280
Short name T131
Test name
Test status
Simulation time 169585199 ps
CPU time 3.06 seconds
Started Jul 31 05:09:01 PM PDT 24
Finished Jul 31 05:09:04 PM PDT 24
Peak memory 200152 kb
Host smart-5ed23564-5c82-4911-8965-0db180c1dc8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052662280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3052662280
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2119872795
Short name T605
Test name
Test status
Simulation time 130398295 ps
CPU time 1.9 seconds
Started Jul 31 05:09:09 PM PDT 24
Finished Jul 31 05:09:11 PM PDT 24
Peak memory 200168 kb
Host smart-018b04d2-4b3d-4c68-81a9-de26fd06182a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119872795 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2119872795
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3332222802
Short name T101
Test name
Test status
Simulation time 58993785 ps
CPU time 0.97 seconds
Started Jul 31 05:09:06 PM PDT 24
Finished Jul 31 05:09:07 PM PDT 24
Peak memory 199800 kb
Host smart-e66fec85-5829-464f-a387-3c68b664d805
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332222802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3332222802
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1230303872
Short name T603
Test name
Test status
Simulation time 13487878 ps
CPU time 0.59 seconds
Started Jul 31 05:09:08 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 194960 kb
Host smart-39f3aa17-6309-418c-9d52-61a12dc7c31e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230303872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1230303872
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3025734737
Short name T653
Test name
Test status
Simulation time 24545484 ps
CPU time 1.1 seconds
Started Jul 31 05:09:08 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 198652 kb
Host smart-ae7bfbc7-9034-4b22-a88c-3f3873777143
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025734737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3025734737
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3039400989
Short name T659
Test name
Test status
Simulation time 257883803 ps
CPU time 3.69 seconds
Started Jul 31 05:09:09 PM PDT 24
Finished Jul 31 05:09:12 PM PDT 24
Peak memory 200160 kb
Host smart-eee07166-3d4d-440a-8991-07b9b11cd7fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039400989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3039400989
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2656057820
Short name T591
Test name
Test status
Simulation time 83202005 ps
CPU time 1.95 seconds
Started Jul 31 05:09:09 PM PDT 24
Finished Jul 31 05:09:11 PM PDT 24
Peak memory 200148 kb
Host smart-7553c0f5-feec-4007-bc65-0afb5ea10f86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656057820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2656057820
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3227571348
Short name T555
Test name
Test status
Simulation time 365660017 ps
CPU time 1.16 seconds
Started Jul 31 05:09:09 PM PDT 24
Finished Jul 31 05:09:10 PM PDT 24
Peak memory 199892 kb
Host smart-79a6c085-c986-4b2c-8ca7-8c4132ac3704
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227571348 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3227571348
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1209246812
Short name T599
Test name
Test status
Simulation time 108676622 ps
CPU time 0.92 seconds
Started Jul 31 05:09:09 PM PDT 24
Finished Jul 31 05:09:10 PM PDT 24
Peak memory 199840 kb
Host smart-cb1f18ee-3099-4547-80c0-6335658186ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209246812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1209246812
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.476009798
Short name T578
Test name
Test status
Simulation time 14549125 ps
CPU time 0.6 seconds
Started Jul 31 05:09:08 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 195000 kb
Host smart-3f8b224b-3ceb-4d9b-a2a1-9215820194bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476009798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.476009798
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4144976797
Short name T650
Test name
Test status
Simulation time 134440251 ps
CPU time 1.63 seconds
Started Jul 31 05:09:08 PM PDT 24
Finished Jul 31 05:09:10 PM PDT 24
Peak memory 200120 kb
Host smart-d1c764f7-7062-4ae1-8e12-be97d782d668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144976797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4144976797
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3965807935
Short name T545
Test name
Test status
Simulation time 98068493 ps
CPU time 1.35 seconds
Started Jul 31 05:09:08 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 200112 kb
Host smart-8730aa4e-ada9-4fbd-b506-b79f1140293a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965807935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3965807935
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2322123357
Short name T586
Test name
Test status
Simulation time 185490603 ps
CPU time 1.76 seconds
Started Jul 31 05:09:09 PM PDT 24
Finished Jul 31 05:09:11 PM PDT 24
Peak memory 200096 kb
Host smart-5e9733cc-41c7-438e-bbd4-dab2a2f24e08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322123357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2322123357
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4255023037
Short name T539
Test name
Test status
Simulation time 451376071 ps
CPU time 5.62 seconds
Started Jul 31 05:08:39 PM PDT 24
Finished Jul 31 05:08:44 PM PDT 24
Peak memory 200048 kb
Host smart-f27a5ff1-7070-48dc-bf04-2edd321c3c83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255023037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4255023037
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3326436711
Short name T621
Test name
Test status
Simulation time 1052191804 ps
CPU time 15.98 seconds
Started Jul 31 05:08:43 PM PDT 24
Finished Jul 31 05:08:59 PM PDT 24
Peak memory 200088 kb
Host smart-6eb84e49-c23a-4d0e-b609-cd555b413acf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326436711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3326436711
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3395267282
Short name T582
Test name
Test status
Simulation time 28938045 ps
CPU time 0.92 seconds
Started Jul 31 05:08:39 PM PDT 24
Finished Jul 31 05:08:40 PM PDT 24
Peak memory 199608 kb
Host smart-ca96e7c7-f1e9-40a8-a961-2bb094229d27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395267282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3395267282
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1563490562
Short name T541
Test name
Test status
Simulation time 139653403 ps
CPU time 1.75 seconds
Started Jul 31 05:08:43 PM PDT 24
Finished Jul 31 05:08:45 PM PDT 24
Peak memory 200168 kb
Host smart-74d238da-17e5-46dc-bbd2-d9a812d71dc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563490562 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1563490562
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3100441505
Short name T118
Test name
Test status
Simulation time 68678511 ps
CPU time 0.67 seconds
Started Jul 31 05:08:43 PM PDT 24
Finished Jul 31 05:08:44 PM PDT 24
Peak memory 197604 kb
Host smart-fda83160-0beb-4c7d-b289-4c4818dceb2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100441505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3100441505
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2565237273
Short name T551
Test name
Test status
Simulation time 13000247 ps
CPU time 0.57 seconds
Started Jul 31 05:08:38 PM PDT 24
Finished Jul 31 05:08:39 PM PDT 24
Peak memory 195136 kb
Host smart-a5eb7a8d-5179-451d-97c5-74c08970c49b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565237273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2565237273
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2715783984
Short name T633
Test name
Test status
Simulation time 94776730 ps
CPU time 1.01 seconds
Started Jul 31 05:08:47 PM PDT 24
Finished Jul 31 05:08:48 PM PDT 24
Peak memory 200084 kb
Host smart-c559d271-f016-4256-855a-f72f3eedecf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715783984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2715783984
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1989750788
Short name T620
Test name
Test status
Simulation time 144159617 ps
CPU time 1.96 seconds
Started Jul 31 05:08:42 PM PDT 24
Finished Jul 31 05:08:44 PM PDT 24
Peak memory 200160 kb
Host smart-76311668-17db-4e1b-bc78-664a274cedbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989750788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1989750788
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.124066673
Short name T134
Test name
Test status
Simulation time 167767754 ps
CPU time 1.92 seconds
Started Jul 31 05:08:39 PM PDT 24
Finished Jul 31 05:08:41 PM PDT 24
Peak memory 200124 kb
Host smart-02fbb1c2-7eda-438f-b410-14bbacbb279c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124066673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.124066673
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2146144344
Short name T642
Test name
Test status
Simulation time 41626065 ps
CPU time 0.61 seconds
Started Jul 31 05:09:09 PM PDT 24
Finished Jul 31 05:09:10 PM PDT 24
Peak memory 194956 kb
Host smart-2fd0a0c2-6235-41ec-857f-c625487716a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146144344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2146144344
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.509801239
Short name T635
Test name
Test status
Simulation time 44663860 ps
CPU time 0.6 seconds
Started Jul 31 05:09:08 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 195028 kb
Host smart-7eb92865-68e9-4705-a6e8-9760c410ace9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509801239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.509801239
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.946074547
Short name T625
Test name
Test status
Simulation time 12611541 ps
CPU time 0.61 seconds
Started Jul 31 05:09:08 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 195156 kb
Host smart-26e55d73-fb59-4fd0-9c21-31d3f908a9ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946074547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.946074547
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1572849572
Short name T646
Test name
Test status
Simulation time 124226724 ps
CPU time 0.63 seconds
Started Jul 31 05:09:09 PM PDT 24
Finished Jul 31 05:09:10 PM PDT 24
Peak memory 195216 kb
Host smart-749b61d7-63e8-4196-8672-5de8969ba1c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572849572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1572849572
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3020111468
Short name T561
Test name
Test status
Simulation time 37221421 ps
CPU time 0.59 seconds
Started Jul 31 05:09:06 PM PDT 24
Finished Jul 31 05:09:06 PM PDT 24
Peak memory 195004 kb
Host smart-846749e8-d1d8-41c2-afa4-8393c4f41f8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020111468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3020111468
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3654090154
Short name T611
Test name
Test status
Simulation time 31771974 ps
CPU time 0.58 seconds
Started Jul 31 05:09:07 PM PDT 24
Finished Jul 31 05:09:08 PM PDT 24
Peak memory 194928 kb
Host smart-b7729d5a-e7e1-4061-b864-4fca271370ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654090154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3654090154
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1552395936
Short name T608
Test name
Test status
Simulation time 38554681 ps
CPU time 0.57 seconds
Started Jul 31 05:09:07 PM PDT 24
Finished Jul 31 05:09:08 PM PDT 24
Peak memory 194928 kb
Host smart-d9f4a951-c61a-407d-a713-f60400f4dabe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552395936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1552395936
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.833790170
Short name T652
Test name
Test status
Simulation time 17257636 ps
CPU time 0.6 seconds
Started Jul 31 05:09:08 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 194988 kb
Host smart-fa4f84df-3412-4b0b-a38f-8c21b6eb4dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833790170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.833790170
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2488971132
Short name T596
Test name
Test status
Simulation time 14499230 ps
CPU time 0.61 seconds
Started Jul 31 05:09:07 PM PDT 24
Finished Jul 31 05:09:08 PM PDT 24
Peak memory 195136 kb
Host smart-f46bc2bc-5f0c-43e0-9193-2a4618602bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488971132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2488971132
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.636371106
Short name T553
Test name
Test status
Simulation time 22299592 ps
CPU time 0.67 seconds
Started Jul 31 05:09:07 PM PDT 24
Finished Jul 31 05:09:08 PM PDT 24
Peak memory 195060 kb
Host smart-d8fa89ab-7953-4117-a806-89c9fde2fd05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636371106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.636371106
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1316977444
Short name T99
Test name
Test status
Simulation time 1855404615 ps
CPU time 8.83 seconds
Started Jul 31 05:08:47 PM PDT 24
Finished Jul 31 05:08:56 PM PDT 24
Peak memory 200016 kb
Host smart-d42b6467-27af-4fe1-b1d0-bc001ba61c81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316977444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1316977444
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1268364551
Short name T581
Test name
Test status
Simulation time 2817489468 ps
CPU time 10.37 seconds
Started Jul 31 05:08:44 PM PDT 24
Finished Jul 31 05:08:54 PM PDT 24
Peak memory 200192 kb
Host smart-2aa737e2-9c02-47e1-9ad9-7c972b549113
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268364551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1268364551
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.384530002
Short name T96
Test name
Test status
Simulation time 19473094 ps
CPU time 0.74 seconds
Started Jul 31 05:08:44 PM PDT 24
Finished Jul 31 05:08:45 PM PDT 24
Peak memory 198036 kb
Host smart-3f4904d4-ec43-4b85-8e09-86f42236533a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384530002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.384530002
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1190504223
Short name T629
Test name
Test status
Simulation time 69402451 ps
CPU time 1.74 seconds
Started Jul 31 05:08:45 PM PDT 24
Finished Jul 31 05:08:46 PM PDT 24
Peak memory 200200 kb
Host smart-79822c76-8954-429e-ba3e-ddbe5f078d54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190504223 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1190504223
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2190782200
Short name T110
Test name
Test status
Simulation time 68583833 ps
CPU time 0.7 seconds
Started Jul 31 05:08:44 PM PDT 24
Finished Jul 31 05:08:45 PM PDT 24
Peak memory 198168 kb
Host smart-2e9adbeb-ec37-49f3-ae5d-69a14b922e9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190782200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2190782200
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.4225479357
Short name T549
Test name
Test status
Simulation time 31977414 ps
CPU time 0.65 seconds
Started Jul 31 05:08:44 PM PDT 24
Finished Jul 31 05:08:44 PM PDT 24
Peak memory 195212 kb
Host smart-ec089d64-c217-4633-bc02-c4a3b2efd1fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225479357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4225479357
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.201148882
Short name T116
Test name
Test status
Simulation time 110616041 ps
CPU time 2.38 seconds
Started Jul 31 05:08:45 PM PDT 24
Finished Jul 31 05:08:48 PM PDT 24
Peak memory 200068 kb
Host smart-11bd8012-ade6-4bc9-8704-531069b93f2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201148882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.201148882
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3195492549
Short name T624
Test name
Test status
Simulation time 182870588 ps
CPU time 3.85 seconds
Started Jul 31 05:08:43 PM PDT 24
Finished Jul 31 05:08:47 PM PDT 24
Peak memory 200056 kb
Host smart-b3b98278-69a5-41c1-89ce-f54ba5cb745a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195492549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3195492549
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3693849283
Short name T67
Test name
Test status
Simulation time 424869142 ps
CPU time 1.82 seconds
Started Jul 31 05:08:45 PM PDT 24
Finished Jul 31 05:08:46 PM PDT 24
Peak memory 200096 kb
Host smart-a9a9b1d8-e932-40a0-8bf7-e142f718aebc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693849283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3693849283
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4185766524
Short name T592
Test name
Test status
Simulation time 40414038 ps
CPU time 0.61 seconds
Started Jul 31 05:09:06 PM PDT 24
Finished Jul 31 05:09:07 PM PDT 24
Peak memory 195100 kb
Host smart-25f30369-99ee-4fb3-88df-2a8f6222a694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185766524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4185766524
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2065466192
Short name T580
Test name
Test status
Simulation time 41198410 ps
CPU time 0.62 seconds
Started Jul 31 05:09:09 PM PDT 24
Finished Jul 31 05:09:10 PM PDT 24
Peak memory 194952 kb
Host smart-128c2fd1-0a54-4265-b2ab-aa154b2782c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065466192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2065466192
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1252296064
Short name T584
Test name
Test status
Simulation time 31414200 ps
CPU time 0.64 seconds
Started Jul 31 05:09:09 PM PDT 24
Finished Jul 31 05:09:10 PM PDT 24
Peak memory 195164 kb
Host smart-b843a393-940c-46e9-b5aa-2c5450528186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252296064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1252296064
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2019704876
Short name T557
Test name
Test status
Simulation time 16745105 ps
CPU time 0.61 seconds
Started Jul 31 05:09:10 PM PDT 24
Finished Jul 31 05:09:10 PM PDT 24
Peak memory 195024 kb
Host smart-4e086b52-bc19-49e6-8837-a4ab0d347c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019704876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2019704876
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3932552354
Short name T655
Test name
Test status
Simulation time 24160263 ps
CPU time 0.6 seconds
Started Jul 31 05:09:08 PM PDT 24
Finished Jul 31 05:09:09 PM PDT 24
Peak memory 194976 kb
Host smart-4954b3f2-f234-4368-afdb-cc2fb1f759c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932552354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3932552354
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1525211197
Short name T552
Test name
Test status
Simulation time 14337108 ps
CPU time 0.62 seconds
Started Jul 31 05:09:08 PM PDT 24
Finished Jul 31 05:09:08 PM PDT 24
Peak memory 195064 kb
Host smart-8c2e5266-8197-4fce-b4ac-f7194380b3a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525211197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1525211197
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.352502825
Short name T609
Test name
Test status
Simulation time 119675469 ps
CPU time 0.61 seconds
Started Jul 31 05:09:12 PM PDT 24
Finished Jul 31 05:09:13 PM PDT 24
Peak memory 195076 kb
Host smart-2b9ec046-ac65-41a4-a52b-eed880d350f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352502825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.352502825
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2792718818
Short name T548
Test name
Test status
Simulation time 23964301 ps
CPU time 0.57 seconds
Started Jul 31 05:09:10 PM PDT 24
Finished Jul 31 05:09:11 PM PDT 24
Peak memory 195056 kb
Host smart-3be6ae62-1e9d-4916-b5ef-147012aa8b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792718818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2792718818
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3586870084
Short name T616
Test name
Test status
Simulation time 26844090 ps
CPU time 0.6 seconds
Started Jul 31 05:09:10 PM PDT 24
Finished Jul 31 05:09:11 PM PDT 24
Peak memory 194904 kb
Host smart-3f4a32d6-2047-4938-903e-7a1de3ed5c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586870084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3586870084
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1468204998
Short name T564
Test name
Test status
Simulation time 39205050 ps
CPU time 0.6 seconds
Started Jul 31 05:09:14 PM PDT 24
Finished Jul 31 05:09:14 PM PDT 24
Peak memory 195060 kb
Host smart-fef42bec-e62d-4b7f-89eb-9e14dd52bde7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468204998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1468204998
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.6091654
Short name T107
Test name
Test status
Simulation time 218649621 ps
CPU time 3.11 seconds
Started Jul 31 05:08:45 PM PDT 24
Finished Jul 31 05:08:48 PM PDT 24
Peak memory 200124 kb
Host smart-1dca66be-3412-4480-a2fe-0e752a7875e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6091654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.6091654
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.565904924
Short name T594
Test name
Test status
Simulation time 111691020 ps
CPU time 5.16 seconds
Started Jul 31 05:08:43 PM PDT 24
Finished Jul 31 05:08:49 PM PDT 24
Peak memory 200076 kb
Host smart-7c95d4ad-b08a-4e7e-994c-2a8da7c567fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565904924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.565904924
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1366996091
Short name T626
Test name
Test status
Simulation time 26673311 ps
CPU time 0.74 seconds
Started Jul 31 05:08:45 PM PDT 24
Finished Jul 31 05:08:46 PM PDT 24
Peak memory 198052 kb
Host smart-b22d258f-d5c6-462d-a0ea-eaca5010a484
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366996091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1366996091
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4091956331
Short name T589
Test name
Test status
Simulation time 74840218 ps
CPU time 1.91 seconds
Started Jul 31 05:08:45 PM PDT 24
Finished Jul 31 05:08:47 PM PDT 24
Peak memory 200152 kb
Host smart-67670fab-6ce7-4dbe-9877-537a3f9c874b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091956331 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4091956331
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.936691559
Short name T638
Test name
Test status
Simulation time 58284510 ps
CPU time 0.8 seconds
Started Jul 31 05:08:47 PM PDT 24
Finished Jul 31 05:08:48 PM PDT 24
Peak memory 199936 kb
Host smart-1fac5e32-a7e9-4e6b-bd47-a52ad99104e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936691559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.936691559
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1227747754
Short name T572
Test name
Test status
Simulation time 21114370 ps
CPU time 0.58 seconds
Started Jul 31 05:08:45 PM PDT 24
Finished Jul 31 05:08:45 PM PDT 24
Peak memory 194996 kb
Host smart-85bd2909-a022-4989-b06e-11c4f90f02e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227747754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1227747754
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2517498709
Short name T117
Test name
Test status
Simulation time 52849522 ps
CPU time 1.13 seconds
Started Jul 31 05:08:43 PM PDT 24
Finished Jul 31 05:08:44 PM PDT 24
Peak memory 198524 kb
Host smart-f9549c0d-34ce-4d61-a964-6f3d11283f6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517498709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2517498709
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1032649449
Short name T660
Test name
Test status
Simulation time 1433960447 ps
CPU time 4.66 seconds
Started Jul 31 05:08:44 PM PDT 24
Finished Jul 31 05:08:49 PM PDT 24
Peak memory 200148 kb
Host smart-e812e3f4-7900-4067-95ca-299d0e33e1d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032649449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1032649449
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2574050840
Short name T547
Test name
Test status
Simulation time 12881884 ps
CPU time 0.65 seconds
Started Jul 31 05:09:13 PM PDT 24
Finished Jul 31 05:09:14 PM PDT 24
Peak memory 195032 kb
Host smart-274fe4fc-1c8d-44cd-9b7d-64d89ec688bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574050840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2574050840
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2885569809
Short name T570
Test name
Test status
Simulation time 18758289 ps
CPU time 0.61 seconds
Started Jul 31 05:09:12 PM PDT 24
Finished Jul 31 05:09:12 PM PDT 24
Peak memory 195116 kb
Host smart-8954a8b7-c5c4-440d-9865-d9986b2dc7fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885569809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2885569809
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3091384998
Short name T567
Test name
Test status
Simulation time 39054933 ps
CPU time 0.57 seconds
Started Jul 31 05:09:12 PM PDT 24
Finished Jul 31 05:09:13 PM PDT 24
Peak memory 195000 kb
Host smart-53c9fb6c-6ebe-4ca4-b81f-55c31eccb8b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091384998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3091384998
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.480504102
Short name T535
Test name
Test status
Simulation time 63426049 ps
CPU time 0.6 seconds
Started Jul 31 05:09:13 PM PDT 24
Finished Jul 31 05:09:14 PM PDT 24
Peak memory 194988 kb
Host smart-0c4e94fb-30a4-4cc8-a9ce-4c687d2f9001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480504102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.480504102
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.356587018
Short name T648
Test name
Test status
Simulation time 53660103 ps
CPU time 0.59 seconds
Started Jul 31 05:09:12 PM PDT 24
Finished Jul 31 05:09:13 PM PDT 24
Peak memory 195000 kb
Host smart-9db0f2f7-6932-4269-bb08-72bfd15b672a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356587018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.356587018
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.4240407695
Short name T640
Test name
Test status
Simulation time 18218955 ps
CPU time 0.62 seconds
Started Jul 31 05:09:12 PM PDT 24
Finished Jul 31 05:09:13 PM PDT 24
Peak memory 194972 kb
Host smart-b512ccc0-4ef1-4aa2-8794-f6d042e760e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240407695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.4240407695
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.4132762686
Short name T636
Test name
Test status
Simulation time 15208538 ps
CPU time 0.6 seconds
Started Jul 31 05:09:11 PM PDT 24
Finished Jul 31 05:09:12 PM PDT 24
Peak memory 195044 kb
Host smart-a44075d2-a6fb-48a3-bacc-cb20d3feb346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132762686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.4132762686
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3412383013
Short name T556
Test name
Test status
Simulation time 85845471 ps
CPU time 0.59 seconds
Started Jul 31 05:09:13 PM PDT 24
Finished Jul 31 05:09:13 PM PDT 24
Peak memory 195120 kb
Host smart-8501b305-6872-4f21-b052-ed8d13f65c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412383013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3412383013
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2530218098
Short name T612
Test name
Test status
Simulation time 22039816 ps
CPU time 0.62 seconds
Started Jul 31 05:09:12 PM PDT 24
Finished Jul 31 05:09:13 PM PDT 24
Peak memory 194984 kb
Host smart-7ef27788-99d6-42ee-9b22-2533830feb7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530218098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2530218098
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.93704125
Short name T546
Test name
Test status
Simulation time 13665796 ps
CPU time 0.59 seconds
Started Jul 31 05:09:15 PM PDT 24
Finished Jul 31 05:09:15 PM PDT 24
Peak memory 194984 kb
Host smart-adc54c75-3d43-4996-9e3c-287739ff3b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93704125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.93704125
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3890695726
Short name T604
Test name
Test status
Simulation time 27064336 ps
CPU time 1.57 seconds
Started Jul 31 05:08:51 PM PDT 24
Finished Jul 31 05:08:52 PM PDT 24
Peak memory 200152 kb
Host smart-08c298a0-6bb1-41f5-acba-ef70439e1e2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890695726 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3890695726
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.684880261
Short name T103
Test name
Test status
Simulation time 77991103 ps
CPU time 0.85 seconds
Started Jul 31 05:08:51 PM PDT 24
Finished Jul 31 05:08:52 PM PDT 24
Peak memory 199636 kb
Host smart-c61b2f5b-64d6-4fb7-9ab0-5b2831224a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684880261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.684880261
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1618100394
Short name T560
Test name
Test status
Simulation time 14891771 ps
CPU time 0.62 seconds
Started Jul 31 05:08:43 PM PDT 24
Finished Jul 31 05:08:44 PM PDT 24
Peak memory 195000 kb
Host smart-1ad0a0df-5ebc-4fce-b2c9-02c7c4460b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618100394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1618100394
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.535121087
Short name T587
Test name
Test status
Simulation time 179627017 ps
CPU time 1.69 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:54 PM PDT 24
Peak memory 200084 kb
Host smart-934a6456-f15a-4b43-bb48-3420b7677166
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535121087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.535121087
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.182210688
Short name T563
Test name
Test status
Simulation time 57697034 ps
CPU time 1.23 seconds
Started Jul 31 05:08:44 PM PDT 24
Finished Jul 31 05:08:45 PM PDT 24
Peak memory 200044 kb
Host smart-9f90c0a5-feeb-40d4-a3ff-4da3d381b475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182210688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.182210688
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3892592160
Short name T647
Test name
Test status
Simulation time 137357152 ps
CPU time 2.82 seconds
Started Jul 31 05:08:51 PM PDT 24
Finished Jul 31 05:08:54 PM PDT 24
Peak memory 200116 kb
Host smart-b1fe0aed-3f45-4236-82cb-665d3fdf7db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892592160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3892592160
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3551896816
Short name T651
Test name
Test status
Simulation time 76150820 ps
CPU time 2.71 seconds
Started Jul 31 05:08:54 PM PDT 24
Finished Jul 31 05:08:57 PM PDT 24
Peak memory 208348 kb
Host smart-235b0c4d-cf68-47f8-bfa6-4002239e0810
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551896816 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3551896816
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3988990103
Short name T601
Test name
Test status
Simulation time 36562061 ps
CPU time 0.9 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:53 PM PDT 24
Peak memory 199604 kb
Host smart-69d7612f-bdb1-47be-b7d1-be835295f6ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988990103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3988990103
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1006954711
Short name T656
Test name
Test status
Simulation time 47142076 ps
CPU time 0.58 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:53 PM PDT 24
Peak memory 195008 kb
Host smart-d5ed0315-6e1c-420f-83c3-11eb9839a920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006954711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1006954711
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1308422278
Short name T598
Test name
Test status
Simulation time 179854849 ps
CPU time 1.72 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:54 PM PDT 24
Peak memory 200068 kb
Host smart-70ed52ab-f138-46a9-bf5a-108697bf3c37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308422278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1308422278
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2394347719
Short name T542
Test name
Test status
Simulation time 101132058 ps
CPU time 2.55 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:55 PM PDT 24
Peak memory 200056 kb
Host smart-7b2711de-141e-43a0-82fc-4dc99b05fa82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394347719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2394347719
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2877983026
Short name T575
Test name
Test status
Simulation time 167226940 ps
CPU time 2.9 seconds
Started Jul 31 05:08:53 PM PDT 24
Finished Jul 31 05:08:56 PM PDT 24
Peak memory 200064 kb
Host smart-bc7a99c5-e6d5-407e-a10d-43baad4a4b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877983026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2877983026
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2822486925
Short name T606
Test name
Test status
Simulation time 58960075 ps
CPU time 3.83 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:56 PM PDT 24
Peak memory 216204 kb
Host smart-8c31f595-6971-4e48-a36c-db02fab12bec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822486925 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2822486925
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4029619947
Short name T610
Test name
Test status
Simulation time 120900132 ps
CPU time 0.72 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:53 PM PDT 24
Peak memory 198320 kb
Host smart-fdc7cc28-bb3f-4694-952d-592357487fe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029619947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.4029619947
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.982926651
Short name T615
Test name
Test status
Simulation time 17597309 ps
CPU time 0.65 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:53 PM PDT 24
Peak memory 195156 kb
Host smart-0cee67d6-c018-4405-822a-3777c1aa1aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982926651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.982926651
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1506090310
Short name T634
Test name
Test status
Simulation time 47057673 ps
CPU time 1.16 seconds
Started Jul 31 05:08:54 PM PDT 24
Finished Jul 31 05:08:55 PM PDT 24
Peak memory 199944 kb
Host smart-12c33920-bd10-47dd-8191-b71333d33005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506090310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1506090310
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1837417387
Short name T579
Test name
Test status
Simulation time 50911550 ps
CPU time 1.57 seconds
Started Jul 31 05:08:53 PM PDT 24
Finished Jul 31 05:08:55 PM PDT 24
Peak memory 200092 kb
Host smart-a892f1f1-6d94-4db2-be24-34f29f545a36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837417387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1837417387
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2210272524
Short name T135
Test name
Test status
Simulation time 110274124 ps
CPU time 2.03 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:54 PM PDT 24
Peak memory 200136 kb
Host smart-5d690ea8-4a37-424d-9a8b-c90002875aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210272524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2210272524
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2346129179
Short name T658
Test name
Test status
Simulation time 595693655 ps
CPU time 1.79 seconds
Started Jul 31 05:08:54 PM PDT 24
Finished Jul 31 05:08:56 PM PDT 24
Peak memory 200152 kb
Host smart-19cd1afd-c26c-458a-b33b-ada65cc41481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346129179 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2346129179
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2774470208
Short name T115
Test name
Test status
Simulation time 33031671 ps
CPU time 0.68 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:53 PM PDT 24
Peak memory 198004 kb
Host smart-80b88078-bc2b-4cac-8a37-3b7ed3b8d898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774470208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2774470208
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3801129941
Short name T558
Test name
Test status
Simulation time 41638957 ps
CPU time 0.61 seconds
Started Jul 31 05:08:50 PM PDT 24
Finished Jul 31 05:08:51 PM PDT 24
Peak memory 195032 kb
Host smart-37ed94bf-9fa4-418e-8e8c-654efbfe6423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801129941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3801129941
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1794545448
Short name T114
Test name
Test status
Simulation time 184212149 ps
CPU time 1.13 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:53 PM PDT 24
Peak memory 198780 kb
Host smart-e38ffbce-6fcf-4513-8c74-5a456d0f0894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794545448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1794545448
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.961533232
Short name T623
Test name
Test status
Simulation time 97435997 ps
CPU time 1.4 seconds
Started Jul 31 05:08:52 PM PDT 24
Finished Jul 31 05:08:53 PM PDT 24
Peak memory 200200 kb
Host smart-61d70690-25d6-487e-b433-7724ff3c6d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961533232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.961533232
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1163792185
Short name T600
Test name
Test status
Simulation time 330230581 ps
CPU time 1.76 seconds
Started Jul 31 05:08:51 PM PDT 24
Finished Jul 31 05:08:53 PM PDT 24
Peak memory 200116 kb
Host smart-62305ef1-5efb-40dc-80df-5c732dbc1bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163792185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1163792185
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.22284202
Short name T566
Test name
Test status
Simulation time 711879531 ps
CPU time 2.59 seconds
Started Jul 31 05:08:58 PM PDT 24
Finished Jul 31 05:09:00 PM PDT 24
Peak memory 200176 kb
Host smart-4a9e6e13-ac87-4b8f-8dc2-3a5f42e6463d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22284202 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.22284202
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3100533929
Short name T597
Test name
Test status
Simulation time 53638677 ps
CPU time 0.67 seconds
Started Jul 31 05:08:55 PM PDT 24
Finished Jul 31 05:08:55 PM PDT 24
Peak memory 198340 kb
Host smart-a17ae09c-e829-4468-a450-743d28b0edb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100533929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3100533929
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1771165039
Short name T617
Test name
Test status
Simulation time 17871299 ps
CPU time 0.6 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:08:57 PM PDT 24
Peak memory 195080 kb
Host smart-8555ab0d-9880-4c21-a733-72c5c8d8d16c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771165039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1771165039
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4018787995
Short name T631
Test name
Test status
Simulation time 91640211 ps
CPU time 2.14 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:08:58 PM PDT 24
Peak memory 200136 kb
Host smart-0e25e5c7-b147-4697-a6d0-494c4d3b9ec9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018787995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4018787995
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2378982355
Short name T649
Test name
Test status
Simulation time 299955875 ps
CPU time 3.84 seconds
Started Jul 31 05:08:56 PM PDT 24
Finished Jul 31 05:09:00 PM PDT 24
Peak memory 200120 kb
Host smart-58f4e7cc-7f73-49ed-aab3-a28038b33418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378982355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2378982355
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.449805278
Short name T69
Test name
Test status
Simulation time 956481500 ps
CPU time 1.98 seconds
Started Jul 31 05:08:54 PM PDT 24
Finished Jul 31 05:08:56 PM PDT 24
Peak memory 200116 kb
Host smart-7c0d7356-b81d-43c4-a897-46d115d9fbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449805278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.449805278
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2480745491
Short name T28
Test name
Test status
Simulation time 32166105 ps
CPU time 0.56 seconds
Started Jul 31 07:06:36 PM PDT 24
Finished Jul 31 07:06:37 PM PDT 24
Peak memory 196696 kb
Host smart-2c4ce521-dd5b-493b-9857-f0d395a24132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480745491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2480745491
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3092072469
Short name T438
Test name
Test status
Simulation time 4497751751 ps
CPU time 66.01 seconds
Started Jul 31 07:06:23 PM PDT 24
Finished Jul 31 07:07:29 PM PDT 24
Peak memory 199936 kb
Host smart-bb0101f5-4b6e-4b0f-8d2d-8289643f64c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3092072469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3092072469
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1684306796
Short name T454
Test name
Test status
Simulation time 13028240388 ps
CPU time 57.74 seconds
Started Jul 31 07:06:26 PM PDT 24
Finished Jul 31 07:07:24 PM PDT 24
Peak memory 216468 kb
Host smart-a7fc642e-baa3-4a60-8ba4-b58e9ff2007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684306796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1684306796
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.180646136
Short name T231
Test name
Test status
Simulation time 10396575221 ps
CPU time 958.71 seconds
Started Jul 31 07:06:23 PM PDT 24
Finished Jul 31 07:22:22 PM PDT 24
Peak memory 727372 kb
Host smart-a0a14dec-f2ed-432b-8011-529be6a5cda3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=180646136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.180646136
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1903400097
Short name T230
Test name
Test status
Simulation time 1460720943 ps
CPU time 80.61 seconds
Started Jul 31 07:06:21 PM PDT 24
Finished Jul 31 07:07:42 PM PDT 24
Peak memory 199904 kb
Host smart-ddb8d986-e89a-4fbf-ab4e-1f10425005e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903400097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1903400097
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1005408822
Short name T366
Test name
Test status
Simulation time 15727537134 ps
CPU time 130.14 seconds
Started Jul 31 07:06:25 PM PDT 24
Finished Jul 31 07:08:35 PM PDT 24
Peak memory 200088 kb
Host smart-886afb9f-3b61-45bd-942c-ab5182ede571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005408822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1005408822
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2840027425
Short name T367
Test name
Test status
Simulation time 815265712 ps
CPU time 3.42 seconds
Started Jul 31 07:06:23 PM PDT 24
Finished Jul 31 07:06:26 PM PDT 24
Peak memory 199912 kb
Host smart-66ced338-5a32-46a4-ac08-b59f771f72f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840027425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2840027425
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.4221039794
Short name T489
Test name
Test status
Simulation time 5485353941 ps
CPU time 61.82 seconds
Started Jul 31 07:06:30 PM PDT 24
Finished Jul 31 07:07:32 PM PDT 24
Peak memory 200052 kb
Host smart-153fc193-afff-428e-b241-21290f5d8913
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4221039794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.4221039794
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.488972201
Short name T303
Test name
Test status
Simulation time 2864303913 ps
CPU time 53.84 seconds
Started Jul 31 07:06:27 PM PDT 24
Finished Jul 31 07:07:21 PM PDT 24
Peak memory 199984 kb
Host smart-50eefe2c-4100-4799-bca4-1d28e20d99e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=488972201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.488972201
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2756282490
Short name T345
Test name
Test status
Simulation time 3037312076 ps
CPU time 127.61 seconds
Started Jul 31 07:06:27 PM PDT 24
Finished Jul 31 07:08:35 PM PDT 24
Peak memory 200104 kb
Host smart-855eb781-86ad-4b85-97ce-d03007d137f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2756282490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2756282490
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3131491981
Short name T315
Test name
Test status
Simulation time 39808155886 ps
CPU time 585.75 seconds
Started Jul 31 07:06:29 PM PDT 24
Finished Jul 31 07:16:15 PM PDT 24
Peak memory 199984 kb
Host smart-dcbb11a9-dd3f-4912-b07f-2ee05d2cad57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3131491981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3131491981
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1071916867
Short name T192
Test name
Test status
Simulation time 132733709824 ps
CPU time 2270.88 seconds
Started Jul 31 07:06:29 PM PDT 24
Finished Jul 31 07:44:20 PM PDT 24
Peak memory 215640 kb
Host smart-7b6f2404-f6c1-4262-85a6-0b1d253e2321
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1071916867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1071916867
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.441168652
Short name T356
Test name
Test status
Simulation time 550095842180 ps
CPU time 2183.13 seconds
Started Jul 31 07:06:28 PM PDT 24
Finished Jul 31 07:42:51 PM PDT 24
Peak memory 215528 kb
Host smart-e6f10137-c202-4cd4-ab51-8ae732a66587
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=441168652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.441168652
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3478178101
Short name T41
Test name
Test status
Simulation time 43563384641 ps
CPU time 137.08 seconds
Started Jul 31 07:06:33 PM PDT 24
Finished Jul 31 07:08:50 PM PDT 24
Peak memory 200052 kb
Host smart-f71fbdd2-28af-4d8c-88a9-852b5cb86d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478178101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3478178101
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.4253282439
Short name T404
Test name
Test status
Simulation time 72533273 ps
CPU time 0.59 seconds
Started Jul 31 07:06:49 PM PDT 24
Finished Jul 31 07:06:50 PM PDT 24
Peak memory 195944 kb
Host smart-3ba56907-5398-46f0-9e2f-f724eda972e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253282439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.4253282439
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.4024306396
Short name T480
Test name
Test status
Simulation time 4055082651 ps
CPU time 73.65 seconds
Started Jul 31 07:06:35 PM PDT 24
Finished Jul 31 07:07:49 PM PDT 24
Peak memory 200052 kb
Host smart-1de74be8-8f14-4ff1-811b-140fded3a8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024306396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.4024306396
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3982812143
Short name T47
Test name
Test status
Simulation time 6464911966 ps
CPU time 1301.2 seconds
Started Jul 31 07:06:34 PM PDT 24
Finished Jul 31 07:28:15 PM PDT 24
Peak memory 797968 kb
Host smart-19a79a78-1c29-4c78-9406-a9743a5be1a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982812143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3982812143
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2595035003
Short name T420
Test name
Test status
Simulation time 14432820154 ps
CPU time 189.47 seconds
Started Jul 31 07:06:34 PM PDT 24
Finished Jul 31 07:09:44 PM PDT 24
Peak memory 200040 kb
Host smart-3122dcbe-6a88-4348-b780-58c8b9ac099d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595035003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2595035003
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1717534485
Short name T95
Test name
Test status
Simulation time 507136949 ps
CPU time 7.49 seconds
Started Jul 31 07:06:35 PM PDT 24
Finished Jul 31 07:06:42 PM PDT 24
Peak memory 199840 kb
Host smart-2b060e11-107b-43e4-aeaf-43fd76cbda4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717534485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1717534485
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2931441718
Short name T55
Test name
Test status
Simulation time 170907616 ps
CPU time 0.96 seconds
Started Jul 31 07:06:47 PM PDT 24
Finished Jul 31 07:06:48 PM PDT 24
Peak memory 219560 kb
Host smart-5d1626b7-ee9c-44c4-ad10-fd73761020a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931441718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2931441718
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3611866408
Short name T458
Test name
Test status
Simulation time 785039546 ps
CPU time 5.06 seconds
Started Jul 31 07:06:36 PM PDT 24
Finished Jul 31 07:06:41 PM PDT 24
Peak memory 199956 kb
Host smart-2c37c92b-4b7f-4781-8afb-148962ce663a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611866408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3611866408
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3482690372
Short name T34
Test name
Test status
Simulation time 117001307957 ps
CPU time 6147.14 seconds
Started Jul 31 07:06:49 PM PDT 24
Finished Jul 31 08:49:17 PM PDT 24
Peak memory 860260 kb
Host smart-bdf54c24-9941-4aaf-a13c-20273ade5bd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482690372 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3482690372
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3418947594
Short name T72
Test name
Test status
Simulation time 138359961866 ps
CPU time 843.28 seconds
Started Jul 31 07:06:46 PM PDT 24
Finished Jul 31 07:20:49 PM PDT 24
Peak memory 717428 kb
Host smart-2cbeffad-42fd-4265-a5fe-b2401c3cd978
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418947594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3418947594
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1639056986
Short name T334
Test name
Test status
Simulation time 4367396073 ps
CPU time 50.66 seconds
Started Jul 31 07:06:45 PM PDT 24
Finished Jul 31 07:07:36 PM PDT 24
Peak memory 200024 kb
Host smart-038420f3-0966-48ad-bb74-fd22a4f4170f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1639056986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1639056986
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2315694176
Short name T268
Test name
Test status
Simulation time 24905917007 ps
CPU time 93.29 seconds
Started Jul 31 07:06:41 PM PDT 24
Finished Jul 31 07:08:15 PM PDT 24
Peak memory 199952 kb
Host smart-2bf5e58d-bd64-4445-872a-e967a7fe423a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2315694176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2315694176
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.291428800
Short name T533
Test name
Test status
Simulation time 16688439482 ps
CPU time 136.66 seconds
Started Jul 31 07:06:50 PM PDT 24
Finished Jul 31 07:09:07 PM PDT 24
Peak memory 200004 kb
Host smart-b1d9fa73-57db-4095-827e-9d3c827b1445
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=291428800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.291428800
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1081552717
Short name T434
Test name
Test status
Simulation time 194109562117 ps
CPU time 643.63 seconds
Started Jul 31 07:06:40 PM PDT 24
Finished Jul 31 07:17:24 PM PDT 24
Peak memory 200048 kb
Host smart-e4478700-98a2-4106-8ce4-9ba53ae5e36a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1081552717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1081552717
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1604650603
Short name T452
Test name
Test status
Simulation time 516772314176 ps
CPU time 2276.96 seconds
Started Jul 31 07:06:47 PM PDT 24
Finished Jul 31 07:44:44 PM PDT 24
Peak memory 216404 kb
Host smart-e002936d-65df-4dea-afe3-fdef107a83ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1604650603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1604650603
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.4036586215
Short name T141
Test name
Test status
Simulation time 77491328776 ps
CPU time 2169.8 seconds
Started Jul 31 07:06:40 PM PDT 24
Finished Jul 31 07:42:51 PM PDT 24
Peak memory 215584 kb
Host smart-0e8eb9be-cb48-4a68-98fb-49cc88bff990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4036586215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.4036586215
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1299594212
Short name T38
Test name
Test status
Simulation time 571291226 ps
CPU time 10.76 seconds
Started Jul 31 07:06:36 PM PDT 24
Finished Jul 31 07:06:47 PM PDT 24
Peak memory 199904 kb
Host smart-b7b1c6e4-9acc-4213-bf48-ffb6c8aeb983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299594212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1299594212
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2628175892
Short name T497
Test name
Test status
Simulation time 38254544 ps
CPU time 0.61 seconds
Started Jul 31 07:08:24 PM PDT 24
Finished Jul 31 07:08:25 PM PDT 24
Peak memory 196016 kb
Host smart-22b10e23-d56c-4bf7-8dce-5c3631cc1980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628175892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2628175892
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4021507300
Short name T203
Test name
Test status
Simulation time 409922956 ps
CPU time 10.74 seconds
Started Jul 31 07:08:17 PM PDT 24
Finished Jul 31 07:08:28 PM PDT 24
Peak memory 199812 kb
Host smart-8c6e54eb-b9cb-4574-bef5-3bc3c132abe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021507300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4021507300
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4049886795
Short name T262
Test name
Test status
Simulation time 540371338 ps
CPU time 4.9 seconds
Started Jul 31 07:08:26 PM PDT 24
Finished Jul 31 07:08:31 PM PDT 24
Peak memory 199956 kb
Host smart-53eaddd8-000a-47df-a7e4-3b3583366973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049886795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4049886795
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3686739049
Short name T323
Test name
Test status
Simulation time 1679353231 ps
CPU time 278.3 seconds
Started Jul 31 07:08:19 PM PDT 24
Finished Jul 31 07:12:57 PM PDT 24
Peak memory 668936 kb
Host smart-a11de839-f56a-45cc-a2c3-2ac7179c98ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686739049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3686739049
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3347167392
Short name T235
Test name
Test status
Simulation time 3201276605 ps
CPU time 40.51 seconds
Started Jul 31 07:08:25 PM PDT 24
Finished Jul 31 07:09:05 PM PDT 24
Peak memory 200016 kb
Host smart-4413255c-7683-4e32-8a3b-e75d434e330a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347167392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3347167392
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3145741595
Short name T173
Test name
Test status
Simulation time 11659945755 ps
CPU time 101.59 seconds
Started Jul 31 07:08:19 PM PDT 24
Finished Jul 31 07:10:01 PM PDT 24
Peak memory 200020 kb
Host smart-f0a3fe1d-6d04-4bc7-8b9b-39f88d7cf649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145741595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3145741595
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.4231664128
Short name T208
Test name
Test status
Simulation time 124398039 ps
CPU time 5.26 seconds
Started Jul 31 07:08:19 PM PDT 24
Finished Jul 31 07:08:25 PM PDT 24
Peak memory 199920 kb
Host smart-3cd40dea-7903-4769-87b8-08c0a2fe0dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231664128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.4231664128
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1051833652
Short name T402
Test name
Test status
Simulation time 19502811475 ps
CPU time 539.65 seconds
Started Jul 31 07:08:23 PM PDT 24
Finished Jul 31 07:17:23 PM PDT 24
Peak memory 503700 kb
Host smart-ed59e975-268e-49c4-aa6f-5af75df319dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051833652 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1051833652
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2461719149
Short name T247
Test name
Test status
Simulation time 19903856589 ps
CPU time 120.36 seconds
Started Jul 31 07:08:23 PM PDT 24
Finished Jul 31 07:10:24 PM PDT 24
Peak memory 200016 kb
Host smart-b13124a0-9abe-40f2-8439-46be0a018ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461719149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2461719149
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1071039107
Short name T153
Test name
Test status
Simulation time 25832425 ps
CPU time 0.61 seconds
Started Jul 31 07:08:38 PM PDT 24
Finished Jul 31 07:08:38 PM PDT 24
Peak memory 195976 kb
Host smart-1fae4e14-cf8f-46dc-a74b-d316a0815cfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071039107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1071039107
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2843893374
Short name T43
Test name
Test status
Simulation time 3710765643 ps
CPU time 109.94 seconds
Started Jul 31 07:08:38 PM PDT 24
Finished Jul 31 07:10:28 PM PDT 24
Peak memory 200004 kb
Host smart-6b6dfbd2-7469-4b0e-bd7e-f7bc2769170b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843893374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2843893374
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.800033200
Short name T21
Test name
Test status
Simulation time 373080681 ps
CPU time 6.44 seconds
Started Jul 31 07:08:38 PM PDT 24
Finished Jul 31 07:08:44 PM PDT 24
Peak memory 199880 kb
Host smart-798fb02b-7938-4633-8fba-2b676e9d775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800033200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.800033200
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1808349232
Short name T190
Test name
Test status
Simulation time 11796250387 ps
CPU time 1105.42 seconds
Started Jul 31 07:08:35 PM PDT 24
Finished Jul 31 07:27:01 PM PDT 24
Peak memory 776292 kb
Host smart-bff9fecc-90b0-4160-b21f-916f019ca456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808349232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1808349232
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1998141263
Short name T238
Test name
Test status
Simulation time 66564976585 ps
CPU time 177.62 seconds
Started Jul 31 07:08:37 PM PDT 24
Finished Jul 31 07:11:35 PM PDT 24
Peak memory 200100 kb
Host smart-41e95391-9e64-4934-b7bc-8c69dcef206d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998141263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1998141263
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.72082124
Short name T357
Test name
Test status
Simulation time 9191309571 ps
CPU time 107.17 seconds
Started Jul 31 07:08:31 PM PDT 24
Finished Jul 31 07:10:18 PM PDT 24
Peak memory 208268 kb
Host smart-7105c69c-c2e1-4c39-ba88-ef14926b49f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72082124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.72082124
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2967049581
Short name T94
Test name
Test status
Simulation time 2892545407 ps
CPU time 11.16 seconds
Started Jul 31 07:08:29 PM PDT 24
Finished Jul 31 07:08:41 PM PDT 24
Peak memory 200092 kb
Host smart-55bd4328-900d-43b2-86f2-113e999ef445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967049581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2967049581
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2796283175
Short name T216
Test name
Test status
Simulation time 72671495595 ps
CPU time 325.98 seconds
Started Jul 31 07:08:37 PM PDT 24
Finished Jul 31 07:14:03 PM PDT 24
Peak memory 216420 kb
Host smart-70b8fd58-6721-426c-b90a-3d3624e4873f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796283175 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2796283175
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1233904959
Short name T123
Test name
Test status
Simulation time 8320979234 ps
CPU time 102.29 seconds
Started Jul 31 07:08:35 PM PDT 24
Finished Jul 31 07:10:17 PM PDT 24
Peak memory 200020 kb
Host smart-61620c0a-096a-4b9b-91f8-845b40a2ff20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233904959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1233904959
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3271060298
Short name T81
Test name
Test status
Simulation time 68697330 ps
CPU time 0.56 seconds
Started Jul 31 07:08:48 PM PDT 24
Finished Jul 31 07:08:49 PM PDT 24
Peak memory 194960 kb
Host smart-2012ef07-1ef4-439b-b5b8-62b118c3acfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271060298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3271060298
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3119636718
Short name T233
Test name
Test status
Simulation time 428336103 ps
CPU time 26.02 seconds
Started Jul 31 07:08:35 PM PDT 24
Finished Jul 31 07:09:02 PM PDT 24
Peak memory 199860 kb
Host smart-e8ff2c84-1586-46ea-bf26-d1abd7e16722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119636718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3119636718
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.641484501
Short name T294
Test name
Test status
Simulation time 3093110932 ps
CPU time 42.61 seconds
Started Jul 31 07:08:47 PM PDT 24
Finished Jul 31 07:09:30 PM PDT 24
Peak memory 200084 kb
Host smart-51411af5-2d82-4528-8af7-27f9609f5449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641484501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.641484501
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3594524399
Short name T414
Test name
Test status
Simulation time 3725355469 ps
CPU time 639.71 seconds
Started Jul 31 07:08:44 PM PDT 24
Finished Jul 31 07:19:23 PM PDT 24
Peak memory 663948 kb
Host smart-7ef2b2da-78ef-44bd-8874-96ac391503e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594524399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3594524399
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3633910498
Short name T317
Test name
Test status
Simulation time 794127956 ps
CPU time 14.34 seconds
Started Jul 31 07:08:43 PM PDT 24
Finished Jul 31 07:08:57 PM PDT 24
Peak memory 199972 kb
Host smart-47ffc3f9-d6a8-4c4c-8372-0df12a992af0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633910498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3633910498
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2544497873
Short name T333
Test name
Test status
Simulation time 13678884028 ps
CPU time 60.47 seconds
Started Jul 31 07:08:38 PM PDT 24
Finished Jul 31 07:09:38 PM PDT 24
Peak memory 200088 kb
Host smart-1e88438b-31f2-4ba9-a646-864651de0557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544497873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2544497873
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.403760762
Short name T139
Test name
Test status
Simulation time 1223227133 ps
CPU time 12.9 seconds
Started Jul 31 07:08:36 PM PDT 24
Finished Jul 31 07:08:49 PM PDT 24
Peak memory 199976 kb
Host smart-0e32c1c2-6dbe-466f-b54b-d9c1c87b5e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403760762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.403760762
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.958553246
Short name T125
Test name
Test status
Simulation time 15555368628 ps
CPU time 1562.77 seconds
Started Jul 31 07:08:47 PM PDT 24
Finished Jul 31 07:34:50 PM PDT 24
Peak memory 710436 kb
Host smart-afdac1cf-f8e5-4bcd-9483-ad28d575afa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958553246 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.958553246
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.265923265
Short name T92
Test name
Test status
Simulation time 63947751 ps
CPU time 3.74 seconds
Started Jul 31 07:08:43 PM PDT 24
Finished Jul 31 07:08:47 PM PDT 24
Peak memory 199756 kb
Host smart-e7c3969e-6f21-4162-827e-8a533897b516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265923265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.265923265
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2346999704
Short name T292
Test name
Test status
Simulation time 36635095 ps
CPU time 0.58 seconds
Started Jul 31 07:08:53 PM PDT 24
Finished Jul 31 07:08:54 PM PDT 24
Peak memory 194960 kb
Host smart-15f1a23e-80d1-4675-9c46-680412aaffcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346999704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2346999704
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1510648079
Short name T245
Test name
Test status
Simulation time 185585533 ps
CPU time 9.9 seconds
Started Jul 31 07:08:51 PM PDT 24
Finished Jul 31 07:09:01 PM PDT 24
Peak memory 199828 kb
Host smart-da3863b2-1807-4f02-88aa-8ea8e3722c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510648079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1510648079
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2547191937
Short name T499
Test name
Test status
Simulation time 82091266 ps
CPU time 4.13 seconds
Started Jul 31 07:08:52 PM PDT 24
Finished Jul 31 07:08:57 PM PDT 24
Peak memory 199896 kb
Host smart-df400af2-c504-402d-b500-89fc0a0f1cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547191937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2547191937
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1369704404
Short name T389
Test name
Test status
Simulation time 1478217515 ps
CPU time 319.23 seconds
Started Jul 31 07:08:48 PM PDT 24
Finished Jul 31 07:14:08 PM PDT 24
Peak memory 681896 kb
Host smart-ce8ba102-bb96-43cf-9959-7cddab8fff1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369704404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1369704404
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2098632414
Short name T498
Test name
Test status
Simulation time 77265823 ps
CPU time 0.65 seconds
Started Jul 31 07:08:54 PM PDT 24
Finished Jul 31 07:08:55 PM PDT 24
Peak memory 196432 kb
Host smart-c5e27772-61de-4283-b894-a2071519962d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098632414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2098632414
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1932282926
Short name T202
Test name
Test status
Simulation time 4779436558 ps
CPU time 67.39 seconds
Started Jul 31 07:08:50 PM PDT 24
Finished Jul 31 07:09:57 PM PDT 24
Peak memory 208260 kb
Host smart-b66a8122-3d0d-4ba7-a46a-6be54dde399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932282926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1932282926
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1765731567
Short name T138
Test name
Test status
Simulation time 2023701103 ps
CPU time 12.82 seconds
Started Jul 31 07:08:53 PM PDT 24
Finished Jul 31 07:09:06 PM PDT 24
Peak memory 199912 kb
Host smart-43d16791-66bf-430f-8886-c5c4cad31551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765731567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1765731567
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2653677207
Short name T78
Test name
Test status
Simulation time 371826605810 ps
CPU time 889.25 seconds
Started Jul 31 07:08:53 PM PDT 24
Finished Jul 31 07:23:42 PM PDT 24
Peak memory 592760 kb
Host smart-75d7e3be-3032-4c9a-907a-a3ea5dc97771
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653677207 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2653677207
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1565595820
Short name T86
Test name
Test status
Simulation time 35345594627 ps
CPU time 101.81 seconds
Started Jul 31 07:08:54 PM PDT 24
Finished Jul 31 07:10:36 PM PDT 24
Peak memory 200016 kb
Host smart-ebb4c941-9469-464f-a262-a1ec4c723132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565595820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1565595820
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3575327334
Short name T475
Test name
Test status
Simulation time 22429034 ps
CPU time 0.6 seconds
Started Jul 31 07:09:07 PM PDT 24
Finished Jul 31 07:09:08 PM PDT 24
Peak memory 194872 kb
Host smart-6ad76e2e-9b95-466a-952c-7093c0b6e60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575327334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3575327334
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2281440980
Short name T300
Test name
Test status
Simulation time 1469700381 ps
CPU time 78.86 seconds
Started Jul 31 07:08:53 PM PDT 24
Finished Jul 31 07:10:12 PM PDT 24
Peak memory 199808 kb
Host smart-2dfc0502-4aca-43ca-8f26-82b8b68ced1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281440980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2281440980
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.436843430
Short name T293
Test name
Test status
Simulation time 14311405625 ps
CPU time 66.17 seconds
Started Jul 31 07:08:54 PM PDT 24
Finished Jul 31 07:10:00 PM PDT 24
Peak memory 200268 kb
Host smart-decfea16-832b-45f3-9cb7-862aa6522eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436843430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.436843430
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3323297325
Short name T204
Test name
Test status
Simulation time 221401507 ps
CPU time 27.15 seconds
Started Jul 31 07:08:54 PM PDT 24
Finished Jul 31 07:09:21 PM PDT 24
Peak memory 254220 kb
Host smart-c10bb5a6-7387-4fa5-b0db-78e49af985ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323297325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3323297325
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1752571478
Short name T344
Test name
Test status
Simulation time 47767773573 ps
CPU time 147.11 seconds
Started Jul 31 07:08:55 PM PDT 24
Finished Jul 31 07:11:22 PM PDT 24
Peak memory 200092 kb
Host smart-66802b0a-e418-40ea-b8bc-1f4cf23e9c15
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752571478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1752571478
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3027300720
Short name T37
Test name
Test status
Simulation time 176158198357 ps
CPU time 205.36 seconds
Started Jul 31 07:08:53 PM PDT 24
Finished Jul 31 07:12:18 PM PDT 24
Peak memory 200088 kb
Host smart-b6f5a2c2-56b0-4d32-a4d9-8849126d94ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027300720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3027300720
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3462386139
Short name T213
Test name
Test status
Simulation time 244282846 ps
CPU time 10.96 seconds
Started Jul 31 07:08:57 PM PDT 24
Finished Jul 31 07:09:08 PM PDT 24
Peak memory 199920 kb
Host smart-9190b840-2720-4665-b915-6f519b6d0559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462386139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3462386139
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.342229773
Short name T11
Test name
Test status
Simulation time 36343063677 ps
CPU time 450.59 seconds
Started Jul 31 07:08:53 PM PDT 24
Finished Jul 31 07:16:24 PM PDT 24
Peak memory 208252 kb
Host smart-3c725ff3-afec-46f6-a553-21290ef464b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342229773 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.342229773
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.244213890
Short name T200
Test name
Test status
Simulation time 367523856 ps
CPU time 5.15 seconds
Started Jul 31 07:08:53 PM PDT 24
Finished Jul 31 07:08:58 PM PDT 24
Peak memory 199788 kb
Host smart-2b05f618-7c32-4c06-bf9a-6c33750b3753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244213890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.244213890
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2724143628
Short name T160
Test name
Test status
Simulation time 13378237 ps
CPU time 0.58 seconds
Started Jul 31 07:09:07 PM PDT 24
Finished Jul 31 07:09:08 PM PDT 24
Peak memory 194932 kb
Host smart-330c5287-0b8d-4618-a246-fa4d67928bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724143628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2724143628
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3813677074
Short name T284
Test name
Test status
Simulation time 2884845770 ps
CPU time 87.23 seconds
Started Jul 31 07:09:00 PM PDT 24
Finished Jul 31 07:10:28 PM PDT 24
Peak memory 200008 kb
Host smart-c40f5b45-daea-41ef-be8b-7812645f2137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813677074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3813677074
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.257375744
Short name T514
Test name
Test status
Simulation time 8636564968 ps
CPU time 21.6 seconds
Started Jul 31 07:09:00 PM PDT 24
Finished Jul 31 07:09:21 PM PDT 24
Peak memory 200068 kb
Host smart-12aa5aa7-1f84-4012-b7fe-aea128257e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257375744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.257375744
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1056122927
Short name T234
Test name
Test status
Simulation time 6676954704 ps
CPU time 1288.89 seconds
Started Jul 31 07:08:59 PM PDT 24
Finished Jul 31 07:30:28 PM PDT 24
Peak memory 787280 kb
Host smart-6fa8c5d4-6bbf-4541-8d22-e1d55024818a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056122927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1056122927
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2754224092
Short name T212
Test name
Test status
Simulation time 97168644856 ps
CPU time 330.81 seconds
Started Jul 31 07:08:59 PM PDT 24
Finished Jul 31 07:14:30 PM PDT 24
Peak memory 200120 kb
Host smart-8add535e-6346-4fe6-82e3-de91cd2565d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754224092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2754224092
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.594905929
Short name T178
Test name
Test status
Simulation time 5245932590 ps
CPU time 149.63 seconds
Started Jul 31 07:09:03 PM PDT 24
Finished Jul 31 07:11:33 PM PDT 24
Peak memory 200104 kb
Host smart-e04efa56-6a1d-4c5e-b2f5-298ca25118b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594905929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.594905929
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3859162504
Short name T199
Test name
Test status
Simulation time 210843825 ps
CPU time 1.94 seconds
Started Jul 31 07:08:58 PM PDT 24
Finished Jul 31 07:09:01 PM PDT 24
Peak memory 199896 kb
Host smart-c2e9a6a2-45d0-4819-a0e9-426181dee946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859162504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3859162504
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1830474396
Short name T25
Test name
Test status
Simulation time 5953560384 ps
CPU time 349.09 seconds
Started Jul 31 07:09:07 PM PDT 24
Finished Jul 31 07:14:56 PM PDT 24
Peak memory 216368 kb
Host smart-1d777716-2426-4197-b3a5-8fc3f004e054
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830474396 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1830474396
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.521502308
Short name T483
Test name
Test status
Simulation time 2986771372 ps
CPU time 101.75 seconds
Started Jul 31 07:09:00 PM PDT 24
Finished Jul 31 07:10:42 PM PDT 24
Peak memory 200128 kb
Host smart-83c77202-29e8-459e-b882-78a8d5253c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521502308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.521502308
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3496571507
Short name T372
Test name
Test status
Simulation time 33370685 ps
CPU time 0.61 seconds
Started Jul 31 07:10:31 PM PDT 24
Finished Jul 31 07:10:32 PM PDT 24
Peak memory 195932 kb
Host smart-1cc5b4f7-ea96-496f-aafb-6e92511bc373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496571507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3496571507
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2118090408
Short name T91
Test name
Test status
Simulation time 1139060786 ps
CPU time 63.23 seconds
Started Jul 31 07:09:08 PM PDT 24
Finished Jul 31 07:10:12 PM PDT 24
Peak memory 199944 kb
Host smart-eb88a123-864e-40b2-8d38-bf7dfad29c6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2118090408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2118090408
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.59449125
Short name T15
Test name
Test status
Simulation time 1127273821 ps
CPU time 56.07 seconds
Started Jul 31 07:09:08 PM PDT 24
Finished Jul 31 07:10:04 PM PDT 24
Peak memory 199896 kb
Host smart-8b2965f5-f8f3-471f-be50-7327c8587dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59449125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.59449125
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.417181487
Short name T506
Test name
Test status
Simulation time 21064719134 ps
CPU time 932.43 seconds
Started Jul 31 07:09:06 PM PDT 24
Finished Jul 31 07:24:39 PM PDT 24
Peak memory 687184 kb
Host smart-0da34d1e-72a7-4969-ae32-c4138b5c6da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417181487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.417181487
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2395209419
Short name T12
Test name
Test status
Simulation time 2223845840 ps
CPU time 31.14 seconds
Started Jul 31 07:09:06 PM PDT 24
Finished Jul 31 07:09:37 PM PDT 24
Peak memory 199916 kb
Host smart-28f8d94a-c98b-4c1e-90a2-c1bc0a05aefb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395209419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2395209419
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1051851281
Short name T391
Test name
Test status
Simulation time 14172448086 ps
CPU time 177.67 seconds
Started Jul 31 07:09:06 PM PDT 24
Finished Jul 31 07:12:04 PM PDT 24
Peak memory 200036 kb
Host smart-ea992dd2-1963-42a1-997d-7200285a9ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051851281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1051851281
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4176288578
Short name T27
Test name
Test status
Simulation time 451513746 ps
CPU time 5.76 seconds
Started Jul 31 07:09:07 PM PDT 24
Finished Jul 31 07:09:13 PM PDT 24
Peak memory 199956 kb
Host smart-0b91da1b-e381-4f16-8e4c-dabcaa8a32c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176288578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4176288578
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2537053951
Short name T306
Test name
Test status
Simulation time 31221957013 ps
CPU time 331.49 seconds
Started Jul 31 07:10:35 PM PDT 24
Finished Jul 31 07:16:06 PM PDT 24
Peak memory 482760 kb
Host smart-b7664ad2-b39c-4833-bcda-7257f9799c39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537053951 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2537053951
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.76881076
Short name T437
Test name
Test status
Simulation time 1570146212 ps
CPU time 80.93 seconds
Started Jul 31 07:10:34 PM PDT 24
Finished Jul 31 07:11:55 PM PDT 24
Peak memory 199888 kb
Host smart-7a1dd980-7bb0-44bc-9c36-10e2af4cf59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76881076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.76881076
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2370427465
Short name T51
Test name
Test status
Simulation time 23909789 ps
CPU time 0.54 seconds
Started Jul 31 07:10:37 PM PDT 24
Finished Jul 31 07:10:38 PM PDT 24
Peak memory 194932 kb
Host smart-728ad6fc-342d-4f45-bfe6-e2d2e7fcbe5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370427465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2370427465
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.502821976
Short name T288
Test name
Test status
Simulation time 637595253 ps
CPU time 36.68 seconds
Started Jul 31 07:10:34 PM PDT 24
Finished Jul 31 07:11:11 PM PDT 24
Peak memory 199836 kb
Host smart-326b2f62-8b44-4f30-a530-a5706ddb0e60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502821976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.502821976
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1455550272
Short name T154
Test name
Test status
Simulation time 1024338378 ps
CPU time 20.04 seconds
Started Jul 31 07:10:34 PM PDT 24
Finished Jul 31 07:10:54 PM PDT 24
Peak memory 199996 kb
Host smart-bc9bef3d-c26a-4f52-b0b7-b0235426a5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455550272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1455550272
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.804614694
Short name T169
Test name
Test status
Simulation time 2055454581 ps
CPU time 315.16 seconds
Started Jul 31 07:10:33 PM PDT 24
Finished Jul 31 07:15:48 PM PDT 24
Peak memory 441848 kb
Host smart-e79fe168-0f33-4df1-8425-1ce9694cdbc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804614694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.804614694
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.563975150
Short name T186
Test name
Test status
Simulation time 4557893504 ps
CPU time 61.55 seconds
Started Jul 31 07:10:32 PM PDT 24
Finished Jul 31 07:11:34 PM PDT 24
Peak memory 200116 kb
Host smart-bf4e708f-b91a-4b71-b770-9e5c2cdc3b19
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563975150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.563975150
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1028988490
Short name T485
Test name
Test status
Simulation time 3659013381 ps
CPU time 49.32 seconds
Started Jul 31 07:10:32 PM PDT 24
Finished Jul 31 07:11:21 PM PDT 24
Peak memory 200032 kb
Host smart-389b0f1f-21cd-4ced-b1ee-6b738036c3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028988490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1028988490
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2321643230
Short name T144
Test name
Test status
Simulation time 323850010 ps
CPU time 14.55 seconds
Started Jul 31 07:10:35 PM PDT 24
Finished Jul 31 07:10:49 PM PDT 24
Peak memory 200036 kb
Host smart-ef119c6d-8def-4f66-af80-7fd0f4924cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321643230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2321643230
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3386480051
Short name T381
Test name
Test status
Simulation time 16138775322 ps
CPU time 290.84 seconds
Started Jul 31 07:10:33 PM PDT 24
Finished Jul 31 07:15:24 PM PDT 24
Peak memory 216444 kb
Host smart-f6e5740c-552b-4c5d-aa61-671642f16dd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386480051 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3386480051
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4022017991
Short name T478
Test name
Test status
Simulation time 206853728 ps
CPU time 3.02 seconds
Started Jul 31 07:10:33 PM PDT 24
Finished Jul 31 07:10:36 PM PDT 24
Peak memory 199948 kb
Host smart-4fd2c44b-03e3-482e-a70a-e4c948e26e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022017991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4022017991
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3832873266
Short name T505
Test name
Test status
Simulation time 12805550 ps
CPU time 0.59 seconds
Started Jul 31 07:10:33 PM PDT 24
Finished Jul 31 07:10:33 PM PDT 24
Peak memory 195600 kb
Host smart-44ba034c-150e-4bce-a54f-08efcba88eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832873266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3832873266
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.610853440
Short name T183
Test name
Test status
Simulation time 3154876805 ps
CPU time 92.09 seconds
Started Jul 31 07:10:33 PM PDT 24
Finished Jul 31 07:12:05 PM PDT 24
Peak memory 200048 kb
Host smart-660efa84-70ff-4234-a366-40abd309eef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=610853440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.610853440
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3257104865
Short name T386
Test name
Test status
Simulation time 2139880187 ps
CPU time 26.72 seconds
Started Jul 31 07:10:34 PM PDT 24
Finished Jul 31 07:11:01 PM PDT 24
Peak memory 200044 kb
Host smart-1410c173-350d-4a6b-b256-4ec4fb8b2c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257104865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3257104865
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2907469257
Short name T390
Test name
Test status
Simulation time 4184027514 ps
CPU time 532.87 seconds
Started Jul 31 07:10:37 PM PDT 24
Finished Jul 31 07:19:30 PM PDT 24
Peak memory 695024 kb
Host smart-16dc3f83-ef9f-49d3-aa8a-bc8f064c859c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2907469257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2907469257
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.4175630278
Short name T441
Test name
Test status
Simulation time 3358730352 ps
CPU time 60.22 seconds
Started Jul 31 07:10:34 PM PDT 24
Finished Jul 31 07:11:34 PM PDT 24
Peak memory 199972 kb
Host smart-57a5770b-191f-4cf1-a3f0-f75082246752
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175630278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4175630278
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.820114075
Short name T171
Test name
Test status
Simulation time 180188168209 ps
CPU time 156.58 seconds
Started Jul 31 07:10:34 PM PDT 24
Finished Jul 31 07:13:11 PM PDT 24
Peak memory 216452 kb
Host smart-f7968289-8c7c-486d-bdaa-df707d11f11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820114075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.820114075
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1311621148
Short name T445
Test name
Test status
Simulation time 724302180 ps
CPU time 5.79 seconds
Started Jul 31 07:10:33 PM PDT 24
Finished Jul 31 07:10:39 PM PDT 24
Peak memory 200052 kb
Host smart-b83936bf-9e2c-4095-88f0-6d9dc267cabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311621148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1311621148
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.4088520409
Short name T421
Test name
Test status
Simulation time 2784544196 ps
CPU time 149.16 seconds
Started Jul 31 07:10:35 PM PDT 24
Finished Jul 31 07:13:04 PM PDT 24
Peak memory 200112 kb
Host smart-7f2d5bdf-f4a4-4d41-acc6-123d65fbc16a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088520409 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.4088520409
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1116670455
Short name T352
Test name
Test status
Simulation time 1242363367 ps
CPU time 63.89 seconds
Started Jul 31 07:10:35 PM PDT 24
Finished Jul 31 07:11:39 PM PDT 24
Peak memory 199988 kb
Host smart-3ac5227a-4090-45af-a961-3d7186bbf126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116670455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1116670455
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1772759713
Short name T265
Test name
Test status
Simulation time 36612567 ps
CPU time 0.6 seconds
Started Jul 31 07:10:35 PM PDT 24
Finished Jul 31 07:10:35 PM PDT 24
Peak memory 196696 kb
Host smart-f276fa30-e1a5-4484-a609-e5336cd7265e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772759713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1772759713
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3870505192
Short name T447
Test name
Test status
Simulation time 1042050320 ps
CPU time 59.35 seconds
Started Jul 31 07:10:33 PM PDT 24
Finished Jul 31 07:11:33 PM PDT 24
Peak memory 199908 kb
Host smart-474700e8-7305-4f60-b5c4-c63fa316d8da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870505192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3870505192
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3978210149
Short name T308
Test name
Test status
Simulation time 86697516 ps
CPU time 4.58 seconds
Started Jul 31 07:10:34 PM PDT 24
Finished Jul 31 07:10:39 PM PDT 24
Peak memory 199888 kb
Host smart-c4e77b90-4635-41d6-8e14-2aeb29491f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978210149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3978210149
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.103247281
Short name T66
Test name
Test status
Simulation time 23631677979 ps
CPU time 1225.34 seconds
Started Jul 31 07:10:33 PM PDT 24
Finished Jul 31 07:30:58 PM PDT 24
Peak memory 736028 kb
Host smart-95b804c8-c470-4643-a263-5d3c655cc28d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103247281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.103247281
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.238329718
Short name T382
Test name
Test status
Simulation time 2288202384 ps
CPU time 126.81 seconds
Started Jul 31 07:10:31 PM PDT 24
Finished Jul 31 07:12:38 PM PDT 24
Peak memory 199936 kb
Host smart-7883b52f-4387-4d22-9aa4-ac7011f17f74
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238329718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.238329718
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2473762583
Short name T260
Test name
Test status
Simulation time 23556184508 ps
CPU time 100.41 seconds
Started Jul 31 07:10:33 PM PDT 24
Finished Jul 31 07:12:13 PM PDT 24
Peak memory 200116 kb
Host smart-74d63301-618f-4cae-a70d-15ff7b259d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473762583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2473762583
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1079324790
Short name T179
Test name
Test status
Simulation time 497227803 ps
CPU time 11.28 seconds
Started Jul 31 07:10:38 PM PDT 24
Finished Jul 31 07:10:49 PM PDT 24
Peak memory 199832 kb
Host smart-1000dd17-49dd-421e-b441-6172076aa575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079324790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1079324790
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1144274737
Short name T486
Test name
Test status
Simulation time 13543147186 ps
CPU time 325.51 seconds
Started Jul 31 07:10:32 PM PDT 24
Finished Jul 31 07:15:57 PM PDT 24
Peak memory 200004 kb
Host smart-04a0c9f3-0cae-4630-bb1f-9d4bc6868e86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144274737 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1144274737
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1535275795
Short name T419
Test name
Test status
Simulation time 4645938541 ps
CPU time 81.1 seconds
Started Jul 31 07:10:34 PM PDT 24
Finished Jul 31 07:11:56 PM PDT 24
Peak memory 200012 kb
Host smart-9a89bf04-d6ed-4ba5-9e32-592993b6ac97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535275795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1535275795
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.515914515
Short name T494
Test name
Test status
Simulation time 39552403 ps
CPU time 0.58 seconds
Started Jul 31 07:07:19 PM PDT 24
Finished Jul 31 07:07:20 PM PDT 24
Peak memory 194956 kb
Host smart-f64e367e-b935-41c8-80e0-46dd47af504a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515914515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.515914515
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.539914727
Short name T341
Test name
Test status
Simulation time 2356347781 ps
CPU time 33.33 seconds
Started Jul 31 07:06:51 PM PDT 24
Finished Jul 31 07:07:25 PM PDT 24
Peak memory 200132 kb
Host smart-bfd122f7-f853-4179-bd09-686a80929b9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=539914727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.539914727
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.4136879929
Short name T147
Test name
Test status
Simulation time 1860785022 ps
CPU time 76.25 seconds
Started Jul 31 07:06:52 PM PDT 24
Finished Jul 31 07:08:08 PM PDT 24
Peak memory 199908 kb
Host smart-5369d84f-657e-43e9-8224-98517586a429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136879929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.4136879929
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2479316862
Short name T285
Test name
Test status
Simulation time 3452339266 ps
CPU time 176.21 seconds
Started Jul 31 07:06:52 PM PDT 24
Finished Jul 31 07:09:48 PM PDT 24
Peak memory 379024 kb
Host smart-060b0393-abc3-4e82-bdb0-94b726ca7148
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2479316862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2479316862
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.441042296
Short name T254
Test name
Test status
Simulation time 236310573 ps
CPU time 3.59 seconds
Started Jul 31 07:06:51 PM PDT 24
Finished Jul 31 07:06:55 PM PDT 24
Peak memory 199844 kb
Host smart-6fc7aa58-babc-4bb2-a51d-93a2dcd65845
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441042296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.441042296
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2655800799
Short name T455
Test name
Test status
Simulation time 1634359713 ps
CPU time 94.03 seconds
Started Jul 31 07:06:48 PM PDT 24
Finished Jul 31 07:08:22 PM PDT 24
Peak memory 199900 kb
Host smart-fedc0d14-3f1c-40e4-b6ce-7fe1904693b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655800799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2655800799
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2824629559
Short name T57
Test name
Test status
Simulation time 198321552 ps
CPU time 0.92 seconds
Started Jul 31 07:07:18 PM PDT 24
Finished Jul 31 07:07:19 PM PDT 24
Peak memory 218484 kb
Host smart-d53ff1a9-460d-4236-8498-3ccc962e8df3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824629559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2824629559
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3696448273
Short name T220
Test name
Test status
Simulation time 847226032 ps
CPU time 9.17 seconds
Started Jul 31 07:06:47 PM PDT 24
Finished Jul 31 07:06:57 PM PDT 24
Peak memory 199936 kb
Host smart-c0c161a0-2c1a-48f9-8404-035b8da25b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696448273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3696448273
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2379507763
Short name T77
Test name
Test status
Simulation time 56445592881 ps
CPU time 739.54 seconds
Started Jul 31 07:06:58 PM PDT 24
Finished Jul 31 07:19:18 PM PDT 24
Peak memory 200144 kb
Host smart-7739b45e-d39a-472d-b81b-b7d1d1e15a65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379507763 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2379507763
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2256800228
Short name T71
Test name
Test status
Simulation time 77843355518 ps
CPU time 1445.88 seconds
Started Jul 31 07:07:03 PM PDT 24
Finished Jul 31 07:31:09 PM PDT 24
Peak memory 646484 kb
Host smart-e634b7e5-c5c6-4858-a816-efea59fb3d09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256800228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2256800228
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3533887186
Short name T30
Test name
Test status
Simulation time 9782697970 ps
CPU time 81.09 seconds
Started Jul 31 07:06:52 PM PDT 24
Finished Jul 31 07:08:13 PM PDT 24
Peak memory 200024 kb
Host smart-eda3d667-e4ed-4fa7-9063-b15dd130a903
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3533887186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3533887186
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1655920407
Short name T49
Test name
Test status
Simulation time 5332526440 ps
CPU time 89.54 seconds
Started Jul 31 07:06:51 PM PDT 24
Finished Jul 31 07:08:21 PM PDT 24
Peak memory 200032 kb
Host smart-c0bd4a87-3827-4a5f-b34a-8997b2cde9aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1655920407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1655920407
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3957998826
Short name T295
Test name
Test status
Simulation time 8686716400 ps
CPU time 125.46 seconds
Started Jul 31 07:06:59 PM PDT 24
Finished Jul 31 07:09:05 PM PDT 24
Peak memory 200084 kb
Host smart-8e6709be-df3e-459f-b7b3-aa55dccbe5dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3957998826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3957998826
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1591744778
Short name T61
Test name
Test status
Simulation time 54930754401 ps
CPU time 632.66 seconds
Started Jul 31 07:06:56 PM PDT 24
Finished Jul 31 07:17:29 PM PDT 24
Peak memory 200000 kb
Host smart-bc94cc41-d306-40e4-bd90-a456da93ea3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1591744778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1591744778
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3165304535
Short name T226
Test name
Test status
Simulation time 832343670544 ps
CPU time 2665.78 seconds
Started Jul 31 07:06:51 PM PDT 24
Finished Jul 31 07:51:18 PM PDT 24
Peak memory 215620 kb
Host smart-292dbb68-fccd-4454-bec7-92893f4577d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3165304535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3165304535
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3786387951
Short name T253
Test name
Test status
Simulation time 38450434696 ps
CPU time 2171.1 seconds
Started Jul 31 07:06:50 PM PDT 24
Finished Jul 31 07:43:02 PM PDT 24
Peak memory 215660 kb
Host smart-d4e4dea6-9e55-47da-912a-4fe0cf520812
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3786387951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3786387951
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1350517341
Short name T310
Test name
Test status
Simulation time 6698405664 ps
CPU time 31.84 seconds
Started Jul 31 07:06:51 PM PDT 24
Finished Jul 31 07:07:23 PM PDT 24
Peak memory 200040 kb
Host smart-b97b1388-cbe7-46be-af2a-7b09a6b4681d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350517341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1350517341
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2570512357
Short name T280
Test name
Test status
Simulation time 46647102 ps
CPU time 0.58 seconds
Started Jul 31 07:10:43 PM PDT 24
Finished Jul 31 07:10:43 PM PDT 24
Peak memory 195560 kb
Host smart-171793ed-3e43-467f-9161-b671bd776cd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570512357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2570512357
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3243311170
Short name T205
Test name
Test status
Simulation time 1331718136 ps
CPU time 37.64 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:11:21 PM PDT 24
Peak memory 199876 kb
Host smart-67307492-d03f-49dc-abf3-2e413aadcc6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3243311170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3243311170
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.521766801
Short name T449
Test name
Test status
Simulation time 3790810448 ps
CPU time 45.53 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:11:30 PM PDT 24
Peak memory 200016 kb
Host smart-20cbd9e3-f5d0-497d-878b-3e38d486ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521766801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.521766801
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.211700131
Short name T219
Test name
Test status
Simulation time 3286904630 ps
CPU time 520.7 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:19:26 PM PDT 24
Peak memory 682008 kb
Host smart-f0a6718f-acb4-4437-bf0d-4350ee79c413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211700131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.211700131
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3536944405
Short name T287
Test name
Test status
Simulation time 6436513466 ps
CPU time 118.23 seconds
Started Jul 31 07:10:46 PM PDT 24
Finished Jul 31 07:12:44 PM PDT 24
Peak memory 199968 kb
Host smart-50709d53-4fad-46c6-b3a5-aea3f8f66d4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536944405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3536944405
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1477115273
Short name T195
Test name
Test status
Simulation time 9384994590 ps
CPU time 68.04 seconds
Started Jul 31 07:10:43 PM PDT 24
Finished Jul 31 07:11:51 PM PDT 24
Peak memory 199992 kb
Host smart-d7a6d566-e7b5-4723-ad60-04997bb7ef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477115273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1477115273
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4033914635
Short name T225
Test name
Test status
Simulation time 996177658 ps
CPU time 12.11 seconds
Started Jul 31 07:10:33 PM PDT 24
Finished Jul 31 07:10:46 PM PDT 24
Peak memory 199964 kb
Host smart-d71db65e-12bc-406c-9640-bac302aec0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033914635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4033914635
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2917577345
Short name T236
Test name
Test status
Simulation time 32778671925 ps
CPU time 4812.25 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 08:30:59 PM PDT 24
Peak memory 864776 kb
Host smart-39159894-847b-4a27-b445-9f5877251217
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917577345 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2917577345
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3168818354
Short name T470
Test name
Test status
Simulation time 4600751717 ps
CPU time 36.56 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:11:21 PM PDT 24
Peak memory 200024 kb
Host smart-13403e62-4d88-4453-baf3-64037da990a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168818354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3168818354
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.449193009
Short name T326
Test name
Test status
Simulation time 12797672 ps
CPU time 0.59 seconds
Started Jul 31 07:10:46 PM PDT 24
Finished Jul 31 07:10:47 PM PDT 24
Peak memory 195968 kb
Host smart-c2158d81-9d4c-4998-8133-16af29890b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449193009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.449193009
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1296838312
Short name T433
Test name
Test status
Simulation time 2561190663 ps
CPU time 35.61 seconds
Started Jul 31 07:10:43 PM PDT 24
Finished Jul 31 07:11:19 PM PDT 24
Peak memory 200032 kb
Host smart-7e54c493-582f-4735-a776-2e3224380882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296838312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1296838312
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1899994806
Short name T504
Test name
Test status
Simulation time 5324614592 ps
CPU time 45.26 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:11:29 PM PDT 24
Peak memory 199984 kb
Host smart-674e6113-76a3-4537-a21f-ff22d5c98309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899994806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1899994806
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2161620355
Short name T347
Test name
Test status
Simulation time 12156324099 ps
CPU time 1159.25 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:30:04 PM PDT 24
Peak memory 728388 kb
Host smart-b10c6574-0077-47b2-88d5-159a2ab212cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161620355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2161620355
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1318741310
Short name T351
Test name
Test status
Simulation time 7047424702 ps
CPU time 185.35 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:13:49 PM PDT 24
Peak memory 199976 kb
Host smart-0f7f473e-afe7-4eb2-9a87-481e73d98257
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318741310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1318741310
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3982655121
Short name T289
Test name
Test status
Simulation time 272744891 ps
CPU time 14.92 seconds
Started Jul 31 07:10:46 PM PDT 24
Finished Jul 31 07:11:01 PM PDT 24
Peak memory 199896 kb
Host smart-022fdbaa-f126-49b7-bfa0-b2b183e9ceaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982655121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3982655121
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3259350438
Short name T198
Test name
Test status
Simulation time 1366127959 ps
CPU time 15.34 seconds
Started Jul 31 07:10:43 PM PDT 24
Finished Jul 31 07:10:58 PM PDT 24
Peak memory 199912 kb
Host smart-c28cadaa-e9ee-4c5f-944d-ef61b7894e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259350438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3259350438
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.353193919
Short name T451
Test name
Test status
Simulation time 251000153899 ps
CPU time 4068.31 seconds
Started Jul 31 07:10:46 PM PDT 24
Finished Jul 31 08:18:35 PM PDT 24
Peak memory 822880 kb
Host smart-fc1fc684-813f-4554-84a0-0f7001dbd9bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353193919 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.353193919
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2016750411
Short name T85
Test name
Test status
Simulation time 3686269774 ps
CPU time 47.48 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:11:32 PM PDT 24
Peak memory 199960 kb
Host smart-cf0568ca-21a0-4f6d-a084-7462294ce63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016750411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2016750411
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2919167275
Short name T184
Test name
Test status
Simulation time 139172019 ps
CPU time 0.58 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:10:46 PM PDT 24
Peak memory 195984 kb
Host smart-5b77b7fa-c005-4bc3-9f57-05e140eb076f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919167275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2919167275
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1108847586
Short name T177
Test name
Test status
Simulation time 592534469 ps
CPU time 33.84 seconds
Started Jul 31 07:10:46 PM PDT 24
Finished Jul 31 07:11:19 PM PDT 24
Peak memory 199900 kb
Host smart-413d12b4-585f-43c5-b8dd-3301770a182a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108847586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1108847586
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3099254584
Short name T325
Test name
Test status
Simulation time 2746195008 ps
CPU time 60.22 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:11:45 PM PDT 24
Peak memory 199960 kb
Host smart-cb09a3cf-0c2a-4e3d-b9bd-457fa6a7f254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099254584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3099254584
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.4051611240
Short name T465
Test name
Test status
Simulation time 11997218360 ps
CPU time 1243.68 seconds
Started Jul 31 07:10:43 PM PDT 24
Finished Jul 31 07:31:27 PM PDT 24
Peak memory 687340 kb
Host smart-5254e04e-8b57-43a2-adf5-c1d8ea876a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051611240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.4051611240
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2165342856
Short name T229
Test name
Test status
Simulation time 17566404419 ps
CPU time 224.53 seconds
Started Jul 31 07:10:46 PM PDT 24
Finished Jul 31 07:14:31 PM PDT 24
Peak memory 200036 kb
Host smart-eee10257-8f1b-41af-a71d-45c1420552c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165342856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2165342856
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3993603294
Short name T435
Test name
Test status
Simulation time 2123038001 ps
CPU time 34.39 seconds
Started Jul 31 07:10:43 PM PDT 24
Finished Jul 31 07:11:18 PM PDT 24
Peak memory 199824 kb
Host smart-2a15ddf6-6345-4200-b4d6-d3edebea634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993603294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3993603294
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1657639377
Short name T322
Test name
Test status
Simulation time 875203408 ps
CPU time 7.75 seconds
Started Jul 31 07:10:47 PM PDT 24
Finished Jul 31 07:10:55 PM PDT 24
Peak memory 199840 kb
Host smart-e3ebc44d-80ad-4a91-b2b9-5568e9371400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657639377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1657639377
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1173626374
Short name T122
Test name
Test status
Simulation time 131546985482 ps
CPU time 822 seconds
Started Jul 31 07:10:48 PM PDT 24
Finished Jul 31 07:24:30 PM PDT 24
Peak memory 208308 kb
Host smart-e72ef828-9c26-403c-8bd7-0c43adf5deee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173626374 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1173626374
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1266248019
Short name T249
Test name
Test status
Simulation time 122880404450 ps
CPU time 124.61 seconds
Started Jul 31 07:10:43 PM PDT 24
Finished Jul 31 07:12:48 PM PDT 24
Peak memory 200040 kb
Host smart-2a6fd8d2-7c09-432a-ad97-33b02f115113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266248019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1266248019
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.4087705539
Short name T194
Test name
Test status
Simulation time 19786728 ps
CPU time 0.59 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:10:46 PM PDT 24
Peak memory 195984 kb
Host smart-f47d533f-f5c0-41ca-957c-89bffd405ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087705539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4087705539
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2162048912
Short name T521
Test name
Test status
Simulation time 911159524 ps
CPU time 12.52 seconds
Started Jul 31 07:10:48 PM PDT 24
Finished Jul 31 07:11:00 PM PDT 24
Peak memory 199828 kb
Host smart-890397a0-5116-4fa9-bcf8-6f7df9f2cf11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162048912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2162048912
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1835559953
Short name T150
Test name
Test status
Simulation time 479437845 ps
CPU time 6.91 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:10:52 PM PDT 24
Peak memory 199912 kb
Host smart-21043b7b-fd93-444f-a6e6-da03c88bed6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835559953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1835559953
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.72302740
Short name T272
Test name
Test status
Simulation time 21172066303 ps
CPU time 963.83 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:26:49 PM PDT 24
Peak memory 715224 kb
Host smart-5bb840de-e97e-48ee-ab35-4ef714b8ad33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72302740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.72302740
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1101573760
Short name T149
Test name
Test status
Simulation time 21454945 ps
CPU time 0.67 seconds
Started Jul 31 07:10:43 PM PDT 24
Finished Jul 31 07:10:44 PM PDT 24
Peak memory 196432 kb
Host smart-23f72fec-8f28-47de-a91f-8f610636ee43
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101573760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1101573760
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2099789013
Short name T258
Test name
Test status
Simulation time 19325411967 ps
CPU time 47.16 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:11:32 PM PDT 24
Peak memory 200076 kb
Host smart-ee1bbcd7-a118-4451-add7-7918406af87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099789013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2099789013
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2168993519
Short name T201
Test name
Test status
Simulation time 67934058 ps
CPU time 2.94 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:10:47 PM PDT 24
Peak memory 199936 kb
Host smart-55d19986-907f-4b39-ae9c-a8bb8d166fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168993519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2168993519
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.4232705445
Short name T301
Test name
Test status
Simulation time 360019575637 ps
CPU time 2550.08 seconds
Started Jul 31 07:10:47 PM PDT 24
Finished Jul 31 07:53:18 PM PDT 24
Peak memory 771344 kb
Host smart-650b9a39-4dd4-4e24-a7f8-9b144427c4b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232705445 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.4232705445
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3282335851
Short name T495
Test name
Test status
Simulation time 81833973111 ps
CPU time 115.48 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:12:40 PM PDT 24
Peak memory 200120 kb
Host smart-fca99a78-e883-49fc-88fd-fd6f5d9d9b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282335851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3282335851
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2728673187
Short name T387
Test name
Test status
Simulation time 35215108 ps
CPU time 0.58 seconds
Started Jul 31 07:10:42 PM PDT 24
Finished Jul 31 07:10:43 PM PDT 24
Peak memory 196652 kb
Host smart-37c33496-8b80-4c70-9aae-8ba0167cf6ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728673187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2728673187
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2784429409
Short name T9
Test name
Test status
Simulation time 1301853909 ps
CPU time 38.57 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:11:23 PM PDT 24
Peak memory 199960 kb
Host smart-d5e51545-1f6a-40aa-959d-6da3f21528ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784429409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2784429409
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.232848100
Short name T405
Test name
Test status
Simulation time 9336154900 ps
CPU time 16.65 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:11:02 PM PDT 24
Peak memory 200048 kb
Host smart-adcf9b00-cad0-4921-81da-e2978cb41c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232848100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.232848100
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3242333645
Short name T93
Test name
Test status
Simulation time 563223789 ps
CPU time 10.4 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:10:55 PM PDT 24
Peak memory 216348 kb
Host smart-14cb9430-8661-4326-a51f-7d071cc0424d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3242333645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3242333645
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.299251077
Short name T524
Test name
Test status
Simulation time 41489435779 ps
CPU time 117 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:12:42 PM PDT 24
Peak memory 200044 kb
Host smart-d0af58de-b3b5-4bef-b48c-1e35b763898a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299251077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.299251077
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2605058465
Short name T364
Test name
Test status
Simulation time 5557253663 ps
CPU time 159.58 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:13:24 PM PDT 24
Peak memory 200000 kb
Host smart-d5115fd3-de39-4dfd-95f8-f3ff0abea903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605058465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2605058465
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1815213203
Short name T164
Test name
Test status
Simulation time 607803031 ps
CPU time 14.1 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:10:59 PM PDT 24
Peak memory 199924 kb
Host smart-5dc164d0-240d-47d0-8cee-d3a3ef301012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815213203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1815213203
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1752872827
Short name T472
Test name
Test status
Simulation time 29329703531 ps
CPU time 786.77 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:23:52 PM PDT 24
Peak memory 216408 kb
Host smart-e68380b0-8072-433d-970c-b0fd30759865
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752872827 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1752872827
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2112810494
Short name T255
Test name
Test status
Simulation time 8746355627 ps
CPU time 116.36 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:12:41 PM PDT 24
Peak memory 200060 kb
Host smart-aa9108af-5b10-4ea3-a54d-c8def6fade5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112810494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2112810494
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1075925619
Short name T459
Test name
Test status
Simulation time 59477996 ps
CPU time 0.59 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:10:45 PM PDT 24
Peak memory 196676 kb
Host smart-5d1da0b7-3f1a-4f43-af30-18c548299ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075925619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1075925619
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3530138061
Short name T393
Test name
Test status
Simulation time 707468249 ps
CPU time 37.29 seconds
Started Jul 31 07:10:46 PM PDT 24
Finished Jul 31 07:11:23 PM PDT 24
Peak memory 199860 kb
Host smart-43d4972c-c110-48f0-afe0-580984b97378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3530138061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3530138061
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1214788666
Short name T337
Test name
Test status
Simulation time 823800723 ps
CPU time 11.17 seconds
Started Jul 31 07:10:43 PM PDT 24
Finished Jul 31 07:10:54 PM PDT 24
Peak memory 199864 kb
Host smart-eb75cce2-7053-4517-8137-1faef9eb012d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214788666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1214788666
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1840394742
Short name T279
Test name
Test status
Simulation time 13603541916 ps
CPU time 769.19 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:23:35 PM PDT 24
Peak memory 670456 kb
Host smart-fd39af44-a681-4a85-8ccb-a5409211bd3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840394742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1840394742
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.878074562
Short name T211
Test name
Test status
Simulation time 1055622268 ps
CPU time 4.66 seconds
Started Jul 31 07:10:44 PM PDT 24
Finished Jul 31 07:10:48 PM PDT 24
Peak memory 199896 kb
Host smart-1e77b358-8d80-45f3-818f-791007dcae60
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878074562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.878074562
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2250891009
Short name T488
Test name
Test status
Simulation time 12082373063 ps
CPU time 91.22 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:12:16 PM PDT 24
Peak memory 216252 kb
Host smart-c4e961b0-4d38-4e66-aa2c-065159406cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250891009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2250891009
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.492751795
Short name T448
Test name
Test status
Simulation time 190520678 ps
CPU time 8.85 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:10:54 PM PDT 24
Peak memory 199916 kb
Host smart-56576eec-045c-4d8e-b23a-3021981cd8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492751795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.492751795
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.946930455
Short name T395
Test name
Test status
Simulation time 28207392119 ps
CPU time 495.22 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:19:01 PM PDT 24
Peak memory 216332 kb
Host smart-d252ad9b-2129-4e47-a4ac-cbde199ba4e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946930455 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.946930455
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1031425559
Short name T379
Test name
Test status
Simulation time 930643988 ps
CPU time 12.86 seconds
Started Jul 31 07:10:45 PM PDT 24
Finished Jul 31 07:10:58 PM PDT 24
Peak memory 199948 kb
Host smart-bf1ec7ec-71be-450e-8617-3837cc35ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031425559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1031425559
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1640070957
Short name T172
Test name
Test status
Simulation time 13042384 ps
CPU time 0.58 seconds
Started Jul 31 07:10:52 PM PDT 24
Finished Jul 31 07:10:53 PM PDT 24
Peak memory 195968 kb
Host smart-1555cf6f-3c64-403e-8310-0c4b22c13f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640070957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1640070957
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2584332340
Short name T383
Test name
Test status
Simulation time 4778762881 ps
CPU time 69.1 seconds
Started Jul 31 07:10:48 PM PDT 24
Finished Jul 31 07:11:57 PM PDT 24
Peak memory 200160 kb
Host smart-c8639725-0e33-479d-bd50-e33e4a7b9261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584332340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2584332340
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.827740560
Short name T468
Test name
Test status
Simulation time 2756792881 ps
CPU time 45.59 seconds
Started Jul 31 07:10:51 PM PDT 24
Finished Jul 31 07:11:36 PM PDT 24
Peak memory 200016 kb
Host smart-281bd7ac-900a-468a-8ce8-19f4a7e7092b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827740560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.827740560
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3905896545
Short name T214
Test name
Test status
Simulation time 20144842579 ps
CPU time 656.18 seconds
Started Jul 31 07:10:53 PM PDT 24
Finished Jul 31 07:21:49 PM PDT 24
Peak memory 702760 kb
Host smart-a6fbab8d-11c6-450e-8150-218bd1e8bd52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905896545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3905896545
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.4091618568
Short name T248
Test name
Test status
Simulation time 12222936566 ps
CPU time 128.24 seconds
Started Jul 31 07:10:54 PM PDT 24
Finished Jul 31 07:13:02 PM PDT 24
Peak memory 200040 kb
Host smart-b9d558c0-7d08-4d23-8784-910517d4158e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091618568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4091618568
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1719757672
Short name T158
Test name
Test status
Simulation time 94389655338 ps
CPU time 85.44 seconds
Started Jul 31 07:10:46 PM PDT 24
Finished Jul 31 07:12:11 PM PDT 24
Peak memory 200040 kb
Host smart-079af6ff-49bf-4e5b-bb83-89d82b93b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719757672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1719757672
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3626478375
Short name T162
Test name
Test status
Simulation time 783771013 ps
CPU time 9.97 seconds
Started Jul 31 07:10:46 PM PDT 24
Finished Jul 31 07:10:56 PM PDT 24
Peak memory 199920 kb
Host smart-ee07ee5e-f6c6-4a84-94aa-6158213ae945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626478375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3626478375
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2183274940
Short name T276
Test name
Test status
Simulation time 43242157667 ps
CPU time 498.71 seconds
Started Jul 31 07:10:54 PM PDT 24
Finished Jul 31 07:19:12 PM PDT 24
Peak memory 216488 kb
Host smart-0b9ce63b-1d12-4b74-a006-723d4f736735
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183274940 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2183274940
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2127964630
Short name T491
Test name
Test status
Simulation time 33479226764 ps
CPU time 101.34 seconds
Started Jul 31 07:10:54 PM PDT 24
Finished Jul 31 07:12:36 PM PDT 24
Peak memory 199972 kb
Host smart-cb6396da-93f3-439e-8d64-68750f05e5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127964630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2127964630
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.569763536
Short name T65
Test name
Test status
Simulation time 15156472 ps
CPU time 0.58 seconds
Started Jul 31 07:10:58 PM PDT 24
Finished Jul 31 07:10:59 PM PDT 24
Peak memory 195004 kb
Host smart-58e4eb97-8cbb-45f2-b117-e51bdc9a25ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569763536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.569763536
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2729461419
Short name T228
Test name
Test status
Simulation time 18984789 ps
CPU time 1.07 seconds
Started Jul 31 07:10:51 PM PDT 24
Finished Jul 31 07:10:52 PM PDT 24
Peak memory 199840 kb
Host smart-8bc1a2b1-77bf-4e78-8eb2-a841199661b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729461419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2729461419
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.86097005
Short name T146
Test name
Test status
Simulation time 1011316525 ps
CPU time 26.4 seconds
Started Jul 31 07:10:55 PM PDT 24
Finished Jul 31 07:11:22 PM PDT 24
Peak memory 199952 kb
Host smart-e331ddfd-0fa5-46d5-bafd-2b027e16ee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86097005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.86097005
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1911648758
Short name T35
Test name
Test status
Simulation time 9247938317 ps
CPU time 1753.49 seconds
Started Jul 31 07:10:54 PM PDT 24
Finished Jul 31 07:40:07 PM PDT 24
Peak memory 764360 kb
Host smart-07d91ae1-a580-432d-8ab4-1b883a2e653d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911648758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1911648758
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3363253804
Short name T151
Test name
Test status
Simulation time 4716347178 ps
CPU time 130.93 seconds
Started Jul 31 07:10:51 PM PDT 24
Finished Jul 31 07:13:02 PM PDT 24
Peak memory 200000 kb
Host smart-bbe4582f-f250-4f8d-a033-14719af3facb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363253804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3363253804
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.374334299
Short name T482
Test name
Test status
Simulation time 1422369582 ps
CPU time 40.73 seconds
Started Jul 31 07:10:50 PM PDT 24
Finished Jul 31 07:11:31 PM PDT 24
Peak memory 199944 kb
Host smart-7fb9e530-fb0b-40e5-8f90-47f39d0aa6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374334299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.374334299
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2937970345
Short name T342
Test name
Test status
Simulation time 864564529 ps
CPU time 7.77 seconds
Started Jul 31 07:10:55 PM PDT 24
Finished Jul 31 07:11:03 PM PDT 24
Peak memory 199920 kb
Host smart-0ee0afec-c4e3-4a71-a972-c657fd63e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937970345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2937970345
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1884595819
Short name T512
Test name
Test status
Simulation time 29598127999 ps
CPU time 92.92 seconds
Started Jul 31 07:10:55 PM PDT 24
Finished Jul 31 07:12:28 PM PDT 24
Peak memory 200052 kb
Host smart-505094a5-6c53-4ec9-a976-c81effbe5e3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884595819 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1884595819
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.730418205
Short name T368
Test name
Test status
Simulation time 14512041315 ps
CPU time 24.11 seconds
Started Jul 31 07:10:54 PM PDT 24
Finished Jul 31 07:11:19 PM PDT 24
Peak memory 199976 kb
Host smart-dec0ad3e-e23a-4cbf-98e0-50156e49fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730418205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.730418205
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.4149660964
Short name T224
Test name
Test status
Simulation time 13755203 ps
CPU time 0.57 seconds
Started Jul 31 07:11:08 PM PDT 24
Finished Jul 31 07:11:09 PM PDT 24
Peak memory 195668 kb
Host smart-7c760b24-5662-4c90-a9dd-8989c6e4dfbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149660964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.4149660964
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.507761709
Short name T380
Test name
Test status
Simulation time 1599982523 ps
CPU time 85.2 seconds
Started Jul 31 07:11:01 PM PDT 24
Finished Jul 31 07:12:27 PM PDT 24
Peak memory 200012 kb
Host smart-949d3fdb-1651-4181-bd35-4eb29b65e08f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=507761709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.507761709
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2848778594
Short name T431
Test name
Test status
Simulation time 637645109 ps
CPU time 33.39 seconds
Started Jul 31 07:10:59 PM PDT 24
Finished Jul 31 07:11:32 PM PDT 24
Peak memory 199952 kb
Host smart-83dc59d1-e35b-4f14-b596-62230a4d27f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848778594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2848778594
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2038815786
Short name T180
Test name
Test status
Simulation time 6881749650 ps
CPU time 713.23 seconds
Started Jul 31 07:10:59 PM PDT 24
Finished Jul 31 07:22:52 PM PDT 24
Peak memory 653456 kb
Host smart-8bc91373-3bc1-4a3e-b35a-f47c0d3ff208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038815786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2038815786
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.413700736
Short name T318
Test name
Test status
Simulation time 3197017059 ps
CPU time 90.14 seconds
Started Jul 31 07:10:57 PM PDT 24
Finished Jul 31 07:12:28 PM PDT 24
Peak memory 200000 kb
Host smart-28483fa2-a95c-4fee-9dc4-327efbdae862
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413700736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.413700736
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.4266112051
Short name T181
Test name
Test status
Simulation time 9281171540 ps
CPU time 98.71 seconds
Started Jul 31 07:10:58 PM PDT 24
Finished Jul 31 07:12:36 PM PDT 24
Peak memory 200036 kb
Host smart-840f9a4a-fb58-4664-9bd4-429cde06d125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266112051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.4266112051
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3754733772
Short name T176
Test name
Test status
Simulation time 2381825522 ps
CPU time 7.45 seconds
Started Jul 31 07:10:58 PM PDT 24
Finished Jul 31 07:11:05 PM PDT 24
Peak memory 200120 kb
Host smart-78c1d5de-900b-482f-ac49-20086daf4a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754733772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3754733772
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2700437420
Short name T18
Test name
Test status
Simulation time 39156118855 ps
CPU time 527.19 seconds
Started Jul 31 07:11:06 PM PDT 24
Finished Jul 31 07:19:53 PM PDT 24
Peak memory 200048 kb
Host smart-283eb948-71ee-43ad-8b61-1f8a37af7350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700437420 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2700437420
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1341539030
Short name T490
Test name
Test status
Simulation time 6651608290 ps
CPU time 32.58 seconds
Started Jul 31 07:10:56 PM PDT 24
Finished Jul 31 07:11:29 PM PDT 24
Peak memory 200028 kb
Host smart-1ace16f2-ef4a-4015-8cca-f452c356cdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341539030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1341539030
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3715033081
Short name T277
Test name
Test status
Simulation time 25862613 ps
CPU time 0.63 seconds
Started Jul 31 07:11:14 PM PDT 24
Finished Jul 31 07:11:15 PM PDT 24
Peak memory 195976 kb
Host smart-fca5c092-b4c8-45a4-b13a-af9d64f8a9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715033081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3715033081
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.518566541
Short name T307
Test name
Test status
Simulation time 4559923000 ps
CPU time 71.06 seconds
Started Jul 31 07:11:07 PM PDT 24
Finished Jul 31 07:12:18 PM PDT 24
Peak memory 200036 kb
Host smart-f0d00fa5-b418-461b-8df2-56917235662a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518566541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.518566541
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3219672366
Short name T401
Test name
Test status
Simulation time 3802929070 ps
CPU time 49.07 seconds
Started Jul 31 07:11:17 PM PDT 24
Finished Jul 31 07:12:06 PM PDT 24
Peak memory 215784 kb
Host smart-c5be6dba-eb59-4a88-883e-b87c4e0125fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219672366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3219672366
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2675175541
Short name T361
Test name
Test status
Simulation time 4662969807 ps
CPU time 973.51 seconds
Started Jul 31 07:11:05 PM PDT 24
Finished Jul 31 07:27:19 PM PDT 24
Peak memory 764736 kb
Host smart-427e1f6e-4e0c-470a-a9ac-fe554e26d426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675175541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2675175541
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3896153652
Short name T31
Test name
Test status
Simulation time 11418456624 ps
CPU time 199.61 seconds
Started Jul 31 07:11:13 PM PDT 24
Finished Jul 31 07:14:33 PM PDT 24
Peak memory 200092 kb
Host smart-0021ea26-82f4-46d8-9e77-15a434a175a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896153652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3896153652
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2792595294
Short name T531
Test name
Test status
Simulation time 1127796291 ps
CPU time 62.75 seconds
Started Jul 31 07:11:05 PM PDT 24
Finished Jul 31 07:12:08 PM PDT 24
Peak memory 200004 kb
Host smart-561f5d43-dba2-445b-866a-06ab1b4d52f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792595294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2792595294
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3876476569
Short name T343
Test name
Test status
Simulation time 1601118674 ps
CPU time 9.64 seconds
Started Jul 31 07:11:06 PM PDT 24
Finished Jul 31 07:11:15 PM PDT 24
Peak memory 199980 kb
Host smart-0d461cd7-7f8b-4bf9-9954-9faaa498e4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876476569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3876476569
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.733342374
Short name T274
Test name
Test status
Simulation time 9860682773 ps
CPU time 82.01 seconds
Started Jul 31 07:11:14 PM PDT 24
Finished Jul 31 07:12:36 PM PDT 24
Peak memory 216368 kb
Host smart-e9489ef2-5eec-40f7-b83c-a964764fca28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733342374 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.733342374
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2073257766
Short name T426
Test name
Test status
Simulation time 2796081352 ps
CPU time 59.96 seconds
Started Jul 31 07:11:14 PM PDT 24
Finished Jul 31 07:12:14 PM PDT 24
Peak memory 200064 kb
Host smart-723a40b3-3aea-40bd-af6e-731d3d2e5444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073257766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2073257766
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2118463012
Short name T221
Test name
Test status
Simulation time 18463594 ps
CPU time 0.57 seconds
Started Jul 31 07:07:23 PM PDT 24
Finished Jul 31 07:07:24 PM PDT 24
Peak memory 195672 kb
Host smart-f50de170-81de-42a6-b7c9-8957a4d242f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118463012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2118463012
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.542761604
Short name T471
Test name
Test status
Simulation time 523777107 ps
CPU time 28.75 seconds
Started Jul 31 07:07:17 PM PDT 24
Finished Jul 31 07:07:46 PM PDT 24
Peak memory 199820 kb
Host smart-e742cea1-59c5-433d-b5ef-6143310ca9e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542761604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.542761604
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.414793492
Short name T316
Test name
Test status
Simulation time 1398967545 ps
CPU time 72.34 seconds
Started Jul 31 07:07:19 PM PDT 24
Finished Jul 31 07:08:32 PM PDT 24
Peak memory 199984 kb
Host smart-e4773474-17b9-4097-90ee-557c40163648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414793492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.414793492
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3358643213
Short name T244
Test name
Test status
Simulation time 496008668 ps
CPU time 40.88 seconds
Started Jul 31 07:07:17 PM PDT 24
Finished Jul 31 07:07:58 PM PDT 24
Peak memory 311516 kb
Host smart-0788d386-fe68-4b22-8153-9a2e599c1284
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358643213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3358643213
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2101970617
Short name T501
Test name
Test status
Simulation time 6362362226 ps
CPU time 61.24 seconds
Started Jul 31 07:07:17 PM PDT 24
Finished Jul 31 07:08:19 PM PDT 24
Peak memory 200096 kb
Host smart-16eb8e2e-e978-4a25-8b89-c0342953f4db
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101970617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2101970617
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.246214788
Short name T371
Test name
Test status
Simulation time 1199550523 ps
CPU time 22.64 seconds
Started Jul 31 07:07:18 PM PDT 24
Finished Jul 31 07:07:40 PM PDT 24
Peak memory 199984 kb
Host smart-5263f71e-c0a9-44a9-b896-beeaddd6252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246214788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.246214788
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2796591333
Short name T56
Test name
Test status
Simulation time 329144230 ps
CPU time 0.92 seconds
Started Jul 31 07:07:24 PM PDT 24
Finished Jul 31 07:07:25 PM PDT 24
Peak memory 218516 kb
Host smart-49499f8a-3ea2-46fb-85ef-7f13171a32b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796591333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2796591333
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2546696695
Short name T185
Test name
Test status
Simulation time 2980361742 ps
CPU time 7.2 seconds
Started Jul 31 07:07:17 PM PDT 24
Finished Jul 31 07:07:25 PM PDT 24
Peak memory 200012 kb
Host smart-afb36aa1-e997-4bd2-b630-12e08454227c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546696695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2546696695
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.666406865
Short name T360
Test name
Test status
Simulation time 57246266615 ps
CPU time 1742.82 seconds
Started Jul 31 07:07:17 PM PDT 24
Finished Jul 31 07:36:20 PM PDT 24
Peak memory 725160 kb
Host smart-f58a1873-7513-441b-ac99-f028f99012f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666406865 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.666406865
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.4148563028
Short name T40
Test name
Test status
Simulation time 48869501517 ps
CPU time 758.2 seconds
Started Jul 31 07:07:24 PM PDT 24
Finished Jul 31 07:20:02 PM PDT 24
Peak memory 415096 kb
Host smart-06a15a9e-b106-49ae-9fd7-00893b844bc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148563028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.4148563028
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3922899243
Short name T358
Test name
Test status
Simulation time 7191899054 ps
CPU time 47.73 seconds
Started Jul 31 07:07:18 PM PDT 24
Finished Jul 31 07:08:06 PM PDT 24
Peak memory 200116 kb
Host smart-70c83231-b80e-4e51-a0d4-0cbf26cf3e50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3922899243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3922899243
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.698013602
Short name T3
Test name
Test status
Simulation time 1657866773 ps
CPU time 52.17 seconds
Started Jul 31 07:07:17 PM PDT 24
Finished Jul 31 07:08:09 PM PDT 24
Peak memory 199948 kb
Host smart-5a3d014c-7596-42a4-8a80-3a57a84d7c99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=698013602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.698013602
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2172556723
Short name T237
Test name
Test status
Simulation time 48741767106 ps
CPU time 73.74 seconds
Started Jul 31 07:07:18 PM PDT 24
Finished Jul 31 07:08:32 PM PDT 24
Peak memory 199996 kb
Host smart-f3c98d70-ca5c-4609-9254-526a2ee58eff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2172556723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2172556723
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2337943199
Short name T261
Test name
Test status
Simulation time 41846526235 ps
CPU time 617.96 seconds
Started Jul 31 07:07:18 PM PDT 24
Finished Jul 31 07:17:37 PM PDT 24
Peak memory 199952 kb
Host smart-aec2df91-1aed-4951-a5a7-086a67d1f6ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2337943199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2337943199
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1933149862
Short name T481
Test name
Test status
Simulation time 81591371728 ps
CPU time 2208.61 seconds
Started Jul 31 07:07:19 PM PDT 24
Finished Jul 31 07:44:08 PM PDT 24
Peak memory 216156 kb
Host smart-04b9e6d4-88ff-469d-9c42-ceb5121cae33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1933149862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1933149862
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2940012811
Short name T242
Test name
Test status
Simulation time 255829751294 ps
CPU time 2191.44 seconds
Started Jul 31 07:07:16 PM PDT 24
Finished Jul 31 07:43:48 PM PDT 24
Peak memory 216424 kb
Host smart-dee88f89-8793-424c-89a9-36ddd72ca388
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2940012811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2940012811
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3804052271
Short name T22
Test name
Test status
Simulation time 25642215253 ps
CPU time 156.66 seconds
Started Jul 31 07:07:16 PM PDT 24
Finished Jul 31 07:09:53 PM PDT 24
Peak memory 200028 kb
Host smart-36344b87-4cf0-4a58-8af2-26baf00827d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804052271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3804052271
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2465086466
Short name T269
Test name
Test status
Simulation time 45493593 ps
CPU time 0.57 seconds
Started Jul 31 07:11:21 PM PDT 24
Finished Jul 31 07:11:21 PM PDT 24
Peak memory 196048 kb
Host smart-7a6df728-183c-456a-8ebe-0c36c1b8f22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465086466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2465086466
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2929883504
Short name T530
Test name
Test status
Simulation time 7785750290 ps
CPU time 53.91 seconds
Started Jul 31 07:11:21 PM PDT 24
Finished Jul 31 07:12:15 PM PDT 24
Peak memory 208184 kb
Host smart-9bca532f-5424-4b95-935f-961c34944e03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929883504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2929883504
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2118579134
Short name T522
Test name
Test status
Simulation time 543195367 ps
CPU time 14.66 seconds
Started Jul 31 07:11:21 PM PDT 24
Finished Jul 31 07:11:35 PM PDT 24
Peak memory 199908 kb
Host smart-2f2b0ff5-1e43-45d3-8cb4-ddcf4e1f613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118579134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2118579134
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.211844159
Short name T187
Test name
Test status
Simulation time 27583145275 ps
CPU time 932.47 seconds
Started Jul 31 07:11:27 PM PDT 24
Finished Jul 31 07:26:59 PM PDT 24
Peak memory 650332 kb
Host smart-c95dfa85-db80-405e-8ae3-c054bb50a53b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211844159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.211844159
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2827015946
Short name T519
Test name
Test status
Simulation time 4451645509 ps
CPU time 200.86 seconds
Started Jul 31 07:11:27 PM PDT 24
Finished Jul 31 07:14:48 PM PDT 24
Peak memory 200016 kb
Host smart-47fc4274-6baa-4ade-af35-372300210393
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827015946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2827015946
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3457767483
Short name T423
Test name
Test status
Simulation time 13094477323 ps
CPU time 166.34 seconds
Started Jul 31 07:11:13 PM PDT 24
Finished Jul 31 07:14:00 PM PDT 24
Peak memory 200168 kb
Host smart-6b0a3c14-5e1f-4899-a152-f351a47eeccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457767483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3457767483
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3895164445
Short name T156
Test name
Test status
Simulation time 2676548299 ps
CPU time 9.05 seconds
Started Jul 31 07:11:15 PM PDT 24
Finished Jul 31 07:11:24 PM PDT 24
Peak memory 200088 kb
Host smart-7cf60e3b-8003-443a-8b1c-47e716981911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895164445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3895164445
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.122818528
Short name T148
Test name
Test status
Simulation time 56795197015 ps
CPU time 1377.86 seconds
Started Jul 31 07:11:22 PM PDT 24
Finished Jul 31 07:34:20 PM PDT 24
Peak memory 545084 kb
Host smart-89d143f1-35da-428c-936a-3c1efec4392b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122818528 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.122818528
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3659826253
Short name T83
Test name
Test status
Simulation time 392140601 ps
CPU time 13.96 seconds
Started Jul 31 07:11:26 PM PDT 24
Finished Jul 31 07:11:40 PM PDT 24
Peak memory 199920 kb
Host smart-72459340-dbea-4ad8-acb9-6c5976d79ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659826253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3659826253
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2694749537
Short name T457
Test name
Test status
Simulation time 16717414 ps
CPU time 0.6 seconds
Started Jul 31 07:11:30 PM PDT 24
Finished Jul 31 07:11:31 PM PDT 24
Peak memory 196000 kb
Host smart-81e67f72-9d14-45c5-8a66-5e3aa404e282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694749537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2694749537
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1742720751
Short name T26
Test name
Test status
Simulation time 11574644277 ps
CPU time 101.3 seconds
Started Jul 31 07:11:29 PM PDT 24
Finished Jul 31 07:13:10 PM PDT 24
Peak memory 199916 kb
Host smart-2d02e644-b150-45af-a280-e4c0bd092ad8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742720751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1742720751
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2580297006
Short name T45
Test name
Test status
Simulation time 8459677826 ps
CPU time 56.86 seconds
Started Jul 31 07:11:29 PM PDT 24
Finished Jul 31 07:12:26 PM PDT 24
Peak memory 200084 kb
Host smart-f726f6a5-5202-45c9-add5-32fed9d401d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580297006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2580297006
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3121469741
Short name T299
Test name
Test status
Simulation time 39785879952 ps
CPU time 881.64 seconds
Started Jul 31 07:11:30 PM PDT 24
Finished Jul 31 07:26:12 PM PDT 24
Peak memory 743300 kb
Host smart-bbea997f-6f7f-4862-9c37-2334217f5e1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3121469741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3121469741
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3793552605
Short name T64
Test name
Test status
Simulation time 19188900861 ps
CPU time 269.35 seconds
Started Jul 31 07:11:34 PM PDT 24
Finished Jul 31 07:16:04 PM PDT 24
Peak memory 200016 kb
Host smart-df2f2ee8-5cf6-4661-a691-f9b3b0c4f0ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793552605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3793552605
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1527677576
Short name T167
Test name
Test status
Simulation time 13129225873 ps
CPU time 63.13 seconds
Started Jul 31 07:11:26 PM PDT 24
Finished Jul 31 07:12:29 PM PDT 24
Peak memory 200092 kb
Host smart-35442a28-4318-49cd-af8d-0228e4c8edbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527677576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1527677576
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3128373040
Short name T2
Test name
Test status
Simulation time 2645663457 ps
CPU time 8.99 seconds
Started Jul 31 07:11:22 PM PDT 24
Finished Jul 31 07:11:31 PM PDT 24
Peak memory 200032 kb
Host smart-77871ddc-94e1-471e-8496-409691e9d751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128373040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3128373040
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1796968031
Short name T365
Test name
Test status
Simulation time 41626727086 ps
CPU time 130.8 seconds
Started Jul 31 07:11:32 PM PDT 24
Finished Jul 31 07:13:43 PM PDT 24
Peak memory 200176 kb
Host smart-492e1f4f-2e81-4f21-8fd2-22b1a3685361
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796968031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1796968031
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1416594234
Short name T32
Test name
Test status
Simulation time 484565632 ps
CPU time 12.46 seconds
Started Jul 31 07:11:29 PM PDT 24
Finished Jul 31 07:11:41 PM PDT 24
Peak memory 199920 kb
Host smart-909db458-2468-4867-aee4-900ffbe46014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416594234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1416594234
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2770618797
Short name T516
Test name
Test status
Simulation time 14161263 ps
CPU time 0.6 seconds
Started Jul 31 07:11:38 PM PDT 24
Finished Jul 31 07:11:39 PM PDT 24
Peak memory 195612 kb
Host smart-e77a1695-9c76-4ebd-bfb9-7614829a32ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770618797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2770618797
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2733914841
Short name T518
Test name
Test status
Simulation time 2276031134 ps
CPU time 33.1 seconds
Started Jul 31 07:11:30 PM PDT 24
Finished Jul 31 07:12:03 PM PDT 24
Peak memory 199964 kb
Host smart-dd412b8a-4830-4095-bd1a-a5cd9332d00c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733914841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2733914841
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2053202544
Short name T58
Test name
Test status
Simulation time 352172442 ps
CPU time 17.96 seconds
Started Jul 31 07:11:29 PM PDT 24
Finished Jul 31 07:11:47 PM PDT 24
Peak memory 199932 kb
Host smart-9aa48ed6-09fc-4ec0-98ae-d00885164818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053202544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2053202544
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2887125695
Short name T406
Test name
Test status
Simulation time 11463991572 ps
CPU time 453.73 seconds
Started Jul 31 07:11:29 PM PDT 24
Finished Jul 31 07:19:03 PM PDT 24
Peak memory 636664 kb
Host smart-2e5bed86-93e8-4542-91a0-e3bf457a4014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887125695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2887125695
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1776340019
Short name T375
Test name
Test status
Simulation time 2378946346 ps
CPU time 27.27 seconds
Started Jul 31 07:11:28 PM PDT 24
Finished Jul 31 07:11:55 PM PDT 24
Peak memory 200056 kb
Host smart-ce0629c7-cc5c-45ae-84c1-fa58adee8ab9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776340019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1776340019
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3731410892
Short name T263
Test name
Test status
Simulation time 1612706964 ps
CPU time 21.97 seconds
Started Jul 31 07:11:29 PM PDT 24
Finished Jul 31 07:11:51 PM PDT 24
Peak memory 199896 kb
Host smart-d463dd0b-ca37-4f31-996f-1beb0ddc6892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731410892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3731410892
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2758712997
Short name T461
Test name
Test status
Simulation time 206437806 ps
CPU time 1.37 seconds
Started Jul 31 07:11:31 PM PDT 24
Finished Jul 31 07:11:32 PM PDT 24
Peak memory 199912 kb
Host smart-24213fbf-03c6-422c-b1fc-2b8eed398904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758712997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2758712997
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3813372951
Short name T246
Test name
Test status
Simulation time 75605783113 ps
CPU time 1073.55 seconds
Started Jul 31 07:11:37 PM PDT 24
Finished Jul 31 07:29:30 PM PDT 24
Peak memory 724068 kb
Host smart-5b943681-b5e9-4cbc-81d7-fc9645d991d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813372951 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3813372951
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.93732364
Short name T63
Test name
Test status
Simulation time 621192116 ps
CPU time 2.82 seconds
Started Jul 31 07:11:31 PM PDT 24
Finished Jul 31 07:11:34 PM PDT 24
Peak memory 199940 kb
Host smart-8becad87-cbf2-4df5-b969-b74520424097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93732364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.93732364
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.414814170
Short name T309
Test name
Test status
Simulation time 29866016 ps
CPU time 0.56 seconds
Started Jul 31 07:11:37 PM PDT 24
Finished Jul 31 07:11:38 PM PDT 24
Peak memory 194960 kb
Host smart-23aa37cd-de63-41ac-b053-ccca685e2c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414814170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.414814170
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3573237648
Short name T493
Test name
Test status
Simulation time 891988937 ps
CPU time 13.75 seconds
Started Jul 31 07:11:38 PM PDT 24
Finished Jul 31 07:11:51 PM PDT 24
Peak memory 200040 kb
Host smart-9ccb3abe-7cb9-4636-b63e-39c999fd820e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573237648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3573237648
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.511598051
Short name T450
Test name
Test status
Simulation time 6511721975 ps
CPU time 20.75 seconds
Started Jul 31 07:11:39 PM PDT 24
Finished Jul 31 07:12:00 PM PDT 24
Peak memory 200044 kb
Host smart-9c0ca99e-6ac4-43aa-81fb-a8d577adba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511598051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.511598051
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2685128465
Short name T388
Test name
Test status
Simulation time 2365700407 ps
CPU time 369.61 seconds
Started Jul 31 07:11:37 PM PDT 24
Finished Jul 31 07:17:46 PM PDT 24
Peak memory 492640 kb
Host smart-5aebb896-f498-4213-bbd4-e54f75b0429a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685128465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2685128465
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1730359475
Short name T467
Test name
Test status
Simulation time 12751246743 ps
CPU time 98.18 seconds
Started Jul 31 07:11:35 PM PDT 24
Finished Jul 31 07:13:13 PM PDT 24
Peak memory 200016 kb
Host smart-11a951a5-31f1-4115-88f8-bdf911b790a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730359475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1730359475
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3518021139
Short name T188
Test name
Test status
Simulation time 1280213787 ps
CPU time 73.37 seconds
Started Jul 31 07:11:38 PM PDT 24
Finished Jul 31 07:12:51 PM PDT 24
Peak memory 199900 kb
Host smart-fd59b86a-2dcf-40e3-8e26-d2027fb44d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518021139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3518021139
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.748868187
Short name T332
Test name
Test status
Simulation time 968725822 ps
CPU time 8.81 seconds
Started Jul 31 07:11:37 PM PDT 24
Finished Jul 31 07:11:46 PM PDT 24
Peak memory 199892 kb
Host smart-ce73168c-6780-4c2e-83ba-aa3afdc1f60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748868187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.748868187
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3290069542
Short name T350
Test name
Test status
Simulation time 3910262981 ps
CPU time 197.87 seconds
Started Jul 31 07:11:37 PM PDT 24
Finished Jul 31 07:14:55 PM PDT 24
Peak memory 199948 kb
Host smart-3f14abf5-84e2-4cef-9e47-233cf9cc755e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290069542 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3290069542
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3152458728
Short name T193
Test name
Test status
Simulation time 12297867812 ps
CPU time 55.57 seconds
Started Jul 31 07:11:35 PM PDT 24
Finished Jul 31 07:12:31 PM PDT 24
Peak memory 200076 kb
Host smart-2a449881-b438-4851-8568-1ad9314e406b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152458728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3152458728
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3695998254
Short name T355
Test name
Test status
Simulation time 10782772 ps
CPU time 0.58 seconds
Started Jul 31 07:11:45 PM PDT 24
Finished Jul 31 07:11:46 PM PDT 24
Peak memory 195712 kb
Host smart-49893b25-77ba-430c-9ce8-a23bf681b3db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695998254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3695998254
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.498828203
Short name T527
Test name
Test status
Simulation time 296143688 ps
CPU time 15.33 seconds
Started Jul 31 07:11:36 PM PDT 24
Finished Jul 31 07:11:52 PM PDT 24
Peak memory 199736 kb
Host smart-c9431b44-6dac-434c-ab8c-f3740a5a0196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=498828203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.498828203
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2796141113
Short name T370
Test name
Test status
Simulation time 3360643470 ps
CPU time 23.61 seconds
Started Jul 31 07:11:46 PM PDT 24
Finished Jul 31 07:12:09 PM PDT 24
Peak memory 200012 kb
Host smart-3e7de15b-4d7a-465b-a1cb-b72a885efb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796141113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2796141113
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1924086967
Short name T508
Test name
Test status
Simulation time 2624058089 ps
CPU time 358.75 seconds
Started Jul 31 07:11:38 PM PDT 24
Finished Jul 31 07:17:36 PM PDT 24
Peak memory 655116 kb
Host smart-613e7517-d40c-404c-8276-47efecc037f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924086967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1924086967
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.55253286
Short name T492
Test name
Test status
Simulation time 8803931799 ps
CPU time 36.96 seconds
Started Jul 31 07:11:46 PM PDT 24
Finished Jul 31 07:12:23 PM PDT 24
Peak memory 200052 kb
Host smart-2d07cb18-5d2b-4a31-9e98-3929b4cff69b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55253286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.55253286
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.993934600
Short name T13
Test name
Test status
Simulation time 4357854782 ps
CPU time 115.31 seconds
Started Jul 31 07:11:36 PM PDT 24
Finished Jul 31 07:13:31 PM PDT 24
Peak memory 216420 kb
Host smart-8a2e5341-5092-4d11-be43-2097423f36eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993934600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.993934600
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.183363270
Short name T500
Test name
Test status
Simulation time 696597211 ps
CPU time 11.54 seconds
Started Jul 31 07:11:36 PM PDT 24
Finished Jul 31 07:11:48 PM PDT 24
Peak memory 199992 kb
Host smart-7d8e1d46-698f-4e24-ab8e-938bebe19f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183363270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.183363270
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1556159777
Short name T394
Test name
Test status
Simulation time 96090691435 ps
CPU time 1662.99 seconds
Started Jul 31 07:11:45 PM PDT 24
Finished Jul 31 07:39:28 PM PDT 24
Peak memory 668932 kb
Host smart-d36c3048-3f29-499f-a289-3daa76c184c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556159777 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1556159777
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.437565834
Short name T443
Test name
Test status
Simulation time 2841528942 ps
CPU time 58.55 seconds
Started Jul 31 07:11:46 PM PDT 24
Finished Jul 31 07:12:45 PM PDT 24
Peak memory 200108 kb
Host smart-9af71303-34fa-47d9-a466-8ba50c7aa968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437565834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.437565834
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2282315865
Short name T384
Test name
Test status
Simulation time 25467090 ps
CPU time 0.58 seconds
Started Jul 31 07:11:52 PM PDT 24
Finished Jul 31 07:11:52 PM PDT 24
Peak memory 195980 kb
Host smart-60674142-e05f-499d-a096-924f15312634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282315865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2282315865
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.85688524
Short name T476
Test name
Test status
Simulation time 4123543562 ps
CPU time 56.11 seconds
Started Jul 31 07:11:53 PM PDT 24
Finished Jul 31 07:12:49 PM PDT 24
Peak memory 199956 kb
Host smart-674f5985-1d15-4747-94d8-c452ac5b0111
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85688524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.85688524
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2158913887
Short name T273
Test name
Test status
Simulation time 1230863542 ps
CPU time 17.42 seconds
Started Jul 31 07:11:52 PM PDT 24
Finished Jul 31 07:12:10 PM PDT 24
Peak memory 199876 kb
Host smart-9faabff5-1740-45d7-8eee-6501d198b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158913887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2158913887
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2587294818
Short name T166
Test name
Test status
Simulation time 24553788275 ps
CPU time 1019.62 seconds
Started Jul 31 07:11:53 PM PDT 24
Finished Jul 31 07:28:53 PM PDT 24
Peak memory 751760 kb
Host smart-992c535f-0545-4b2c-8d78-a30b272ff0fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587294818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2587294818
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2139567904
Short name T257
Test name
Test status
Simulation time 11649605210 ps
CPU time 48.75 seconds
Started Jul 31 07:11:52 PM PDT 24
Finished Jul 31 07:12:41 PM PDT 24
Peak memory 199992 kb
Host smart-a576ce21-5bc7-4fdc-bc32-7f7f5f8d8340
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139567904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2139567904
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.861355867
Short name T399
Test name
Test status
Simulation time 2365704076 ps
CPU time 30.84 seconds
Started Jul 31 07:11:52 PM PDT 24
Finished Jul 31 07:12:23 PM PDT 24
Peak memory 200044 kb
Host smart-cfefa803-a9d0-4585-a841-dc38175d8719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861355867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.861355867
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3233999968
Short name T240
Test name
Test status
Simulation time 2485028385 ps
CPU time 11 seconds
Started Jul 31 07:11:47 PM PDT 24
Finished Jul 31 07:11:58 PM PDT 24
Peak memory 200044 kb
Host smart-d82052b8-b4cf-4218-b200-ec62ef8bffcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233999968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3233999968
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4203253238
Short name T462
Test name
Test status
Simulation time 94874926666 ps
CPU time 1316.74 seconds
Started Jul 31 07:11:52 PM PDT 24
Finished Jul 31 07:33:48 PM PDT 24
Peak memory 658428 kb
Host smart-78aacd02-9d6b-48bb-8571-a76bf2b5b110
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203253238 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4203253238
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2011838607
Short name T418
Test name
Test status
Simulation time 514638413 ps
CPU time 7.05 seconds
Started Jul 31 07:11:51 PM PDT 24
Finished Jul 31 07:11:58 PM PDT 24
Peak memory 199872 kb
Host smart-8b0dd05c-b229-4ff8-a620-6c80ff0fffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011838607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2011838607
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1598089476
Short name T152
Test name
Test status
Simulation time 11293027 ps
CPU time 0.59 seconds
Started Jul 31 07:12:00 PM PDT 24
Finished Jul 31 07:12:01 PM PDT 24
Peak memory 196692 kb
Host smart-ff85ce43-3d82-4bec-830f-57f1ccd8310a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598089476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1598089476
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.586750161
Short name T17
Test name
Test status
Simulation time 839209794 ps
CPU time 49.74 seconds
Started Jul 31 07:11:58 PM PDT 24
Finished Jul 31 07:12:48 PM PDT 24
Peak memory 199892 kb
Host smart-301f7fd1-4906-4108-a04b-081fb8d1febd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586750161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.586750161
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.25917476
Short name T369
Test name
Test status
Simulation time 7592233713 ps
CPU time 23.62 seconds
Started Jul 31 07:11:58 PM PDT 24
Finished Jul 31 07:12:22 PM PDT 24
Peak memory 199932 kb
Host smart-c96f52fd-0a35-47eb-af69-d14126fbc4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25917476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.25917476
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1098813542
Short name T7
Test name
Test status
Simulation time 321673423 ps
CPU time 33.26 seconds
Started Jul 31 07:11:58 PM PDT 24
Finished Jul 31 07:12:31 PM PDT 24
Peak memory 246944 kb
Host smart-4cf7327a-1426-4f89-939b-d64009230437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098813542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1098813542
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2556752519
Short name T48
Test name
Test status
Simulation time 11491566340 ps
CPU time 96.72 seconds
Started Jul 31 07:12:03 PM PDT 24
Finished Jul 31 07:13:39 PM PDT 24
Peak memory 200016 kb
Host smart-d4a34f36-f749-4dbb-9c4f-0b26f11cbee1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556752519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2556752519
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3133425677
Short name T1
Test name
Test status
Simulation time 27207519499 ps
CPU time 157.35 seconds
Started Jul 31 07:12:03 PM PDT 24
Finished Jul 31 07:14:40 PM PDT 24
Peak memory 200020 kb
Host smart-a2ebef9b-4871-4c34-8ed6-61e7926904c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133425677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3133425677
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.474256579
Short name T396
Test name
Test status
Simulation time 953555045 ps
CPU time 10.57 seconds
Started Jul 31 07:11:53 PM PDT 24
Finished Jul 31 07:12:04 PM PDT 24
Peak memory 199944 kb
Host smart-12f334f8-0e86-4520-b777-7281741ba783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474256579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.474256579
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2906356811
Short name T76
Test name
Test status
Simulation time 41643128123 ps
CPU time 498.95 seconds
Started Jul 31 07:11:58 PM PDT 24
Finished Jul 31 07:20:17 PM PDT 24
Peak memory 215476 kb
Host smart-8e8717ea-0459-4e71-bf1f-c359253c8318
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906356811 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2906356811
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3003054913
Short name T346
Test name
Test status
Simulation time 8703896909 ps
CPU time 79.07 seconds
Started Jul 31 07:11:58 PM PDT 24
Finished Jul 31 07:13:17 PM PDT 24
Peak memory 200112 kb
Host smart-93c066cc-428b-4bb9-9e27-9171fd7901a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003054913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3003054913
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4279066440
Short name T408
Test name
Test status
Simulation time 38247063 ps
CPU time 0.58 seconds
Started Jul 31 07:12:09 PM PDT 24
Finished Jul 31 07:12:10 PM PDT 24
Peak memory 195676 kb
Host smart-fefdf74e-00cf-4154-8c99-db226f162f57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279066440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4279066440
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3523901999
Short name T321
Test name
Test status
Simulation time 1413439642 ps
CPU time 21.67 seconds
Started Jul 31 07:11:59 PM PDT 24
Finished Jul 31 07:12:21 PM PDT 24
Peak memory 199896 kb
Host smart-2448ebc7-2d4c-4649-a62e-0b4e61f67f6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523901999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3523901999
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.491433199
Short name T339
Test name
Test status
Simulation time 6929691890 ps
CPU time 22.13 seconds
Started Jul 31 07:12:08 PM PDT 24
Finished Jul 31 07:12:30 PM PDT 24
Peak memory 200076 kb
Host smart-c8a17df5-54c7-44d0-9ba2-9697d4e98cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491433199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.491433199
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3975768508
Short name T159
Test name
Test status
Simulation time 6352364998 ps
CPU time 212.68 seconds
Started Jul 31 07:12:07 PM PDT 24
Finished Jul 31 07:15:40 PM PDT 24
Peak memory 465748 kb
Host smart-ebbe9b7e-757f-4ac9-bc75-17af135ed751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975768508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3975768508
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1871929716
Short name T397
Test name
Test status
Simulation time 12557866822 ps
CPU time 80.81 seconds
Started Jul 31 07:12:06 PM PDT 24
Finished Jul 31 07:13:27 PM PDT 24
Peak memory 200040 kb
Host smart-d328af76-de32-4915-b98e-acc931d6491d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871929716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1871929716
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1186344347
Short name T409
Test name
Test status
Simulation time 999430141 ps
CPU time 15.28 seconds
Started Jul 31 07:12:00 PM PDT 24
Finished Jul 31 07:12:15 PM PDT 24
Peak memory 199976 kb
Host smart-4940d681-d011-4b45-a2f1-9dbb762d2dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186344347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1186344347
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.4189779344
Short name T142
Test name
Test status
Simulation time 207805913 ps
CPU time 2.39 seconds
Started Jul 31 07:11:58 PM PDT 24
Finished Jul 31 07:12:01 PM PDT 24
Peak memory 199896 kb
Host smart-f9b984b8-3d66-4f50-9f3e-e7d0e0367e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189779344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.4189779344
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1981316647
Short name T526
Test name
Test status
Simulation time 494374181390 ps
CPU time 3363.61 seconds
Started Jul 31 07:12:08 PM PDT 24
Finished Jul 31 08:08:12 PM PDT 24
Peak memory 799784 kb
Host smart-abef8cc9-42ce-4529-845a-54f23b641c8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981316647 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1981316647
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.4106928088
Short name T189
Test name
Test status
Simulation time 4340735891 ps
CPU time 81.28 seconds
Started Jul 31 07:12:06 PM PDT 24
Finished Jul 31 07:13:28 PM PDT 24
Peak memory 200012 kb
Host smart-c3bb7d53-42b6-4231-b4ab-5024953a21b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106928088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.4106928088
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3805819692
Short name T415
Test name
Test status
Simulation time 14752641 ps
CPU time 0.58 seconds
Started Jul 31 07:12:15 PM PDT 24
Finished Jul 31 07:12:16 PM PDT 24
Peak memory 194952 kb
Host smart-7dc8d0e4-b78f-4741-966e-1f3b90e70f66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805819692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3805819692
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.649086969
Short name T270
Test name
Test status
Simulation time 1457611623 ps
CPU time 85.36 seconds
Started Jul 31 07:12:07 PM PDT 24
Finished Jul 31 07:13:32 PM PDT 24
Peak memory 199956 kb
Host smart-11b2be4f-4844-4a39-939f-d60e99257318
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649086969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.649086969
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1565916717
Short name T16
Test name
Test status
Simulation time 1272690006 ps
CPU time 43.48 seconds
Started Jul 31 07:12:17 PM PDT 24
Finished Jul 31 07:13:01 PM PDT 24
Peak memory 199964 kb
Host smart-407a5336-6343-4d91-8e34-cece74989ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565916717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1565916717
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4237627650
Short name T515
Test name
Test status
Simulation time 17810246 ps
CPU time 0.66 seconds
Started Jul 31 07:12:17 PM PDT 24
Finished Jul 31 07:12:17 PM PDT 24
Peak memory 198204 kb
Host smart-d7409127-6642-4592-9288-ae90318ec5ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237627650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4237627650
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2962786482
Short name T218
Test name
Test status
Simulation time 8475614492 ps
CPU time 109.36 seconds
Started Jul 31 07:12:18 PM PDT 24
Finished Jul 31 07:14:07 PM PDT 24
Peak memory 200088 kb
Host smart-719c4f76-7108-483b-86e5-a7209c870809
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962786482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2962786482
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.913949819
Short name T329
Test name
Test status
Simulation time 1731269788 ps
CPU time 21.83 seconds
Started Jul 31 07:12:06 PM PDT 24
Finished Jul 31 07:12:28 PM PDT 24
Peak memory 199944 kb
Host smart-a715e2cd-8e5c-4073-a103-9679534ed28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913949819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.913949819
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2337526552
Short name T473
Test name
Test status
Simulation time 473105732 ps
CPU time 8.03 seconds
Started Jul 31 07:12:09 PM PDT 24
Finished Jul 31 07:12:17 PM PDT 24
Peak memory 199948 kb
Host smart-9279ad22-c5a3-4e1b-8358-860473aeff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337526552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2337526552
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1367328208
Short name T275
Test name
Test status
Simulation time 7165447081 ps
CPU time 91.9 seconds
Started Jul 31 07:12:17 PM PDT 24
Finished Jul 31 07:13:49 PM PDT 24
Peak memory 200092 kb
Host smart-9cbf83d2-1dc5-45e1-b7e4-5a592c8cc74f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367328208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1367328208
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2436682210
Short name T126
Test name
Test status
Simulation time 5337488392 ps
CPU time 72.9 seconds
Started Jul 31 07:12:16 PM PDT 24
Finished Jul 31 07:13:29 PM PDT 24
Peak memory 200052 kb
Host smart-2bb0987d-520b-4856-82cf-8be3013237ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436682210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2436682210
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1569515970
Short name T348
Test name
Test status
Simulation time 24528305 ps
CPU time 0.59 seconds
Started Jul 31 07:12:17 PM PDT 24
Finished Jul 31 07:12:18 PM PDT 24
Peak memory 196708 kb
Host smart-c097b245-351f-401c-bf74-e3ea18f4220d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569515970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1569515970
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.4168866605
Short name T311
Test name
Test status
Simulation time 3684670141 ps
CPU time 48.91 seconds
Started Jul 31 07:12:17 PM PDT 24
Finished Jul 31 07:13:06 PM PDT 24
Peak memory 200076 kb
Host smart-13bda087-9f03-409f-a206-4db9e406c538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168866605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.4168866605
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3479150907
Short name T354
Test name
Test status
Simulation time 713882227 ps
CPU time 36.88 seconds
Started Jul 31 07:12:16 PM PDT 24
Finished Jul 31 07:12:53 PM PDT 24
Peak memory 200016 kb
Host smart-15d0e4a6-712f-455d-b9b5-45ea65a8b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479150907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3479150907
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.168773313
Short name T502
Test name
Test status
Simulation time 19415129720 ps
CPU time 1001.67 seconds
Started Jul 31 07:12:18 PM PDT 24
Finished Jul 31 07:29:00 PM PDT 24
Peak memory 734184 kb
Host smart-3376f303-4088-493c-810e-d7ddb3433da4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=168773313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.168773313
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1244462945
Short name T484
Test name
Test status
Simulation time 14333428179 ps
CPU time 190.75 seconds
Started Jul 31 07:12:17 PM PDT 24
Finished Jul 31 07:15:28 PM PDT 24
Peak memory 200040 kb
Host smart-51996d56-c818-469b-aa48-aa2d16e70001
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244462945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1244462945
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.4058048651
Short name T157
Test name
Test status
Simulation time 42073933778 ps
CPU time 137.63 seconds
Started Jul 31 07:12:15 PM PDT 24
Finished Jul 31 07:14:33 PM PDT 24
Peak memory 199948 kb
Host smart-60b873cb-e397-4d39-b1f8-b1eb72206462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058048651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.4058048651
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3003629280
Short name T251
Test name
Test status
Simulation time 37520250 ps
CPU time 2.02 seconds
Started Jul 31 07:12:14 PM PDT 24
Finished Jul 31 07:12:16 PM PDT 24
Peak memory 199908 kb
Host smart-945c039c-b9ee-4d90-a88b-0d29d167a704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003629280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3003629280
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2462736843
Short name T331
Test name
Test status
Simulation time 13878548668 ps
CPU time 1283.1 seconds
Started Jul 31 07:12:16 PM PDT 24
Finished Jul 31 07:33:40 PM PDT 24
Peak memory 742436 kb
Host smart-be51c627-75e6-49d2-8191-ca4f62c9dad9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462736843 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2462736843
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3549220651
Short name T523
Test name
Test status
Simulation time 4572924783 ps
CPU time 102.13 seconds
Started Jul 31 07:12:15 PM PDT 24
Finished Jul 31 07:13:57 PM PDT 24
Peak memory 200028 kb
Host smart-c22b7e89-c430-4144-bd55-5ccd8783388d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549220651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3549220651
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3340212120
Short name T411
Test name
Test status
Simulation time 36390823 ps
CPU time 0.57 seconds
Started Jul 31 07:07:31 PM PDT 24
Finished Jul 31 07:07:31 PM PDT 24
Peak memory 196652 kb
Host smart-861f7ca5-a181-43d7-b807-38efe2aa8643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340212120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3340212120
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1728423565
Short name T336
Test name
Test status
Simulation time 1224152440 ps
CPU time 70.28 seconds
Started Jul 31 07:07:29 PM PDT 24
Finished Jul 31 07:08:40 PM PDT 24
Peak memory 199904 kb
Host smart-21068d6a-f5ad-4e21-b4b4-ff405bc9d341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728423565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1728423565
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.448328003
Short name T528
Test name
Test status
Simulation time 301276505 ps
CPU time 4.55 seconds
Started Jul 31 07:07:25 PM PDT 24
Finished Jul 31 07:07:30 PM PDT 24
Peak memory 199900 kb
Host smart-2f0255aa-d0dd-47cf-82ed-25d6c25b529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448328003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.448328003
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2223086308
Short name T392
Test name
Test status
Simulation time 523577624 ps
CPU time 93.66 seconds
Started Jul 31 07:07:26 PM PDT 24
Finished Jul 31 07:09:00 PM PDT 24
Peak memory 441688 kb
Host smart-2a4320a7-f092-4892-965c-f22200d88e6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223086308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2223086308
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.360974923
Short name T155
Test name
Test status
Simulation time 67383479 ps
CPU time 1.63 seconds
Started Jul 31 07:07:24 PM PDT 24
Finished Jul 31 07:07:26 PM PDT 24
Peak memory 199764 kb
Host smart-33bb7ec9-df56-4238-8bb8-b3033e17191f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360974923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.360974923
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.4068103567
Short name T60
Test name
Test status
Simulation time 7315935012 ps
CPU time 92.54 seconds
Started Jul 31 07:07:28 PM PDT 24
Finished Jul 31 07:09:01 PM PDT 24
Peak memory 200056 kb
Host smart-2361c8d6-260b-45cc-9ddc-fae37e2b559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068103567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.4068103567
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3379117126
Short name T53
Test name
Test status
Simulation time 164413272 ps
CPU time 0.95 seconds
Started Jul 31 07:07:36 PM PDT 24
Finished Jul 31 07:07:37 PM PDT 24
Peak memory 219592 kb
Host smart-4bd8bd07-bf40-40bb-b4df-a0fe1ab68941
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379117126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3379117126
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1512792631
Short name T252
Test name
Test status
Simulation time 198298237 ps
CPU time 8.65 seconds
Started Jul 31 07:07:23 PM PDT 24
Finished Jul 31 07:07:31 PM PDT 24
Peak memory 199920 kb
Host smart-0467d46f-546b-4555-887b-b88b6eb4c2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512792631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1512792631
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3919226191
Short name T428
Test name
Test status
Simulation time 352326054933 ps
CPU time 731.95 seconds
Started Jul 31 07:07:30 PM PDT 24
Finished Jul 31 07:19:42 PM PDT 24
Peak memory 208256 kb
Host smart-edb65abf-7c83-437e-831a-d6088edd60a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919226191 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3919226191
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1225694536
Short name T20
Test name
Test status
Simulation time 134892233321 ps
CPU time 2488.52 seconds
Started Jul 31 07:07:29 PM PDT 24
Finished Jul 31 07:48:58 PM PDT 24
Peak memory 527596 kb
Host smart-27eef2b4-a6a0-44ce-8cc3-dd38b6bb7a0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225694536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1225694536
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.946919761
Short name T82
Test name
Test status
Simulation time 3121547397 ps
CPU time 69.05 seconds
Started Jul 31 07:07:29 PM PDT 24
Finished Jul 31 07:08:38 PM PDT 24
Peak memory 200052 kb
Host smart-513fe654-649f-4c40-a8b5-f8c2fe9c8fe8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=946919761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.946919761
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2935771053
Short name T62
Test name
Test status
Simulation time 1671961405 ps
CPU time 51.09 seconds
Started Jul 31 07:07:30 PM PDT 24
Finished Jul 31 07:08:21 PM PDT 24
Peak memory 199980 kb
Host smart-a230a448-9c98-4233-bfb7-1eb960485cc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2935771053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2935771053
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2585204417
Short name T291
Test name
Test status
Simulation time 9886749772 ps
CPU time 112.89 seconds
Started Jul 31 07:07:32 PM PDT 24
Finished Jul 31 07:09:25 PM PDT 24
Peak memory 199964 kb
Host smart-73166462-b0a4-4231-8af4-025fdd7a7aa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2585204417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2585204417
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2671692221
Short name T444
Test name
Test status
Simulation time 11129515535 ps
CPU time 588.6 seconds
Started Jul 31 07:07:28 PM PDT 24
Finished Jul 31 07:17:17 PM PDT 24
Peak memory 200044 kb
Host smart-01ea5f31-954f-43ef-88ff-550a4bd6cf7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2671692221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2671692221
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.566120275
Short name T509
Test name
Test status
Simulation time 208220823620 ps
CPU time 2555.61 seconds
Started Jul 31 07:07:32 PM PDT 24
Finished Jul 31 07:50:08 PM PDT 24
Peak memory 208364 kb
Host smart-17aaef66-4559-4cdc-9292-d54615f98cd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=566120275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.566120275
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1236906156
Short name T278
Test name
Test status
Simulation time 149045619007 ps
CPU time 2414.57 seconds
Started Jul 31 07:07:24 PM PDT 24
Finished Jul 31 07:47:39 PM PDT 24
Peak memory 215424 kb
Host smart-c8aef91d-021b-4266-abaf-ce5007930c45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1236906156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1236906156
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1423162917
Short name T256
Test name
Test status
Simulation time 535085035 ps
CPU time 27.74 seconds
Started Jul 31 07:07:26 PM PDT 24
Finished Jul 31 07:07:54 PM PDT 24
Peak memory 199972 kb
Host smart-a7f3ca9b-acb9-49d7-ae11-9ad81cc7c665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423162917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1423162917
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.4279371831
Short name T464
Test name
Test status
Simulation time 5465607120 ps
CPU time 82.39 seconds
Started Jul 31 07:12:15 PM PDT 24
Finished Jul 31 07:13:37 PM PDT 24
Peak memory 199948 kb
Host smart-54114245-71a4-4a48-86bf-b3a99c441c94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279371831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.4279371831
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.797108813
Short name T191
Test name
Test status
Simulation time 3991424853 ps
CPU time 12.69 seconds
Started Jul 31 07:12:16 PM PDT 24
Finished Jul 31 07:12:28 PM PDT 24
Peak memory 200068 kb
Host smart-0308ea27-d5ac-4c03-8cf9-e208a5b6eb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797108813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.797108813
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2370291942
Short name T243
Test name
Test status
Simulation time 5112682402 ps
CPU time 1073.65 seconds
Started Jul 31 07:12:18 PM PDT 24
Finished Jul 31 07:30:12 PM PDT 24
Peak memory 772544 kb
Host smart-d4206134-01d4-4e64-b74f-1b4480059997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370291942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2370291942
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1200878149
Short name T335
Test name
Test status
Simulation time 4555773806 ps
CPU time 58.33 seconds
Started Jul 31 07:12:14 PM PDT 24
Finished Jul 31 07:13:13 PM PDT 24
Peak memory 200040 kb
Host smart-ebf1661d-4f00-488c-89e9-48289518e180
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200878149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1200878149
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.824032214
Short name T14
Test name
Test status
Simulation time 31831633847 ps
CPU time 108.56 seconds
Started Jul 31 07:12:15 PM PDT 24
Finished Jul 31 07:14:04 PM PDT 24
Peak memory 200044 kb
Host smart-66a6ec4d-35fe-427f-8f90-8a121fb470f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824032214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.824032214
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.129974177
Short name T374
Test name
Test status
Simulation time 805420503 ps
CPU time 12.91 seconds
Started Jul 31 07:12:17 PM PDT 24
Finished Jul 31 07:12:30 PM PDT 24
Peak memory 200032 kb
Host smart-5faa9078-aff7-49bb-81e4-050622eb3b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129974177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.129974177
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3683608855
Short name T496
Test name
Test status
Simulation time 52726183580 ps
CPU time 1411.46 seconds
Started Jul 31 07:12:27 PM PDT 24
Finished Jul 31 07:35:59 PM PDT 24
Peak memory 745420 kb
Host smart-36ffe942-cca2-4d9f-a1e0-15682404e025
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683608855 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3683608855
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.161421389
Short name T23
Test name
Test status
Simulation time 438253348 ps
CPU time 8.12 seconds
Started Jul 31 07:12:24 PM PDT 24
Finished Jul 31 07:12:32 PM PDT 24
Peak memory 199972 kb
Host smart-6af00d7f-fc61-4117-9c62-2b2c27c0b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161421389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.161421389
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1708219503
Short name T161
Test name
Test status
Simulation time 15517547 ps
CPU time 0.58 seconds
Started Jul 31 07:12:31 PM PDT 24
Finished Jul 31 07:12:32 PM PDT 24
Peak memory 195960 kb
Host smart-6ab1d3fe-9621-44e6-a345-2e7f1a42a88f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708219503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1708219503
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2408428866
Short name T283
Test name
Test status
Simulation time 1050872952 ps
CPU time 60.33 seconds
Started Jul 31 07:12:23 PM PDT 24
Finished Jul 31 07:13:24 PM PDT 24
Peak memory 199964 kb
Host smart-621cf3a6-859f-4654-9932-5771794782d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2408428866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2408428866
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2021966552
Short name T227
Test name
Test status
Simulation time 138186284 ps
CPU time 7.22 seconds
Started Jul 31 07:12:24 PM PDT 24
Finished Jul 31 07:12:31 PM PDT 24
Peak memory 199952 kb
Host smart-f48f1199-aa72-4052-8ef2-2574f3b2f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021966552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2021966552
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1437643460
Short name T328
Test name
Test status
Simulation time 4986941802 ps
CPU time 361.49 seconds
Started Jul 31 07:12:27 PM PDT 24
Finished Jul 31 07:18:29 PM PDT 24
Peak memory 690092 kb
Host smart-e168e7f2-d3a6-4bca-9d98-d606b5d97c19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1437643460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1437643460
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3073523318
Short name T36
Test name
Test status
Simulation time 9529859762 ps
CPU time 129.98 seconds
Started Jul 31 07:12:30 PM PDT 24
Finished Jul 31 07:14:40 PM PDT 24
Peak memory 199976 kb
Host smart-67d110af-4404-4943-94e9-1e413cd960c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073523318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3073523318
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1287099517
Short name T143
Test name
Test status
Simulation time 16750552943 ps
CPU time 115.16 seconds
Started Jul 31 07:12:27 PM PDT 24
Finished Jul 31 07:14:22 PM PDT 24
Peak memory 200064 kb
Host smart-f95fade7-7eae-465c-b9ed-42ff24779e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287099517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1287099517
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3980089559
Short name T271
Test name
Test status
Simulation time 61363906 ps
CPU time 1.83 seconds
Started Jul 31 07:12:24 PM PDT 24
Finished Jul 31 07:12:26 PM PDT 24
Peak memory 199908 kb
Host smart-f5f61778-f95e-4b79-8b7a-a62f5c1bc7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980089559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3980089559
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2952707305
Short name T338
Test name
Test status
Simulation time 2780502257 ps
CPU time 51.9 seconds
Started Jul 31 07:12:31 PM PDT 24
Finished Jul 31 07:13:23 PM PDT 24
Peak memory 200072 kb
Host smart-d0c774e9-ed79-4492-9f32-c908783390b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952707305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2952707305
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3989791965
Short name T453
Test name
Test status
Simulation time 44874338 ps
CPU time 0.6 seconds
Started Jul 31 07:12:39 PM PDT 24
Finished Jul 31 07:12:40 PM PDT 24
Peak memory 196648 kb
Host smart-4f9e51b0-ab84-4631-bc55-fd5c2187e43f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989791965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3989791965
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3344845727
Short name T46
Test name
Test status
Simulation time 5806319406 ps
CPU time 94.45 seconds
Started Jul 31 07:12:31 PM PDT 24
Finished Jul 31 07:14:06 PM PDT 24
Peak memory 200068 kb
Host smart-3ef06098-eb07-43f9-895d-d6b04f8c8c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3344845727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3344845727
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.220283787
Short name T511
Test name
Test status
Simulation time 130113493 ps
CPU time 7.08 seconds
Started Jul 31 07:12:30 PM PDT 24
Finished Jul 31 07:12:38 PM PDT 24
Peak memory 199992 kb
Host smart-911fb9ee-be73-43a6-9992-d1cebd1ea67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220283787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.220283787
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1761599118
Short name T250
Test name
Test status
Simulation time 10019576361 ps
CPU time 436.23 seconds
Started Jul 31 07:12:36 PM PDT 24
Finished Jul 31 07:19:53 PM PDT 24
Peak memory 487688 kb
Host smart-d7a0e84f-e414-43d9-acea-db818cfc4855
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761599118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1761599118
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.746025704
Short name T89
Test name
Test status
Simulation time 2094431840 ps
CPU time 116.94 seconds
Started Jul 31 07:12:31 PM PDT 24
Finished Jul 31 07:14:28 PM PDT 24
Peak memory 199896 kb
Host smart-06e9ac2a-7e49-4511-bdf9-bd5410c0922f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746025704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.746025704
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4014109306
Short name T413
Test name
Test status
Simulation time 65386903410 ps
CPU time 180.84 seconds
Started Jul 31 07:12:31 PM PDT 24
Finished Jul 31 07:15:32 PM PDT 24
Peak memory 200036 kb
Host smart-af680ae9-2b76-49c0-9c16-9e77e29abf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014109306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4014109306
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.527731535
Short name T513
Test name
Test status
Simulation time 469461263 ps
CPU time 5.98 seconds
Started Jul 31 07:12:32 PM PDT 24
Finished Jul 31 07:12:38 PM PDT 24
Peak memory 199888 kb
Host smart-d9408131-ca13-4c06-b927-a4660d91d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527731535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.527731535
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1801547127
Short name T373
Test name
Test status
Simulation time 2250398450717 ps
CPU time 3269.86 seconds
Started Jul 31 07:12:39 PM PDT 24
Finished Jul 31 08:07:09 PM PDT 24
Peak memory 811156 kb
Host smart-f7a7fb4e-8a6f-4a6f-ba29-b89576febc2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801547127 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1801547127
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3608861908
Short name T296
Test name
Test status
Simulation time 700459424 ps
CPU time 9.68 seconds
Started Jul 31 07:12:32 PM PDT 24
Finished Jul 31 07:12:42 PM PDT 24
Peak memory 199996 kb
Host smart-2faceddd-de5a-499a-989b-15e4db07f07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608861908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3608861908
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3260216471
Short name T241
Test name
Test status
Simulation time 15444460 ps
CPU time 0.56 seconds
Started Jul 31 07:12:38 PM PDT 24
Finished Jul 31 07:12:38 PM PDT 24
Peak memory 194940 kb
Host smart-754041cc-1da0-4985-9843-4723086225c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260216471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3260216471
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3642603867
Short name T29
Test name
Test status
Simulation time 2689312791 ps
CPU time 69.12 seconds
Started Jul 31 07:12:42 PM PDT 24
Finished Jul 31 07:13:51 PM PDT 24
Peak memory 200100 kb
Host smart-21b62b61-1cdb-4b96-a1af-11332aa4a4e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3642603867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3642603867
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3379148262
Short name T264
Test name
Test status
Simulation time 963269066 ps
CPU time 12.31 seconds
Started Jul 31 07:12:40 PM PDT 24
Finished Jul 31 07:12:52 PM PDT 24
Peak memory 199932 kb
Host smart-7b7eaea2-9ba2-4b0a-8824-86e4eb47a2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379148262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3379148262
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2028157379
Short name T359
Test name
Test status
Simulation time 9776875812 ps
CPU time 907.12 seconds
Started Jul 31 07:12:39 PM PDT 24
Finished Jul 31 07:27:46 PM PDT 24
Peak memory 665736 kb
Host smart-24fc6426-8ae8-4ac2-a2de-8220774ef680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2028157379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2028157379
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3564606943
Short name T469
Test name
Test status
Simulation time 1900587828 ps
CPU time 100.67 seconds
Started Jul 31 07:12:38 PM PDT 24
Finished Jul 31 07:14:19 PM PDT 24
Peak memory 199868 kb
Host smart-da75aa6a-8dac-4ff0-b736-ccf10fea426b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564606943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3564606943
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3506730701
Short name T163
Test name
Test status
Simulation time 7192994583 ps
CPU time 128.36 seconds
Started Jul 31 07:12:39 PM PDT 24
Finished Jul 31 07:14:48 PM PDT 24
Peak memory 216328 kb
Host smart-230a756a-f421-48bd-b986-61bef06569a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506730701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3506730701
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.461343053
Short name T377
Test name
Test status
Simulation time 5463031242 ps
CPU time 14.96 seconds
Started Jul 31 07:12:39 PM PDT 24
Finished Jul 31 07:12:54 PM PDT 24
Peak memory 200044 kb
Host smart-8b3cf4c1-b581-4fdb-8722-1cfcb8981ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461343053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.461343053
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.234565856
Short name T446
Test name
Test status
Simulation time 25921293349 ps
CPU time 463.22 seconds
Started Jul 31 07:12:38 PM PDT 24
Finished Jul 31 07:20:22 PM PDT 24
Peak memory 583148 kb
Host smart-14ff8dd0-b612-4c42-b863-4960ffc6d6c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234565856 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.234565856
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1017044912
Short name T410
Test name
Test status
Simulation time 894858602 ps
CPU time 12.98 seconds
Started Jul 31 07:12:39 PM PDT 24
Finished Jul 31 07:12:52 PM PDT 24
Peak memory 199920 kb
Host smart-7a14cee8-ccaa-4f94-a477-1fcbf93b8115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017044912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1017044912
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3682221418
Short name T412
Test name
Test status
Simulation time 15090899 ps
CPU time 0.58 seconds
Started Jul 31 07:12:46 PM PDT 24
Finished Jul 31 07:12:47 PM PDT 24
Peak memory 194960 kb
Host smart-77e18b7b-1a94-471c-80da-bbc596c21b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682221418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3682221418
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3547111450
Short name T422
Test name
Test status
Simulation time 6292812765 ps
CPU time 93.89 seconds
Started Jul 31 07:12:44 PM PDT 24
Finished Jul 31 07:14:18 PM PDT 24
Peak memory 200080 kb
Host smart-83d3b1cb-2802-48ea-95fc-41b2e5055683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3547111450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3547111450
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2605064041
Short name T425
Test name
Test status
Simulation time 534548596 ps
CPU time 9.89 seconds
Started Jul 31 07:12:45 PM PDT 24
Finished Jul 31 07:12:55 PM PDT 24
Peak memory 199852 kb
Host smart-c169f05d-25ee-408d-aae1-69a2ec153e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605064041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2605064041
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3991590012
Short name T175
Test name
Test status
Simulation time 19893023486 ps
CPU time 983.62 seconds
Started Jul 31 07:12:45 PM PDT 24
Finished Jul 31 07:29:09 PM PDT 24
Peak memory 753084 kb
Host smart-4d65fca3-656c-4d09-a28b-95b97581d73a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3991590012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3991590012
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1151888473
Short name T137
Test name
Test status
Simulation time 17464922841 ps
CPU time 152.77 seconds
Started Jul 31 07:12:45 PM PDT 24
Finished Jul 31 07:15:18 PM PDT 24
Peak memory 200088 kb
Host smart-3d30cf7d-cdcf-4390-8485-fec55fac6558
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151888473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1151888473
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2343320717
Short name T182
Test name
Test status
Simulation time 2299769853 ps
CPU time 19.31 seconds
Started Jul 31 07:12:45 PM PDT 24
Finished Jul 31 07:13:05 PM PDT 24
Peak memory 200004 kb
Host smart-ae76e36b-4fd5-4b99-9ac0-3eb556fdfdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343320717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2343320717
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1777320422
Short name T168
Test name
Test status
Simulation time 4048593461 ps
CPU time 11.39 seconds
Started Jul 31 07:12:40 PM PDT 24
Finished Jul 31 07:12:51 PM PDT 24
Peak memory 200044 kb
Host smart-296b3953-0a3c-4f1c-8826-44bb680c26e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777320422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1777320422
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.356704686
Short name T456
Test name
Test status
Simulation time 305850598546 ps
CPU time 2273.14 seconds
Started Jul 31 07:12:44 PM PDT 24
Finished Jul 31 07:50:38 PM PDT 24
Peak memory 757040 kb
Host smart-7596eb60-11ce-4c80-b761-506c2af97bd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356704686 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.356704686
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.4233669374
Short name T460
Test name
Test status
Simulation time 14316559192 ps
CPU time 128.48 seconds
Started Jul 31 07:12:45 PM PDT 24
Finished Jul 31 07:14:54 PM PDT 24
Peak memory 200032 kb
Host smart-5696832b-2d99-42e3-91e6-bf4b9b685dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233669374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.4233669374
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2691822853
Short name T209
Test name
Test status
Simulation time 46249058 ps
CPU time 0.59 seconds
Started Jul 31 07:12:55 PM PDT 24
Finished Jul 31 07:12:56 PM PDT 24
Peak memory 194960 kb
Host smart-8c30624d-2b09-4ee7-8561-f830c9a81edf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691822853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2691822853
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3330588057
Short name T222
Test name
Test status
Simulation time 3999738118 ps
CPU time 52.01 seconds
Started Jul 31 07:12:52 PM PDT 24
Finished Jul 31 07:13:44 PM PDT 24
Peak memory 200064 kb
Host smart-6df64fb7-be4b-48a8-8015-99198dc9f3b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3330588057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3330588057
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.656736210
Short name T474
Test name
Test status
Simulation time 992205958 ps
CPU time 54.99 seconds
Started Jul 31 07:12:56 PM PDT 24
Finished Jul 31 07:13:51 PM PDT 24
Peak memory 199912 kb
Host smart-b025d938-4217-4aec-958c-26434a175486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656736210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.656736210
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1645001686
Short name T282
Test name
Test status
Simulation time 7349734250 ps
CPU time 226.95 seconds
Started Jul 31 07:12:55 PM PDT 24
Finished Jul 31 07:16:42 PM PDT 24
Peak memory 458772 kb
Host smart-63c7c6ab-d443-4bc5-a095-4560856aae46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645001686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1645001686
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3562019113
Short name T532
Test name
Test status
Simulation time 7812575341 ps
CPU time 103.48 seconds
Started Jul 31 07:12:54 PM PDT 24
Finished Jul 31 07:14:37 PM PDT 24
Peak memory 200088 kb
Host smart-95754aa8-cec9-466e-9e9e-753e92564c40
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562019113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3562019113
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3221344443
Short name T232
Test name
Test status
Simulation time 9302126574 ps
CPU time 61.08 seconds
Started Jul 31 07:12:52 PM PDT 24
Finished Jul 31 07:13:53 PM PDT 24
Peak memory 199720 kb
Host smart-32b39694-7708-42b2-a521-702fdd692a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221344443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3221344443
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3073444024
Short name T487
Test name
Test status
Simulation time 1077361576 ps
CPU time 11.76 seconds
Started Jul 31 07:12:45 PM PDT 24
Finished Jul 31 07:12:57 PM PDT 24
Peak memory 199888 kb
Host smart-99bdddb2-b17f-434a-9da4-c57f0e5c033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073444024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3073444024
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.179240657
Short name T42
Test name
Test status
Simulation time 41930849617 ps
CPU time 1576.93 seconds
Started Jul 31 07:12:56 PM PDT 24
Finished Jul 31 07:39:13 PM PDT 24
Peak memory 761624 kb
Host smart-92ceb713-3480-4792-a47d-696ac9ca021d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179240657 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.179240657
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3348198736
Short name T84
Test name
Test status
Simulation time 28767947840 ps
CPU time 84.46 seconds
Started Jul 31 07:12:52 PM PDT 24
Finished Jul 31 07:14:16 PM PDT 24
Peak memory 199704 kb
Host smart-bf32a83f-f3f2-485b-9098-86526ea84bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348198736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3348198736
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1925105583
Short name T324
Test name
Test status
Simulation time 14291180 ps
CPU time 0.59 seconds
Started Jul 31 07:12:59 PM PDT 24
Finished Jul 31 07:13:00 PM PDT 24
Peak memory 195600 kb
Host smart-006d4dc7-a4c6-4598-906c-3bf6fb15e1f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925105583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1925105583
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3583066486
Short name T463
Test name
Test status
Simulation time 4020465236 ps
CPU time 59.46 seconds
Started Jul 31 07:12:52 PM PDT 24
Finished Jul 31 07:13:52 PM PDT 24
Peak memory 200144 kb
Host smart-65fb9e33-b3e4-4fdf-974f-84fba1492718
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583066486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3583066486
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3850940887
Short name T33
Test name
Test status
Simulation time 5903089823 ps
CPU time 39.72 seconds
Started Jul 31 07:12:54 PM PDT 24
Finished Jul 31 07:13:34 PM PDT 24
Peak memory 200080 kb
Host smart-7f1d8848-c20d-475c-a951-3799d32e06cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850940887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3850940887
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.229111312
Short name T385
Test name
Test status
Simulation time 4366222475 ps
CPU time 630.44 seconds
Started Jul 31 07:12:51 PM PDT 24
Finished Jul 31 07:23:22 PM PDT 24
Peak memory 745724 kb
Host smart-467d0691-10b6-4b52-ab70-2c7df151432a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229111312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.229111312
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.409861572
Short name T90
Test name
Test status
Simulation time 10422448589 ps
CPU time 63.34 seconds
Started Jul 31 07:12:59 PM PDT 24
Finished Jul 31 07:14:03 PM PDT 24
Peak memory 199960 kb
Host smart-78d7f927-0d54-448a-8433-baaae55be7a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409861572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.409861572
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3414832769
Short name T210
Test name
Test status
Simulation time 779953928 ps
CPU time 41.04 seconds
Started Jul 31 07:12:51 PM PDT 24
Finished Jul 31 07:13:32 PM PDT 24
Peak memory 199952 kb
Host smart-10a88336-1b76-41d3-8c48-74d624a292d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414832769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3414832769
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.871871852
Short name T206
Test name
Test status
Simulation time 1151597089 ps
CPU time 13.82 seconds
Started Jul 31 07:12:52 PM PDT 24
Finished Jul 31 07:13:06 PM PDT 24
Peak memory 199932 kb
Host smart-d801a657-f2af-4499-8154-18e7982054da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871871852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.871871852
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.851282334
Short name T439
Test name
Test status
Simulation time 81267755811 ps
CPU time 2288.25 seconds
Started Jul 31 07:13:00 PM PDT 24
Finished Jul 31 07:51:08 PM PDT 24
Peak memory 770284 kb
Host smart-ee9bbf57-07df-4f0e-a0c1-1149e2c7f277
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851282334 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.851282334
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1853672826
Short name T432
Test name
Test status
Simulation time 8356615623 ps
CPU time 75.85 seconds
Started Jul 31 07:12:59 PM PDT 24
Finished Jul 31 07:14:15 PM PDT 24
Peak memory 200032 kb
Host smart-95e9195d-5c35-42ff-b706-571a41f3ce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853672826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1853672826
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2410926339
Short name T59
Test name
Test status
Simulation time 18375184 ps
CPU time 0.59 seconds
Started Jul 31 07:13:07 PM PDT 24
Finished Jul 31 07:13:08 PM PDT 24
Peak memory 194868 kb
Host smart-5257f4cc-da3b-472b-99c8-df6ec84e5e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410926339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2410926339
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1480390409
Short name T215
Test name
Test status
Simulation time 2911091070 ps
CPU time 83.14 seconds
Started Jul 31 07:13:01 PM PDT 24
Finished Jul 31 07:14:24 PM PDT 24
Peak memory 200020 kb
Host smart-952ede4a-2cde-47f0-9ff7-d358a11499eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480390409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1480390409
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2385609424
Short name T290
Test name
Test status
Simulation time 19716195296 ps
CPU time 81.69 seconds
Started Jul 31 07:13:00 PM PDT 24
Finished Jul 31 07:14:22 PM PDT 24
Peak memory 208332 kb
Host smart-d82c772c-f630-4bcd-8bb7-7a6db7a97363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385609424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2385609424
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2210998073
Short name T281
Test name
Test status
Simulation time 12609323919 ps
CPU time 1059.81 seconds
Started Jul 31 07:12:58 PM PDT 24
Finished Jul 31 07:30:38 PM PDT 24
Peak memory 725284 kb
Host smart-e215b9df-5fff-47c5-b95a-67b3403ed23c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210998073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2210998073
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2202189728
Short name T424
Test name
Test status
Simulation time 2215132122 ps
CPU time 20.3 seconds
Started Jul 31 07:13:01 PM PDT 24
Finished Jul 31 07:13:22 PM PDT 24
Peak memory 199892 kb
Host smart-70b44b23-7bca-4d0d-a04b-21759cc8b496
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202189728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2202189728
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_smoke.4028908563
Short name T507
Test name
Test status
Simulation time 808270338 ps
CPU time 3.48 seconds
Started Jul 31 07:12:59 PM PDT 24
Finished Jul 31 07:13:02 PM PDT 24
Peak memory 199972 kb
Host smart-24d500d9-74cc-47db-bf66-7789bd996fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028908563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4028908563
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2618699316
Short name T378
Test name
Test status
Simulation time 26372298685 ps
CPU time 1174.22 seconds
Started Jul 31 07:13:00 PM PDT 24
Finished Jul 31 07:32:34 PM PDT 24
Peak memory 678584 kb
Host smart-dda17c0b-f36b-4b3f-b2c2-5309e54eefab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618699316 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2618699316
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.4092583404
Short name T376
Test name
Test status
Simulation time 1564075481 ps
CPU time 67.48 seconds
Started Jul 31 07:12:59 PM PDT 24
Finished Jul 31 07:14:06 PM PDT 24
Peak memory 199844 kb
Host smart-4af280d3-908c-41c8-85cf-d9c0e0be4cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092583404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.4092583404
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3055897444
Short name T314
Test name
Test status
Simulation time 45049470 ps
CPU time 0.61 seconds
Started Jul 31 07:13:08 PM PDT 24
Finished Jul 31 07:13:09 PM PDT 24
Peak memory 196728 kb
Host smart-eab1e977-4685-4d3f-9198-84c4e297e4e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055897444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3055897444
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2919414843
Short name T327
Test name
Test status
Simulation time 1435460955 ps
CPU time 73.33 seconds
Started Jul 31 07:13:08 PM PDT 24
Finished Jul 31 07:14:22 PM PDT 24
Peak memory 199952 kb
Host smart-cb6c1e3f-0c96-43cd-ad9c-7213d2907b4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919414843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2919414843
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.655756660
Short name T400
Test name
Test status
Simulation time 2096295479 ps
CPU time 15.04 seconds
Started Jul 31 07:13:07 PM PDT 24
Finished Jul 31 07:13:23 PM PDT 24
Peak memory 199916 kb
Host smart-8a06ebd7-4a1d-4344-9aa5-5eebb79ce4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655756660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.655756660
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1752665063
Short name T517
Test name
Test status
Simulation time 4546586401 ps
CPU time 414.18 seconds
Started Jul 31 07:13:07 PM PDT 24
Finished Jul 31 07:20:01 PM PDT 24
Peak memory 464468 kb
Host smart-6436e91e-2883-49e1-b237-768254cbb9d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1752665063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1752665063
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1197267267
Short name T305
Test name
Test status
Simulation time 21864918119 ps
CPU time 187.12 seconds
Started Jul 31 07:13:10 PM PDT 24
Finished Jul 31 07:16:17 PM PDT 24
Peak memory 200024 kb
Host smart-ac915f88-3718-40aa-b8a3-4574afd13feb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197267267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1197267267
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1930968816
Short name T416
Test name
Test status
Simulation time 29960573631 ps
CPU time 126.79 seconds
Started Jul 31 07:13:07 PM PDT 24
Finished Jul 31 07:15:14 PM PDT 24
Peak memory 200124 kb
Host smart-8f1463dc-23be-4eb1-90b4-b16116bfa240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930968816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1930968816
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1979939097
Short name T503
Test name
Test status
Simulation time 246690015 ps
CPU time 4.67 seconds
Started Jul 31 07:13:07 PM PDT 24
Finished Jul 31 07:13:12 PM PDT 24
Peak memory 199928 kb
Host smart-ae234f85-a84c-4acf-8981-2d74263e09cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979939097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1979939097
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1968191426
Short name T430
Test name
Test status
Simulation time 383879804504 ps
CPU time 1472.79 seconds
Started Jul 31 07:13:10 PM PDT 24
Finished Jul 31 07:37:43 PM PDT 24
Peak memory 674136 kb
Host smart-dba16267-3524-4f9b-8db5-284b2fe69ef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968191426 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1968191426
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3518168486
Short name T121
Test name
Test status
Simulation time 45568671320 ps
CPU time 140.38 seconds
Started Jul 31 07:13:07 PM PDT 24
Finished Jul 31 07:15:27 PM PDT 24
Peak memory 200044 kb
Host smart-c03b98a8-81aa-4902-a5fc-20926886662e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518168486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3518168486
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2788834088
Short name T80
Test name
Test status
Simulation time 49007980 ps
CPU time 0.58 seconds
Started Jul 31 07:13:13 PM PDT 24
Finished Jul 31 07:13:14 PM PDT 24
Peak memory 195980 kb
Host smart-bf9b3d4e-2e52-41c2-be2e-8d6b6aa661a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788834088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2788834088
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4271673700
Short name T320
Test name
Test status
Simulation time 16631564628 ps
CPU time 81.63 seconds
Started Jul 31 07:13:15 PM PDT 24
Finished Jul 31 07:14:37 PM PDT 24
Peak memory 200020 kb
Host smart-cb482a6e-d12c-4895-8838-948fba0e4429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271673700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4271673700
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3084427572
Short name T170
Test name
Test status
Simulation time 1387306496 ps
CPU time 19.11 seconds
Started Jul 31 07:13:13 PM PDT 24
Finished Jul 31 07:13:33 PM PDT 24
Peak memory 199892 kb
Host smart-1d3480c8-6379-49c8-b91a-0c310a3f3b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084427572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3084427572
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2349015482
Short name T340
Test name
Test status
Simulation time 14710962380 ps
CPU time 650.23 seconds
Started Jul 31 07:13:14 PM PDT 24
Finished Jul 31 07:24:05 PM PDT 24
Peak memory 660152 kb
Host smart-2c5e9b29-6dd9-4af8-8a09-9c2475812e12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349015482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2349015482
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.566506911
Short name T529
Test name
Test status
Simulation time 3666233063 ps
CPU time 192.93 seconds
Started Jul 31 07:13:13 PM PDT 24
Finished Jul 31 07:16:26 PM PDT 24
Peak memory 200104 kb
Host smart-87c89b9b-b562-4652-a729-6e3f6069cfbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566506911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.566506911
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1018524390
Short name T429
Test name
Test status
Simulation time 5691025627 ps
CPU time 100.33 seconds
Started Jul 31 07:13:13 PM PDT 24
Finished Jul 31 07:14:54 PM PDT 24
Peak memory 200044 kb
Host smart-d27aecf3-c069-4bf9-93b7-e8f6a56c5ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018524390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1018524390
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3265163886
Short name T442
Test name
Test status
Simulation time 483555405 ps
CPU time 8.03 seconds
Started Jul 31 07:13:13 PM PDT 24
Finished Jul 31 07:13:21 PM PDT 24
Peak memory 199960 kb
Host smart-57770325-12a6-4053-8ea1-1df3c438e32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265163886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3265163886
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2498544287
Short name T127
Test name
Test status
Simulation time 41207441009 ps
CPU time 764.45 seconds
Started Jul 31 07:13:13 PM PDT 24
Finished Jul 31 07:25:58 PM PDT 24
Peak memory 412496 kb
Host smart-080da26f-2136-4370-9d77-0a602ddb145b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498544287 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2498544287
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3471990683
Short name T313
Test name
Test status
Simulation time 573158445 ps
CPU time 5.25 seconds
Started Jul 31 07:13:13 PM PDT 24
Finished Jul 31 07:13:18 PM PDT 24
Peak memory 199944 kb
Host smart-02257512-85c7-4108-9adc-1c4b3f05b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471990683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3471990683
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2202780273
Short name T267
Test name
Test status
Simulation time 31455830 ps
CPU time 0.59 seconds
Started Jul 31 07:07:44 PM PDT 24
Finished Jul 31 07:07:44 PM PDT 24
Peak memory 194932 kb
Host smart-2498578e-2b8e-45a6-ab33-a3bf814dff6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202780273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2202780273
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1722086683
Short name T165
Test name
Test status
Simulation time 3623304604 ps
CPU time 51.15 seconds
Started Jul 31 07:07:37 PM PDT 24
Finished Jul 31 07:08:28 PM PDT 24
Peak memory 200048 kb
Host smart-408da6ba-181d-4b89-8eaa-9c9e24887fd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722086683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1722086683
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2160594771
Short name T466
Test name
Test status
Simulation time 2020016419 ps
CPU time 39.36 seconds
Started Jul 31 07:07:36 PM PDT 24
Finished Jul 31 07:08:16 PM PDT 24
Peak memory 199888 kb
Host smart-09fb2d4b-c9e3-47dd-bf4c-f83bdbafbc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160594771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2160594771
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1541465334
Short name T417
Test name
Test status
Simulation time 4281375310 ps
CPU time 504.71 seconds
Started Jul 31 07:07:40 PM PDT 24
Finished Jul 31 07:16:05 PM PDT 24
Peak memory 673860 kb
Host smart-75dfd4fd-9ca4-4da5-9d45-3f451ffa8a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541465334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1541465334
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3041993922
Short name T302
Test name
Test status
Simulation time 3457388091 ps
CPU time 30.37 seconds
Started Jul 31 07:07:47 PM PDT 24
Finished Jul 31 07:08:17 PM PDT 24
Peak memory 200112 kb
Host smart-cf1d04ec-8051-4952-91be-08cb7af816c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041993922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3041993922
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3170168240
Short name T479
Test name
Test status
Simulation time 20433449070 ps
CPU time 108.76 seconds
Started Jul 31 07:07:38 PM PDT 24
Finished Jul 31 07:09:27 PM PDT 24
Peak memory 200076 kb
Host smart-03088e03-5eb1-470b-96fa-35003e25b80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170168240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3170168240
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.715960254
Short name T510
Test name
Test status
Simulation time 1349669165 ps
CPU time 17.29 seconds
Started Jul 31 07:07:42 PM PDT 24
Finished Jul 31 07:07:59 PM PDT 24
Peak memory 199904 kb
Host smart-bfb53677-0cd1-4aca-8dfc-288a218318ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715960254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.715960254
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.702117228
Short name T87
Test name
Test status
Simulation time 68859865439 ps
CPU time 1043.37 seconds
Started Jul 31 07:07:42 PM PDT 24
Finished Jul 31 07:25:05 PM PDT 24
Peak memory 613612 kb
Host smart-8a0f0324-825f-4997-b0f7-c5c6325788f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702117228 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.702117228
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.381071081
Short name T73
Test name
Test status
Simulation time 65062440629 ps
CPU time 1444.86 seconds
Started Jul 31 07:07:47 PM PDT 24
Finished Jul 31 07:31:52 PM PDT 24
Peak memory 620092 kb
Host smart-f858fb29-4ee1-4735-9154-d6fb22cc3f1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=381071081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.381071081
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1842194535
Short name T124
Test name
Test status
Simulation time 12410453933 ps
CPU time 111.82 seconds
Started Jul 31 07:07:42 PM PDT 24
Finished Jul 31 07:09:34 PM PDT 24
Peak memory 200040 kb
Host smart-50023bcc-2425-48e4-9d98-68f5aac9cb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842194535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1842194535
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.437585565
Short name T398
Test name
Test status
Simulation time 156376377 ps
CPU time 0.58 seconds
Started Jul 31 07:07:59 PM PDT 24
Finished Jul 31 07:08:00 PM PDT 24
Peak memory 195912 kb
Host smart-2d053330-6098-42a6-91ba-0fd42eba77b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437585565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.437585565
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2750612820
Short name T319
Test name
Test status
Simulation time 723045820 ps
CPU time 18.03 seconds
Started Jul 31 07:07:58 PM PDT 24
Finished Jul 31 07:08:16 PM PDT 24
Peak memory 199980 kb
Host smart-33ee5bb9-9271-4b7d-8b05-ea2e902a992a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750612820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2750612820
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1878565537
Short name T353
Test name
Test status
Simulation time 9551954322 ps
CPU time 42.01 seconds
Started Jul 31 07:08:03 PM PDT 24
Finished Jul 31 07:08:45 PM PDT 24
Peak memory 200104 kb
Host smart-f905222c-48b2-48ed-98d0-f25cdcd94d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878565537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1878565537
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1588997061
Short name T174
Test name
Test status
Simulation time 8178276498 ps
CPU time 699.7 seconds
Started Jul 31 07:07:59 PM PDT 24
Finished Jul 31 07:19:39 PM PDT 24
Peak memory 727476 kb
Host smart-f8e0de5b-a1c4-403a-b4ee-239d5e0d991a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588997061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1588997061
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2534951091
Short name T440
Test name
Test status
Simulation time 2749201438 ps
CPU time 142.77 seconds
Started Jul 31 07:07:59 PM PDT 24
Finished Jul 31 07:10:22 PM PDT 24
Peak memory 200072 kb
Host smart-810894d0-b4fd-420e-8835-5ee71c01841a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534951091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2534951091
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.554224251
Short name T79
Test name
Test status
Simulation time 6969476201 ps
CPU time 145.6 seconds
Started Jul 31 07:07:42 PM PDT 24
Finished Jul 31 07:10:08 PM PDT 24
Peak memory 200028 kb
Host smart-649e693b-c68f-40c1-9b7e-915dd08ce56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554224251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.554224251
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2159923783
Short name T403
Test name
Test status
Simulation time 2144930964 ps
CPU time 10.18 seconds
Started Jul 31 07:07:46 PM PDT 24
Finished Jul 31 07:07:56 PM PDT 24
Peak memory 199924 kb
Host smart-0e5283fb-0d82-4aac-9cfd-b4f5cd27943e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159923783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2159923783
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2776562179
Short name T145
Test name
Test status
Simulation time 197898487857 ps
CPU time 3699.16 seconds
Started Jul 31 07:07:53 PM PDT 24
Finished Jul 31 08:09:33 PM PDT 24
Peak memory 840988 kb
Host smart-ff28ea7c-14f9-4fa6-b8b2-71a611267d1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776562179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2776562179
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.535098627
Short name T8
Test name
Test status
Simulation time 98346496077 ps
CPU time 1608.1 seconds
Started Jul 31 07:07:55 PM PDT 24
Finished Jul 31 07:34:43 PM PDT 24
Peak memory 609348 kb
Host smart-94aea3db-ea32-4341-91f7-38d7fdeb4f55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535098627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.535098627
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2077401688
Short name T312
Test name
Test status
Simulation time 33976355211 ps
CPU time 34.81 seconds
Started Jul 31 07:07:54 PM PDT 24
Finished Jul 31 07:08:29 PM PDT 24
Peak memory 200016 kb
Host smart-f74a4884-fb2d-4f79-9097-da4d67f934d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077401688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2077401688
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.702005621
Short name T52
Test name
Test status
Simulation time 31094292 ps
CPU time 0.56 seconds
Started Jul 31 07:08:00 PM PDT 24
Finished Jul 31 07:08:01 PM PDT 24
Peak memory 195640 kb
Host smart-4b08b70f-c08f-4c96-aa21-ec06ae728007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702005621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.702005621
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2083262590
Short name T74
Test name
Test status
Simulation time 14484003950 ps
CPU time 41.47 seconds
Started Jul 31 07:08:02 PM PDT 24
Finished Jul 31 07:08:44 PM PDT 24
Peak memory 200160 kb
Host smart-885b2b25-6e9a-42f6-a5b1-e9d6b9da5c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083262590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2083262590
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2866916666
Short name T259
Test name
Test status
Simulation time 1747465512 ps
CPU time 31.4 seconds
Started Jul 31 07:07:59 PM PDT 24
Finished Jul 31 07:08:31 PM PDT 24
Peak memory 199900 kb
Host smart-76891355-0538-41d5-b251-348056b2a549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866916666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2866916666
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.4029405793
Short name T239
Test name
Test status
Simulation time 534774453 ps
CPU time 136.48 seconds
Started Jul 31 07:08:00 PM PDT 24
Finished Jul 31 07:10:17 PM PDT 24
Peak memory 594444 kb
Host smart-37f1617b-eca5-4079-a5a3-53a80b7eba31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4029405793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.4029405793
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3555042388
Short name T330
Test name
Test status
Simulation time 4931338140 ps
CPU time 131.13 seconds
Started Jul 31 07:07:58 PM PDT 24
Finished Jul 31 07:10:10 PM PDT 24
Peak memory 200024 kb
Host smart-9f6df831-857f-4437-87f9-0d65a041d62a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555042388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3555042388
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1099827428
Short name T39
Test name
Test status
Simulation time 1624959165 ps
CPU time 93.1 seconds
Started Jul 31 07:08:02 PM PDT 24
Finished Jul 31 07:09:35 PM PDT 24
Peak memory 199864 kb
Host smart-bfd7eb69-fbb2-48df-bc58-1177ba36efa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099827428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1099827428
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2844469642
Short name T286
Test name
Test status
Simulation time 17116928632 ps
CPU time 16.31 seconds
Started Jul 31 07:08:02 PM PDT 24
Finished Jul 31 07:08:18 PM PDT 24
Peak memory 200012 kb
Host smart-238088a2-4a34-4907-967d-8ab751c7100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844469642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2844469642
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.4020780780
Short name T520
Test name
Test status
Simulation time 795898066 ps
CPU time 34.17 seconds
Started Jul 31 07:08:00 PM PDT 24
Finished Jul 31 07:08:35 PM PDT 24
Peak memory 199916 kb
Host smart-86709e9d-dd33-4ba9-98ad-4a45d9f8042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020780780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.4020780780
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1060461112
Short name T363
Test name
Test status
Simulation time 11246885 ps
CPU time 0.57 seconds
Started Jul 31 07:08:12 PM PDT 24
Finished Jul 31 07:08:12 PM PDT 24
Peak memory 194888 kb
Host smart-425b2836-dee5-4000-b3eb-79e94f9386e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060461112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1060461112
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2373446084
Short name T436
Test name
Test status
Simulation time 11272891594 ps
CPU time 45.05 seconds
Started Jul 31 07:08:00 PM PDT 24
Finished Jul 31 07:08:45 PM PDT 24
Peak memory 200048 kb
Host smart-fcf4c354-640a-47ab-b13f-0033c1cd2335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2373446084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2373446084
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.4187579325
Short name T477
Test name
Test status
Simulation time 8168475792 ps
CPU time 76.48 seconds
Started Jul 31 07:08:08 PM PDT 24
Finished Jul 31 07:09:25 PM PDT 24
Peak memory 200016 kb
Host smart-a82c16dc-a271-4708-ba1e-9d3df120e3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187579325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.4187579325
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2386947071
Short name T297
Test name
Test status
Simulation time 23378821817 ps
CPU time 650.03 seconds
Started Jul 31 07:08:06 PM PDT 24
Finished Jul 31 07:18:57 PM PDT 24
Peak memory 722944 kb
Host smart-fd554d99-3421-4c76-ba35-d7c4692be316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386947071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2386947071
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1554694394
Short name T407
Test name
Test status
Simulation time 2973080624 ps
CPU time 53.8 seconds
Started Jul 31 07:08:11 PM PDT 24
Finished Jul 31 07:09:05 PM PDT 24
Peak memory 200140 kb
Host smart-1d8dec78-55e3-457d-a488-dace6d25d36a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554694394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1554694394
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.4225012855
Short name T88
Test name
Test status
Simulation time 1568333830 ps
CPU time 76.01 seconds
Started Jul 31 07:07:59 PM PDT 24
Finished Jul 31 07:09:15 PM PDT 24
Peak memory 199864 kb
Host smart-10bd79f0-ec87-47c5-81c4-64f071f50713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225012855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.4225012855
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.254640301
Short name T197
Test name
Test status
Simulation time 4608196106 ps
CPU time 16 seconds
Started Jul 31 07:07:59 PM PDT 24
Finished Jul 31 07:08:16 PM PDT 24
Peak memory 200040 kb
Host smart-180f0d8f-298e-44a3-a3a4-44a86c0a947e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254640301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.254640301
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2746799120
Short name T298
Test name
Test status
Simulation time 42855245735 ps
CPU time 558.77 seconds
Started Jul 31 07:08:07 PM PDT 24
Finished Jul 31 07:17:26 PM PDT 24
Peak memory 703224 kb
Host smart-971f09c6-9cf5-4b6a-bd98-f151d1a986b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746799120 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2746799120
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.3477841916
Short name T19
Test name
Test status
Simulation time 56136694618 ps
CPU time 1202.54 seconds
Started Jul 31 07:08:06 PM PDT 24
Finished Jul 31 07:28:09 PM PDT 24
Peak memory 732204 kb
Host smart-dcc03b31-a4d8-45fc-b808-50d3f78fd8d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477841916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.3477841916
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.285255806
Short name T427
Test name
Test status
Simulation time 1985399907 ps
CPU time 9.67 seconds
Started Jul 31 07:08:07 PM PDT 24
Finished Jul 31 07:08:16 PM PDT 24
Peak memory 199940 kb
Host smart-51d1feea-2059-4e29-b630-54d3bbccc519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285255806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.285255806
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3265353243
Short name T196
Test name
Test status
Simulation time 16903077 ps
CPU time 0.58 seconds
Started Jul 31 07:08:18 PM PDT 24
Finished Jul 31 07:08:19 PM PDT 24
Peak memory 196052 kb
Host smart-c0713409-81cb-405d-97fc-40ecb2ac9a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265353243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3265353243
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3431045933
Short name T217
Test name
Test status
Simulation time 5764504024 ps
CPU time 75.41 seconds
Started Jul 31 07:08:13 PM PDT 24
Finished Jul 31 07:09:28 PM PDT 24
Peak memory 200072 kb
Host smart-3a94b53d-f435-4ca6-a590-0a8858353a9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3431045933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3431045933
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.47704669
Short name T362
Test name
Test status
Simulation time 11376952351 ps
CPU time 34.79 seconds
Started Jul 31 07:08:12 PM PDT 24
Finished Jul 31 07:08:47 PM PDT 24
Peak memory 199996 kb
Host smart-33111c51-1103-470d-b5dd-956aca160e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47704669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.47704669
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2296449013
Short name T207
Test name
Test status
Simulation time 9829246254 ps
CPU time 850.11 seconds
Started Jul 31 07:08:16 PM PDT 24
Finished Jul 31 07:22:26 PM PDT 24
Peak memory 641976 kb
Host smart-bd11e441-a655-45d0-9676-fc3a5acff7ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296449013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2296449013
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1816455492
Short name T304
Test name
Test status
Simulation time 2804077745 ps
CPU time 129.69 seconds
Started Jul 31 07:08:12 PM PDT 24
Finished Jul 31 07:10:21 PM PDT 24
Peak memory 200096 kb
Host smart-9a432132-e3e3-411a-99bb-62f8475ba849
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816455492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1816455492
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.389864772
Short name T525
Test name
Test status
Simulation time 20049932090 ps
CPU time 85.6 seconds
Started Jul 31 07:08:11 PM PDT 24
Finished Jul 31 07:09:36 PM PDT 24
Peak memory 200068 kb
Host smart-a8aef1cb-37a3-4902-8874-00dd5d9af7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389864772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.389864772
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3662774195
Short name T223
Test name
Test status
Simulation time 3968858566 ps
CPU time 15.52 seconds
Started Jul 31 07:08:12 PM PDT 24
Finished Jul 31 07:08:28 PM PDT 24
Peak memory 200000 kb
Host smart-c7cc6cd5-96f0-40f6-aefc-c71ee67418b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662774195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3662774195
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3869992165
Short name T349
Test name
Test status
Simulation time 16519038620 ps
CPU time 2843.25 seconds
Started Jul 31 07:08:12 PM PDT 24
Finished Jul 31 07:55:36 PM PDT 24
Peak memory 765288 kb
Host smart-9391f974-8e98-4db3-85b5-091ccde9546e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869992165 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3869992165
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1765814153
Short name T266
Test name
Test status
Simulation time 6200955394 ps
CPU time 108.48 seconds
Started Jul 31 07:08:12 PM PDT 24
Finished Jul 31 07:10:01 PM PDT 24
Peak memory 200004 kb
Host smart-a24f3159-36b3-4d67-af47-09d0c226c791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765814153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1765814153
Directory /workspace/9.hmac_wipe_secret/latest
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