Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	20056580	1			T1	25413		T2	25554		T3	1924
all_values[1]	20056580	1			T1	25413		T2	25554		T3	1924
all_values[2]	20056580	1			T1	25413		T2	25554		T3	1924

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297798

1

T3

1454

T6

377

T18

864

auto[1]

59871942

1

T1

76239

T2

76662

T3

4318

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51091456

1

T1

68876

T2

57167

T3

5362

auto[1]

9078284

1

T1

7363

T2

19495

T3

410

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	90616	1			T9	2798		T10	1		T8	320
all_values[0]	auto[0]	auto[1]	406	1			T9	2		T8	10		T22	6
all_values[0]	auto[1]	auto[0]	19944171	1			T1	25376		T2	25544		T3	1922
all_values[0]	auto[1]	auto[1]	21387	1			T1	37		T2	10		T3	2
all_values[1]	auto[0]	auto[0]	107047	1			T3	450		T6	377		T18	864
all_values[1]	auto[0]	auto[1]	251	1			T8	2		T22	5		T11	11
all_values[1]	auto[1]	auto[0]	19948894	1			T1	25413		T2	25554		T3	1474
all_values[1]	auto[1]	auto[1]	388	1			T8	4		T22	14		T11	16
all_values[2]	auto[0]	auto[0]	48896	1			T3	596		T10	1		T8	112
all_values[2]	auto[0]	auto[1]	50582	1			T3	408		T8	2		T22	10
all_values[2]	auto[1]	auto[0]	10951832	1			T1	18087		T2	6069		T3	920
all_values[2]	auto[1]	auto[1]	9005270	1			T1	7326		T2	19485		T4	599