Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132203

1

T1

44

T2

42

T4

48

auto[1]

134720

1

T1

30

T2

16

T3

2

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	102743	1			T1	26		T2	12		T3	1
len_1026_2046	8016	1			T2	2		T4	2		T6	1
len_514_1022	3295	1			T1	1		T4	7		T8	19
len_2_510	3877	1			T4	4		T8	28		T69	3
len_2056	221	1			T4	5		T10	5		T8	4
len_2048	339	1			T1	1		T4	1		T8	3
len_2040	204	1			T78	2		T76	1		T126	7
len_1032	168	1			T1	1		T4	1		T10	4
len_1024	1814	1			T1	2		T4	3		T8	1
len_1016	191	1			T4	4		T76	6		T127	2
len_520	223	1			T10	5		T22	1		T76	1
len_512	361	1			T4	2		T5	1		T21	1
len_504	282	1			T4	5		T21	2		T76	1
len_8	1310	1			T9	2		T10	20		T8	22
len_0	10418	1			T1	6		T2	15		T4	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

118

1

T1

1

T4

2

T7

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	51245	1			T1	16		T2	8		T6	12
auto[0]	len_1026_2046	3499	1			T4	2		T6	1		T5	1
auto[0]	len_514_1022	2147	1			T4	7		T8	16		T70	1
auto[0]	len_2_510	2908	1			T4	2		T8	22		T69	2
auto[0]	len_2056	117	1			T4	3		T10	5		T8	2
auto[0]	len_2048	190	1			T1	1		T4	1		T8	3
auto[0]	len_2040	108	1			T78	1		T76	1		T126	1
auto[0]	len_1032	86	1			T1	1		T4	1		T10	4
auto[0]	len_1024	283	1			T1	1		T4	3		T8	1
auto[0]	len_1016	102	1			T4	1		T76	3		T127	2
auto[0]	len_520	114	1			T10	1		T76	1		T126	2
auto[0]	len_512	227	1			T4	1		T5	1		T21	1
auto[0]	len_504	172	1			T4	3		T21	2		T76	1
auto[0]	len_8	25	1			T76	1		T11	1		T128	1
auto[0]	len_0	4879	1			T1	3		T2	13		T18	1
auto[1]	len_2050_plus	51498	1			T1	10		T2	4		T3	1
auto[1]	len_1026_2046	4517	1			T2	2		T5	3		T10	1
auto[1]	len_514_1022	1148	1			T1	1		T8	3		T111	4
auto[1]	len_2_510	969	1			T4	2		T8	6		T69	1
auto[1]	len_2056	104	1			T4	2		T8	2		T126	2
auto[1]	len_2048	149	1			T22	2		T126	1		T129	1
auto[1]	len_2040	96	1			T78	1		T126	6		T11	7
auto[1]	len_1032	82	1			T11	2		T130	3		T12	3
auto[1]	len_1024	1531	1			T1	1		T78	2		T22	3
auto[1]	len_1016	89	1			T4	3		T76	3		T11	7
auto[1]	len_520	109	1			T10	4		T22	1		T126	1
auto[1]	len_512	134	1			T4	1		T22	8		T20	1
auto[1]	len_504	110	1			T4	2		T127	2		T11	6
auto[1]	len_8	1285	1			T9	2		T10	20		T8	22
auto[1]	len_0	5539	1			T1	3		T2	2		T4	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

68

1

T1

1

T4

2

T7

2

auto[1]

len_upper

50

1

T22

1

T131

1

T132

1