Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4959739 1 T1 8236 T2 2131 T3 444
auto[1] 3258874 1 T1 4404 T2 1751 T3 488


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3276399 1 T1 4490 T2 936 T4 268
auto[1] 4942214 1 T1 8150 T2 2946 T3 932


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3544121 1 T1 5377 T2 2434 T3 675
auto[1] 4674492 1 T1 7263 T2 1448 T3 257


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4970654 1 T1 7082 T2 2237 T3 488
auto[1] 3247959 1 T1 5558 T2 1645 T3 444


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7368581 1 T1 12445 T2 3827 T3 919
fifo_depth[1] 134051 1 T1 159 T2 42 T3 11
fifo_depth[2] 104365 1 T1 33 T2 12 T3 2
fifo_depth[3] 83390 1 T1 2 T2 1 T4 4
fifo_depth[4] 75390 1 T1 1 T4 3 T6 156
fifo_depth[5] 60047 1 T6 106 T9 56 T7 1
fifo_depth[6] 48192 1 T6 51 T9 68 T7 1
fifo_depth[7] 32444 1 T6 22 T9 40 T7 1


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 850032 1 T1 195 T2 55 T3 13
auto[1] 7368581 1 T1 12445 T2 3827 T3 919


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8206080 1 T1 12640 T2 3882 T3 932
auto[1] 12533 1 T8 5 T26 40 T22 956


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 46576 1 T1 11 T5 38 T10 7
auto[0] auto[0] auto[0] auto[0] auto[1] 39029 1 T6 110 T5 19 T8 1101
auto[0] auto[0] auto[0] auto[1] auto[0] 40448 1 T18 15 T5 12 T8 592
auto[0] auto[0] auto[0] auto[1] auto[1] 40115 1 T1 22 T5 11 T10 2
auto[0] auto[0] auto[1] auto[0] auto[0] 150910 1 T1 6 T4 1 T6 439
auto[0] auto[0] auto[1] auto[0] auto[1] 45650 1 T1 27 T2 3 T3 9
auto[0] auto[0] auto[1] auto[1] auto[0] 47060 1 T1 40 T2 41 T3 4
auto[0] auto[0] auto[1] auto[1] auto[1] 47378 1 T1 15 T4 1 T5 26
auto[0] auto[1] auto[0] auto[0] auto[0] 49279 1 T1 11 T2 6 T7 1
auto[0] auto[1] auto[0] auto[0] auto[1] 51501 1 T1 11 T10 97 T7 2
auto[0] auto[1] auto[0] auto[1] auto[0] 51210 1 T9 339 T8 1048 T69 35
auto[0] auto[1] auto[0] auto[1] auto[1] 47676 1 T6 70 T5 13 T10 29
auto[0] auto[1] auto[1] auto[0] auto[0] 52558 1 T1 17 T5 14 T8 144
auto[0] auto[1] auto[1] auto[0] auto[1] 47589 1 T1 35 T4 2 T6 157
auto[0] auto[1] auto[1] auto[1] auto[0] 39706 1 T2 5 T4 6 T9 140
auto[0] auto[1] auto[1] auto[1] auto[1] 53347 1 T4 5 T6 117 T5 33
auto[1] auto[0] auto[0] auto[0] auto[0] 223433 1 T1 459 T2 190 T4 48
auto[1] auto[0] auto[0] auto[0] auto[1] 173307 1 T2 1 T4 80 T6 943
auto[1] auto[0] auto[0] auto[1] auto[0] 189420 1 T1 470 T2 288 T4 56
auto[1] auto[0] auto[0] auto[1] auto[1] 175578 1 T1 1523 T2 2 T4 11
auto[1] auto[0] auto[1] auto[0] auto[0] 1742077 1 T1 415 T2 31 T4 113
auto[1] auto[0] auto[1] auto[0] auto[1] 190258 1 T1 801 T2 968 T3 435
auto[1] auto[0] auto[1] auto[1] auto[0] 192288 1 T1 1252 T2 909 T3 227
auto[1] auto[0] auto[1] auto[1] auto[1] 200594 1 T1 336 T2 1 T4 112
auto[1] auto[1] auto[0] auto[0] auto[0] 538354 1 T1 1351 T2 445 T4 17
auto[1] auto[1] auto[0] auto[0] auto[1] 511303 1 T1 632 T2 2 T4 45
auto[1] auto[1] auto[0] auto[1] auto[0] 531155 1 T2 1 T4 11 T6 453
auto[1] auto[1] auto[0] auto[1] auto[1] 568015 1 T2 1 T6 817 T9 1301
auto[1] auto[1] auto[1] auto[0] auto[0] 580212 1 T1 2545 T4 14 T6 186
auto[1] auto[1] auto[1] auto[0] auto[1] 517703 1 T1 1915 T2 485 T4 23
auto[1] auto[1] auto[1] auto[1] auto[0] 495968 1 T1 505 T2 321 T3 257
auto[1] auto[1] auto[1] auto[1] auto[1] 538916 1 T1 241 T2 182 T4 60


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 268520 1 T1 470 T2 190 T4 48
auto[0] auto[0] auto[0] auto[0] auto[1] 210992 1 T2 1 T4 80 T6 1053
auto[0] auto[0] auto[0] auto[1] auto[0] 228678 1 T1 470 T2 288 T4 56
auto[0] auto[0] auto[0] auto[1] auto[1] 214947 1 T1 1545 T2 2 T4 11
auto[0] auto[0] auto[1] auto[0] auto[0] 1892244 1 T1 421 T2 31 T4 114
auto[0] auto[0] auto[1] auto[0] auto[1] 234926 1 T1 828 T2 971 T3 444
auto[0] auto[0] auto[1] auto[1] auto[0] 238583 1 T1 1292 T2 950 T3 231
auto[0] auto[0] auto[1] auto[1] auto[1] 246800 1 T1 351 T2 1 T4 113
auto[0] auto[1] auto[0] auto[0] auto[0] 586756 1 T1 1362 T2 451 T4 17
auto[0] auto[1] auto[0] auto[0] auto[1] 562139 1 T1 643 T2 2 T4 45
auto[0] auto[1] auto[0] auto[1] auto[0] 582159 1 T2 1 T4 11 T6 453
auto[0] auto[1] auto[0] auto[1] auto[1] 615305 1 T2 1 T6 887 T9 1301
auto[0] auto[1] auto[1] auto[0] auto[0] 632652 1 T1 2562 T4 14 T6 186
auto[0] auto[1] auto[1] auto[0] auto[1] 565108 1 T1 1950 T2 485 T4 25
auto[0] auto[1] auto[1] auto[1] auto[0] 534589 1 T1 505 T2 326 T3 257
auto[0] auto[1] auto[1] auto[1] auto[1] 591682 1 T1 241 T2 182 T4 65
auto[1] auto[0] auto[0] auto[0] auto[0] 1489 1 T26 20 T22 214 T11 3
auto[1] auto[0] auto[0] auto[0] auto[1] 1344 1 T11 4 T112 361 T85 39
auto[1] auto[0] auto[0] auto[1] auto[0] 1190 1 T22 188 T11 15 T112 16
auto[1] auto[0] auto[0] auto[1] auto[1] 746 1 T11 77 T112 21 T85 295
auto[1] auto[0] auto[1] auto[0] auto[0] 743 1 T8 2 T11 10 T112 125
auto[1] auto[0] auto[1] auto[0] auto[1] 982 1 T26 5 T22 3 T11 19
auto[1] auto[0] auto[1] auto[1] auto[0] 765 1 T26 6 T11 157 T112 27
auto[1] auto[0] auto[1] auto[1] auto[1] 1172 1 T26 2 T22 30 T11 338
auto[1] auto[1] auto[0] auto[0] auto[0] 877 1 T22 45 T11 93 T112 26
auto[1] auto[1] auto[0] auto[0] auto[1] 665 1 T8 1 T22 1 T11 482
auto[1] auto[1] auto[0] auto[1] auto[0] 206 1 T26 3 T22 7 T85 14
auto[1] auto[1] auto[0] auto[1] auto[1] 386 1 T22 12 T11 8 T112 1
auto[1] auto[1] auto[1] auto[0] auto[0] 118 1 T112 15 T51 1 T136 16
auto[1] auto[1] auto[1] auto[0] auto[1] 184 1 T26 4 T112 1 T85 88
auto[1] auto[1] auto[1] auto[1] auto[0] 1085 1 T22 412 T11 359 T87 7
auto[1] auto[1] auto[1] auto[1] auto[1] 581 1 T8 2 T22 44 T11 420


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 223433 1 T1 459 T2 190 T4 48
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 173307 1 T2 1 T4 80 T6 943
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 189420 1 T1 470 T2 288 T4 56
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 175578 1 T1 1523 T2 2 T4 11
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1742077 1 T1 415 T2 31 T4 113
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 190258 1 T1 801 T2 968 T3 435
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 192288 1 T1 1252 T2 909 T3 227
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 200594 1 T1 336 T2 1 T4 112
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 538354 1 T1 1351 T2 445 T4 17
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 511303 1 T1 632 T2 2 T4 45
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 531155 1 T2 1 T4 11 T6 453
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 568015 1 T2 1 T6 817 T9 1301
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 580212 1 T1 2545 T4 14 T6 186
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 517703 1 T1 1915 T2 485 T4 23
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 495968 1 T1 505 T2 321 T3 257
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 538916 1 T1 241 T2 182 T4 60
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 4865 1 T1 10 T5 33 T10 7
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 4113 1 T6 16 T5 13 T8 97
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 4768 1 T18 11 T5 9 T8 17
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3967 1 T1 17 T5 6 T10 2
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 43393 1 T1 5 T4 1 T6 124
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3927 1 T1 21 T2 3 T3 7
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 4367 1 T1 28 T2 30 T3 4
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 4235 1 T1 15 T4 1 T5 20
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 7071 1 T1 10 T2 4 T8 153
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 8074 1 T1 9 T10 72 T8 54
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 7643 1 T9 46 T8 161 T69 25
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 7362 1 T6 16 T5 6 T10 26
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 9379 1 T1 13 T5 13 T8 26
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 7745 1 T1 31 T6 29 T5 1
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 5492 1 T2 5 T4 2 T9 18
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 7650 1 T6 40 T5 27 T8 65
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3703 1 T1 1 T5 4 T8 55
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3447 1 T6 15 T5 6 T8 99
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3848 1 T18 3 T5 3 T8 18
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 3228 1 T1 5 T5 5 T8 67
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 27821 1 T1 1 T6 105 T5 3
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3243 1 T1 5 T3 2 T4 2
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3849 1 T1 10 T2 10 T6 23
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3669 1 T5 6 T10 2 T8 8
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 6041 1 T1 1 T2 2 T8 124
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 6953 1 T1 2 T10 23 T8 46
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 6919 1 T9 53 T8 153 T69 10
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 6195 1 T6 13 T5 5 T10 3
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 7639 1 T1 4 T8 29 T70 131
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 6759 1 T1 4 T6 31 T5 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4671 1 T4 3 T9 25 T5 9
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 6380 1 T4 1 T6 37 T5 6
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2634 1 T5 1 T8 50 T70 14
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2757 1 T6 11 T8 94 T70 32
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 3064 1 T18 1 T8 20 T70 93
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2793 1 T8 54 T70 131 T22 63
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 19653 1 T6 72 T5 2 T8 81
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2553 1 T1 1 T7 1 T8 33
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 3156 1 T1 1 T2 1 T6 31
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 3098 1 T8 5 T69 2 T70 92
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 5152 1 T8 145 T70 10 T26 6
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 5666 1 T10 2 T8 40 T111 28
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 5853 1 T9 51 T8 148 T78 2
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 5220 1 T6 10 T5 2 T8 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 6351 1 T5 1 T8 24 T70 115
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 5656 1 T4 1 T6 28 T10 4
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4150 1 T4 1 T9 22 T8 41
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 5634 1 T4 2 T6 25 T8 68
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2681 1 T8 47 T70 14 T26 8
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2859 1 T6 21 T8 112 T70 31
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 3091 1 T8 26 T70 77 T22 342
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2851 1 T8 67 T70 121 T22 67
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 14078 1 T6 58 T8 122 T70 64
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2575 1 T8 27 T70 23 T22 131
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 3051 1 T1 1 T6 22 T8 59
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 3197 1 T8 3 T70 90 T78 2
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4849 1 T8 144 T70 13 T26 6
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 5320 1 T8 57 T111 24 T22 319
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 5613 1 T9 48 T8 161 T111 37
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4900 1 T6 14 T8 1 T22 240
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5701 1 T8 24 T70 115 T111 10
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 5323 1 T4 1 T6 29 T10 2
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 3939 1 T9 16 T8 46 T111 6
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 5362 1 T4 2 T6 12 T8 70
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 2159 1 T8 39 T70 18 T26 2
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 2188 1 T6 17 T8 95 T70 35
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 2236 1 T8 25 T70 68 T60 1
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 2179 1 T8 54 T70 103 T60 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 9812 1 T6 51 T8 105 T70 52
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1827 1 T7 1 T8 21 T70 18
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 2467 1 T6 9 T8 62 T111 15
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 2381 1 T8 6 T70 72 T78 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 4236 1 T8 116 T70 18 T26 4
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 4647 1 T8 53 T111 13 T22 312
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 4462 1 T9 35 T8 150 T78 2
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 4086 1 T6 8 T8 2 T22 225
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4910 1 T8 23 T70 81 T111 11
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 4449 1 T6 19 T8 98 T22 182
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3308 1 T9 21 T8 43 T111 12
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 4700 1 T6 2 T8 53 T111 10
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1653 1 T8 27 T70 7 T26 2
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1840 1 T6 10 T8 91 T70 25
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1822 1 T8 56 T70 41 T22 192
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1713 1 T7 1 T8 41 T70 57
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 7070 1 T6 20 T8 92 T70 46
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1686 1 T8 16 T70 11 T26 15
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1977 1 T6 5 T8 43 T111 10
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 2181 1 T8 3 T70 42 T26 4
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3295 1 T8 100 T70 7 T26 15
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3761 1 T8 44 T111 16 T22 230
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3829 1 T9 53 T8 96 T111 17
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3370 1 T6 4 T8 1 T60 1
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3946 1 T8 11 T70 48 T111 12
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3715 1 T6 11 T8 74 T22 139
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2623 1 T9 15 T8 30 T111 5
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 3711 1 T6 1 T8 35 T111 9
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1172 1 T7 1 T8 14 T70 11
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1195 1 T6 6 T8 90 T70 18
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1215 1 T8 45 T70 24 T26 2
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1199 1 T8 27 T70 24 T22 25
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4239 1 T6 8 T8 52 T70 25
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1058 1 T8 8 T70 7 T26 13
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1476 1 T6 1 T8 32 T111 6
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1502 1 T8 3 T70 16 T22 55
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2325 1 T8 68 T70 7 T26 13
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2574 1 T8 21 T111 7 T22 192
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2608 1 T9 28 T8 84 T78 1
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2293 1 T6 2 T8 1 T22 99
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2620 1 T8 2 T70 30 T111 8
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2413 1 T6 5 T8 54 T26 2
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1903 1 T9 12 T8 14 T111 4
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2652 1 T8 37 T60 1 T111 5

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