Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	20056580	1			T1	25413		T2	25554		T3	1924
all_pins[1]	20056580	1			T1	25413		T2	25554		T3	1924
all_pins[2]	20056580	1			T1	25413		T2	25554		T3	1924

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	51141688	1			T1	68873		T2	57167		T3	5770
values[0x1]	9028052	1			T1	7366		T2	19495		T3	2
transitions[0x0=>0x1]	9027858	1			T1	7366		T2	19495		T3	2
transitions[0x1=>0x0]	9027868	1			T1	7366		T2	19495		T3	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	20034228	1			T1	25373		T2	25544		T3	1922
all_pins[0]	values[0x1]	22352	1			T1	40		T2	10		T3	2
all_pins[0]	transitions[0x0=>0x1]	22275	1			T1	40		T2	10		T3	2
all_pins[0]	transitions[0x1=>0x0]	9005203	1			T1	7326		T2	19485		T4	599
all_pins[1]	values[0x0]	20056150	1			T1	25413		T2	25554		T3	1924
all_pins[1]	values[0x1]	430	1			T8	5		T22	18		T11	19
all_pins[1]	transitions[0x0=>0x1]	368	1			T8	3		T22	17		T11	16
all_pins[1]	transitions[0x1=>0x0]	22290	1			T1	40		T2	10		T3	2
all_pins[2]	values[0x0]	11051310	1			T1	18087		T2	6069		T3	1924
all_pins[2]	values[0x1]	9005270	1			T1	7326		T2	19485		T4	599
all_pins[2]	transitions[0x0=>0x1]	9005215	1			T1	7326		T2	19485		T4	599
all_pins[2]	transitions[0x1=>0x0]	375	1			T8	5		T22	17		T11	19