Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1200 1 T8 10 T22 20 T76 4
all_values[1] 1200 1 T8 10 T22 20 T76 4
all_values[2] 1200 1 T8 10 T22 20 T76 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1806 1 T8 11 T22 35 T76 5
auto[1] 1794 1 T8 19 T22 25 T76 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1296 1 T8 11 T22 21 T76 10
auto[1] 2304 1 T8 19 T22 39 T76 2


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2073 1 T8 19 T22 33 T76 11
auto[1] 1527 1 T8 11 T22 27 T76 1


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 233 1 T22 2 T76 1 T11 6
all_values[0] auto[0] auto[0] auto[1] 117 1 T8 2 T22 2 T112 1
all_values[0] auto[0] auto[1] auto[0] 229 1 T22 5 T76 3 T11 9
all_values[0] auto[0] auto[1] auto[1] 130 1 T8 3 T22 3 T11 7
all_values[0] auto[1] auto[0] auto[1] 231 1 T8 2 T22 4 T11 2
all_values[0] auto[1] auto[1] auto[1] 260 1 T8 3 T22 4 T11 14
all_values[1] auto[0] auto[0] auto[0] 211 1 T8 1 T22 6 T76 2
all_values[1] auto[0] auto[0] auto[1] 154 1 T8 1 T22 2 T11 5
all_values[1] auto[0] auto[1] auto[0] 191 1 T8 2 T22 3 T76 2
all_values[1] auto[0] auto[1] auto[1] 142 1 T8 2 T22 2 T11 4
all_values[1] auto[1] auto[0] auto[1] 253 1 T8 1 T22 4 T11 10
all_values[1] auto[1] auto[1] auto[1] 249 1 T8 3 T22 3 T11 9
all_values[2] auto[0] auto[0] auto[0] 209 1 T8 3 T22 3 T76 1
all_values[2] auto[0] auto[0] auto[1] 125 1 T22 3 T76 1 T11 2
all_values[2] auto[0] auto[1] auto[0] 223 1 T8 5 T22 2 T76 1
all_values[2] auto[0] auto[1] auto[1] 109 1 T11 6 T112 2 T114 4
all_values[2] auto[1] auto[0] auto[1] 273 1 T8 1 T22 9 T11 7
all_values[2] auto[1] auto[1] auto[1] 261 1 T8 1 T22 3 T76 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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