Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4760	1			T1	4		T2	18		T3	1
sha2_none	4894	1			T1	6		T2	2		T4	12
sha2_512	8335	1			T1	9		T2	11		T4	8
sha2_384	7865	1			T1	11		T2	6		T3	2
sha2_256	7006	1			T1	11		T2	4		T4	8

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20221

1

T1

25

T2

20

T3

1

auto[1]

13055

1

T1

16

T2

22

T3

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12866

1

T1

18

T2

16

T4

18

auto[1]

20410

1

T1

23

T2

26

T3

3

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17373

1

T1

20

T2

21

T3

1

disabled

15903

1

T1

21

T2

21

T3

2

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5276	1			T1	9		T2	22		T3	2
key_none	8224	1			T1	5		T2	5		T4	7
key_1024	4760	1			T1	7		T2	2		T3	1
key_512	4236	1			T1	5		T2	2		T4	6
key_384	3780	1			T1	4		T2	2		T4	8
key_256	3528	1			T1	10		T2	2		T4	2
key_128	3370	1			T1	1		T2	7		T4	5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20602

1

T1

23

T2

23

T3

2

auto[1]

12674

1

T1

18

T2

19

T3

1

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

33046

1

T1

41

T2

38

T3

3

disabled

230

1

T2

4

T6

1

T5

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1868

1

T1

4

T2

5

T4

1

enabled

auto[0]

auto[0]

auto[1]

1748

1

T1

3

T2

1

T4

2

enabled

auto[0]

auto[1]

auto[0]

1821

1

T4

1

T6

1

T9

1

enabled

auto[0]

auto[1]

auto[1]

1927

1

T2

3

T6

3

T9

2

enabled

auto[1]

auto[0]

auto[0]

4557

1

T1

6

T2

1

T4

2

enabled

auto[1]

auto[0]

auto[1]

1703

1

T1

4

T2

3

T4

2

enabled

auto[1]

auto[1]

auto[0]

1977

1

T1

2

T2

5

T3

1

enabled

auto[1]

auto[1]

auto[1]

1772

1

T1

1

T2

3

T4

3

disabled

auto[0]

auto[0]

auto[0]

1403

1

T1

3

T2

2

T4

5

disabled

auto[0]

auto[0]

auto[1]

1331

1

T4

4

T6

3

T5

5

disabled

auto[0]

auto[1]

auto[0]

1392

1

T1

1

T2

3

T4

4

disabled

auto[0]

auto[1]

auto[1]

1376

1

T1

7

T2

2

T4

1

disabled

auto[1]

auto[0]

auto[0]

6240

1

T1

3

T2

3

T4

5

disabled

auto[1]

auto[0]

auto[1]

1371

1

T1

2

T2

5

T3

1

disabled

auto[1]

auto[1]

auto[0]

1344

1

T1

4

T2

4

T3

1

disabled

auto[1]

auto[1]

auto[1]

1446

1

T1

1

T2

2

T4

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17280

1

T1

20

T2

20

T3

1

enabled

disabled

93

1

T2

1

T6

1

T5

1

disabled

disabled

137

1

T2

3

T5

1

T10

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15766

1

T1

21

T2

18

T3

2

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1208	1			T1	2		T2	12		T3	1
key_invalid	sha2_none	981	1			T1	3		T2	2		T4	4
key_invalid	sha2_512	1015	1			T2	3		T4	2		T9	2
key_invalid	sha2_384	991	1			T1	2		T2	4		T3	1
key_invalid	sha2_256	976	1			T1	2		T4	1		T9	1
key_none	sha2_invalid	588	1			T2	1		T4	1		T9	1
key_none	sha2_none	690	1			T1	1		T4	2		T6	1
key_none	sha2_512	2623	1			T1	1		T2	1		T4	2
key_none	sha2_384	2603	1			T1	2		T2	1		T5	8
key_none	sha2_256	1679	1			T1	1		T2	2		T4	2
key_1024	sha2_invalid	554	1			T2	1		T4	1		T6	1
key_1024	sha2_none	638	1			T4	1		T5	1		T10	4
key_1024	sha2_512	1869	1			T1	1		T9	1		T5	4
key_1024	sha2_384	985	1			T1	4		T3	1		T4	2
key_512	sha2_invalid	595	1			T6	1		T5	5		T7	1
key_512	sha2_none	662	1			T4	1		T6	2		T9	3
key_512	sha2_512	695	1			T1	2		T2	2		T4	2
key_512	sha2_384	1287	1			T1	1		T4	2		T6	2
key_512	sha2_256	939	1			T1	2		T4	1		T5	2
key_384	sha2_invalid	633	1			T1	1		T2	1		T4	2
key_384	sha2_none	620	1			T1	1		T4	2		T6	2
key_384	sha2_512	686	1			T2	1		T4	1		T18	1
key_384	sha2_384	631	1			T4	1		T6	2		T5	5
key_384	sha2_256	1142	1			T1	2		T4	2		T6	3
key_256	sha2_invalid	586	1			T1	1		T2	1		T4	1
key_256	sha2_none	639	1			T1	1		T5	3		T10	3
key_256	sha2_512	723	1			T1	5		T6	1		T5	2
key_256	sha2_384	641	1			T1	1		T5	3		T10	3
key_256	sha2_256	898	1			T1	2		T2	1		T5	4
key_128	sha2_invalid	566	1			T2	2		T4	1		T5	7
key_128	sha2_none	649	1			T4	1		T6	1		T5	2
key_128	sha2_512	708	1			T2	4		T4	1		T6	2
key_128	sha2_384	710	1			T1	1		T2	1		T4	1
key_128	sha2_256	688	1			T4	1		T5	3		T10	3

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

661

1

T1

2

T2

1

T4

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1208	1			T1	2		T2	12		T3	1
key_invalid	sha2_none	981	1			T1	3		T2	2		T4	4
key_invalid	sha2_512	1015	1			T2	3		T4	2		T9	2
key_invalid	sha2_384	991	1			T1	2		T2	4		T3	1
key_invalid	sha2_256	976	1			T1	2		T4	1		T9	1
key_none	sha2_invalid	588	1			T2	1		T4	1		T9	1
key_none	sha2_none	690	1			T1	1		T4	2		T6	1
key_none	sha2_512	2623	1			T1	1		T2	1		T4	2
key_none	sha2_384	2603	1			T1	2		T2	1		T5	8
key_none	sha2_256	1679	1			T1	1		T2	2		T4	2
key_1024	sha2_invalid	554	1			T2	1		T4	1		T6	1
key_1024	sha2_none	638	1			T4	1		T5	1		T10	4
key_1024	sha2_512	1869	1			T1	1		T9	1		T5	4
key_1024	sha2_384	985	1			T1	4		T3	1		T4	2
key_1024	sha2_256	661	1			T1	2		T2	1		T4	1
key_512	sha2_invalid	595	1			T6	1		T5	5		T7	1
key_512	sha2_none	662	1			T4	1		T6	2		T9	3
key_512	sha2_512	695	1			T1	2		T2	2		T4	2
key_512	sha2_384	1287	1			T1	1		T4	2		T6	2
key_512	sha2_256	939	1			T1	2		T4	1		T5	2
key_384	sha2_invalid	633	1			T1	1		T2	1		T4	2
key_384	sha2_none	620	1			T1	1		T4	2		T6	2
key_384	sha2_512	686	1			T2	1		T4	1		T18	1
key_384	sha2_384	631	1			T4	1		T6	2		T5	5
key_384	sha2_256	1142	1			T1	2		T4	2		T6	3
key_256	sha2_invalid	586	1			T1	1		T2	1		T4	1
key_256	sha2_none	639	1			T1	1		T5	3		T10	3
key_256	sha2_512	723	1			T1	5		T6	1		T5	2
key_256	sha2_384	641	1			T1	1		T5	3		T10	3
key_256	sha2_256	898	1			T1	2		T2	1		T5	4
key_128	sha2_invalid	566	1			T2	2		T4	1		T5	7
key_128	sha2_none	649	1			T4	1		T6	1		T5	2
key_128	sha2_512	708	1			T2	4		T4	1		T6	2
key_128	sha2_384	710	1			T1	1		T2	1		T4	1
key_128	sha2_256	688	1			T4	1		T5	3		T10	3