Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.46 95.40 97.22 100.00 100.00 98.27 98.48 99.85


Total test records in report: 660
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T534 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3252350018 Aug 01 06:48:21 PM PDT 24 Aug 01 06:48:22 PM PDT 24 47731181 ps
T74 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3995957102 Aug 01 06:48:35 PM PDT 24 Aug 01 06:48:38 PM PDT 24 86796525 ps
T90 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4006548856 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:34 PM PDT 24 62843193 ps
T75 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1611664119 Aug 01 06:48:41 PM PDT 24 Aug 01 06:48:43 PM PDT 24 87252737 ps
T105 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.615407944 Aug 01 06:48:42 PM PDT 24 Aug 01 06:48:45 PM PDT 24 121283945 ps
T535 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1714277286 Aug 01 06:48:51 PM PDT 24 Aug 01 06:48:52 PM PDT 24 98704636 ps
T536 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2166680367 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:34 PM PDT 24 39343032 ps
T537 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1374253003 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:33 PM PDT 24 107884429 ps
T91 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2007157936 Aug 01 06:48:21 PM PDT 24 Aug 01 06:48:22 PM PDT 24 26945697 ps
T92 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1441575488 Aug 01 06:48:27 PM PDT 24 Aug 01 06:48:28 PM PDT 24 27059937 ps
T93 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1184077694 Aug 01 06:48:20 PM PDT 24 Aug 01 06:48:21 PM PDT 24 51362775 ps
T538 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2945925479 Aug 01 06:48:52 PM PDT 24 Aug 01 06:48:53 PM PDT 24 81512037 ps
T539 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1774887468 Aug 01 06:48:50 PM PDT 24 Aug 01 06:48:51 PM PDT 24 16317789 ps
T94 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1977828453 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:39 PM PDT 24 634378938 ps
T115 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1926255657 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:34 PM PDT 24 149617750 ps
T540 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1609823989 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:31 PM PDT 24 41763140 ps
T116 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2636100687 Aug 01 06:48:20 PM PDT 24 Aug 01 06:48:24 PM PDT 24 275943379 ps
T106 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.973377587 Aug 01 06:48:43 PM PDT 24 Aug 01 06:48:45 PM PDT 24 429189108 ps
T107 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1197345254 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:35 PM PDT 24 355101494 ps
T541 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3284799133 Aug 01 06:48:34 PM PDT 24 Aug 01 06:48:36 PM PDT 24 62345555 ps
T108 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1856313960 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:31 PM PDT 24 327970914 ps
T542 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3264451766 Aug 01 06:48:17 PM PDT 24 Aug 01 06:48:18 PM PDT 24 45746736 ps
T543 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2862200549 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:31 PM PDT 24 288690752 ps
T544 /workspace/coverage/cover_reg_top/36.hmac_intr_test.71348283 Aug 01 06:48:52 PM PDT 24 Aug 01 06:48:53 PM PDT 24 18974834 ps
T545 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1836790218 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:35 PM PDT 24 299211638 ps
T546 /workspace/coverage/cover_reg_top/21.hmac_intr_test.603168262 Aug 01 06:48:52 PM PDT 24 Aug 01 06:48:52 PM PDT 24 19973196 ps
T547 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2130587666 Aug 01 06:48:32 PM PDT 24 Aug 01 06:48:33 PM PDT 24 52182382 ps
T548 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2701269018 Aug 01 06:48:58 PM PDT 24 Aug 01 06:48:59 PM PDT 24 29921721 ps
T109 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2967913015 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:32 PM PDT 24 100409595 ps
T549 /workspace/coverage/cover_reg_top/4.hmac_intr_test.227359228 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:33 PM PDT 24 23277408 ps
T110 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.310831127 Aug 01 06:48:38 PM PDT 24 Aug 01 06:48:40 PM PDT 24 418120068 ps
T550 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.555799151 Aug 01 06:48:32 PM PDT 24 Aug 01 06:48:34 PM PDT 24 234627902 ps
T551 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1471245372 Aug 01 06:48:58 PM PDT 24 Aug 01 06:48:59 PM PDT 24 42515122 ps
T552 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2105997821 Aug 01 06:48:43 PM PDT 24 Aug 01 06:48:45 PM PDT 24 488246973 ps
T553 /workspace/coverage/cover_reg_top/44.hmac_intr_test.165979958 Aug 01 06:48:54 PM PDT 24 Aug 01 06:48:55 PM PDT 24 21218802 ps
T554 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2495656038 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:43 PM PDT 24 410346599 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4287185027 Aug 01 06:48:17 PM PDT 24 Aug 01 06:48:18 PM PDT 24 147790625 ps
T555 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1128930553 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:32 PM PDT 24 234876963 ps
T556 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2452193008 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:36 PM PDT 24 111897946 ps
T96 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3545082797 Aug 01 06:48:42 PM PDT 24 Aug 01 06:48:43 PM PDT 24 18619244 ps
T557 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3682507248 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:33 PM PDT 24 28800449 ps
T558 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2672304700 Aug 01 06:48:53 PM PDT 24 Aug 01 06:48:53 PM PDT 24 66119982 ps
T559 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2902854119 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:31 PM PDT 24 38530851 ps
T560 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1138296243 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:31 PM PDT 24 186884090 ps
T119 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2143606652 Aug 01 06:48:22 PM PDT 24 Aug 01 06:48:25 PM PDT 24 161371095 ps
T561 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3670889347 Aug 01 06:48:57 PM PDT 24 Aug 01 06:48:58 PM PDT 24 17064662 ps
T562 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2412085843 Aug 01 06:48:30 PM PDT 24 Aug 01 07:04:35 PM PDT 24 102783758383 ps
T563 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2444670676 Aug 01 06:48:55 PM PDT 24 Aug 01 06:48:56 PM PDT 24 44580610 ps
T564 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3486991877 Aug 01 06:48:17 PM PDT 24 Aug 01 06:48:20 PM PDT 24 568554223 ps
T565 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3356320320 Aug 01 06:48:18 PM PDT 24 Aug 01 06:48:21 PM PDT 24 111881973 ps
T122 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2955779715 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:44 PM PDT 24 167793729 ps
T566 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2099491644 Aug 01 06:48:41 PM PDT 24 Aug 01 06:48:42 PM PDT 24 60189530 ps
T567 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3125056939 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:45 PM PDT 24 5704875895 ps
T568 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.787991183 Aug 01 06:48:41 PM PDT 24 Aug 01 06:48:43 PM PDT 24 123054475 ps
T569 /workspace/coverage/cover_reg_top/32.hmac_intr_test.481268601 Aug 01 06:48:53 PM PDT 24 Aug 01 06:48:54 PM PDT 24 30959028 ps
T97 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3944164929 Aug 01 06:48:21 PM PDT 24 Aug 01 06:48:35 PM PDT 24 324417735 ps
T570 /workspace/coverage/cover_reg_top/40.hmac_intr_test.145475840 Aug 01 06:48:53 PM PDT 24 Aug 01 06:48:54 PM PDT 24 13890266 ps
T571 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.57882730 Aug 01 06:48:44 PM PDT 24 Aug 01 06:48:47 PM PDT 24 261386389 ps
T572 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1853138834 Aug 01 06:48:34 PM PDT 24 Aug 01 06:48:36 PM PDT 24 483966408 ps
T98 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2742566825 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:32 PM PDT 24 13064542 ps
T573 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3404422276 Aug 01 06:48:54 PM PDT 24 Aug 01 06:48:55 PM PDT 24 42656309 ps
T574 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1795736041 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:34 PM PDT 24 24608638 ps
T575 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2608616502 Aug 01 06:48:20 PM PDT 24 Aug 01 06:48:22 PM PDT 24 36945712 ps
T576 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3347091424 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:36 PM PDT 24 108220566 ps
T577 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3636310208 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:32 PM PDT 24 116785928 ps
T578 /workspace/coverage/cover_reg_top/31.hmac_intr_test.312664660 Aug 01 06:48:54 PM PDT 24 Aug 01 06:48:55 PM PDT 24 26962416 ps
T579 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2044671970 Aug 01 06:48:55 PM PDT 24 Aug 01 06:48:56 PM PDT 24 46362030 ps
T580 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1475065165 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:35 PM PDT 24 424283370 ps
T581 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3363885189 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:41 PM PDT 24 550056790 ps
T582 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2812811456 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:41 PM PDT 24 56859409 ps
T583 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1164981003 Aug 01 06:48:18 PM PDT 24 Aug 01 06:48:24 PM PDT 24 1526864242 ps
T584 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1413683990 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:32 PM PDT 24 25397424 ps
T99 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1240090974 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:34 PM PDT 24 27318853 ps
T100 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3185744735 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:40 PM PDT 24 9672080948 ps
T585 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2469051825 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:44 PM PDT 24 139515380 ps
T586 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1923337725 Aug 01 06:48:42 PM PDT 24 Aug 01 06:48:45 PM PDT 24 82458819 ps
T123 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3361376465 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:35 PM PDT 24 162411569 ps
T587 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4191083428 Aug 01 06:48:39 PM PDT 24 Aug 01 06:48:43 PM PDT 24 711373878 ps
T588 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1005351233 Aug 01 06:48:39 PM PDT 24 Aug 01 06:48:41 PM PDT 24 1272131263 ps
T101 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1109701967 Aug 01 06:48:18 PM PDT 24 Aug 01 06:48:26 PM PDT 24 153958594 ps
T589 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.836978706 Aug 01 06:48:19 PM PDT 24 Aug 01 06:48:21 PM PDT 24 135082440 ps
T590 /workspace/coverage/cover_reg_top/26.hmac_intr_test.819523512 Aug 01 06:48:54 PM PDT 24 Aug 01 06:48:55 PM PDT 24 16610430 ps
T591 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3869659818 Aug 01 06:48:28 PM PDT 24 Aug 01 06:52:50 PM PDT 24 111715962096 ps
T592 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1638799858 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:42 PM PDT 24 81663209 ps
T118 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3391424482 Aug 01 06:48:44 PM PDT 24 Aug 01 06:48:48 PM PDT 24 261255124 ps
T102 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2530824192 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:42 PM PDT 24 16660886 ps
T593 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3752956629 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:31 PM PDT 24 26955141 ps
T594 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1277496803 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:32 PM PDT 24 351186238 ps
T595 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1186312048 Aug 01 06:48:55 PM PDT 24 Aug 01 06:48:56 PM PDT 24 24542001 ps
T596 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4285308443 Aug 01 06:48:41 PM PDT 24 Aug 01 06:48:43 PM PDT 24 44306150 ps
T597 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4039772380 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:42 PM PDT 24 56223195 ps
T598 /workspace/coverage/cover_reg_top/49.hmac_intr_test.4111262434 Aug 01 06:48:54 PM PDT 24 Aug 01 06:48:55 PM PDT 24 46670369 ps
T103 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3617583602 Aug 01 06:48:41 PM PDT 24 Aug 01 06:48:42 PM PDT 24 62052926 ps
T599 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.359297952 Aug 01 06:48:41 PM PDT 24 Aug 01 06:48:43 PM PDT 24 122542907 ps
T120 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2207458824 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:30 PM PDT 24 98009358 ps
T117 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4243554996 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:43 PM PDT 24 82892172 ps
T121 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.245322828 Aug 01 06:48:20 PM PDT 24 Aug 01 06:48:25 PM PDT 24 256374567 ps
T600 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3970131213 Aug 01 06:48:42 PM PDT 24 Aug 01 06:48:43 PM PDT 24 14636902 ps
T601 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2498676351 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:30 PM PDT 24 27281015 ps
T602 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3656304829 Aug 01 06:48:40 PM PDT 24 Aug 01 06:59:25 PM PDT 24 242882262179 ps
T125 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2654525886 Aug 01 06:48:38 PM PDT 24 Aug 01 06:48:42 PM PDT 24 4182832882 ps
T603 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2806075393 Aug 01 06:48:41 PM PDT 24 Aug 01 06:48:44 PM PDT 24 1056998452 ps
T604 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.463454140 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:32 PM PDT 24 210754490 ps
T605 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1919579199 Aug 01 06:48:20 PM PDT 24 Aug 01 06:48:21 PM PDT 24 170777760 ps
T606 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2681622778 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:32 PM PDT 24 159102123 ps
T607 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4062503484 Aug 01 06:48:42 PM PDT 24 Aug 01 06:48:44 PM PDT 24 523221749 ps
T608 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.626060749 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:42 PM PDT 24 177708999 ps
T609 /workspace/coverage/cover_reg_top/12.hmac_intr_test.4174270294 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:41 PM PDT 24 12308691 ps
T610 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2058012193 Aug 01 06:48:54 PM PDT 24 Aug 01 06:48:55 PM PDT 24 14359379 ps
T611 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1774190677 Aug 01 06:48:41 PM PDT 24 Aug 01 06:48:41 PM PDT 24 25334629 ps
T612 /workspace/coverage/cover_reg_top/27.hmac_intr_test.421342020 Aug 01 06:48:52 PM PDT 24 Aug 01 06:48:53 PM PDT 24 17111322 ps
T613 /workspace/coverage/cover_reg_top/47.hmac_intr_test.120403316 Aug 01 06:48:53 PM PDT 24 Aug 01 06:48:54 PM PDT 24 12413673 ps
T614 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4197921314 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:32 PM PDT 24 168268462 ps
T615 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3834750110 Aug 01 06:48:54 PM PDT 24 Aug 01 06:48:55 PM PDT 24 55934424 ps
T616 /workspace/coverage/cover_reg_top/2.hmac_intr_test.517328355 Aug 01 06:48:20 PM PDT 24 Aug 01 06:48:21 PM PDT 24 16300468 ps
T617 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2685678307 Aug 01 06:48:21 PM PDT 24 Aug 01 06:48:23 PM PDT 24 137425719 ps
T618 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3164062600 Aug 01 06:48:43 PM PDT 24 Aug 01 06:48:44 PM PDT 24 151585229 ps
T619 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2981427631 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:40 PM PDT 24 53857337 ps
T620 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1470694028 Aug 01 06:48:20 PM PDT 24 Aug 01 06:48:21 PM PDT 24 12797588 ps
T621 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2556271738 Aug 01 06:48:43 PM PDT 24 Aug 01 06:48:44 PM PDT 24 28449408 ps
T622 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3381106946 Aug 01 06:48:44 PM PDT 24 Aug 01 06:48:46 PM PDT 24 310569165 ps
T623 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2056534531 Aug 01 06:48:32 PM PDT 24 Aug 01 06:48:33 PM PDT 24 39013773 ps
T624 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3692505881 Aug 01 06:48:28 PM PDT 24 Aug 01 06:48:28 PM PDT 24 54944950 ps
T625 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3408868262 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:34 PM PDT 24 1124192361 ps
T626 /workspace/coverage/cover_reg_top/28.hmac_intr_test.990014913 Aug 01 06:48:53 PM PDT 24 Aug 01 06:48:53 PM PDT 24 16747050 ps
T627 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2946010995 Aug 01 06:48:54 PM PDT 24 Aug 01 06:48:55 PM PDT 24 131214549 ps
T628 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3225345424 Aug 01 06:48:50 PM PDT 24 Aug 01 06:48:51 PM PDT 24 28519008 ps
T629 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1326562274 Aug 01 06:48:32 PM PDT 24 Aug 01 06:48:33 PM PDT 24 92042320 ps
T630 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.655184304 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:41 PM PDT 24 68741674 ps
T631 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2556199730 Aug 01 06:48:43 PM PDT 24 Aug 01 06:48:45 PM PDT 24 102080826 ps
T632 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1538999775 Aug 01 06:48:39 PM PDT 24 Aug 01 06:48:42 PM PDT 24 87453298 ps
T633 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3035895197 Aug 01 06:48:32 PM PDT 24 Aug 01 06:51:48 PM PDT 24 74204439839 ps
T634 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2674021957 Aug 01 06:48:51 PM PDT 24 Aug 01 06:48:52 PM PDT 24 60590709 ps
T635 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1759589489 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:41 PM PDT 24 15709445 ps
T636 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1527749656 Aug 01 06:48:40 PM PDT 24 Aug 01 06:48:43 PM PDT 24 627822265 ps
T637 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1661544275 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:34 PM PDT 24 240509247 ps
T638 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3487536717 Aug 01 06:48:54 PM PDT 24 Aug 01 06:48:56 PM PDT 24 258706321 ps
T639 /workspace/coverage/cover_reg_top/33.hmac_intr_test.914960235 Aug 01 06:48:53 PM PDT 24 Aug 01 06:48:54 PM PDT 24 29290355 ps
T640 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2885221915 Aug 01 06:48:41 PM PDT 24 Aug 01 06:48:42 PM PDT 24 89440835 ps
T641 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1814152807 Aug 01 06:48:54 PM PDT 24 Aug 01 06:48:55 PM PDT 24 20270100 ps
T642 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1436510048 Aug 01 06:48:43 PM PDT 24 Aug 01 06:48:44 PM PDT 24 80068364 ps
T643 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1621271448 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:30 PM PDT 24 119836266 ps
T644 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.271785646 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:36 PM PDT 24 95368805 ps
T645 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1115351592 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:31 PM PDT 24 18414450 ps
T646 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.290548228 Aug 01 06:48:42 PM PDT 24 Aug 01 06:48:45 PM PDT 24 1743273393 ps
T647 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3194749333 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:30 PM PDT 24 17775122 ps
T648 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3670496312 Aug 01 06:48:58 PM PDT 24 Aug 01 06:48:59 PM PDT 24 47492544 ps
T649 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3775808857 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:34 PM PDT 24 24334891 ps
T650 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.973482749 Aug 01 06:48:21 PM PDT 24 Aug 01 06:48:24 PM PDT 24 157680273 ps
T651 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3533122474 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:32 PM PDT 24 137064760 ps
T652 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3008458778 Aug 01 06:48:33 PM PDT 24 Aug 01 06:48:36 PM PDT 24 448032359 ps
T124 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.909706698 Aug 01 06:48:39 PM PDT 24 Aug 01 06:48:41 PM PDT 24 63657357 ps
T653 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2588329766 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:32 PM PDT 24 80305206 ps
T654 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3079661398 Aug 01 06:48:31 PM PDT 24 Aug 01 06:48:32 PM PDT 24 28071831 ps
T655 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.353945970 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:35 PM PDT 24 476922296 ps
T656 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3027641475 Aug 01 06:48:41 PM PDT 24 Aug 01 06:48:42 PM PDT 24 141242018 ps
T657 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1327344235 Aug 01 06:48:21 PM PDT 24 Aug 01 06:48:22 PM PDT 24 18837230 ps
T658 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3872587057 Aug 01 06:48:28 PM PDT 24 Aug 01 06:48:29 PM PDT 24 68104192 ps
T659 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3822195798 Aug 01 06:48:30 PM PDT 24 Aug 01 06:48:32 PM PDT 24 35778030 ps
T660 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1013842497 Aug 01 06:48:29 PM PDT 24 Aug 01 06:48:29 PM PDT 24 14391904 ps

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3474871309
Short name T10
Test name
Test status
Simulation time 42944674134 ps
CPU time 1411.7 seconds
Started Aug 01 06:26:34 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 724948 kb
Host smart-0ebd7fbe-b107-4dcc-ad02-721e46360dcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474871309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3474871309
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1446083922
Short name T22
Test name
Test status
Simulation time 115422812225 ps
CPU time 3047.26 seconds
Started Aug 01 06:27:05 PM PDT 24
Finished Aug 01 07:17:53 PM PDT 24
Peak memory 778180 kb
Host smart-98ea4e44-cf50-481d-b81c-4b27bd2e9ffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446083922 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1446083922
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_smoke.37321734
Short name T4
Test name
Test status
Simulation time 717141446 ps
CPU time 12.17 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:28:36 PM PDT 24
Peak memory 199884 kb
Host smart-b822083d-320b-4303-b844-cb86703238c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37321734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.37321734
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3701251331
Short name T25
Test name
Test status
Simulation time 393887249833 ps
CPU time 7029.24 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 08:24:06 PM PDT 24
Peak memory 860800 kb
Host smart-82ee73cb-262a-4e2e-a895-15be8204fc4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701251331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3701251331
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2636100687
Short name T116
Test name
Test status
Simulation time 275943379 ps
CPU time 4.27 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:24 PM PDT 24
Peak memory 200136 kb
Host smart-540b04b1-f154-4697-bd89-4721ae7cff3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636100687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2636100687
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2652161245
Short name T23
Test name
Test status
Simulation time 116142867792 ps
CPU time 7324.84 seconds
Started Aug 01 06:27:00 PM PDT 24
Finished Aug 01 08:29:06 PM PDT 24
Peak memory 827672 kb
Host smart-3fd85f92-54bf-4edb-bb0d-73dfe21f1159
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652161245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2652161245
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3124320018
Short name T19
Test name
Test status
Simulation time 96465337 ps
CPU time 1 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 06:26:57 PM PDT 24
Peak memory 219532 kb
Host smart-a6621be7-0b75-4ecf-b2ab-c73727adca1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124320018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3124320018
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2007157936
Short name T91
Test name
Test status
Simulation time 26945697 ps
CPU time 0.78 seconds
Started Aug 01 06:48:21 PM PDT 24
Finished Aug 01 06:48:22 PM PDT 24
Peak memory 199448 kb
Host smart-ed806a1b-acb8-42c4-9a74-2c832cf13ef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007157936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2007157936
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2126851248
Short name T11
Test name
Test status
Simulation time 989048611908 ps
CPU time 6162.93 seconds
Started Aug 01 06:26:59 PM PDT 24
Finished Aug 01 08:09:43 PM PDT 24
Peak memory 847152 kb
Host smart-8a63dbce-1533-4e7c-b3b4-706a720c102e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126851248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2126851248
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3769452867
Short name T8
Test name
Test status
Simulation time 44055506107 ps
CPU time 1442.43 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:51:07 PM PDT 24
Peak memory 742748 kb
Host smart-8bd6b195-07a4-492a-a8d1-a3f2660b3215
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769452867 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3769452867
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2654525886
Short name T125
Test name
Test status
Simulation time 4182832882 ps
CPU time 4.18 seconds
Started Aug 01 06:48:38 PM PDT 24
Finished Aug 01 06:48:42 PM PDT 24
Peak memory 200220 kb
Host smart-4a9d6899-d1e0-4a8f-bfec-f0699f088779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654525886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2654525886
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2380876080
Short name T112
Test name
Test status
Simulation time 26983550955 ps
CPU time 3036.91 seconds
Started Aug 01 06:26:59 PM PDT 24
Finished Aug 01 07:17:36 PM PDT 24
Peak memory 826472 kb
Host smart-c2aed29b-082c-4f9e-afb4-fcc09ad745ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380876080 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2380876080
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1218326774
Short name T36
Test name
Test status
Simulation time 13241666 ps
CPU time 0.61 seconds
Started Aug 01 06:26:54 PM PDT 24
Finished Aug 01 06:26:55 PM PDT 24
Peak memory 195600 kb
Host smart-7cc5a5ea-6fa4-413d-9bab-b8f367c25e3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218326774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1218326774
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.245322828
Short name T121
Test name
Test status
Simulation time 256374567 ps
CPU time 4.04 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:25 PM PDT 24
Peak memory 200092 kb
Host smart-8a58ceca-0174-4011-afbb-e1e98c99323a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245322828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.245322828
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.454082705
Short name T20
Test name
Test status
Simulation time 1660957914 ps
CPU time 88.4 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:29:20 PM PDT 24
Peak memory 199852 kb
Host smart-f997c710-0f1c-42e5-ac33-7b32cb5e2e82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454082705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.454082705
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3995957102
Short name T74
Test name
Test status
Simulation time 86796525 ps
CPU time 2.93 seconds
Started Aug 01 06:48:35 PM PDT 24
Finished Aug 01 06:48:38 PM PDT 24
Peak memory 200184 kb
Host smart-2cd076a4-7722-4806-bd2f-8a99a80b33cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995957102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3995957102
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.973482749
Short name T650
Test name
Test status
Simulation time 157680273 ps
CPU time 3.44 seconds
Started Aug 01 06:48:21 PM PDT 24
Finished Aug 01 06:48:24 PM PDT 24
Peak memory 200052 kb
Host smart-9ea7cf11-2e3d-4de9-8c64-eb7c59bfcd29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973482749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.973482749
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1164981003
Short name T583
Test name
Test status
Simulation time 1526864242 ps
CPU time 5.31 seconds
Started Aug 01 06:48:18 PM PDT 24
Finished Aug 01 06:48:24 PM PDT 24
Peak memory 200116 kb
Host smart-2b9da1f3-d1a2-40f1-ab8d-1afebf3d10f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164981003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1164981003
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4287185027
Short name T95
Test name
Test status
Simulation time 147790625 ps
CPU time 1.01 seconds
Started Aug 01 06:48:17 PM PDT 24
Finished Aug 01 06:48:18 PM PDT 24
Peak memory 199680 kb
Host smart-7673269f-1a95-476f-b7a4-7ed3f1a92ee8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287185027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4287185027
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1919579199
Short name T605
Test name
Test status
Simulation time 170777760 ps
CPU time 1.65 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:21 PM PDT 24
Peak memory 200120 kb
Host smart-41b2dc10-4b3d-47d0-9df4-2385a4b187db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919579199 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1919579199
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1470694028
Short name T620
Test name
Test status
Simulation time 12797588 ps
CPU time 0.58 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:21 PM PDT 24
Peak memory 195080 kb
Host smart-e3e0c2c4-7ac0-49d0-8c54-e0799f66e96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470694028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1470694028
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2685678307
Short name T617
Test name
Test status
Simulation time 137425719 ps
CPU time 2.4 seconds
Started Aug 01 06:48:21 PM PDT 24
Finished Aug 01 06:48:23 PM PDT 24
Peak memory 200136 kb
Host smart-2d7afc5d-5f7d-48d2-8bbd-73074058741f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685678307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2685678307
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3356320320
Short name T565
Test name
Test status
Simulation time 111881973 ps
CPU time 3.19 seconds
Started Aug 01 06:48:18 PM PDT 24
Finished Aug 01 06:48:21 PM PDT 24
Peak memory 200168 kb
Host smart-94ee53de-8fd4-4be0-baea-af119fdcc653
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356320320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3356320320
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1109701967
Short name T101
Test name
Test status
Simulation time 153958594 ps
CPU time 7.83 seconds
Started Aug 01 06:48:18 PM PDT 24
Finished Aug 01 06:48:26 PM PDT 24
Peak memory 200172 kb
Host smart-e5d3f388-8a52-4ed3-9264-23d01c451e8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109701967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1109701967
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3944164929
Short name T97
Test name
Test status
Simulation time 324417735 ps
CPU time 14.65 seconds
Started Aug 01 06:48:21 PM PDT 24
Finished Aug 01 06:48:35 PM PDT 24
Peak memory 200064 kb
Host smart-4ea475a4-919b-4666-8b35-ae5f9d58f7a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944164929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3944164929
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3252350018
Short name T534
Test name
Test status
Simulation time 47731181 ps
CPU time 0.74 seconds
Started Aug 01 06:48:21 PM PDT 24
Finished Aug 01 06:48:22 PM PDT 24
Peak memory 198104 kb
Host smart-3337a2c7-d138-4005-83e5-c78ce8346579
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252350018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3252350018
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3264451766
Short name T542
Test name
Test status
Simulation time 45746736 ps
CPU time 1.35 seconds
Started Aug 01 06:48:17 PM PDT 24
Finished Aug 01 06:48:18 PM PDT 24
Peak memory 200156 kb
Host smart-c48a5223-648b-4974-9055-a11cf45a7e52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264451766 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3264451766
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1184077694
Short name T93
Test name
Test status
Simulation time 51362775 ps
CPU time 0.9 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:21 PM PDT 24
Peak memory 199848 kb
Host smart-06159036-1b18-4fbc-afd5-be501cbaf357
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184077694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1184077694
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1327344235
Short name T657
Test name
Test status
Simulation time 18837230 ps
CPU time 0.58 seconds
Started Aug 01 06:48:21 PM PDT 24
Finished Aug 01 06:48:22 PM PDT 24
Peak memory 195024 kb
Host smart-7886a3f2-17f6-41a2-95c5-55dbf1081c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327344235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1327344235
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.836978706
Short name T589
Test name
Test status
Simulation time 135082440 ps
CPU time 1.75 seconds
Started Aug 01 06:48:19 PM PDT 24
Finished Aug 01 06:48:21 PM PDT 24
Peak memory 199424 kb
Host smart-b205faa2-bc16-4e74-a95a-b7f00f13da5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836978706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.836978706
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3486991877
Short name T564
Test name
Test status
Simulation time 568554223 ps
CPU time 2.64 seconds
Started Aug 01 06:48:17 PM PDT 24
Finished Aug 01 06:48:20 PM PDT 24
Peak memory 200400 kb
Host smart-3c6602e1-ee3d-4e6c-bced-52f752b32c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486991877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3486991877
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2143606652
Short name T119
Test name
Test status
Simulation time 161371095 ps
CPU time 3.04 seconds
Started Aug 01 06:48:22 PM PDT 24
Finished Aug 01 06:48:25 PM PDT 24
Peak memory 200132 kb
Host smart-a93bb7c5-12b4-497e-b76d-b2cf2cf34eb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143606652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2143606652
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.555799151
Short name T550
Test name
Test status
Simulation time 234627902 ps
CPU time 1.71 seconds
Started Aug 01 06:48:32 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 200160 kb
Host smart-bf87009c-1f5b-4472-952b-7b46fa264565
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555799151 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.555799151
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1115351592
Short name T645
Test name
Test status
Simulation time 18414450 ps
CPU time 0.92 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:31 PM PDT 24
Peak memory 199964 kb
Host smart-8971cc41-17ed-42ba-98f5-428498dc7d73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115351592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1115351592
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2056534531
Short name T623
Test name
Test status
Simulation time 39013773 ps
CPU time 0.59 seconds
Started Aug 01 06:48:32 PM PDT 24
Finished Aug 01 06:48:33 PM PDT 24
Peak memory 195104 kb
Host smart-c4202697-2389-4ab8-96ef-66781ab9c5a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056534531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2056534531
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4197921314
Short name T614
Test name
Test status
Simulation time 168268462 ps
CPU time 2.48 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 200076 kb
Host smart-93c5fa75-840d-470a-b9bb-19786a831fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197921314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4197921314
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3284799133
Short name T541
Test name
Test status
Simulation time 62345555 ps
CPU time 1.83 seconds
Started Aug 01 06:48:34 PM PDT 24
Finished Aug 01 06:48:36 PM PDT 24
Peak memory 200116 kb
Host smart-996baa14-787b-45ec-a539-ee67cbecb8cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284799133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3284799133
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3008458778
Short name T652
Test name
Test status
Simulation time 448032359 ps
CPU time 2.98 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:36 PM PDT 24
Peak memory 200192 kb
Host smart-e4ab4e38-4863-4601-a5df-4e9d78a64034
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008458778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3008458778
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4039772380
Short name T597
Test name
Test status
Simulation time 56223195 ps
CPU time 1.82 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:42 PM PDT 24
Peak memory 200200 kb
Host smart-af4c38a5-c742-454f-9124-5949f02f96ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039772380 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.4039772380
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3872587057
Short name T658
Test name
Test status
Simulation time 68104192 ps
CPU time 0.79 seconds
Started Aug 01 06:48:28 PM PDT 24
Finished Aug 01 06:48:29 PM PDT 24
Peak memory 199292 kb
Host smart-4b3dd45f-88ea-4219-8c23-488b8dd1f389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872587057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3872587057
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2130587666
Short name T547
Test name
Test status
Simulation time 52182382 ps
CPU time 0.61 seconds
Started Aug 01 06:48:32 PM PDT 24
Finished Aug 01 06:48:33 PM PDT 24
Peak memory 195008 kb
Host smart-60c13777-666a-468e-9d2c-0f710efbfc8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130587666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2130587666
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.310831127
Short name T110
Test name
Test status
Simulation time 418120068 ps
CPU time 1.57 seconds
Started Aug 01 06:48:38 PM PDT 24
Finished Aug 01 06:48:40 PM PDT 24
Peak memory 200012 kb
Host smart-c8225ce2-ef4c-467f-825b-ec7a8e184531
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310831127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.310831127
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3822195798
Short name T659
Test name
Test status
Simulation time 35778030 ps
CPU time 1.76 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 200176 kb
Host smart-52ec96f4-d3dd-4b58-991c-a3daf2782a0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822195798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3822195798
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2207458824
Short name T120
Test name
Test status
Simulation time 98009358 ps
CPU time 1.79 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:30 PM PDT 24
Peak memory 200100 kb
Host smart-870e05ec-71b9-4daa-b6b0-09abc39b824e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207458824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2207458824
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.57882730
Short name T571
Test name
Test status
Simulation time 261386389 ps
CPU time 2.3 seconds
Started Aug 01 06:48:44 PM PDT 24
Finished Aug 01 06:48:47 PM PDT 24
Peak memory 208416 kb
Host smart-c9ce1b6f-7538-44e7-ac64-58691259e990
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57882730 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.57882730
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2556271738
Short name T621
Test name
Test status
Simulation time 28449408 ps
CPU time 0.8 seconds
Started Aug 01 06:48:43 PM PDT 24
Finished Aug 01 06:48:44 PM PDT 24
Peak memory 199428 kb
Host smart-aa1e8968-8fdc-495b-b22d-34d9cf8bc5b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556271738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2556271738
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.4174270294
Short name T609
Test name
Test status
Simulation time 12308691 ps
CPU time 0.59 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:41 PM PDT 24
Peak memory 195164 kb
Host smart-dd4aeaeb-0741-4a3b-a05a-1d95ac77b9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174270294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.4174270294
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1638799858
Short name T592
Test name
Test status
Simulation time 81663209 ps
CPU time 1.96 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:42 PM PDT 24
Peak memory 200096 kb
Host smart-0934b9d6-3c61-4e2e-b22f-8b725275295c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638799858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1638799858
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.290548228
Short name T646
Test name
Test status
Simulation time 1743273393 ps
CPU time 3.54 seconds
Started Aug 01 06:48:42 PM PDT 24
Finished Aug 01 06:48:45 PM PDT 24
Peak memory 200088 kb
Host smart-a77c4db5-94fb-491d-ac7c-6369f44be3d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290548228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.290548228
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1538999775
Short name T632
Test name
Test status
Simulation time 87453298 ps
CPU time 2.82 seconds
Started Aug 01 06:48:39 PM PDT 24
Finished Aug 01 06:48:42 PM PDT 24
Peak memory 200116 kb
Host smart-09ef0815-7b9d-4049-8ee8-6558ab28654f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538999775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1538999775
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3656304829
Short name T602
Test name
Test status
Simulation time 242882262179 ps
CPU time 645.57 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 216644 kb
Host smart-a36ec8fe-120e-420a-850c-0312b19fd9ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656304829 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3656304829
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3545082797
Short name T96
Test name
Test status
Simulation time 18619244 ps
CPU time 0.72 seconds
Started Aug 01 06:48:42 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 198064 kb
Host smart-0f00e244-1263-4af3-8823-e06fe2dcad84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545082797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3545082797
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2812811456
Short name T582
Test name
Test status
Simulation time 56859409 ps
CPU time 0.67 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:41 PM PDT 24
Peak memory 195040 kb
Host smart-2268dcc0-bbc5-425e-8f8e-10d12f1fb19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812811456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2812811456
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4285308443
Short name T596
Test name
Test status
Simulation time 44306150 ps
CPU time 1.1 seconds
Started Aug 01 06:48:41 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 198608 kb
Host smart-3503ec9a-ce1b-4fed-8de2-5096a50ade1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285308443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.4285308443
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.787991183
Short name T568
Test name
Test status
Simulation time 123054475 ps
CPU time 1.65 seconds
Started Aug 01 06:48:41 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 200164 kb
Host smart-5d3def37-2145-4b13-b923-441a9be78faf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787991183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.787991183
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.909706698
Short name T124
Test name
Test status
Simulation time 63657357 ps
CPU time 1.79 seconds
Started Aug 01 06:48:39 PM PDT 24
Finished Aug 01 06:48:41 PM PDT 24
Peak memory 200128 kb
Host smart-eba22d85-84f4-4d75-89ab-bc5ace8b167f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909706698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.909706698
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2099491644
Short name T566
Test name
Test status
Simulation time 60189530 ps
CPU time 1.12 seconds
Started Aug 01 06:48:41 PM PDT 24
Finished Aug 01 06:48:42 PM PDT 24
Peak memory 199980 kb
Host smart-d4e9297a-af6d-4fa2-9330-537e72bf5d72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099491644 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2099491644
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4062503484
Short name T607
Test name
Test status
Simulation time 523221749 ps
CPU time 0.93 seconds
Started Aug 01 06:48:42 PM PDT 24
Finished Aug 01 06:48:44 PM PDT 24
Peak memory 199952 kb
Host smart-08ea51e0-11b4-4c34-9610-2bf6990980fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062503484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4062503484
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2981427631
Short name T619
Test name
Test status
Simulation time 53857337 ps
CPU time 0.63 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:40 PM PDT 24
Peak memory 195004 kb
Host smart-d6d83e12-6947-40ee-8897-9e9cac58be31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981427631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2981427631
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2105997821
Short name T552
Test name
Test status
Simulation time 488246973 ps
CPU time 2.19 seconds
Started Aug 01 06:48:43 PM PDT 24
Finished Aug 01 06:48:45 PM PDT 24
Peak memory 200148 kb
Host smart-04a68422-6251-4342-97cd-f084892ff9f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105997821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2105997821
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1527749656
Short name T636
Test name
Test status
Simulation time 627822265 ps
CPU time 2.5 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 200068 kb
Host smart-09623c6a-8791-4b6e-8a10-21d0f94d7330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527749656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1527749656
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1611664119
Short name T75
Test name
Test status
Simulation time 87252737 ps
CPU time 1.88 seconds
Started Aug 01 06:48:41 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 200092 kb
Host smart-3d8a6402-eae2-4811-a40b-5b3776c1e601
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611664119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1611664119
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1923337725
Short name T586
Test name
Test status
Simulation time 82458819 ps
CPU time 2.48 seconds
Started Aug 01 06:48:42 PM PDT 24
Finished Aug 01 06:48:45 PM PDT 24
Peak memory 200296 kb
Host smart-85e46a95-770d-4b8c-b1d5-1069f3617848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923337725 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1923337725
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.655184304
Short name T630
Test name
Test status
Simulation time 68741674 ps
CPU time 0.75 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:41 PM PDT 24
Peak memory 197600 kb
Host smart-975c4013-4c96-47fe-9cec-6f73d20d9eef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655184304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.655184304
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2885221915
Short name T640
Test name
Test status
Simulation time 89440835 ps
CPU time 0.6 seconds
Started Aug 01 06:48:41 PM PDT 24
Finished Aug 01 06:48:42 PM PDT 24
Peak memory 195000 kb
Host smart-3847235f-af56-419b-a40a-557c846649c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885221915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2885221915
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3363885189
Short name T581
Test name
Test status
Simulation time 550056790 ps
CPU time 1.16 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:41 PM PDT 24
Peak memory 200080 kb
Host smart-0372fcd9-0464-439f-8e3e-b64c45492036
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363885189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3363885189
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.359297952
Short name T599
Test name
Test status
Simulation time 122542907 ps
CPU time 1.79 seconds
Started Aug 01 06:48:41 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 200072 kb
Host smart-7ba4dd19-238f-4700-8016-92ef90222f95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359297952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.359297952
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.626060749
Short name T608
Test name
Test status
Simulation time 177708999 ps
CPU time 1.81 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:42 PM PDT 24
Peak memory 200140 kb
Host smart-d4a49254-1a42-4823-863d-9505fc391938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626060749 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.626060749
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1759589489
Short name T635
Test name
Test status
Simulation time 15709445 ps
CPU time 0.8 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:41 PM PDT 24
Peak memory 199572 kb
Host smart-89f8bdf6-3bdd-4b13-985f-1bc4b5f426d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759589489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1759589489
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3970131213
Short name T600
Test name
Test status
Simulation time 14636902 ps
CPU time 0.61 seconds
Started Aug 01 06:48:42 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 195076 kb
Host smart-a4a85fd5-0e75-4be5-9289-bd8eb70b9881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970131213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3970131213
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.615407944
Short name T105
Test name
Test status
Simulation time 121283945 ps
CPU time 2.31 seconds
Started Aug 01 06:48:42 PM PDT 24
Finished Aug 01 06:48:45 PM PDT 24
Peak memory 200192 kb
Host smart-7b37463d-929c-4251-8ce2-8ff10556a503
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615407944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.615407944
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1005351233
Short name T588
Test name
Test status
Simulation time 1272131263 ps
CPU time 1.77 seconds
Started Aug 01 06:48:39 PM PDT 24
Finished Aug 01 06:48:41 PM PDT 24
Peak memory 200128 kb
Host smart-56ca48fd-e393-4702-a0ed-91256d17d2f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005351233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1005351233
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3391424482
Short name T118
Test name
Test status
Simulation time 261255124 ps
CPU time 4.28 seconds
Started Aug 01 06:48:44 PM PDT 24
Finished Aug 01 06:48:48 PM PDT 24
Peak memory 200104 kb
Host smart-faff5e81-72f8-439f-af18-5d2ebbe28a08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391424482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3391424482
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1436510048
Short name T642
Test name
Test status
Simulation time 80068364 ps
CPU time 1.13 seconds
Started Aug 01 06:48:43 PM PDT 24
Finished Aug 01 06:48:44 PM PDT 24
Peak memory 199796 kb
Host smart-ce63d2dd-7db9-45ff-8d06-45448fef68aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436510048 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1436510048
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3617583602
Short name T103
Test name
Test status
Simulation time 62052926 ps
CPU time 0.86 seconds
Started Aug 01 06:48:41 PM PDT 24
Finished Aug 01 06:48:42 PM PDT 24
Peak memory 199956 kb
Host smart-61cf2633-3796-4082-a42f-72e603bdefcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617583602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3617583602
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3027641475
Short name T656
Test name
Test status
Simulation time 141242018 ps
CPU time 0.62 seconds
Started Aug 01 06:48:41 PM PDT 24
Finished Aug 01 06:48:42 PM PDT 24
Peak memory 195016 kb
Host smart-8b1340bc-d1fe-4e51-850e-76ab422aad30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027641475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3027641475
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2495656038
Short name T554
Test name
Test status
Simulation time 410346599 ps
CPU time 2.33 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 200060 kb
Host smart-2abfc6e5-c4b1-482a-835e-ed505806e5cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495656038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2495656038
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2806075393
Short name T603
Test name
Test status
Simulation time 1056998452 ps
CPU time 2.92 seconds
Started Aug 01 06:48:41 PM PDT 24
Finished Aug 01 06:48:44 PM PDT 24
Peak memory 200168 kb
Host smart-5655c09d-f8d2-4de7-8f0f-888286ffe06c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806075393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2806075393
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4243554996
Short name T117
Test name
Test status
Simulation time 82892172 ps
CPU time 2.58 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 200208 kb
Host smart-7098be22-bb11-4316-b729-4bb7da9515b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243554996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.4243554996
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2556199730
Short name T631
Test name
Test status
Simulation time 102080826 ps
CPU time 1.82 seconds
Started Aug 01 06:48:43 PM PDT 24
Finished Aug 01 06:48:45 PM PDT 24
Peak memory 200088 kb
Host smart-ad03272b-0469-4e54-86ae-dedcda681635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556199730 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2556199730
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2530824192
Short name T102
Test name
Test status
Simulation time 16660886 ps
CPU time 0.91 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:42 PM PDT 24
Peak memory 200024 kb
Host smart-da3fef87-5c97-4292-b699-baca11886ca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530824192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2530824192
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1774190677
Short name T611
Test name
Test status
Simulation time 25334629 ps
CPU time 0.59 seconds
Started Aug 01 06:48:41 PM PDT 24
Finished Aug 01 06:48:41 PM PDT 24
Peak memory 194984 kb
Host smart-03a6ed8c-981f-4539-975a-fc59870f35d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774190677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1774190677
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.973377587
Short name T106
Test name
Test status
Simulation time 429189108 ps
CPU time 2.23 seconds
Started Aug 01 06:48:43 PM PDT 24
Finished Aug 01 06:48:45 PM PDT 24
Peak memory 200072 kb
Host smart-ed66f57c-0b24-498f-b91f-a07c715d9eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973377587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.973377587
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4191083428
Short name T587
Test name
Test status
Simulation time 711373878 ps
CPU time 3.86 seconds
Started Aug 01 06:48:39 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 200212 kb
Host smart-29a8b586-7174-445b-8b1d-d7edeea752b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191083428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4191083428
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2955779715
Short name T122
Test name
Test status
Simulation time 167793729 ps
CPU time 2.95 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:44 PM PDT 24
Peak memory 200208 kb
Host smart-032a3543-9838-409a-999f-04c985a977c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955779715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2955779715
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3487536717
Short name T638
Test name
Test status
Simulation time 258706321 ps
CPU time 1.86 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:56 PM PDT 24
Peak memory 200140 kb
Host smart-0217759e-4671-4147-a324-60b6895b226e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487536717 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3487536717
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3164062600
Short name T618
Test name
Test status
Simulation time 151585229 ps
CPU time 0.91 seconds
Started Aug 01 06:48:43 PM PDT 24
Finished Aug 01 06:48:44 PM PDT 24
Peak memory 199624 kb
Host smart-50ba7d15-013b-4e2a-9513-8b48a30d9a71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164062600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3164062600
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.960732729
Short name T533
Test name
Test status
Simulation time 22704933 ps
CPU time 0.61 seconds
Started Aug 01 06:48:42 PM PDT 24
Finished Aug 01 06:48:43 PM PDT 24
Peak memory 195004 kb
Host smart-8a343190-7178-410a-8e6c-e8857a90a6f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960732729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.960732729
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4250309481
Short name T104
Test name
Test status
Simulation time 213141411 ps
CPU time 1.13 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 199952 kb
Host smart-608e0aca-8c9d-416d-93b5-bb6210c605de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250309481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4250309481
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2469051825
Short name T585
Test name
Test status
Simulation time 139515380 ps
CPU time 3.05 seconds
Started Aug 01 06:48:40 PM PDT 24
Finished Aug 01 06:48:44 PM PDT 24
Peak memory 200128 kb
Host smart-3c522387-cf5c-482f-95f0-7a339dbb6e02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469051825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2469051825
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3381106946
Short name T622
Test name
Test status
Simulation time 310569165 ps
CPU time 1.86 seconds
Started Aug 01 06:48:44 PM PDT 24
Finished Aug 01 06:48:46 PM PDT 24
Peak memory 200148 kb
Host smart-dcf397fa-5300-45ce-b1ee-33a84136f96c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381106946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3381106946
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1977828453
Short name T94
Test name
Test status
Simulation time 634378938 ps
CPU time 8.85 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:39 PM PDT 24
Peak memory 200112 kb
Host smart-c99366c5-5be2-41fd-9afe-d4fb83c0fd7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977828453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1977828453
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1475065165
Short name T580
Test name
Test status
Simulation time 424283370 ps
CPU time 5.14 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:35 PM PDT 24
Peak memory 200068 kb
Host smart-e0f2d9ce-3a9c-49ab-b760-885db250e1fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475065165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1475065165
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1441575488
Short name T92
Test name
Test status
Simulation time 27059937 ps
CPU time 0.96 seconds
Started Aug 01 06:48:27 PM PDT 24
Finished Aug 01 06:48:28 PM PDT 24
Peak memory 199852 kb
Host smart-05772938-4eed-4fbd-8595-a3d16db7783e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441575488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1441575488
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3869659818
Short name T591
Test name
Test status
Simulation time 111715962096 ps
CPU time 261.82 seconds
Started Aug 01 06:48:28 PM PDT 24
Finished Aug 01 06:52:50 PM PDT 24
Peak memory 216696 kb
Host smart-ac48f02a-5367-4143-a2ac-d221e7033d59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869659818 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3869659818
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1013842497
Short name T660
Test name
Test status
Simulation time 14391904 ps
CPU time 0.8 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:29 PM PDT 24
Peak memory 198964 kb
Host smart-9f2a48f9-aec9-467f-a78d-9d4a19eb2460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013842497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1013842497
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.517328355
Short name T616
Test name
Test status
Simulation time 16300468 ps
CPU time 0.62 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:21 PM PDT 24
Peak memory 195104 kb
Host smart-17814e6f-9b33-494a-857b-ec727580c0b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517328355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.517328355
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1621271448
Short name T643
Test name
Test status
Simulation time 119836266 ps
CPU time 1.1 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:30 PM PDT 24
Peak memory 198624 kb
Host smart-c1a816eb-3c30-4ae9-850a-06043103df26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621271448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1621271448
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2608616502
Short name T575
Test name
Test status
Simulation time 36945712 ps
CPU time 1.89 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:22 PM PDT 24
Peak memory 200064 kb
Host smart-a4fd6cbc-d3ca-4823-b781-b767ad0627f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608616502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2608616502
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1714277286
Short name T535
Test name
Test status
Simulation time 98704636 ps
CPU time 0.6 seconds
Started Aug 01 06:48:51 PM PDT 24
Finished Aug 01 06:48:52 PM PDT 24
Peak memory 195116 kb
Host smart-3d6f5cbb-05c4-41b9-9b84-15e6d38effec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714277286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1714277286
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.603168262
Short name T546
Test name
Test status
Simulation time 19973196 ps
CPU time 0.63 seconds
Started Aug 01 06:48:52 PM PDT 24
Finished Aug 01 06:48:52 PM PDT 24
Peak memory 195092 kb
Host smart-a11c5065-53b8-45c2-ac58-ca388faaa9ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603168262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.603168262
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1471245372
Short name T551
Test name
Test status
Simulation time 42515122 ps
CPU time 0.61 seconds
Started Aug 01 06:48:58 PM PDT 24
Finished Aug 01 06:48:59 PM PDT 24
Peak memory 194812 kb
Host smart-b55ce132-bf5b-47dd-9e83-d2bd0254bdba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471245372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1471245372
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3834750110
Short name T615
Test name
Test status
Simulation time 55934424 ps
CPU time 0.57 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 195000 kb
Host smart-5a52c296-dc2a-4fc8-932e-bd067a80923b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834750110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3834750110
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2044671970
Short name T579
Test name
Test status
Simulation time 46362030 ps
CPU time 0.55 seconds
Started Aug 01 06:48:55 PM PDT 24
Finished Aug 01 06:48:56 PM PDT 24
Peak memory 195108 kb
Host smart-e65eb26a-1c3c-48cc-bda4-7ae3ddd44d45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044671970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2044671970
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3225345424
Short name T628
Test name
Test status
Simulation time 28519008 ps
CPU time 0.6 seconds
Started Aug 01 06:48:50 PM PDT 24
Finished Aug 01 06:48:51 PM PDT 24
Peak memory 195108 kb
Host smart-2df934e5-dbf1-45fe-a54e-4e28b3796a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225345424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3225345424
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.819523512
Short name T590
Test name
Test status
Simulation time 16610430 ps
CPU time 0.62 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 195092 kb
Host smart-858199d6-cc97-4803-a636-67b903f08c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819523512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.819523512
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.421342020
Short name T612
Test name
Test status
Simulation time 17111322 ps
CPU time 0.64 seconds
Started Aug 01 06:48:52 PM PDT 24
Finished Aug 01 06:48:53 PM PDT 24
Peak memory 195044 kb
Host smart-00c690c3-bd30-47e0-9793-69026104b65b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421342020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.421342020
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.990014913
Short name T626
Test name
Test status
Simulation time 16747050 ps
CPU time 0.61 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:53 PM PDT 24
Peak memory 195176 kb
Host smart-09e9fafb-0fb0-487e-b7e7-611f5334c55c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990014913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.990014913
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1774887468
Short name T539
Test name
Test status
Simulation time 16317789 ps
CPU time 0.62 seconds
Started Aug 01 06:48:50 PM PDT 24
Finished Aug 01 06:48:51 PM PDT 24
Peak memory 195120 kb
Host smart-428e1cf3-5be9-48e7-942a-083e7b6a37bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774887468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1774887468
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3185744735
Short name T100
Test name
Test status
Simulation time 9672080948 ps
CPU time 9 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:40 PM PDT 24
Peak memory 200236 kb
Host smart-fc52ab0a-0dc7-4e39-8f7f-db7c3c000b73
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185744735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3185744735
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3125056939
Short name T567
Test name
Test status
Simulation time 5704875895 ps
CPU time 16.02 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:45 PM PDT 24
Peak memory 200152 kb
Host smart-cf6f4daf-62ac-43a8-a4d2-83accee5e08c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125056939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3125056939
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2498676351
Short name T601
Test name
Test status
Simulation time 27281015 ps
CPU time 0.87 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:30 PM PDT 24
Peak memory 199692 kb
Host smart-bef5b099-1f4f-4686-8c1a-bc00d04aa270
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498676351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2498676351
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3035895197
Short name T633
Test name
Test status
Simulation time 74204439839 ps
CPU time 195.69 seconds
Started Aug 01 06:48:32 PM PDT 24
Finished Aug 01 06:51:48 PM PDT 24
Peak memory 216152 kb
Host smart-f9982db4-3577-49b7-b580-c38e23d20c4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035895197 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3035895197
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1240090974
Short name T99
Test name
Test status
Simulation time 27318853 ps
CPU time 0.9 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 199700 kb
Host smart-a0ef10d2-5c26-491f-afa0-5b08d7667504
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240090974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1240090974
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1413683990
Short name T584
Test name
Test status
Simulation time 25397424 ps
CPU time 0.66 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 195092 kb
Host smart-c38e7b88-64fb-4fc7-83c9-28adfe2124a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413683990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1413683990
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2902854119
Short name T559
Test name
Test status
Simulation time 38530851 ps
CPU time 1.76 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:31 PM PDT 24
Peak memory 200152 kb
Host smart-fc4c721e-f339-4c88-9673-e3a7fd840478
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902854119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2902854119
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1374253003
Short name T537
Test name
Test status
Simulation time 107884429 ps
CPU time 3.97 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:33 PM PDT 24
Peak memory 200160 kb
Host smart-dec89c07-42b3-4164-a2e2-8ce531ba7421
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374253003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1374253003
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.271785646
Short name T644
Test name
Test status
Simulation time 95368805 ps
CPU time 2.78 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:36 PM PDT 24
Peak memory 200088 kb
Host smart-c767def5-64a8-4b84-88b5-9b39ef9d1b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271785646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.271785646
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1186312048
Short name T595
Test name
Test status
Simulation time 24542001 ps
CPU time 0.6 seconds
Started Aug 01 06:48:55 PM PDT 24
Finished Aug 01 06:48:56 PM PDT 24
Peak memory 194988 kb
Host smart-85841781-12e0-4a90-bc82-8a2eeaf9fcb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186312048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1186312048
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.312664660
Short name T578
Test name
Test status
Simulation time 26962416 ps
CPU time 0.6 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 195152 kb
Host smart-056cd707-1772-4db0-b039-9aeee7061067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312664660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.312664660
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.481268601
Short name T569
Test name
Test status
Simulation time 30959028 ps
CPU time 0.6 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 194960 kb
Host smart-28d38ae0-f040-4f58-b656-7f9494ac7e03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481268601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.481268601
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.914960235
Short name T639
Test name
Test status
Simulation time 29290355 ps
CPU time 0.58 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 194984 kb
Host smart-e566ee03-ff6b-41bf-be43-ab0de732d49b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914960235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.914960235
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3670496312
Short name T648
Test name
Test status
Simulation time 47492544 ps
CPU time 0.59 seconds
Started Aug 01 06:48:58 PM PDT 24
Finished Aug 01 06:48:59 PM PDT 24
Peak memory 194880 kb
Host smart-829ab509-b8d0-446c-9efb-19e70017d166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670496312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3670496312
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1814152807
Short name T641
Test name
Test status
Simulation time 20270100 ps
CPU time 0.62 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 195076 kb
Host smart-beceef0d-9d50-4607-85be-a13459f8adcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814152807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1814152807
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.71348283
Short name T544
Test name
Test status
Simulation time 18974834 ps
CPU time 0.57 seconds
Started Aug 01 06:48:52 PM PDT 24
Finished Aug 01 06:48:53 PM PDT 24
Peak memory 195044 kb
Host smart-b82d75c1-37dd-429c-8f4d-8c3a3231baae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71348283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.71348283
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3404422276
Short name T573
Test name
Test status
Simulation time 42656309 ps
CPU time 0.62 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 195216 kb
Host smart-bc82a48e-7a2d-4dd1-9b7e-9b0d39a26f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404422276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3404422276
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2674021957
Short name T634
Test name
Test status
Simulation time 60590709 ps
CPU time 0.68 seconds
Started Aug 01 06:48:51 PM PDT 24
Finished Aug 01 06:48:52 PM PDT 24
Peak memory 195024 kb
Host smart-d4e313d8-2ea2-404d-93a6-8ad069f5c9ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674021957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2674021957
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2701269018
Short name T548
Test name
Test status
Simulation time 29921721 ps
CPU time 0.59 seconds
Started Aug 01 06:48:58 PM PDT 24
Finished Aug 01 06:48:59 PM PDT 24
Peak memory 195020 kb
Host smart-58bcdab1-3d83-477b-993f-73886bd0e7d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701269018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2701269018
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1836790218
Short name T545
Test name
Test status
Simulation time 299211638 ps
CPU time 5.74 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:35 PM PDT 24
Peak memory 199748 kb
Host smart-cd1ed3ac-28e7-46fc-917c-95b86a837425
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836790218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1836790218
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.353945970
Short name T655
Test name
Test status
Simulation time 476922296 ps
CPU time 5.62 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:35 PM PDT 24
Peak memory 200112 kb
Host smart-12521fd1-45ba-4251-82ad-c6f2a2f5071d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353945970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.353945970
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2681622778
Short name T606
Test name
Test status
Simulation time 159102123 ps
CPU time 0.74 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 198040 kb
Host smart-c771831a-d197-420a-9f1b-f12bd39415d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681622778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2681622778
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3408868262
Short name T625
Test name
Test status
Simulation time 1124192361 ps
CPU time 2.19 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 200348 kb
Host smart-7407a8a8-ff64-4d8e-b92b-a0a317b66393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408868262 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3408868262
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4006548856
Short name T90
Test name
Test status
Simulation time 62843193 ps
CPU time 0.67 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 197940 kb
Host smart-62a706e0-cdb4-4082-a3d9-d537e4814df1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006548856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.4006548856
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.227359228
Short name T549
Test name
Test status
Simulation time 23277408 ps
CPU time 0.58 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:33 PM PDT 24
Peak memory 194996 kb
Host smart-000aa188-05c0-422c-bdaf-b06636c40b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227359228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.227359228
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1138296243
Short name T560
Test name
Test status
Simulation time 186884090 ps
CPU time 1.04 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:31 PM PDT 24
Peak memory 198780 kb
Host smart-dbe5c115-1a18-428d-ab8d-c987cd96ae2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138296243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1138296243
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1128930553
Short name T555
Test name
Test status
Simulation time 234876963 ps
CPU time 1.62 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 200116 kb
Host smart-23a1db95-5ddd-40b1-ad04-a7db240f753c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128930553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1128930553
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1661544275
Short name T637
Test name
Test status
Simulation time 240509247 ps
CPU time 2.83 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 200064 kb
Host smart-d45b2d4b-1d52-4383-81db-843e9dcbbc6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661544275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1661544275
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.145475840
Short name T570
Test name
Test status
Simulation time 13890266 ps
CPU time 0.62 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 195100 kb
Host smart-ef2d8531-940f-4641-9f1c-2ad9709741f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145475840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.145475840
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2444670676
Short name T563
Test name
Test status
Simulation time 44580610 ps
CPU time 0.59 seconds
Started Aug 01 06:48:55 PM PDT 24
Finished Aug 01 06:48:56 PM PDT 24
Peak memory 195072 kb
Host smart-97c06774-e878-4e6c-8694-1663183f3280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444670676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2444670676
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2058012193
Short name T610
Test name
Test status
Simulation time 14359379 ps
CPU time 0.62 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 195016 kb
Host smart-a3929135-e798-413f-bdff-0aef477e8c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058012193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2058012193
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2946010995
Short name T627
Test name
Test status
Simulation time 131214549 ps
CPU time 0.58 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 194972 kb
Host smart-3af107fe-fc2c-4db7-9482-fdedb5767a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946010995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2946010995
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.165979958
Short name T553
Test name
Test status
Simulation time 21218802 ps
CPU time 0.61 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 195036 kb
Host smart-bead0806-0fd9-4308-927f-d069ef006c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165979958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.165979958
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3670889347
Short name T561
Test name
Test status
Simulation time 17064662 ps
CPU time 0.61 seconds
Started Aug 01 06:48:57 PM PDT 24
Finished Aug 01 06:48:58 PM PDT 24
Peak memory 195084 kb
Host smart-b2f69bd9-845f-4464-aa13-ef3fcff339e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670889347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3670889347
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2672304700
Short name T558
Test name
Test status
Simulation time 66119982 ps
CPU time 0.59 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:53 PM PDT 24
Peak memory 194980 kb
Host smart-601cf771-ac89-4255-a52d-65b9e1b55912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672304700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2672304700
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.120403316
Short name T613
Test name
Test status
Simulation time 12413673 ps
CPU time 0.62 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 194896 kb
Host smart-1ca7fbab-ebea-4a62-84fd-3b80403c7cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120403316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.120403316
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2945925479
Short name T538
Test name
Test status
Simulation time 81512037 ps
CPU time 0.63 seconds
Started Aug 01 06:48:52 PM PDT 24
Finished Aug 01 06:48:53 PM PDT 24
Peak memory 195128 kb
Host smart-741277e2-c7e9-4199-b865-8199a40dc0be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945925479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2945925479
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4111262434
Short name T598
Test name
Test status
Simulation time 46670369 ps
CPU time 0.63 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 195052 kb
Host smart-cde08bca-f70c-4b47-9a44-bfab6be8bee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111262434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4111262434
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2862200549
Short name T543
Test name
Test status
Simulation time 288690752 ps
CPU time 1.85 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:31 PM PDT 24
Peak memory 200344 kb
Host smart-89a90cac-90e8-419b-be78-26978ea65df2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862200549 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2862200549
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3079661398
Short name T654
Test name
Test status
Simulation time 28071831 ps
CPU time 0.85 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 199668 kb
Host smart-5482b33d-7086-4eb5-8a68-c36425badf78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079661398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3079661398
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3692505881
Short name T624
Test name
Test status
Simulation time 54944950 ps
CPU time 0.66 seconds
Started Aug 01 06:48:28 PM PDT 24
Finished Aug 01 06:48:28 PM PDT 24
Peak memory 195104 kb
Host smart-fc6feac6-e54b-4d9d-ad30-0921dfa5c8ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692505881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3692505881
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1277496803
Short name T594
Test name
Test status
Simulation time 351186238 ps
CPU time 1.75 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 200052 kb
Host smart-719bf1f3-da16-474f-ac26-4de4db533b2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277496803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1277496803
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3347091424
Short name T576
Test name
Test status
Simulation time 108220566 ps
CPU time 2.33 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:36 PM PDT 24
Peak memory 200136 kb
Host smart-bfa23658-8b0d-44dc-88a4-f473be5577d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347091424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3347091424
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1926255657
Short name T115
Test name
Test status
Simulation time 149617750 ps
CPU time 3.15 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 200212 kb
Host smart-8e60cef1-0ba2-4361-9d00-6fbb2ad1f2d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926255657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1926255657
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2588329766
Short name T653
Test name
Test status
Simulation time 80305206 ps
CPU time 1.22 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 199960 kb
Host smart-decb4ad0-7819-4532-8280-0838ffa65045
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588329766 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2588329766
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3682507248
Short name T557
Test name
Test status
Simulation time 28800449 ps
CPU time 0.84 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:33 PM PDT 24
Peak memory 199932 kb
Host smart-d8ee78b4-62d9-439d-981d-9d2b17a15878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682507248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3682507248
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3752956629
Short name T593
Test name
Test status
Simulation time 26955141 ps
CPU time 0.62 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:31 PM PDT 24
Peak memory 195004 kb
Host smart-86f4e945-8562-475b-a0a1-3f55b433b876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752956629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3752956629
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3775808857
Short name T649
Test name
Test status
Simulation time 24334891 ps
CPU time 1.13 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 199980 kb
Host smart-0928dd1a-d4a8-4123-914a-be26c00fb62d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775808857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3775808857
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3812678090
Short name T532
Test name
Test status
Simulation time 259062321 ps
CPU time 1.7 seconds
Started Aug 01 06:48:32 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 200072 kb
Host smart-553f2c7d-74b6-4afb-810b-fd75ca69c567
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812678090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3812678090
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2452193008
Short name T556
Test name
Test status
Simulation time 111897946 ps
CPU time 2.54 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:36 PM PDT 24
Peak memory 200240 kb
Host smart-e4f08e44-888d-4c06-b030-d530b9885870
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452193008 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2452193008
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3636310208
Short name T577
Test name
Test status
Simulation time 116785928 ps
CPU time 0.87 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 199700 kb
Host smart-d831970c-93cd-4b54-ad35-a5fe4a249960
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636310208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3636310208
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3194749333
Short name T647
Test name
Test status
Simulation time 17775122 ps
CPU time 0.61 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:30 PM PDT 24
Peak memory 195056 kb
Host smart-2dd506a5-38d0-4695-a08f-db95aa53d941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194749333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3194749333
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2967913015
Short name T109
Test name
Test status
Simulation time 100409595 ps
CPU time 1.22 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 198648 kb
Host smart-eeea83fb-82c9-436e-a406-e9677fe439a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967913015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2967913015
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.463454140
Short name T604
Test name
Test status
Simulation time 210754490 ps
CPU time 1.37 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 200076 kb
Host smart-afe6ca94-5911-455c-a857-76bb3ae65186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463454140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.463454140
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3140729195
Short name T73
Test name
Test status
Simulation time 1067324778 ps
CPU time 4.43 seconds
Started Aug 01 06:48:32 PM PDT 24
Finished Aug 01 06:48:37 PM PDT 24
Peak memory 200180 kb
Host smart-30fc759a-bc5e-497d-a53d-a317c057bd44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140729195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3140729195
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2166680367
Short name T536
Test name
Test status
Simulation time 39343032 ps
CPU time 1.31 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 200148 kb
Host smart-ec768815-5b69-4c7e-9a5f-2b65ff9b58c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166680367 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2166680367
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2742566825
Short name T98
Test name
Test status
Simulation time 13064542 ps
CPU time 0.69 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 197852 kb
Host smart-5246f091-9e95-4d29-bbef-8f5ca84918de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742566825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2742566825
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1795736041
Short name T574
Test name
Test status
Simulation time 24608638 ps
CPU time 0.6 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 194884 kb
Host smart-c570f0ee-1884-40eb-8854-36dd41a738c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795736041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1795736041
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1856313960
Short name T108
Test name
Test status
Simulation time 327970914 ps
CPU time 1.71 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:31 PM PDT 24
Peak memory 200072 kb
Host smart-5bcd0e73-7f98-4f79-999c-6f06ada0b153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856313960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1856313960
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3584149842
Short name T531
Test name
Test status
Simulation time 303238112 ps
CPU time 3.23 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 200120 kb
Host smart-58fcfe54-b7cf-4512-8427-587538c81c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584149842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3584149842
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3361376465
Short name T123
Test name
Test status
Simulation time 162411569 ps
CPU time 3.18 seconds
Started Aug 01 06:48:31 PM PDT 24
Finished Aug 01 06:48:35 PM PDT 24
Peak memory 200168 kb
Host smart-3a621f0b-5b0b-4bc7-85de-e83943ec32fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361376465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3361376465
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2412085843
Short name T562
Test name
Test status
Simulation time 102783758383 ps
CPU time 964.61 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 07:04:35 PM PDT 24
Peak memory 224884 kb
Host smart-5e97acac-4282-4788-94c7-a72dd7b570ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412085843 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2412085843
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1326562274
Short name T629
Test name
Test status
Simulation time 92042320 ps
CPU time 0.92 seconds
Started Aug 01 06:48:32 PM PDT 24
Finished Aug 01 06:48:33 PM PDT 24
Peak memory 199812 kb
Host smart-20e703c1-c2d8-405b-a15f-9282fa2e6d4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326562274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1326562274
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1609823989
Short name T540
Test name
Test status
Simulation time 41763140 ps
CPU time 0.58 seconds
Started Aug 01 06:48:30 PM PDT 24
Finished Aug 01 06:48:31 PM PDT 24
Peak memory 194948 kb
Host smart-709d0ee9-f2a6-4b18-b1e8-c014be417329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609823989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1609823989
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1197345254
Short name T107
Test name
Test status
Simulation time 355101494 ps
CPU time 1.84 seconds
Started Aug 01 06:48:33 PM PDT 24
Finished Aug 01 06:48:35 PM PDT 24
Peak memory 200112 kb
Host smart-af645ef4-2b1d-4daa-8f7b-6a23e3148141
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197345254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1197345254
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3533122474
Short name T651
Test name
Test status
Simulation time 137064760 ps
CPU time 2.66 seconds
Started Aug 01 06:48:29 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 200224 kb
Host smart-13ab24d7-9f39-4632-bf66-00ed5508f645
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533122474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3533122474
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1853138834
Short name T572
Test name
Test status
Simulation time 483966408 ps
CPU time 1.83 seconds
Started Aug 01 06:48:34 PM PDT 24
Finished Aug 01 06:48:36 PM PDT 24
Peak memory 200112 kb
Host smart-261a53b4-3b92-4d07-a748-83040dfb5b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853138834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1853138834
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3823061414
Short name T196
Test name
Test status
Simulation time 13492929 ps
CPU time 0.58 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 06:26:34 PM PDT 24
Peak memory 194900 kb
Host smart-9a8b3e4a-f184-4fb4-8c5d-6b7afd723766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823061414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3823061414
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2128118091
Short name T487
Test name
Test status
Simulation time 53410908 ps
CPU time 2.84 seconds
Started Aug 01 06:26:39 PM PDT 24
Finished Aug 01 06:26:42 PM PDT 24
Peak memory 199872 kb
Host smart-03eea517-a3fc-471e-818d-baff0fa10477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128118091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2128118091
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.354078226
Short name T135
Test name
Test status
Simulation time 1989421456 ps
CPU time 7.07 seconds
Started Aug 01 06:26:50 PM PDT 24
Finished Aug 01 06:26:58 PM PDT 24
Peak memory 199844 kb
Host smart-f8f6812e-434b-45c8-a0f0-5f38d39f804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354078226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.354078226
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3114556751
Short name T143
Test name
Test status
Simulation time 17327520412 ps
CPU time 796.16 seconds
Started Aug 01 06:26:51 PM PDT 24
Finished Aug 01 06:40:07 PM PDT 24
Peak memory 734664 kb
Host smart-f06f44fd-46c5-4e47-826c-74a63338569e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114556751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3114556751
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3465971745
Short name T511
Test name
Test status
Simulation time 10435411029 ps
CPU time 88.4 seconds
Started Aug 01 06:26:32 PM PDT 24
Finished Aug 01 06:28:00 PM PDT 24
Peak memory 199864 kb
Host smart-b2b02173-7e08-4f02-87db-4294306aed45
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465971745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3465971745
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3628916444
Short name T277
Test name
Test status
Simulation time 17492116652 ps
CPU time 164.74 seconds
Started Aug 01 06:26:52 PM PDT 24
Finished Aug 01 06:29:36 PM PDT 24
Peak memory 199948 kb
Host smart-8790d2e5-4b13-4ce4-8c99-2cedc96f6c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628916444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3628916444
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.536005362
Short name T68
Test name
Test status
Simulation time 125293516 ps
CPU time 0.92 seconds
Started Aug 01 06:26:35 PM PDT 24
Finished Aug 01 06:26:36 PM PDT 24
Peak memory 218584 kb
Host smart-7730aeb6-1356-4cb7-80d2-7f93d853bc9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536005362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.536005362
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2918989354
Short name T395
Test name
Test status
Simulation time 499437279 ps
CPU time 8.82 seconds
Started Aug 01 06:26:32 PM PDT 24
Finished Aug 01 06:26:41 PM PDT 24
Peak memory 199804 kb
Host smart-2ccade41-e185-48e4-9fea-80aa5f57f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918989354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2918989354
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1129174575
Short name T184
Test name
Test status
Simulation time 260584662617 ps
CPU time 823.31 seconds
Started Aug 01 06:26:34 PM PDT 24
Finished Aug 01 06:40:18 PM PDT 24
Peak memory 216348 kb
Host smart-5138b43d-6f2c-4c4e-825d-217abf061e2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129174575 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1129174575
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.599241895
Short name T17
Test name
Test status
Simulation time 198544346941 ps
CPU time 1567.98 seconds
Started Aug 01 06:26:40 PM PDT 24
Finished Aug 01 06:52:48 PM PDT 24
Peak memory 487408 kb
Host smart-158e91ea-bbfc-466c-8f95-c930b8f50f68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599241895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.599241895
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.1944689359
Short name T349
Test name
Test status
Simulation time 10867977619 ps
CPU time 41.1 seconds
Started Aug 01 06:26:59 PM PDT 24
Finished Aug 01 06:27:41 PM PDT 24
Peak memory 199976 kb
Host smart-bae4b49e-cfea-42fb-87fb-ee861b6a589c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1944689359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.1944689359
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3158961919
Short name T497
Test name
Test status
Simulation time 20233907312 ps
CPU time 87.82 seconds
Started Aug 01 06:26:34 PM PDT 24
Finished Aug 01 06:28:02 PM PDT 24
Peak memory 199988 kb
Host smart-a8711bfa-8815-40c0-b9ea-f4f006f4fd5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3158961919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3158961919
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2765782669
Short name T458
Test name
Test status
Simulation time 7084489671 ps
CPU time 88.33 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 06:28:02 PM PDT 24
Peak memory 199920 kb
Host smart-63747b1a-9bc3-471b-86d6-2bce0594b8cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2765782669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2765782669
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2217665865
Short name T258
Test name
Test status
Simulation time 46930472203 ps
CPU time 602.82 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:36:59 PM PDT 24
Peak memory 199956 kb
Host smart-d299578e-9526-400a-a3b1-8aa9f59b8297
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2217665865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2217665865
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3697753426
Short name T128
Test name
Test status
Simulation time 39541111218 ps
CPU time 2200.96 seconds
Started Aug 01 06:26:41 PM PDT 24
Finished Aug 01 07:03:22 PM PDT 24
Peak memory 208248 kb
Host smart-712b65db-dc72-4304-a139-d50a3d4626aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3697753426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3697753426
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.171461158
Short name T326
Test name
Test status
Simulation time 83405971907 ps
CPU time 2141.23 seconds
Started Aug 01 06:26:57 PM PDT 24
Finished Aug 01 07:02:38 PM PDT 24
Peak memory 214804 kb
Host smart-f8653404-4d9b-43d3-ad14-d1afbb8c3cdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=171461158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.171461158
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.4103288906
Short name T358
Test name
Test status
Simulation time 1575470435 ps
CPU time 31.61 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 06:27:05 PM PDT 24
Peak memory 199864 kb
Host smart-b7ce3d80-28e3-470b-b7d9-3ced20942859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103288906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.4103288906
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3454186971
Short name T144
Test name
Test status
Simulation time 361172995 ps
CPU time 22.1 seconds
Started Aug 01 06:26:49 PM PDT 24
Finished Aug 01 06:27:11 PM PDT 24
Peak memory 199872 kb
Host smart-1f81d3cd-9c7d-4a06-aee8-8fa0f5033830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3454186971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3454186971
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.138356550
Short name T246
Test name
Test status
Simulation time 551387078 ps
CPU time 29.46 seconds
Started Aug 01 06:26:48 PM PDT 24
Finished Aug 01 06:27:18 PM PDT 24
Peak memory 199812 kb
Host smart-b863cff3-c7a2-4c04-a39a-a245245c5b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138356550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.138356550
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2200412239
Short name T199
Test name
Test status
Simulation time 16383034914 ps
CPU time 703.54 seconds
Started Aug 01 06:26:46 PM PDT 24
Finished Aug 01 06:38:30 PM PDT 24
Peak memory 494812 kb
Host smart-39efec0e-1657-42cc-8b59-17e7b3f6bb6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200412239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2200412239
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2547355796
Short name T154
Test name
Test status
Simulation time 4403252789 ps
CPU time 78.59 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 06:27:52 PM PDT 24
Peak memory 199960 kb
Host smart-866ebfe8-774a-47f1-8e0e-37ea92f4bd8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547355796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2547355796
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.43656011
Short name T138
Test name
Test status
Simulation time 4750030028 ps
CPU time 59.64 seconds
Started Aug 01 06:26:49 PM PDT 24
Finished Aug 01 06:27:49 PM PDT 24
Peak memory 199992 kb
Host smart-d95aa5b3-7c13-4cd0-a357-1f4b23bfc7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43656011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.43656011
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2195273531
Short name T66
Test name
Test status
Simulation time 83185804 ps
CPU time 0.95 seconds
Started Aug 01 06:26:36 PM PDT 24
Finished Aug 01 06:26:37 PM PDT 24
Peak memory 219540 kb
Host smart-dd9dce78-d516-45d3-8c39-1a36cd089b24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195273531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2195273531
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2611964187
Short name T420
Test name
Test status
Simulation time 488488085 ps
CPU time 9.35 seconds
Started Aug 01 06:26:35 PM PDT 24
Finished Aug 01 06:26:44 PM PDT 24
Peak memory 199860 kb
Host smart-09c10d50-ff6f-4e94-929c-286a3f7c6485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611964187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2611964187
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1589897154
Short name T385
Test name
Test status
Simulation time 32633621285 ps
CPU time 1790.44 seconds
Started Aug 01 06:26:49 PM PDT 24
Finished Aug 01 06:56:40 PM PDT 24
Peak memory 787096 kb
Host smart-d6377d29-abb9-4ea2-ae4f-672b73d0071e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589897154 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1589897154
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.903536429
Short name T293
Test name
Test status
Simulation time 4415198558 ps
CPU time 38.01 seconds
Started Aug 01 06:26:35 PM PDT 24
Finished Aug 01 06:27:14 PM PDT 24
Peak memory 199952 kb
Host smart-7996433c-221e-48fe-9300-edaa1f02b5a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=903536429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.903536429
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1934796721
Short name T439
Test name
Test status
Simulation time 12353319723 ps
CPU time 91.69 seconds
Started Aug 01 06:26:38 PM PDT 24
Finished Aug 01 06:28:10 PM PDT 24
Peak memory 199948 kb
Host smart-01cc350a-eaf8-47f2-b10c-7ddfe40f249c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1934796721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1934796721
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.2980586953
Short name T388
Test name
Test status
Simulation time 12842307861 ps
CPU time 73.51 seconds
Started Aug 01 06:26:32 PM PDT 24
Finished Aug 01 06:27:46 PM PDT 24
Peak memory 199972 kb
Host smart-133149ee-5b26-4872-a88d-517f08a890f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2980586953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2980586953
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1991674501
Short name T436
Test name
Test status
Simulation time 39874050314 ps
CPU time 527.32 seconds
Started Aug 01 06:26:35 PM PDT 24
Finished Aug 01 06:35:22 PM PDT 24
Peak memory 200024 kb
Host smart-140f4354-c3f3-4d94-87a7-66369e0253e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1991674501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1991674501
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1534491641
Short name T205
Test name
Test status
Simulation time 142943763067 ps
CPU time 2429 seconds
Started Aug 01 06:26:54 PM PDT 24
Finished Aug 01 07:07:23 PM PDT 24
Peak memory 208248 kb
Host smart-148a35e2-243a-4b8b-ba5d-48aadc11bc25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1534491641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1534491641
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2477107719
Short name T212
Test name
Test status
Simulation time 293378772932 ps
CPU time 2523.08 seconds
Started Aug 01 06:26:53 PM PDT 24
Finished Aug 01 07:08:56 PM PDT 24
Peak memory 215992 kb
Host smart-9608a560-e1d5-4b12-972f-03826e167544
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2477107719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2477107719
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.4222373456
Short name T394
Test name
Test status
Simulation time 1556082872 ps
CPU time 9.08 seconds
Started Aug 01 06:26:51 PM PDT 24
Finished Aug 01 06:27:00 PM PDT 24
Peak memory 199840 kb
Host smart-3c8f88c2-014b-4355-a94c-8e4d12e7cf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222373456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.4222373456
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.191467793
Short name T356
Test name
Test status
Simulation time 22761291 ps
CPU time 0.57 seconds
Started Aug 01 06:27:07 PM PDT 24
Finished Aug 01 06:27:07 PM PDT 24
Peak memory 195572 kb
Host smart-82b547d0-80db-48e5-83ef-2cb6293a2510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191467793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.191467793
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1898308840
Short name T336
Test name
Test status
Simulation time 6957679842 ps
CPU time 21.29 seconds
Started Aug 01 06:27:06 PM PDT 24
Finished Aug 01 06:27:27 PM PDT 24
Peak memory 199744 kb
Host smart-75dc2a98-edff-40c1-8f90-1eda741f139b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1898308840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1898308840
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.882285275
Short name T441
Test name
Test status
Simulation time 6059818574 ps
CPU time 78.28 seconds
Started Aug 01 06:27:02 PM PDT 24
Finished Aug 01 06:28:21 PM PDT 24
Peak memory 208236 kb
Host smart-5299b031-dba2-45a6-916a-5e7be0d8c25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882285275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.882285275
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.931408160
Short name T459
Test name
Test status
Simulation time 4695069170 ps
CPU time 162.47 seconds
Started Aug 01 06:27:12 PM PDT 24
Finished Aug 01 06:29:55 PM PDT 24
Peak memory 358424 kb
Host smart-9f0a04e2-f3cc-49ae-b933-9a53abcc599d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931408160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.931408160
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.518765689
Short name T281
Test name
Test status
Simulation time 7770996622 ps
CPU time 29.1 seconds
Started Aug 01 06:27:05 PM PDT 24
Finished Aug 01 06:27:34 PM PDT 24
Peak memory 199884 kb
Host smart-a75203ab-4d6d-41cb-957e-0e54c8b2b4b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518765689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.518765689
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3206819967
Short name T140
Test name
Test status
Simulation time 1306777198 ps
CPU time 36.45 seconds
Started Aug 01 06:27:13 PM PDT 24
Finished Aug 01 06:27:50 PM PDT 24
Peak memory 199832 kb
Host smart-0325847e-24fb-40b1-ba91-b4c1c469c30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206819967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3206819967
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.709464169
Short name T288
Test name
Test status
Simulation time 49442170 ps
CPU time 2.41 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:27:06 PM PDT 24
Peak memory 199800 kb
Host smart-a5e080fb-f025-491b-8460-16cb8ef4923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709464169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.709464169
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3135239540
Short name T31
Test name
Test status
Simulation time 103427177788 ps
CPU time 1855.28 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:58:00 PM PDT 24
Peak memory 485816 kb
Host smart-473d7eab-5ed7-4620-971e-21db73be9a2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135239540 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3135239540
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.361365349
Short name T3
Test name
Test status
Simulation time 1723657617 ps
CPU time 11.26 seconds
Started Aug 01 06:27:06 PM PDT 24
Finished Aug 01 06:27:18 PM PDT 24
Peak memory 199920 kb
Host smart-0673710e-2f88-43d9-aa90-7f95879d3946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361365349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.361365349
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2402141454
Short name T224
Test name
Test status
Simulation time 24801955 ps
CPU time 0.61 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:27:02 PM PDT 24
Peak memory 194892 kb
Host smart-293069be-63c3-4512-8b08-ec2741574199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402141454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2402141454
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3441071799
Short name T213
Test name
Test status
Simulation time 2100393191 ps
CPU time 7.31 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:27:09 PM PDT 24
Peak memory 199872 kb
Host smart-8681d363-2ec7-426a-a863-d2457f0a05ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441071799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3441071799
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3317877704
Short name T422
Test name
Test status
Simulation time 4602704758 ps
CPU time 23.88 seconds
Started Aug 01 06:27:03 PM PDT 24
Finished Aug 01 06:27:27 PM PDT 24
Peak memory 199956 kb
Host smart-c7ceaf40-77c2-4463-824a-5f30495b2bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317877704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3317877704
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4038582821
Short name T266
Test name
Test status
Simulation time 4183743406 ps
CPU time 641.34 seconds
Started Aug 01 06:27:05 PM PDT 24
Finished Aug 01 06:37:46 PM PDT 24
Peak memory 692004 kb
Host smart-5f6ff4ec-99d2-4ae1-97ae-2cde1e58e1a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038582821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4038582821
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.943543920
Short name T242
Test name
Test status
Simulation time 17662333 ps
CPU time 0.67 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:27:05 PM PDT 24
Peak memory 196332 kb
Host smart-6226bab5-ab6f-49ac-a9c6-0c0a4d0763f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943543920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.943543920
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2294479978
Short name T404
Test name
Test status
Simulation time 4508869846 ps
CPU time 41.48 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:27:43 PM PDT 24
Peak memory 199960 kb
Host smart-24fea204-2169-4c29-af66-33d254ed3104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294479978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2294479978
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1642356336
Short name T270
Test name
Test status
Simulation time 239933540 ps
CPU time 4.34 seconds
Started Aug 01 06:26:58 PM PDT 24
Finished Aug 01 06:27:02 PM PDT 24
Peak memory 199860 kb
Host smart-b34067e5-c3d1-4fc4-b671-1d04c088b9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642356336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1642356336
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3584205645
Short name T399
Test name
Test status
Simulation time 846790794 ps
CPU time 11.3 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:27:12 PM PDT 24
Peak memory 199912 kb
Host smart-0515bf7a-3008-42ec-abb9-cc9b1591a4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584205645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3584205645
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1230739963
Short name T294
Test name
Test status
Simulation time 11249117 ps
CPU time 0.61 seconds
Started Aug 01 06:27:06 PM PDT 24
Finished Aug 01 06:27:06 PM PDT 24
Peak memory 195720 kb
Host smart-52f137cd-f73f-4fb7-8aa3-0ff51abd52b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230739963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1230739963
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.4250764317
Short name T41
Test name
Test status
Simulation time 1641817543 ps
CPU time 88.85 seconds
Started Aug 01 06:27:09 PM PDT 24
Finished Aug 01 06:28:38 PM PDT 24
Peak memory 199804 kb
Host smart-78006945-dcbf-43a2-a196-2ab2f53d53dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250764317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.4250764317
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2406537349
Short name T444
Test name
Test status
Simulation time 1979202940 ps
CPU time 36.48 seconds
Started Aug 01 06:27:02 PM PDT 24
Finished Aug 01 06:27:39 PM PDT 24
Peak memory 199848 kb
Host smart-df68ecac-4abe-49c1-8367-1b021db05741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406537349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2406537349
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3229502513
Short name T498
Test name
Test status
Simulation time 9377502255 ps
CPU time 59.28 seconds
Started Aug 01 06:27:06 PM PDT 24
Finished Aug 01 06:28:06 PM PDT 24
Peak memory 314444 kb
Host smart-d2938947-ec6e-4c00-a0e2-c24ae9e98f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229502513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3229502513
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2108069288
Short name T230
Test name
Test status
Simulation time 19069292105 ps
CPU time 245.76 seconds
Started Aug 01 06:27:13 PM PDT 24
Finished Aug 01 06:31:19 PM PDT 24
Peak memory 199976 kb
Host smart-13702646-f73c-45f1-b8d1-ac868c721378
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108069288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2108069288
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.301291316
Short name T492
Test name
Test status
Simulation time 2728941657 ps
CPU time 69.76 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:28:06 PM PDT 24
Peak memory 199972 kb
Host smart-eb51cc07-34ad-4789-9cb8-f91574f8a8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301291316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.301291316
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2565816886
Short name T323
Test name
Test status
Simulation time 285876106 ps
CPU time 14.23 seconds
Started Aug 01 06:26:59 PM PDT 24
Finished Aug 01 06:27:13 PM PDT 24
Peak memory 199828 kb
Host smart-d1e39b2c-721e-46d4-ab63-48702235d27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565816886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2565816886
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2885268195
Short name T307
Test name
Test status
Simulation time 3882945706 ps
CPU time 65.12 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:28:07 PM PDT 24
Peak memory 199936 kb
Host smart-d8e873fb-ae80-4445-969d-079756c03435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885268195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2885268195
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2034024879
Short name T169
Test name
Test status
Simulation time 47651020 ps
CPU time 0.57 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:27:05 PM PDT 24
Peak memory 195568 kb
Host smart-6348009e-4b6f-4e75-913b-a39a2304d6cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034024879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2034024879
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.705775550
Short name T14
Test name
Test status
Simulation time 27354322582 ps
CPU time 96.47 seconds
Started Aug 01 06:27:13 PM PDT 24
Finished Aug 01 06:28:50 PM PDT 24
Peak memory 199940 kb
Host smart-91852b64-ebdb-48a0-8606-33c62f441bf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705775550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.705775550
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1489400296
Short name T407
Test name
Test status
Simulation time 4471939380 ps
CPU time 37.74 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:27:39 PM PDT 24
Peak memory 216428 kb
Host smart-660d520f-ec6e-4942-8aae-b3350113b7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489400296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1489400296
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3703458708
Short name T42
Test name
Test status
Simulation time 2516420743 ps
CPU time 387.01 seconds
Started Aug 01 06:27:03 PM PDT 24
Finished Aug 01 06:33:31 PM PDT 24
Peak memory 659300 kb
Host smart-6595308e-16c8-4e60-b158-b30efd3681fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703458708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3703458708
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1951254273
Short name T6
Test name
Test status
Simulation time 6760393903 ps
CPU time 191.22 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 06:30:07 PM PDT 24
Peak memory 200000 kb
Host smart-d800ca5f-ba10-44ba-baa4-8a8078dbdf1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951254273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1951254273
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3290099517
Short name T442
Test name
Test status
Simulation time 7198849343 ps
CPU time 72.49 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:28:22 PM PDT 24
Peak memory 199964 kb
Host smart-5008a5a1-91a7-4e3a-9e8f-6f61c77463df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290099517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3290099517
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2141749341
Short name T178
Test name
Test status
Simulation time 513801613 ps
CPU time 6.53 seconds
Started Aug 01 06:26:59 PM PDT 24
Finished Aug 01 06:27:06 PM PDT 24
Peak memory 199892 kb
Host smart-672df1ba-6cc2-4fd6-8522-8e7dc5656501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141749341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2141749341
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1283798926
Short name T194
Test name
Test status
Simulation time 75798467500 ps
CPU time 1466.87 seconds
Started Aug 01 06:27:15 PM PDT 24
Finished Aug 01 06:51:42 PM PDT 24
Peak memory 715224 kb
Host smart-836c361b-2e0b-40cd-93b2-3bf16ed7b110
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283798926 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1283798926
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2371597243
Short name T522
Test name
Test status
Simulation time 741654931 ps
CPU time 42.87 seconds
Started Aug 01 06:27:00 PM PDT 24
Finished Aug 01 06:27:43 PM PDT 24
Peak memory 199864 kb
Host smart-c602fa84-978e-4dbb-9bd9-86d734641ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371597243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2371597243
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1200311179
Short name T391
Test name
Test status
Simulation time 12370348 ps
CPU time 0.63 seconds
Started Aug 01 06:27:07 PM PDT 24
Finished Aug 01 06:27:08 PM PDT 24
Peak memory 195552 kb
Host smart-0173af8d-2650-47b7-ba9c-cd88b41770a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200311179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1200311179
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.4112546860
Short name T27
Test name
Test status
Simulation time 634972311 ps
CPU time 17.59 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:27:19 PM PDT 24
Peak memory 199852 kb
Host smart-d099b5c1-9eec-4db0-b984-d6a9217a0a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4112546860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.4112546860
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1020376365
Short name T141
Test name
Test status
Simulation time 3837289331 ps
CPU time 16.94 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:27:18 PM PDT 24
Peak memory 199972 kb
Host smart-ff6e9182-237c-48d6-86a1-c6ad046b20a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020376365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1020376365
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.819833378
Short name T490
Test name
Test status
Simulation time 1048042709 ps
CPU time 176 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:30:00 PM PDT 24
Peak memory 465452 kb
Host smart-f97bf8ca-b794-4123-8a8a-dbd49c3d8185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819833378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.819833378
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.822043560
Short name T298
Test name
Test status
Simulation time 2025938627 ps
CPU time 114.26 seconds
Started Aug 01 06:27:02 PM PDT 24
Finished Aug 01 06:28:57 PM PDT 24
Peak memory 199904 kb
Host smart-ff09ab66-c58c-4dbb-a1c2-05c8fa703b3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822043560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.822043560
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2272267117
Short name T446
Test name
Test status
Simulation time 1418307429 ps
CPU time 83.88 seconds
Started Aug 01 06:27:17 PM PDT 24
Finished Aug 01 06:28:41 PM PDT 24
Peak memory 199872 kb
Host smart-4eeeeb5a-8f59-458e-bd67-d1e233511d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272267117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2272267117
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1448955948
Short name T291
Test name
Test status
Simulation time 308012493 ps
CPU time 5.57 seconds
Started Aug 01 06:27:15 PM PDT 24
Finished Aug 01 06:27:21 PM PDT 24
Peak memory 199816 kb
Host smart-45ecdcda-b530-445d-bb2e-e8164e29eb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448955948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1448955948
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.723318304
Short name T81
Test name
Test status
Simulation time 81806348675 ps
CPU time 1020.95 seconds
Started Aug 01 06:27:03 PM PDT 24
Finished Aug 01 06:44:04 PM PDT 24
Peak memory 199988 kb
Host smart-85229e24-f685-44ff-a30a-b6fb985a75b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723318304 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.723318304
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3389950684
Short name T113
Test name
Test status
Simulation time 9058136301 ps
CPU time 25.1 seconds
Started Aug 01 06:27:02 PM PDT 24
Finished Aug 01 06:27:27 PM PDT 24
Peak memory 199920 kb
Host smart-c3e4824f-1162-4221-a382-141d5f1e232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389950684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3389950684
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3398333568
Short name T483
Test name
Test status
Simulation time 25958995 ps
CPU time 0.56 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:27:10 PM PDT 24
Peak memory 196572 kb
Host smart-09730c99-8948-44a2-afbf-bb97510388f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398333568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3398333568
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2558005839
Short name T164
Test name
Test status
Simulation time 1063633948 ps
CPU time 11.5 seconds
Started Aug 01 06:27:06 PM PDT 24
Finished Aug 01 06:27:18 PM PDT 24
Peak memory 199888 kb
Host smart-8c168b07-698a-44fe-adca-8bc82e1c75c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558005839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2558005839
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.810487745
Short name T411
Test name
Test status
Simulation time 29155963 ps
CPU time 0.71 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:27:05 PM PDT 24
Peak memory 196528 kb
Host smart-e035ce85-86e1-4340-898b-a4796c98d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810487745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.810487745
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3810117996
Short name T516
Test name
Test status
Simulation time 5294989873 ps
CPU time 1037.51 seconds
Started Aug 01 06:27:00 PM PDT 24
Finished Aug 01 06:44:17 PM PDT 24
Peak memory 689320 kb
Host smart-738caa58-7025-472d-844b-06711a5ac0ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810117996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3810117996
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.564499788
Short name T513
Test name
Test status
Simulation time 899301209 ps
CPU time 12.13 seconds
Started Aug 01 06:26:59 PM PDT 24
Finished Aug 01 06:27:12 PM PDT 24
Peak memory 199756 kb
Host smart-b99ad9e3-6e5c-43f2-a3be-f322c61c37af
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564499788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.564499788
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3778955020
Short name T453
Test name
Test status
Simulation time 6290019616 ps
CPU time 110.33 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:28:46 PM PDT 24
Peak memory 208224 kb
Host smart-0f5cd2ca-e7ad-4ea7-aec3-c457af41dab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778955020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3778955020
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.4093735390
Short name T473
Test name
Test status
Simulation time 693553664 ps
CPU time 12.66 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:27:14 PM PDT 24
Peak memory 199860 kb
Host smart-3dff6947-3bf7-4360-8355-5262e87217c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093735390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4093735390
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3331598356
Short name T427
Test name
Test status
Simulation time 1386849539 ps
CPU time 73.64 seconds
Started Aug 01 06:27:09 PM PDT 24
Finished Aug 01 06:28:23 PM PDT 24
Peak memory 199880 kb
Host smart-76b472d8-a4d6-4d73-8f08-ad8560083077
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331598356 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3331598356
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.575991690
Short name T335
Test name
Test status
Simulation time 9939897199 ps
CPU time 63.4 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:28:05 PM PDT 24
Peak memory 199944 kb
Host smart-6c035e89-f760-43ef-ab5d-08b46b47da40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575991690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.575991690
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3682287402
Short name T475
Test name
Test status
Simulation time 184555734 ps
CPU time 0.56 seconds
Started Aug 01 06:27:14 PM PDT 24
Finished Aug 01 06:27:14 PM PDT 24
Peak memory 195576 kb
Host smart-c82bbef2-5d66-4eae-ba7e-ed56ad43a9d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682287402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3682287402
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1962842655
Short name T58
Test name
Test status
Simulation time 4148462289 ps
CPU time 52.9 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:27:57 PM PDT 24
Peak memory 200148 kb
Host smart-d7796a3e-2342-4a29-af6b-163ffb9ce70a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1962842655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1962842655
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3454689464
Short name T168
Test name
Test status
Simulation time 56544225 ps
CPU time 3 seconds
Started Aug 01 06:27:00 PM PDT 24
Finished Aug 01 06:27:03 PM PDT 24
Peak memory 199820 kb
Host smart-dfb0248c-db3f-46e0-b338-4954e74d058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454689464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3454689464
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1776327922
Short name T162
Test name
Test status
Simulation time 15294780869 ps
CPU time 530.13 seconds
Started Aug 01 06:27:02 PM PDT 24
Finished Aug 01 06:35:52 PM PDT 24
Peak memory 716452 kb
Host smart-6ab8b161-e6e8-417f-87f2-55a656c6b8f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776327922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1776327922
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1728514713
Short name T146
Test name
Test status
Simulation time 2852491121 ps
CPU time 164.1 seconds
Started Aug 01 06:27:05 PM PDT 24
Finished Aug 01 06:29:49 PM PDT 24
Peak memory 199916 kb
Host smart-a92cdfde-8ff7-4acd-91b3-9f9f56365e78
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728514713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1728514713
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3047552548
Short name T1
Test name
Test status
Simulation time 11110818312 ps
CPU time 147.32 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:29:37 PM PDT 24
Peak memory 200180 kb
Host smart-5620e377-4051-4ceb-9867-e9be4304726d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047552548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3047552548
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1258411268
Short name T33
Test name
Test status
Simulation time 660611384 ps
CPU time 10.91 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:27:12 PM PDT 24
Peak memory 199840 kb
Host smart-0eccffd3-0f11-4eb4-b12a-370209271e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258411268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1258411268
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1423535626
Short name T5
Test name
Test status
Simulation time 39609440183 ps
CPU time 470.84 seconds
Started Aug 01 06:27:17 PM PDT 24
Finished Aug 01 06:35:08 PM PDT 24
Peak memory 200000 kb
Host smart-56e15454-7ab4-491e-8585-403f18f23fcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423535626 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1423535626
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.134464857
Short name T222
Test name
Test status
Simulation time 21214396487 ps
CPU time 97.75 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:28:48 PM PDT 24
Peak memory 200028 kb
Host smart-8dc83d15-c791-4484-9da9-4c395a18fc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134464857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.134464857
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3761560450
Short name T314
Test name
Test status
Simulation time 11954016 ps
CPU time 0.56 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:27:20 PM PDT 24
Peak memory 194812 kb
Host smart-ef9fc796-a68e-421c-8a1e-4bda2be44cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761560450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3761560450
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3887829265
Short name T273
Test name
Test status
Simulation time 6078047757 ps
CPU time 48.71 seconds
Started Aug 01 06:27:15 PM PDT 24
Finished Aug 01 06:28:03 PM PDT 24
Peak memory 199948 kb
Host smart-7874ab75-5dac-421a-ac29-4e486dd9266f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887829265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3887829265
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3526737836
Short name T26
Test name
Test status
Simulation time 763212877 ps
CPU time 38.34 seconds
Started Aug 01 06:27:09 PM PDT 24
Finished Aug 01 06:27:48 PM PDT 24
Peak memory 199832 kb
Host smart-b0a292bf-5286-4966-a986-b4007ea45622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526737836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3526737836
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2229057957
Short name T300
Test name
Test status
Simulation time 3399488318 ps
CPU time 608.17 seconds
Started Aug 01 06:27:11 PM PDT 24
Finished Aug 01 06:37:20 PM PDT 24
Peak memory 689468 kb
Host smart-6a658ffc-9bb0-464f-8f49-c9b3fe45c81f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229057957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2229057957
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.4279448146
Short name T380
Test name
Test status
Simulation time 58015435142 ps
CPU time 201.7 seconds
Started Aug 01 06:27:09 PM PDT 24
Finished Aug 01 06:30:31 PM PDT 24
Peak memory 199924 kb
Host smart-efcbb830-969c-497e-8b38-6dc962940ae3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279448146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.4279448146
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2562615714
Short name T530
Test name
Test status
Simulation time 27668289793 ps
CPU time 188.95 seconds
Started Aug 01 06:27:06 PM PDT 24
Finished Aug 01 06:30:15 PM PDT 24
Peak memory 216360 kb
Host smart-07677e5d-ddd2-441c-8e73-82438d2d2438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562615714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2562615714
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3779359842
Short name T34
Test name
Test status
Simulation time 741857137 ps
CPU time 6.46 seconds
Started Aug 01 06:27:11 PM PDT 24
Finished Aug 01 06:27:17 PM PDT 24
Peak memory 199880 kb
Host smart-8579efb3-5eb1-4d58-9f9e-3a25ca0f2830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779359842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3779359842
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1146886876
Short name T464
Test name
Test status
Simulation time 3387022596 ps
CPU time 32.97 seconds
Started Aug 01 06:27:12 PM PDT 24
Finished Aug 01 06:27:45 PM PDT 24
Peak memory 200032 kb
Host smart-0abec013-392a-4097-be44-1cff6c6f4e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146886876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1146886876
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3452915255
Short name T377
Test name
Test status
Simulation time 27603821 ps
CPU time 0.61 seconds
Started Aug 01 06:27:22 PM PDT 24
Finished Aug 01 06:27:23 PM PDT 24
Peak memory 195924 kb
Host smart-3bf6dce3-884e-4475-b70d-ce18c85d42b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452915255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3452915255
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.4147465397
Short name T355
Test name
Test status
Simulation time 7280853169 ps
CPU time 78.64 seconds
Started Aug 01 06:27:09 PM PDT 24
Finished Aug 01 06:28:28 PM PDT 24
Peak memory 199972 kb
Host smart-784527ef-eebb-4939-8ba3-424f54029bff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147465397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.4147465397
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3191137658
Short name T353
Test name
Test status
Simulation time 3405185728 ps
CPU time 43.75 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:28:03 PM PDT 24
Peak memory 200036 kb
Host smart-efc16c55-5fb4-4cb2-832f-85f47bbb3e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191137658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3191137658
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2781666142
Short name T392
Test name
Test status
Simulation time 5926579509 ps
CPU time 248.85 seconds
Started Aug 01 06:27:09 PM PDT 24
Finished Aug 01 06:31:18 PM PDT 24
Peak memory 634008 kb
Host smart-425b4144-d2b5-43c6-a4be-b1bb901b520c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781666142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2781666142
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3379412428
Short name T192
Test name
Test status
Simulation time 70445732114 ps
CPU time 254.67 seconds
Started Aug 01 06:27:16 PM PDT 24
Finished Aug 01 06:31:31 PM PDT 24
Peak memory 199968 kb
Host smart-5dc4c658-14b0-488d-919e-de3c110e951d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379412428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3379412428
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3986844396
Short name T275
Test name
Test status
Simulation time 3233352460 ps
CPU time 185.14 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:30:24 PM PDT 24
Peak memory 216128 kb
Host smart-05735556-bdb3-4ac6-ac85-d6cf5ac3a9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986844396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3986844396
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3034993855
Short name T177
Test name
Test status
Simulation time 4461187323 ps
CPU time 13.16 seconds
Started Aug 01 06:27:11 PM PDT 24
Finished Aug 01 06:27:24 PM PDT 24
Peak memory 200196 kb
Host smart-3f5debb9-432e-4bfb-b829-a47c23dbd18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034993855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3034993855
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1542068776
Short name T423
Test name
Test status
Simulation time 11403889052 ps
CPU time 151.14 seconds
Started Aug 01 06:27:14 PM PDT 24
Finished Aug 01 06:29:45 PM PDT 24
Peak memory 216408 kb
Host smart-5e9051f2-fb52-47a2-8d92-8def5a028f69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542068776 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1542068776
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.226705267
Short name T72
Test name
Test status
Simulation time 16415284007 ps
CPU time 71.13 seconds
Started Aug 01 06:27:05 PM PDT 24
Finished Aug 01 06:28:16 PM PDT 24
Peak memory 200028 kb
Host smart-1f743653-ba7b-4b87-bf8e-a9ea59767ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226705267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.226705267
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1086017047
Short name T163
Test name
Test status
Simulation time 38262404 ps
CPU time 0.57 seconds
Started Aug 01 06:27:11 PM PDT 24
Finished Aug 01 06:27:12 PM PDT 24
Peak memory 194940 kb
Host smart-23d44891-4af4-4271-b652-3e83b490a52b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086017047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1086017047
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1252342141
Short name T384
Test name
Test status
Simulation time 2066303754 ps
CPU time 59.64 seconds
Started Aug 01 06:27:05 PM PDT 24
Finished Aug 01 06:28:05 PM PDT 24
Peak memory 199816 kb
Host smart-dfb098dd-0217-4f1f-b1c9-e19d43e85424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252342141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1252342141
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2308650310
Short name T330
Test name
Test status
Simulation time 2655698387 ps
CPU time 51.2 seconds
Started Aug 01 06:27:16 PM PDT 24
Finished Aug 01 06:28:07 PM PDT 24
Peak memory 200204 kb
Host smart-22e37ed5-d0a4-4d0c-b534-71ed08243674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308650310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2308650310
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3619423365
Short name T324
Test name
Test status
Simulation time 1382493431 ps
CPU time 34.91 seconds
Started Aug 01 06:27:11 PM PDT 24
Finished Aug 01 06:27:46 PM PDT 24
Peak memory 256620 kb
Host smart-d769fd0d-36d3-4891-b5d9-a508441b9bd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619423365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3619423365
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2616724316
Short name T214
Test name
Test status
Simulation time 4457862175 ps
CPU time 127.33 seconds
Started Aug 01 06:27:16 PM PDT 24
Finished Aug 01 06:29:24 PM PDT 24
Peak memory 200004 kb
Host smart-264d055b-c22c-477e-a79c-d669053e2aad
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616724316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2616724316
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4177806584
Short name T219
Test name
Test status
Simulation time 24806236548 ps
CPU time 87.13 seconds
Started Aug 01 06:27:06 PM PDT 24
Finished Aug 01 06:28:33 PM PDT 24
Peak memory 199968 kb
Host smart-8615bbd0-3c6f-4ac6-aab7-e54bb2d8f9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177806584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4177806584
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3592533003
Short name T44
Test name
Test status
Simulation time 49572852 ps
CPU time 0.83 seconds
Started Aug 01 06:27:12 PM PDT 24
Finished Aug 01 06:27:12 PM PDT 24
Peak memory 198696 kb
Host smart-71df1067-d31a-4c80-aca1-fb936ace1523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592533003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3592533003
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1295544633
Short name T508
Test name
Test status
Simulation time 57603793884 ps
CPU time 2857.24 seconds
Started Aug 01 06:27:13 PM PDT 24
Finished Aug 01 07:14:51 PM PDT 24
Peak memory 794888 kb
Host smart-273fafa1-ad45-4460-96f7-ad4d45446359
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295544633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1295544633
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.4151435208
Short name T447
Test name
Test status
Simulation time 1157413135 ps
CPU time 10.55 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:27:20 PM PDT 24
Peak memory 199860 kb
Host smart-966205a0-fe09-4641-8bdd-c55c207063b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151435208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.4151435208
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.4064253384
Short name T408
Test name
Test status
Simulation time 16248068 ps
CPU time 0.57 seconds
Started Aug 01 06:26:49 PM PDT 24
Finished Aug 01 06:26:50 PM PDT 24
Peak memory 194892 kb
Host smart-ebdef5f8-c034-468c-b70e-301fe14a0dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064253384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4064253384
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2307127415
Short name T495
Test name
Test status
Simulation time 1214990503 ps
CPU time 74.37 seconds
Started Aug 01 06:26:47 PM PDT 24
Finished Aug 01 06:28:01 PM PDT 24
Peak memory 199912 kb
Host smart-7e7763b7-2ad2-4e61-9796-00986699e7ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2307127415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2307127415
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.30024986
Short name T51
Test name
Test status
Simulation time 2543135544 ps
CPU time 34.66 seconds
Started Aug 01 06:26:44 PM PDT 24
Finished Aug 01 06:27:18 PM PDT 24
Peak memory 199988 kb
Host smart-87bd43b1-3468-431f-977d-9e8dd10f0249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30024986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.30024986
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3545384094
Short name T59
Test name
Test status
Simulation time 2268871183 ps
CPU time 373 seconds
Started Aug 01 06:26:42 PM PDT 24
Finished Aug 01 06:32:55 PM PDT 24
Peak memory 492376 kb
Host smart-7a1b0119-02d5-45ec-9d65-b2a24facc872
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545384094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3545384094
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.152533665
Short name T179
Test name
Test status
Simulation time 10403020725 ps
CPU time 142.21 seconds
Started Aug 01 06:26:41 PM PDT 24
Finished Aug 01 06:29:03 PM PDT 24
Peak memory 199968 kb
Host smart-c8aa77db-749c-447f-a800-0726c73a1771
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152533665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.152533665
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2119247610
Short name T512
Test name
Test status
Simulation time 17760956444 ps
CPU time 55.14 seconds
Started Aug 01 06:26:51 PM PDT 24
Finished Aug 01 06:27:47 PM PDT 24
Peak memory 199928 kb
Host smart-34f73747-b97f-47ff-b4e6-bdced9387759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119247610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2119247610
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3282776324
Short name T67
Test name
Test status
Simulation time 521302764 ps
CPU time 1.02 seconds
Started Aug 01 06:26:53 PM PDT 24
Finished Aug 01 06:26:55 PM PDT 24
Peak memory 219552 kb
Host smart-f595388a-a0bd-474e-869a-5d516b8846fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282776324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3282776324
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.694953762
Short name T462
Test name
Test status
Simulation time 494965280 ps
CPU time 6.48 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 06:27:02 PM PDT 24
Peak memory 199812 kb
Host smart-a1f12345-8b30-4d2f-aa49-3f94a8955b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694953762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.694953762
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3221710733
Short name T127
Test name
Test status
Simulation time 5288850328 ps
CPU time 350.48 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:32:54 PM PDT 24
Peak memory 337440 kb
Host smart-488df1c2-2756-4d15-aa7c-e88ada1e129b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221710733 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3221710733
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1805797965
Short name T24
Test name
Test status
Simulation time 57213464746 ps
CPU time 1275.41 seconds
Started Aug 01 06:27:06 PM PDT 24
Finished Aug 01 06:48:21 PM PDT 24
Peak memory 761604 kb
Host smart-6276a07c-4088-4796-ae3c-4dd88a21c30a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805797965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1805797965
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2979556155
Short name T183
Test name
Test status
Simulation time 5715612518 ps
CPU time 72.06 seconds
Started Aug 01 06:26:58 PM PDT 24
Finished Aug 01 06:28:10 PM PDT 24
Peak memory 200240 kb
Host smart-56a10077-d0ea-4410-a796-f03a5f6e2b8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2979556155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2979556155
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.831623885
Short name T247
Test name
Test status
Simulation time 4623805971 ps
CPU time 56.85 seconds
Started Aug 01 06:26:47 PM PDT 24
Finished Aug 01 06:27:44 PM PDT 24
Peak memory 200028 kb
Host smart-3233139c-7aee-4270-8d59-3972671737dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=831623885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.831623885
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.218291909
Short name T416
Test name
Test status
Simulation time 2358972996 ps
CPU time 75.81 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:28:12 PM PDT 24
Peak memory 199984 kb
Host smart-cb0b1c24-fc58-43a2-8e87-ad53ee29cb0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=218291909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.218291909
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1795992354
Short name T21
Test name
Test status
Simulation time 263656679962 ps
CPU time 594.2 seconds
Started Aug 01 06:26:43 PM PDT 24
Finished Aug 01 06:36:38 PM PDT 24
Peak memory 199988 kb
Host smart-34d90aed-50c6-47c6-8c91-cb761cfc4d27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1795992354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1795992354
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1329544718
Short name T301
Test name
Test status
Simulation time 414420851125 ps
CPU time 2359.51 seconds
Started Aug 01 06:26:47 PM PDT 24
Finished Aug 01 07:06:07 PM PDT 24
Peak memory 215584 kb
Host smart-cd475d5f-a5b6-4101-8c05-ec5df6d1a95a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1329544718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1329544718
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1992820778
Short name T529
Test name
Test status
Simulation time 489421276478 ps
CPU time 2562.94 seconds
Started Aug 01 06:26:45 PM PDT 24
Finished Aug 01 07:09:28 PM PDT 24
Peak memory 215420 kb
Host smart-1790898d-2f62-4960-8ec5-5103c2203cd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1992820778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1992820778
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.4222544219
Short name T521
Test name
Test status
Simulation time 28827324038 ps
CPU time 134.71 seconds
Started Aug 01 06:26:53 PM PDT 24
Finished Aug 01 06:29:08 PM PDT 24
Peak memory 200032 kb
Host smart-7530b7c9-ea8f-4dfb-96c8-a3fd200c8ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222544219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4222544219
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2154924314
Short name T52
Test name
Test status
Simulation time 11354741 ps
CPU time 0.57 seconds
Started Aug 01 06:27:08 PM PDT 24
Finished Aug 01 06:27:09 PM PDT 24
Peak memory 195572 kb
Host smart-3692fb83-d76d-4ff7-b573-0c2641c77a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154924314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2154924314
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1684936607
Short name T30
Test name
Test status
Simulation time 6886927703 ps
CPU time 99.55 seconds
Started Aug 01 06:27:08 PM PDT 24
Finished Aug 01 06:28:48 PM PDT 24
Peak memory 216360 kb
Host smart-07f190a4-4236-4b45-82f2-c512f4c117fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1684936607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1684936607
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2182973730
Short name T304
Test name
Test status
Simulation time 10731706868 ps
CPU time 40.94 seconds
Started Aug 01 06:27:18 PM PDT 24
Finished Aug 01 06:27:59 PM PDT 24
Peak memory 208184 kb
Host smart-5d3389a1-b6cb-45f1-b5ce-b71b350add6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182973730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2182973730
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3315065763
Short name T142
Test name
Test status
Simulation time 169052660 ps
CPU time 16.47 seconds
Started Aug 01 06:27:09 PM PDT 24
Finished Aug 01 06:27:26 PM PDT 24
Peak memory 233036 kb
Host smart-f2d26675-492d-43c4-8e67-e8665f494755
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3315065763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3315065763
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1995611879
Short name T229
Test name
Test status
Simulation time 65791710 ps
CPU time 0.66 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:27:11 PM PDT 24
Peak memory 196328 kb
Host smart-a9f84a91-9ecf-4dfc-9fa8-09cf428ff818
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995611879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1995611879
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2709544190
Short name T351
Test name
Test status
Simulation time 2941945292 ps
CPU time 166.8 seconds
Started Aug 01 06:27:12 PM PDT 24
Finished Aug 01 06:29:59 PM PDT 24
Peak memory 199964 kb
Host smart-d9629c1d-9dfb-4ab0-8376-ee1c869d9038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709544190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2709544190
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.570357001
Short name T322
Test name
Test status
Simulation time 270130544 ps
CPU time 12.91 seconds
Started Aug 01 06:27:18 PM PDT 24
Finished Aug 01 06:27:31 PM PDT 24
Peak memory 199848 kb
Host smart-35e1941b-b0f2-4fae-a277-7a05b190d199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570357001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.570357001
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3625426655
Short name T286
Test name
Test status
Simulation time 18066141550 ps
CPU time 573.82 seconds
Started Aug 01 06:27:15 PM PDT 24
Finished Aug 01 06:36:49 PM PDT 24
Peak memory 703008 kb
Host smart-3c63ec5c-284e-4b52-a55c-8fe70b038e7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625426655 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3625426655
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1100687660
Short name T86
Test name
Test status
Simulation time 1795747578 ps
CPU time 84.44 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:28:34 PM PDT 24
Peak memory 199804 kb
Host smart-aaee5c60-d69e-491f-8481-070823a30b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100687660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1100687660
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2644576662
Short name T305
Test name
Test status
Simulation time 58597920 ps
CPU time 0.58 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:27:11 PM PDT 24
Peak memory 195920 kb
Host smart-4b6ed2ce-f262-42ff-a9d5-c19b8d8c4c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644576662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2644576662
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.329740515
Short name T341
Test name
Test status
Simulation time 2168690663 ps
CPU time 39.08 seconds
Started Aug 01 06:27:12 PM PDT 24
Finished Aug 01 06:27:52 PM PDT 24
Peak memory 199952 kb
Host smart-db2e9828-94db-4a4a-bde7-7013cd7b94db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329740515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.329740515
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2854545127
Short name T63
Test name
Test status
Simulation time 5409118847 ps
CPU time 49.75 seconds
Started Aug 01 06:27:18 PM PDT 24
Finished Aug 01 06:28:08 PM PDT 24
Peak memory 199948 kb
Host smart-4466b5d6-6d32-42c6-a69e-3425589d4127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854545127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2854545127
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1050909232
Short name T354
Test name
Test status
Simulation time 2156983274 ps
CPU time 366.57 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:33:17 PM PDT 24
Peak memory 656008 kb
Host smart-307001bf-4beb-48c6-942d-d1283b5988f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1050909232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1050909232
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.4260706066
Short name T274
Test name
Test status
Simulation time 1762474391 ps
CPU time 101.92 seconds
Started Aug 01 06:27:17 PM PDT 24
Finished Aug 01 06:28:59 PM PDT 24
Peak memory 199844 kb
Host smart-af9e362a-a9c2-40ff-b667-d002f07c3736
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260706066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.4260706066
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3911840107
Short name T267
Test name
Test status
Simulation time 10344135453 ps
CPU time 198.33 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:30:28 PM PDT 24
Peak memory 199996 kb
Host smart-4dafdbce-43d3-4377-b274-9bd3bf435bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911840107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3911840107
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2893901522
Short name T463
Test name
Test status
Simulation time 1781151310 ps
CPU time 7.61 seconds
Started Aug 01 06:27:16 PM PDT 24
Finished Aug 01 06:27:24 PM PDT 24
Peak memory 199860 kb
Host smart-d01b0822-33db-44ab-b5ef-388fcd89378a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893901522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2893901522
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3929495533
Short name T227
Test name
Test status
Simulation time 261341668943 ps
CPU time 2495.79 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 07:08:46 PM PDT 24
Peak memory 774428 kb
Host smart-927c024b-51c6-46e4-b1fe-414da3383a1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929495533 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3929495533
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3105275783
Short name T88
Test name
Test status
Simulation time 25762572695 ps
CPU time 86.18 seconds
Started Aug 01 06:27:18 PM PDT 24
Finished Aug 01 06:28:44 PM PDT 24
Peak memory 200020 kb
Host smart-3ed471ed-217b-4815-a4fb-2b4a39faf309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105275783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3105275783
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1744375443
Short name T321
Test name
Test status
Simulation time 15708780 ps
CPU time 0.59 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:27:25 PM PDT 24
Peak memory 194900 kb
Host smart-cfaf3842-50bb-4151-bb8f-c6374f60ab94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744375443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1744375443
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1576513748
Short name T493
Test name
Test status
Simulation time 1028464686 ps
CPU time 61.16 seconds
Started Aug 01 06:27:12 PM PDT 24
Finished Aug 01 06:28:13 PM PDT 24
Peak memory 199844 kb
Host smart-ab5ce1ad-fa1d-49b6-b5e4-086bed40a845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1576513748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1576513748
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.4023320906
Short name T373
Test name
Test status
Simulation time 687265366 ps
CPU time 36.84 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:27:56 PM PDT 24
Peak memory 199912 kb
Host smart-99d40912-7c1f-479d-8872-c0a1565a1aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023320906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4023320906
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3550678718
Short name T130
Test name
Test status
Simulation time 10239126325 ps
CPU time 347.43 seconds
Started Aug 01 06:27:08 PM PDT 24
Finished Aug 01 06:32:55 PM PDT 24
Peak memory 596848 kb
Host smart-cdeb49b3-2260-4d3e-bcb7-f0e24e9aefbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3550678718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3550678718
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.4104407090
Short name T71
Test name
Test status
Simulation time 28302578189 ps
CPU time 210.59 seconds
Started Aug 01 06:27:18 PM PDT 24
Finished Aug 01 06:30:49 PM PDT 24
Peak memory 199988 kb
Host smart-485088ba-c04f-4cca-aa54-a57bac723c4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104407090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4104407090
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3221217811
Short name T195
Test name
Test status
Simulation time 8237758784 ps
CPU time 144.3 seconds
Started Aug 01 06:27:15 PM PDT 24
Finished Aug 01 06:29:39 PM PDT 24
Peak memory 216220 kb
Host smart-3164a658-6215-4def-9d79-66f56b475fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221217811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3221217811
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2581381633
Short name T372
Test name
Test status
Simulation time 2014110129 ps
CPU time 11.36 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:27:16 PM PDT 24
Peak memory 199840 kb
Host smart-ca0ddd12-8819-49b1-8b96-70b20e9524b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581381633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2581381633
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3983728097
Short name T448
Test name
Test status
Simulation time 1766984942972 ps
CPU time 1152.27 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:46:33 PM PDT 24
Peak memory 208192 kb
Host smart-cc6515c5-290a-44c5-8549-f86f91388647
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983728097 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3983728097
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1978808743
Short name T204
Test name
Test status
Simulation time 4508347979 ps
CPU time 39.85 seconds
Started Aug 01 06:27:10 PM PDT 24
Finished Aug 01 06:27:50 PM PDT 24
Peak memory 200024 kb
Host smart-915160db-ccfc-4245-85a6-f72371a0e698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978808743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1978808743
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2483743858
Short name T191
Test name
Test status
Simulation time 15755518 ps
CPU time 0.57 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:27:25 PM PDT 24
Peak memory 195564 kb
Host smart-ce754711-2397-4fae-8941-cc62228a3de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483743858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2483743858
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3086515295
Short name T415
Test name
Test status
Simulation time 2869838338 ps
CPU time 39.51 seconds
Started Aug 01 06:27:17 PM PDT 24
Finished Aug 01 06:27:57 PM PDT 24
Peak memory 199972 kb
Host smart-68c056f5-3012-4c2f-b7cb-4c9061fdf679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086515295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3086515295
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1515552381
Short name T282
Test name
Test status
Simulation time 9908203314 ps
CPU time 26.08 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:27:46 PM PDT 24
Peak memory 200028 kb
Host smart-bf48abcb-2cac-4be6-845b-6bc459120f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515552381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1515552381
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1750741670
Short name T405
Test name
Test status
Simulation time 7401584070 ps
CPU time 1046.07 seconds
Started Aug 01 06:27:26 PM PDT 24
Finished Aug 01 06:44:52 PM PDT 24
Peak memory 716872 kb
Host smart-70502f0b-a12a-4932-92c0-087d0bb13e9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750741670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1750741670
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2382014041
Short name T174
Test name
Test status
Simulation time 3801897834 ps
CPU time 102.13 seconds
Started Aug 01 06:27:17 PM PDT 24
Finished Aug 01 06:29:00 PM PDT 24
Peak memory 199980 kb
Host smart-f5a20da8-f9e3-488b-a307-8ea11d07e6d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382014041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2382014041
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1569343669
Short name T264
Test name
Test status
Simulation time 21176786204 ps
CPU time 130.02 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:29:35 PM PDT 24
Peak memory 199904 kb
Host smart-089aaa89-c988-46d7-80b8-a3f729befb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569343669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1569343669
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3964234777
Short name T243
Test name
Test status
Simulation time 928812728 ps
CPU time 12.52 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:27:32 PM PDT 24
Peak memory 199900 kb
Host smart-1dd4d180-b862-4e2d-93e2-2772240b9375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964234777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3964234777
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1639781411
Short name T84
Test name
Test status
Simulation time 158745641984 ps
CPU time 461.82 seconds
Started Aug 01 06:27:23 PM PDT 24
Finished Aug 01 06:35:06 PM PDT 24
Peak memory 199944 kb
Host smart-86590801-3edb-49d2-b472-5d15e8a250ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639781411 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1639781411
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2478520320
Short name T425
Test name
Test status
Simulation time 3015438334 ps
CPU time 23.01 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:27:43 PM PDT 24
Peak memory 199980 kb
Host smart-b2c7690e-6cb1-4055-82a8-979328eaaac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478520320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2478520320
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1267324292
Short name T318
Test name
Test status
Simulation time 15914011 ps
CPU time 0.63 seconds
Started Aug 01 06:27:22 PM PDT 24
Finished Aug 01 06:27:23 PM PDT 24
Peak memory 194892 kb
Host smart-09a8f0d1-64e1-4865-a5f6-9ea55cd56af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267324292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1267324292
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3151778427
Short name T209
Test name
Test status
Simulation time 2896518023 ps
CPU time 77.82 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:28:38 PM PDT 24
Peak memory 199964 kb
Host smart-3aadc12b-5537-44d5-bb2c-b4dc9c70f687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3151778427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3151778427
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.503774724
Short name T470
Test name
Test status
Simulation time 3012833113 ps
CPU time 38.45 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:27:59 PM PDT 24
Peak memory 199904 kb
Host smart-89ab030d-f10c-41c5-a7e0-d168d0fb3d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503774724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.503774724
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3062827169
Short name T208
Test name
Test status
Simulation time 16794748559 ps
CPU time 735.38 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:39:35 PM PDT 24
Peak memory 634152 kb
Host smart-be1ddb4e-d7ab-49ed-abbb-daecf809dc14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3062827169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3062827169
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1140126701
Short name T188
Test name
Test status
Simulation time 36674453184 ps
CPU time 166.92 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:30:12 PM PDT 24
Peak memory 199936 kb
Host smart-db22cde0-4644-44ed-9b95-3f5c8a9b079c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140126701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1140126701
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2256958849
Short name T381
Test name
Test status
Simulation time 5468161578 ps
CPU time 186.99 seconds
Started Aug 01 06:27:18 PM PDT 24
Finished Aug 01 06:30:26 PM PDT 24
Peak memory 216256 kb
Host smart-97043228-cce6-4b51-8dc3-f5fa667d9ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256958849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2256958849
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.563406233
Short name T316
Test name
Test status
Simulation time 715058722 ps
CPU time 8.99 seconds
Started Aug 01 06:27:17 PM PDT 24
Finished Aug 01 06:27:26 PM PDT 24
Peak memory 199836 kb
Host smart-5e2a1ffa-112e-421a-a7b3-c5498b2a2cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563406233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.563406233
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3173456369
Short name T396
Test name
Test status
Simulation time 4163149492 ps
CPU time 100.35 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:28:59 PM PDT 24
Peak memory 199948 kb
Host smart-03c43c78-743f-4c50-bade-c8124952eb86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173456369 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3173456369
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2408012310
Short name T437
Test name
Test status
Simulation time 4528087479 ps
CPU time 66.13 seconds
Started Aug 01 06:27:17 PM PDT 24
Finished Aug 01 06:28:23 PM PDT 24
Peak memory 200036 kb
Host smart-2ac4a91b-a301-4781-baff-90fd24dd84d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408012310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2408012310
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3059533628
Short name T433
Test name
Test status
Simulation time 43845260 ps
CPU time 0.6 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:27:21 PM PDT 24
Peak memory 196512 kb
Host smart-41e3e481-4d29-4940-8786-1405f129d5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059533628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3059533628
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.985725703
Short name T7
Test name
Test status
Simulation time 19424169564 ps
CPU time 78.82 seconds
Started Aug 01 06:27:21 PM PDT 24
Finished Aug 01 06:28:40 PM PDT 24
Peak memory 215444 kb
Host smart-f763f14d-04c8-4558-a33a-ebdabb81de90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985725703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.985725703
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2859130429
Short name T268
Test name
Test status
Simulation time 409385544 ps
CPU time 2.57 seconds
Started Aug 01 06:27:21 PM PDT 24
Finished Aug 01 06:27:24 PM PDT 24
Peak memory 199848 kb
Host smart-c3b06e81-3db0-42ff-936e-bad50eae342d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859130429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2859130429
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2384024887
Short name T218
Test name
Test status
Simulation time 1009993329 ps
CPU time 166.24 seconds
Started Aug 01 06:27:18 PM PDT 24
Finished Aug 01 06:30:05 PM PDT 24
Peak memory 483952 kb
Host smart-a9c16612-aff5-4519-83fc-0605ad4de64c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384024887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2384024887
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.504436678
Short name T251
Test name
Test status
Simulation time 3116948409 ps
CPU time 163.74 seconds
Started Aug 01 06:27:17 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 199992 kb
Host smart-a3240a05-45b9-465b-9e75-24b0517dea21
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504436678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.504436678
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2861261326
Short name T312
Test name
Test status
Simulation time 1303962250 ps
CPU time 4.55 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:27:24 PM PDT 24
Peak memory 199824 kb
Host smart-d759d047-4f9b-4ace-afdd-b959e43cb7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861261326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2861261326
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1565802344
Short name T443
Test name
Test status
Simulation time 2109267191 ps
CPU time 8.95 seconds
Started Aug 01 06:27:22 PM PDT 24
Finished Aug 01 06:27:31 PM PDT 24
Peak memory 199836 kb
Host smart-b7796164-fca3-4b93-b4a2-6e8adf1d0823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565802344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1565802344
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1690165798
Short name T289
Test name
Test status
Simulation time 295572397772 ps
CPU time 3817.48 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 07:30:57 PM PDT 24
Peak memory 877000 kb
Host smart-a0b90641-c8ec-48a0-b3a4-fe1561396ff8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690165798 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1690165798
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3723098547
Short name T111
Test name
Test status
Simulation time 3755669772 ps
CPU time 50.69 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:28:11 PM PDT 24
Peak memory 200012 kb
Host smart-1a58b5a3-6e17-434a-9607-33e23e664d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723098547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3723098547
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3763562425
Short name T378
Test name
Test status
Simulation time 60888605 ps
CPU time 0.61 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:27:20 PM PDT 24
Peak memory 195920 kb
Host smart-3bfd373a-0538-4ee5-8cd7-0100b9e34565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763562425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3763562425
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.282332078
Short name T370
Test name
Test status
Simulation time 896371845 ps
CPU time 26.46 seconds
Started Aug 01 06:27:27 PM PDT 24
Finished Aug 01 06:27:54 PM PDT 24
Peak memory 199852 kb
Host smart-04958d96-1fb5-49e8-9e67-853d0e70aafa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282332078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.282332078
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.4294015705
Short name T499
Test name
Test status
Simulation time 4404110168 ps
CPU time 55.49 seconds
Started Aug 01 06:27:16 PM PDT 24
Finished Aug 01 06:28:12 PM PDT 24
Peak memory 199964 kb
Host smart-9e83b14b-4b0f-4b0e-9139-0ab98701df93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294015705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.4294015705
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.532833767
Short name T278
Test name
Test status
Simulation time 26306573772 ps
CPU time 630.03 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:37:49 PM PDT 24
Peak memory 658076 kb
Host smart-ed9710fd-1a6f-4585-b824-22e9bc4107b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532833767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.532833767
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1773985961
Short name T409
Test name
Test status
Simulation time 12371935974 ps
CPU time 19.35 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:27:40 PM PDT 24
Peak memory 199944 kb
Host smart-a35b3b22-4560-41e5-8d2d-e48fcb74f6b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773985961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1773985961
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2445138072
Short name T70
Test name
Test status
Simulation time 5276397792 ps
CPU time 153.79 seconds
Started Aug 01 06:27:21 PM PDT 24
Finished Aug 01 06:29:55 PM PDT 24
Peak memory 199980 kb
Host smart-5c285a6e-8186-4da2-b42b-ef54115964d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445138072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2445138072
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.103978330
Short name T160
Test name
Test status
Simulation time 284827186 ps
CPU time 6.36 seconds
Started Aug 01 06:27:21 PM PDT 24
Finished Aug 01 06:27:27 PM PDT 24
Peak memory 199888 kb
Host smart-7d4d1d5d-e98f-467c-8a72-165eaf91fd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103978330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.103978330
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1764055153
Short name T523
Test name
Test status
Simulation time 10239865418 ps
CPU time 188.83 seconds
Started Aug 01 06:27:21 PM PDT 24
Finished Aug 01 06:30:30 PM PDT 24
Peak memory 200040 kb
Host smart-8f646ab3-2668-4cc6-8771-18e2c1306720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764055153 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1764055153
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3442238060
Short name T249
Test name
Test status
Simulation time 379645637 ps
CPU time 5.22 seconds
Started Aug 01 06:27:16 PM PDT 24
Finished Aug 01 06:27:21 PM PDT 24
Peak memory 199796 kb
Host smart-1c2c5354-3dd1-46ce-9309-c539848931b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442238060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3442238060
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2445691784
Short name T465
Test name
Test status
Simulation time 36300259 ps
CPU time 0.58 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:27:20 PM PDT 24
Peak memory 194888 kb
Host smart-4f3dd3b9-204a-4570-9a6d-f4610afe332a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445691784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2445691784
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2027923569
Short name T389
Test name
Test status
Simulation time 1507452912 ps
CPU time 76.87 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:28:37 PM PDT 24
Peak memory 199812 kb
Host smart-53e127cd-d10c-41ce-a29c-ad38f74f6d75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027923569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2027923569
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1121369042
Short name T136
Test name
Test status
Simulation time 172046776 ps
CPU time 4.45 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:27:24 PM PDT 24
Peak memory 199868 kb
Host smart-be28a9a9-b6c5-48e9-813b-24389b2df58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121369042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1121369042
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2868082568
Short name T257
Test name
Test status
Simulation time 432046803 ps
CPU time 86.61 seconds
Started Aug 01 06:27:25 PM PDT 24
Finished Aug 01 06:28:52 PM PDT 24
Peak memory 441476 kb
Host smart-5dafc1fe-6604-4225-bacf-31541e424522
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868082568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2868082568
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.452296724
Short name T254
Test name
Test status
Simulation time 3236437122 ps
CPU time 15.35 seconds
Started Aug 01 06:27:18 PM PDT 24
Finished Aug 01 06:27:34 PM PDT 24
Peak memory 199860 kb
Host smart-d9e5bb60-da15-4041-8abe-00569cee7a3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452296724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.452296724
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1236211273
Short name T430
Test name
Test status
Simulation time 8033051224 ps
CPU time 114.36 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:29:13 PM PDT 24
Peak memory 216208 kb
Host smart-be15e16f-34e5-4f8c-9379-d5a65dd90f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236211273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1236211273
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.4167130634
Short name T466
Test name
Test status
Simulation time 609514261 ps
CPU time 3.73 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:27:23 PM PDT 24
Peak memory 199908 kb
Host smart-ce7f4c91-db51-4955-9ff6-5ed59922b97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167130634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4167130634
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3498400603
Short name T299
Test name
Test status
Simulation time 77951724686 ps
CPU time 1584.13 seconds
Started Aug 01 06:27:19 PM PDT 24
Finished Aug 01 06:53:44 PM PDT 24
Peak memory 681200 kb
Host smart-6dd603ca-8341-4473-8d2e-352339f2983e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498400603 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3498400603
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.867244305
Short name T412
Test name
Test status
Simulation time 23396520150 ps
CPU time 101.74 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:29:02 PM PDT 24
Peak memory 199944 kb
Host smart-0bc03cb0-e02b-4af7-8b5c-65d5519d0118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867244305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.867244305
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1454826398
Short name T478
Test name
Test status
Simulation time 16747454 ps
CPU time 0.57 seconds
Started Aug 01 06:27:22 PM PDT 24
Finished Aug 01 06:27:23 PM PDT 24
Peak memory 195912 kb
Host smart-e164839a-ae7f-4d9d-af1e-578a6b98f4b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454826398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1454826398
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3033642456
Short name T451
Test name
Test status
Simulation time 992844086 ps
CPU time 15.16 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:27:36 PM PDT 24
Peak memory 199832 kb
Host smart-598d790a-f01f-4bce-9f48-dd17ce7bb365
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033642456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3033642456
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2759864126
Short name T455
Test name
Test status
Simulation time 8405779875 ps
CPU time 47.2 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:28:08 PM PDT 24
Peak memory 199872 kb
Host smart-921e4729-9d74-4e39-8735-aded3ba720e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759864126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2759864126
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2488366201
Short name T371
Test name
Test status
Simulation time 8045978420 ps
CPU time 687.81 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:38:48 PM PDT 24
Peak memory 689908 kb
Host smart-7e68d435-15d5-40b3-84fd-da9052d0889c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2488366201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2488366201
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2785250621
Short name T501
Test name
Test status
Simulation time 48862492664 ps
CPU time 168.98 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:30:13 PM PDT 24
Peak memory 199984 kb
Host smart-a686c6e1-ebfb-49d9-a407-c1bcccdd57b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785250621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2785250621
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2579376206
Short name T182
Test name
Test status
Simulation time 51452309841 ps
CPU time 178.12 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:30:18 PM PDT 24
Peak memory 208136 kb
Host smart-e3d7711c-a39a-44f0-b381-2816d2188b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579376206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2579376206
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3438050444
Short name T175
Test name
Test status
Simulation time 197811472 ps
CPU time 9.32 seconds
Started Aug 01 06:27:22 PM PDT 24
Finished Aug 01 06:27:32 PM PDT 24
Peak memory 199864 kb
Host smart-6d2faa74-7917-42d2-8cc9-43e712bfde5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438050444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3438050444
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3273104009
Short name T85
Test name
Test status
Simulation time 68728881628 ps
CPU time 4583.54 seconds
Started Aug 01 06:27:23 PM PDT 24
Finished Aug 01 07:43:48 PM PDT 24
Peak memory 861248 kb
Host smart-c86c46f0-aaee-48e0-9d8d-eae9e2593951
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273104009 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3273104009
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3875109171
Short name T159
Test name
Test status
Simulation time 6751931821 ps
CPU time 121.53 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:29:26 PM PDT 24
Peak memory 199928 kb
Host smart-c0eca7b9-505c-41ba-8aeb-ffefd90c036c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875109171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3875109171
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.321457361
Short name T403
Test name
Test status
Simulation time 45855197 ps
CPU time 0.59 seconds
Started Aug 01 06:27:21 PM PDT 24
Finished Aug 01 06:27:22 PM PDT 24
Peak memory 195524 kb
Host smart-e0e1a193-08e1-47c2-a0b8-de93ca89108a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321457361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.321457361
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.4082094384
Short name T150
Test name
Test status
Simulation time 6464703097 ps
CPU time 79.37 seconds
Started Aug 01 06:27:23 PM PDT 24
Finished Aug 01 06:28:43 PM PDT 24
Peak memory 216360 kb
Host smart-5d2a2e43-fffb-40da-bcd0-92dc1edcae43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082094384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.4082094384
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2683507944
Short name T519
Test name
Test status
Simulation time 1275891147 ps
CPU time 66.53 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:28:30 PM PDT 24
Peak memory 199928 kb
Host smart-e0c096e9-ac15-4d5e-8e41-aec4838e234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683507944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2683507944
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2112480227
Short name T352
Test name
Test status
Simulation time 32227873392 ps
CPU time 1687.47 seconds
Started Aug 01 06:27:23 PM PDT 24
Finished Aug 01 06:55:31 PM PDT 24
Peak memory 781056 kb
Host smart-83c16db2-d491-4f3b-a98c-03a7397cb5f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112480227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2112480227
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.837165419
Short name T171
Test name
Test status
Simulation time 5214851399 ps
CPU time 89.09 seconds
Started Aug 01 06:27:20 PM PDT 24
Finished Aug 01 06:28:49 PM PDT 24
Peak memory 199988 kb
Host smart-e82d981f-4464-4181-acd2-e89d8ba38112
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837165419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.837165419
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1248510583
Short name T340
Test name
Test status
Simulation time 14823850416 ps
CPU time 87.7 seconds
Started Aug 01 06:27:22 PM PDT 24
Finished Aug 01 06:28:50 PM PDT 24
Peak memory 200080 kb
Host smart-2696b5b4-d080-4336-976a-095ec8c8963e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248510583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1248510583
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1229211023
Short name T328
Test name
Test status
Simulation time 3350726225 ps
CPU time 11.38 seconds
Started Aug 01 06:27:26 PM PDT 24
Finished Aug 01 06:27:37 PM PDT 24
Peak memory 200032 kb
Host smart-04951230-bf8d-4a4f-a30a-0f3dbc893503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229211023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1229211023
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3671463851
Short name T76
Test name
Test status
Simulation time 355056416808 ps
CPU time 2175.02 seconds
Started Aug 01 06:27:22 PM PDT 24
Finished Aug 01 07:03:38 PM PDT 24
Peak memory 700660 kb
Host smart-a13c8dcf-048d-426c-878d-eb55f2e33440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671463851 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3671463851
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2934420058
Short name T255
Test name
Test status
Simulation time 503054166 ps
CPU time 6.5 seconds
Started Aug 01 06:27:23 PM PDT 24
Finished Aug 01 06:27:29 PM PDT 24
Peak memory 199844 kb
Host smart-db343532-3a42-4506-84c5-5be1bb37597c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934420058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2934420058
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.737920439
Short name T56
Test name
Test status
Simulation time 51468169 ps
CPU time 0.66 seconds
Started Aug 01 06:26:52 PM PDT 24
Finished Aug 01 06:26:53 PM PDT 24
Peak memory 195948 kb
Host smart-7f1c7109-5a1a-41a9-90ea-6df6784d3211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737920439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.737920439
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2995975287
Short name T216
Test name
Test status
Simulation time 1127437665 ps
CPU time 65.36 seconds
Started Aug 01 06:26:49 PM PDT 24
Finished Aug 01 06:27:54 PM PDT 24
Peak memory 199820 kb
Host smart-072cf6aa-31d6-4454-85cb-0c7ef4949a80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995975287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2995975287
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1987536769
Short name T292
Test name
Test status
Simulation time 863413268 ps
CPU time 45.09 seconds
Started Aug 01 06:26:45 PM PDT 24
Finished Aug 01 06:27:30 PM PDT 24
Peak memory 199896 kb
Host smart-e8e7b1d4-1cdf-48b7-adbc-acac6df1ec9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987536769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1987536769
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3184729402
Short name T329
Test name
Test status
Simulation time 33066055253 ps
CPU time 450.9 seconds
Started Aug 01 06:26:39 PM PDT 24
Finished Aug 01 06:34:10 PM PDT 24
Peak memory 482020 kb
Host smart-dd15a561-ee79-4b0c-9a9e-781bf6be6922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3184729402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3184729402
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2144633788
Short name T414
Test name
Test status
Simulation time 6530807958 ps
CPU time 167.99 seconds
Started Aug 01 06:26:53 PM PDT 24
Finished Aug 01 06:29:41 PM PDT 24
Peak memory 199960 kb
Host smart-f8a7d787-41b3-4c21-b0b2-4db9b4d44af2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144633788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2144633788
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1632296883
Short name T158
Test name
Test status
Simulation time 5858895394 ps
CPU time 55.58 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 06:27:56 PM PDT 24
Peak memory 200252 kb
Host smart-13a407dc-2a25-4cbf-b581-039b049e0bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632296883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1632296883
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2656779782
Short name T65
Test name
Test status
Simulation time 35803121 ps
CPU time 0.8 seconds
Started Aug 01 06:26:50 PM PDT 24
Finished Aug 01 06:26:51 PM PDT 24
Peak memory 218612 kb
Host smart-8099ec6e-f3d8-4507-9a8f-83fd9c6a7423
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656779782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2656779782
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2222543641
Short name T350
Test name
Test status
Simulation time 640672302 ps
CPU time 15.14 seconds
Started Aug 01 06:26:54 PM PDT 24
Finished Aug 01 06:27:09 PM PDT 24
Peak memory 200080 kb
Host smart-264f4ce0-89ee-4592-991a-e5576e1cb7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222543641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2222543641
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1838438021
Short name T504
Test name
Test status
Simulation time 470172041516 ps
CPU time 3840.12 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 07:30:56 PM PDT 24
Peak memory 817180 kb
Host smart-5a42a368-149d-431b-a0e0-029f40b8d3da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838438021 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1838438021
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.99922280
Short name T139
Test name
Test status
Simulation time 6057781876 ps
CPU time 77.81 seconds
Started Aug 01 06:26:51 PM PDT 24
Finished Aug 01 06:28:09 PM PDT 24
Peak memory 200036 kb
Host smart-1f0455c4-b563-489a-9d67-a9b3009eb53a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=99922280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.99922280
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.2057009422
Short name T345
Test name
Test status
Simulation time 15279627770 ps
CPU time 67.95 seconds
Started Aug 01 06:27:02 PM PDT 24
Finished Aug 01 06:28:10 PM PDT 24
Peak memory 199960 kb
Host smart-3d078d0c-9bf0-4e5a-beed-1a39633cf2ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2057009422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2057009422
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2380344857
Short name T510
Test name
Test status
Simulation time 35755871966 ps
CPU time 90.72 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:28:27 PM PDT 24
Peak memory 199960 kb
Host smart-303e894d-195d-4437-be0a-989e72edf131
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2380344857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2380344857
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2671920382
Short name T166
Test name
Test status
Simulation time 20853265020 ps
CPU time 615.98 seconds
Started Aug 01 06:27:00 PM PDT 24
Finished Aug 01 06:37:17 PM PDT 24
Peak memory 199928 kb
Host smart-99970660-c6af-4d5e-9f60-1f106e530423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2671920382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2671920382
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.826725311
Short name T438
Test name
Test status
Simulation time 285759153122 ps
CPU time 2466.01 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 07:08:02 PM PDT 24
Peak memory 215420 kb
Host smart-791c9285-a7e6-43d1-baf6-9883ee3a3b16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=826725311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.826725311
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2157367907
Short name T225
Test name
Test status
Simulation time 769590527343 ps
CPU time 2362.89 seconds
Started Aug 01 06:26:53 PM PDT 24
Finished Aug 01 07:06:16 PM PDT 24
Peak memory 216232 kb
Host smart-cbebe799-46f6-4a27-a1a4-2c4cd89655d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2157367907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2157367907
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1609135774
Short name T18
Test name
Test status
Simulation time 1987453833 ps
CPU time 15.95 seconds
Started Aug 01 06:26:48 PM PDT 24
Finished Aug 01 06:27:04 PM PDT 24
Peak memory 199808 kb
Host smart-10c79560-d6ae-46b1-a0f6-17a17e4ced6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609135774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1609135774
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2990434338
Short name T39
Test name
Test status
Simulation time 12045532 ps
CPU time 0.59 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:27:25 PM PDT 24
Peak memory 195652 kb
Host smart-d022b983-da61-431c-a561-4c1ce3df0173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990434338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2990434338
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2308504625
Short name T15
Test name
Test status
Simulation time 2531688642 ps
CPU time 75.49 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:28:39 PM PDT 24
Peak memory 199968 kb
Host smart-2ca7ffef-9cdc-4e7c-a57b-1c0428b57888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308504625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2308504625
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3187846945
Short name T367
Test name
Test status
Simulation time 218148668 ps
CPU time 11.04 seconds
Started Aug 01 06:27:25 PM PDT 24
Finished Aug 01 06:27:36 PM PDT 24
Peak memory 199888 kb
Host smart-96186935-3d96-40fb-940d-19abecd321f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187846945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3187846945
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2046159577
Short name T145
Test name
Test status
Simulation time 566272924 ps
CPU time 79.08 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:28:43 PM PDT 24
Peak memory 417164 kb
Host smart-275ba254-c6c0-48ca-9d0b-7cddceb4b978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046159577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2046159577
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.53972988
Short name T176
Test name
Test status
Simulation time 13911562986 ps
CPU time 128.55 seconds
Started Aug 01 06:27:25 PM PDT 24
Finished Aug 01 06:29:34 PM PDT 24
Peak memory 199932 kb
Host smart-5cce4c5b-ca94-4f65-8846-117136ba6dbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53972988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.53972988
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2233469277
Short name T489
Test name
Test status
Simulation time 899602007 ps
CPU time 16.28 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:27:41 PM PDT 24
Peak memory 199824 kb
Host smart-9998e2ca-32fa-46ad-b475-7806881dfe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233469277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2233469277
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3781855124
Short name T469
Test name
Test status
Simulation time 868654731 ps
CPU time 11.35 seconds
Started Aug 01 06:27:25 PM PDT 24
Finished Aug 01 06:27:36 PM PDT 24
Peak memory 199920 kb
Host smart-7d546691-54ec-4c7a-b51a-3be0da86c538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781855124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3781855124
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.208977605
Short name T248
Test name
Test status
Simulation time 10411065183 ps
CPU time 176.99 seconds
Started Aug 01 06:27:26 PM PDT 24
Finished Aug 01 06:30:23 PM PDT 24
Peak memory 199964 kb
Host smart-6f51730c-ec9f-4440-9890-c5bb76f169f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208977605 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.208977605
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2455289189
Short name T187
Test name
Test status
Simulation time 5191953713 ps
CPU time 93.44 seconds
Started Aug 01 06:27:28 PM PDT 24
Finished Aug 01 06:29:01 PM PDT 24
Peak memory 199960 kb
Host smart-a5baa921-312e-4b88-a633-23b38911aedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455289189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2455289189
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2310667855
Short name T494
Test name
Test status
Simulation time 140570008 ps
CPU time 0.57 seconds
Started Aug 01 06:27:26 PM PDT 24
Finished Aug 01 06:27:27 PM PDT 24
Peak memory 194900 kb
Host smart-a17c9225-c3cc-4b22-947b-b0f1115bd654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310667855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2310667855
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3550680973
Short name T457
Test name
Test status
Simulation time 9625284207 ps
CPU time 99.9 seconds
Started Aug 01 06:27:21 PM PDT 24
Finished Aug 01 06:29:01 PM PDT 24
Peak memory 208172 kb
Host smart-bb022eb5-7671-473e-ae8f-267e92800009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3550680973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3550680973
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.152322925
Short name T346
Test name
Test status
Simulation time 7670511583 ps
CPU time 32.31 seconds
Started Aug 01 06:27:28 PM PDT 24
Finished Aug 01 06:28:01 PM PDT 24
Peak memory 199964 kb
Host smart-4665df40-1b05-4373-8ad7-6c86483e5b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152322925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.152322925
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3520170815
Short name T514
Test name
Test status
Simulation time 7633713347 ps
CPU time 724.88 seconds
Started Aug 01 06:27:26 PM PDT 24
Finished Aug 01 06:39:31 PM PDT 24
Peak memory 654396 kb
Host smart-df2728cc-40a0-4d64-9f68-bac35f5acca0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520170815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3520170815
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2975731509
Short name T262
Test name
Test status
Simulation time 1327770576 ps
CPU time 19.27 seconds
Started Aug 01 06:27:23 PM PDT 24
Finished Aug 01 06:27:42 PM PDT 24
Peak memory 199872 kb
Host smart-c7da79d1-8b8a-4a63-8101-d651ecc4bd59
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975731509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2975731509
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.4001714431
Short name T285
Test name
Test status
Simulation time 14353695138 ps
CPU time 190.39 seconds
Started Aug 01 06:27:28 PM PDT 24
Finished Aug 01 06:30:39 PM PDT 24
Peak memory 199948 kb
Host smart-90a36264-d892-44e3-8eb1-ba690b8c66c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001714431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.4001714431
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2823811799
Short name T149
Test name
Test status
Simulation time 723006947 ps
CPU time 12.74 seconds
Started Aug 01 06:27:24 PM PDT 24
Finished Aug 01 06:27:37 PM PDT 24
Peak memory 199828 kb
Host smart-8ca2a7e5-ab41-4cc8-b974-07fc0f61d0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823811799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2823811799
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2024231464
Short name T269
Test name
Test status
Simulation time 37903917234 ps
CPU time 181.65 seconds
Started Aug 01 06:27:33 PM PDT 24
Finished Aug 01 06:30:35 PM PDT 24
Peak memory 200044 kb
Host smart-7388eb60-f467-48a5-a7dc-20a71383ac2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024231464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2024231464
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.143405663
Short name T311
Test name
Test status
Simulation time 231087416 ps
CPU time 13.76 seconds
Started Aug 01 06:27:32 PM PDT 24
Finished Aug 01 06:27:46 PM PDT 24
Peak memory 199816 kb
Host smart-cc2332f1-aaf7-40de-b3e5-e2509f873e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143405663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.143405663
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.962000768
Short name T237
Test name
Test status
Simulation time 11586465 ps
CPU time 0.57 seconds
Started Aug 01 06:27:36 PM PDT 24
Finished Aug 01 06:27:37 PM PDT 24
Peak memory 195568 kb
Host smart-19133725-8d2e-4066-9dcf-46b044ac0303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962000768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.962000768
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1565965961
Short name T62
Test name
Test status
Simulation time 1683546199 ps
CPU time 51.75 seconds
Started Aug 01 06:27:35 PM PDT 24
Finished Aug 01 06:28:27 PM PDT 24
Peak memory 199916 kb
Host smart-7f51a501-8aca-4c66-9b30-a578a2ec3099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565965961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1565965961
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.4149416651
Short name T509
Test name
Test status
Simulation time 2546740921 ps
CPU time 7.66 seconds
Started Aug 01 06:27:32 PM PDT 24
Finished Aug 01 06:27:40 PM PDT 24
Peak memory 199972 kb
Host smart-23521a44-2a4b-4b3c-bd71-ee7b03e3be29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149416651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.4149416651
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2230223946
Short name T233
Test name
Test status
Simulation time 39780928407 ps
CPU time 2084.71 seconds
Started Aug 01 06:27:28 PM PDT 24
Finished Aug 01 07:02:13 PM PDT 24
Peak memory 729648 kb
Host smart-c7884171-395a-432f-9d71-9c4bc68fb70f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230223946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2230223946
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.648549171
Short name T2
Test name
Test status
Simulation time 7676486093 ps
CPU time 140.08 seconds
Started Aug 01 06:27:28 PM PDT 24
Finished Aug 01 06:29:48 PM PDT 24
Peak memory 199980 kb
Host smart-392ed04c-d556-4e30-807f-6c2a3bdc4b5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648549171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.648549171
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1501527543
Short name T211
Test name
Test status
Simulation time 18325210488 ps
CPU time 55.44 seconds
Started Aug 01 06:27:30 PM PDT 24
Finished Aug 01 06:28:25 PM PDT 24
Peak memory 200088 kb
Host smart-2ab3b18e-acac-4fee-8c40-d8f72493ae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501527543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1501527543
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.574124614
Short name T362
Test name
Test status
Simulation time 130952150 ps
CPU time 5.59 seconds
Started Aug 01 06:27:27 PM PDT 24
Finished Aug 01 06:27:33 PM PDT 24
Peak memory 199900 kb
Host smart-ef08815f-faac-487f-a70f-2634e4845325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574124614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.574124614
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1534790572
Short name T253
Test name
Test status
Simulation time 8797843329 ps
CPU time 902.4 seconds
Started Aug 01 06:27:36 PM PDT 24
Finished Aug 01 06:42:38 PM PDT 24
Peak memory 697228 kb
Host smart-61e78da4-299a-4ce4-8e73-82743ff4f747
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534790572 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1534790572
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.729076986
Short name T347
Test name
Test status
Simulation time 2829050698 ps
CPU time 29.03 seconds
Started Aug 01 06:27:36 PM PDT 24
Finished Aug 01 06:28:06 PM PDT 24
Peak memory 199944 kb
Host smart-15de630f-ab54-4874-9f8b-657c984ec9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729076986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.729076986
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1706205788
Short name T368
Test name
Test status
Simulation time 15713821 ps
CPU time 0.59 seconds
Started Aug 01 06:27:30 PM PDT 24
Finished Aug 01 06:27:31 PM PDT 24
Peak memory 195528 kb
Host smart-ceb26eeb-b4e9-494b-aed4-7b3b5aba2aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706205788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1706205788
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3562491920
Short name T161
Test name
Test status
Simulation time 702956892 ps
CPU time 39.39 seconds
Started Aug 01 06:27:34 PM PDT 24
Finished Aug 01 06:28:14 PM PDT 24
Peak memory 199916 kb
Host smart-822e4343-f2e4-40e4-bebe-b9b11d0af09d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562491920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3562491920
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2449265114
Short name T296
Test name
Test status
Simulation time 2366362883 ps
CPU time 59.13 seconds
Started Aug 01 06:27:32 PM PDT 24
Finished Aug 01 06:28:31 PM PDT 24
Peak memory 199948 kb
Host smart-45ea3816-603f-4eaa-972d-0685524dbfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449265114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2449265114
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2345735003
Short name T259
Test name
Test status
Simulation time 4133719997 ps
CPU time 782.59 seconds
Started Aug 01 06:27:37 PM PDT 24
Finished Aug 01 06:40:40 PM PDT 24
Peak memory 732220 kb
Host smart-3fab96d5-9983-43b5-bdec-851a74d9bfa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345735003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2345735003
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2019563083
Short name T155
Test name
Test status
Simulation time 101634813374 ps
CPU time 175.24 seconds
Started Aug 01 06:27:31 PM PDT 24
Finished Aug 01 06:30:26 PM PDT 24
Peak memory 199940 kb
Host smart-693f3e30-92ad-44cc-9571-4d8f1e43cef3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019563083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2019563083
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1338427970
Short name T426
Test name
Test status
Simulation time 26292592264 ps
CPU time 68.85 seconds
Started Aug 01 06:27:28 PM PDT 24
Finished Aug 01 06:28:37 PM PDT 24
Peak memory 199940 kb
Host smart-91b9e7a7-77d5-4407-b08a-ed39db7de0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338427970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1338427970
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3066964714
Short name T126
Test name
Test status
Simulation time 1613274367 ps
CPU time 13.93 seconds
Started Aug 01 06:27:28 PM PDT 24
Finished Aug 01 06:27:42 PM PDT 24
Peak memory 199924 kb
Host smart-fb891cc6-51ef-4a97-800e-9263032190d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066964714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3066964714
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.375412610
Short name T181
Test name
Test status
Simulation time 4459862386 ps
CPU time 687.18 seconds
Started Aug 01 06:27:28 PM PDT 24
Finished Aug 01 06:38:55 PM PDT 24
Peak memory 728804 kb
Host smart-a2c91066-3887-4e14-9515-de05cfd9160b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375412610 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.375412610
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2956374283
Short name T172
Test name
Test status
Simulation time 284887089 ps
CPU time 15.25 seconds
Started Aug 01 06:27:34 PM PDT 24
Finished Aug 01 06:27:49 PM PDT 24
Peak memory 199908 kb
Host smart-bd9808fd-c707-4812-a70d-c0a22d9ca537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956374283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2956374283
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1616027727
Short name T265
Test name
Test status
Simulation time 20949387 ps
CPU time 0.58 seconds
Started Aug 01 06:27:31 PM PDT 24
Finished Aug 01 06:27:32 PM PDT 24
Peak memory 195560 kb
Host smart-61a942f1-6334-4a62-92bd-c96787f19db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616027727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1616027727
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.945148172
Short name T137
Test name
Test status
Simulation time 943302377 ps
CPU time 51.26 seconds
Started Aug 01 06:27:33 PM PDT 24
Finished Aug 01 06:28:24 PM PDT 24
Peak memory 199904 kb
Host smart-273d1258-7f48-486c-b43d-fa8b57e3d4c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945148172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.945148172
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1459196741
Short name T239
Test name
Test status
Simulation time 8311084503 ps
CPU time 33.88 seconds
Started Aug 01 06:27:29 PM PDT 24
Finished Aug 01 06:28:03 PM PDT 24
Peak memory 208228 kb
Host smart-e80c4899-6317-42a1-b19b-1392504ab6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459196741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1459196741
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.492335756
Short name T418
Test name
Test status
Simulation time 8911974360 ps
CPU time 1243.89 seconds
Started Aug 01 06:27:31 PM PDT 24
Finished Aug 01 06:48:16 PM PDT 24
Peak memory 769260 kb
Host smart-90488def-435a-4101-aa2a-d38307080fdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492335756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.492335756
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.974991818
Short name T234
Test name
Test status
Simulation time 1120187093 ps
CPU time 62.89 seconds
Started Aug 01 06:27:36 PM PDT 24
Finished Aug 01 06:28:39 PM PDT 24
Peak memory 199780 kb
Host smart-ba2cd9c7-bd7a-4b0a-b0d3-c23e2b5217de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974991818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.974991818
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3313341455
Short name T481
Test name
Test status
Simulation time 17623425554 ps
CPU time 126.45 seconds
Started Aug 01 06:27:35 PM PDT 24
Finished Aug 01 06:29:41 PM PDT 24
Peak memory 200132 kb
Host smart-7b8407e3-6a58-4ca1-80d3-55bfb6ebc255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313341455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3313341455
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.247894904
Short name T364
Test name
Test status
Simulation time 892417668 ps
CPU time 11.99 seconds
Started Aug 01 06:27:29 PM PDT 24
Finished Aug 01 06:27:41 PM PDT 24
Peak memory 199904 kb
Host smart-96c191ed-c7ad-4e81-9693-9df6298186d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247894904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.247894904
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.964152928
Short name T89
Test name
Test status
Simulation time 506018274033 ps
CPU time 1148.25 seconds
Started Aug 01 06:27:28 PM PDT 24
Finished Aug 01 06:46:36 PM PDT 24
Peak memory 673240 kb
Host smart-090a1d9c-313d-4f22-960e-c123c480b1dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964152928 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.964152928
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1633119714
Short name T476
Test name
Test status
Simulation time 69914754821 ps
CPU time 126.28 seconds
Started Aug 01 06:27:32 PM PDT 24
Finished Aug 01 06:29:38 PM PDT 24
Peak memory 199988 kb
Host smart-e4048860-daa5-4bd1-ab86-8354a7427ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633119714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1633119714
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.834075193
Short name T280
Test name
Test status
Simulation time 24031369 ps
CPU time 0.57 seconds
Started Aug 01 06:27:42 PM PDT 24
Finished Aug 01 06:27:43 PM PDT 24
Peak memory 195652 kb
Host smart-6c932884-d9f8-4e14-9329-d8844f713899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834075193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.834075193
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2467701654
Short name T397
Test name
Test status
Simulation time 331786943 ps
CPU time 5.46 seconds
Started Aug 01 06:27:33 PM PDT 24
Finished Aug 01 06:27:38 PM PDT 24
Peak memory 199840 kb
Host smart-dc869313-f57e-4f73-85a6-03842de3b7d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467701654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2467701654
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.715849962
Short name T440
Test name
Test status
Simulation time 5861994066 ps
CPU time 16.94 seconds
Started Aug 01 06:27:32 PM PDT 24
Finished Aug 01 06:27:49 PM PDT 24
Peak memory 199964 kb
Host smart-59e835a6-2623-4ce2-9a14-3fa5948e6504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715849962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.715849962
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1433391773
Short name T131
Test name
Test status
Simulation time 6031692417 ps
CPU time 862.88 seconds
Started Aug 01 06:27:35 PM PDT 24
Finished Aug 01 06:41:58 PM PDT 24
Peak memory 682088 kb
Host smart-36985df3-b2ce-4ab5-9ea0-b20ee5832ac7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433391773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1433391773
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1128831099
Short name T315
Test name
Test status
Simulation time 4328576193 ps
CPU time 47.17 seconds
Started Aug 01 06:27:36 PM PDT 24
Finished Aug 01 06:28:24 PM PDT 24
Peak memory 199956 kb
Host smart-5f944d4d-fcc0-4263-aff1-1a75519862da
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128831099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1128831099
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3913356186
Short name T132
Test name
Test status
Simulation time 2931407009 ps
CPU time 165.75 seconds
Started Aug 01 06:27:27 PM PDT 24
Finished Aug 01 06:30:13 PM PDT 24
Peak memory 200024 kb
Host smart-d7330627-3603-49dd-996f-6fe675c8913e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913356186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3913356186
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3121873342
Short name T419
Test name
Test status
Simulation time 229642311 ps
CPU time 6.98 seconds
Started Aug 01 06:27:31 PM PDT 24
Finished Aug 01 06:27:38 PM PDT 24
Peak memory 199840 kb
Host smart-56de7e1b-294f-440d-a1b0-9353d2b57ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121873342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3121873342
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3606521996
Short name T50
Test name
Test status
Simulation time 21667370260 ps
CPU time 98.77 seconds
Started Aug 01 06:27:39 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 199908 kb
Host smart-77f284ad-c192-4a85-9232-60549d99af0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606521996 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3606521996
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1782748555
Short name T460
Test name
Test status
Simulation time 127077601400 ps
CPU time 111.75 seconds
Started Aug 01 06:27:31 PM PDT 24
Finished Aug 01 06:29:23 PM PDT 24
Peak memory 200000 kb
Host smart-0bee60f9-7b1d-4323-a6a6-c1ef90656967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782748555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1782748555
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2586355929
Short name T517
Test name
Test status
Simulation time 37042126 ps
CPU time 0.58 seconds
Started Aug 01 06:27:40 PM PDT 24
Finished Aug 01 06:27:40 PM PDT 24
Peak memory 195904 kb
Host smart-81a1ed00-fed0-4e50-b7d1-58b97d4e04cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586355929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2586355929
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3367305171
Short name T331
Test name
Test status
Simulation time 298967114 ps
CPU time 18.34 seconds
Started Aug 01 06:27:39 PM PDT 24
Finished Aug 01 06:27:57 PM PDT 24
Peak memory 199796 kb
Host smart-9b764347-5e7e-48f7-b604-082237b81f62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3367305171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3367305171
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.701867822
Short name T520
Test name
Test status
Simulation time 924576269 ps
CPU time 48.21 seconds
Started Aug 01 06:27:46 PM PDT 24
Finished Aug 01 06:28:35 PM PDT 24
Peak memory 199916 kb
Host smart-532c2955-82dc-4125-b39f-3c79619603fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701867822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.701867822
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3528259635
Short name T228
Test name
Test status
Simulation time 5176362117 ps
CPU time 161.84 seconds
Started Aug 01 06:27:38 PM PDT 24
Finished Aug 01 06:30:20 PM PDT 24
Peak memory 367648 kb
Host smart-cb055e70-2145-49b8-a1b9-601ab8d7bec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528259635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3528259635
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3551395813
Short name T375
Test name
Test status
Simulation time 2752351318 ps
CPU time 78.41 seconds
Started Aug 01 06:27:39 PM PDT 24
Finished Aug 01 06:28:57 PM PDT 24
Peak memory 199988 kb
Host smart-6cd17545-f2c9-410d-a4b4-131bd99da13b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551395813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3551395813
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.866419517
Short name T359
Test name
Test status
Simulation time 7933327365 ps
CPU time 54.04 seconds
Started Aug 01 06:27:39 PM PDT 24
Finished Aug 01 06:28:33 PM PDT 24
Peak memory 199976 kb
Host smart-c757b15d-3b2a-4aa3-9f49-5a200ca26a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866419517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.866419517
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2756315904
Short name T432
Test name
Test status
Simulation time 1334529613 ps
CPU time 14.1 seconds
Started Aug 01 06:27:41 PM PDT 24
Finished Aug 01 06:27:55 PM PDT 24
Peak memory 199872 kb
Host smart-87517f7c-2169-4bef-bce2-f0dbcd8f8734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756315904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2756315904
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3410977717
Short name T220
Test name
Test status
Simulation time 152080278484 ps
CPU time 1182.52 seconds
Started Aug 01 06:27:38 PM PDT 24
Finished Aug 01 06:47:21 PM PDT 24
Peak memory 709536 kb
Host smart-3f95feb6-2c03-4463-a0b5-bcddcab0eefc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410977717 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3410977717
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.788612296
Short name T226
Test name
Test status
Simulation time 11784366194 ps
CPU time 125.32 seconds
Started Aug 01 06:27:40 PM PDT 24
Finished Aug 01 06:29:45 PM PDT 24
Peak memory 200040 kb
Host smart-b0619ed2-72c2-4093-8dde-30f31d6ab1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788612296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.788612296
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2118483422
Short name T48
Test name
Test status
Simulation time 12223620 ps
CPU time 0.61 seconds
Started Aug 01 06:27:40 PM PDT 24
Finished Aug 01 06:27:41 PM PDT 24
Peak memory 195916 kb
Host smart-faa6604a-4369-49dd-b25e-4b07351653c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118483422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2118483422
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2073233434
Short name T374
Test name
Test status
Simulation time 889106640 ps
CPU time 50.78 seconds
Started Aug 01 06:27:41 PM PDT 24
Finished Aug 01 06:28:32 PM PDT 24
Peak memory 199844 kb
Host smart-b82ff512-6755-4661-83ad-512b9560a272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073233434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2073233434
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.155978418
Short name T348
Test name
Test status
Simulation time 2202929238 ps
CPU time 10.04 seconds
Started Aug 01 06:27:41 PM PDT 24
Finished Aug 01 06:27:51 PM PDT 24
Peak memory 199920 kb
Host smart-48394765-21b6-4e30-baae-af93bc5c0057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155978418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.155978418
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1741712097
Short name T424
Test name
Test status
Simulation time 16611176760 ps
CPU time 936.38 seconds
Started Aug 01 06:27:40 PM PDT 24
Finished Aug 01 06:43:17 PM PDT 24
Peak memory 732412 kb
Host smart-d602c741-38f2-4d17-812b-bc42a5aa41f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741712097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1741712097
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3828747015
Short name T153
Test name
Test status
Simulation time 13450770923 ps
CPU time 176.2 seconds
Started Aug 01 06:27:47 PM PDT 24
Finished Aug 01 06:30:43 PM PDT 24
Peak memory 200080 kb
Host smart-6ee351a9-8f53-4f3e-9a0a-a0e34bc4c27b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828747015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3828747015
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.719269990
Short name T472
Test name
Test status
Simulation time 105141310 ps
CPU time 5.26 seconds
Started Aug 01 06:27:42 PM PDT 24
Finished Aug 01 06:27:47 PM PDT 24
Peak memory 199868 kb
Host smart-717b7e39-be0f-44f4-b42d-37fcb8149d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719269990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.719269990
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.378569272
Short name T488
Test name
Test status
Simulation time 459550304 ps
CPU time 4.33 seconds
Started Aug 01 06:27:38 PM PDT 24
Finished Aug 01 06:27:42 PM PDT 24
Peak memory 199844 kb
Host smart-5f995152-dfd8-44f8-8e80-0ffabfb19096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378569272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.378569272
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.480237626
Short name T365
Test name
Test status
Simulation time 61141200949 ps
CPU time 2405.93 seconds
Started Aug 01 06:27:40 PM PDT 24
Finished Aug 01 07:07:46 PM PDT 24
Peak memory 731380 kb
Host smart-93f7ab40-b402-4a59-a14f-db14846e1bdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480237626 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.480237626
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.117065175
Short name T46
Test name
Test status
Simulation time 11278700343 ps
CPU time 99.93 seconds
Started Aug 01 06:27:39 PM PDT 24
Finished Aug 01 06:29:19 PM PDT 24
Peak memory 199972 kb
Host smart-31d67d6f-7861-4d89-9abe-04b84f545beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117065175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.117065175
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.416621134
Short name T467
Test name
Test status
Simulation time 16761473 ps
CPU time 0.61 seconds
Started Aug 01 06:27:52 PM PDT 24
Finished Aug 01 06:27:53 PM PDT 24
Peak memory 196600 kb
Host smart-032f4176-86b7-421c-9d7e-6516bd35ac7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416621134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.416621134
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1258907817
Short name T449
Test name
Test status
Simulation time 3370871615 ps
CPU time 46.48 seconds
Started Aug 01 06:27:47 PM PDT 24
Finished Aug 01 06:28:33 PM PDT 24
Peak memory 200000 kb
Host smart-cd1ee0f1-0d0b-4ccb-9a3c-c0632900e5a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258907817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1258907817
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3204220092
Short name T431
Test name
Test status
Simulation time 11153682505 ps
CPU time 47.81 seconds
Started Aug 01 06:27:50 PM PDT 24
Finished Aug 01 06:28:38 PM PDT 24
Peak memory 199988 kb
Host smart-68c2859b-028c-4d95-9084-3f6517e13609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204220092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3204220092
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.990273960
Short name T35
Test name
Test status
Simulation time 32670229943 ps
CPU time 888.26 seconds
Started Aug 01 06:27:42 PM PDT 24
Finished Aug 01 06:42:31 PM PDT 24
Peak memory 729684 kb
Host smart-15d02381-bfa0-40c5-89f2-38e4b79a3c96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990273960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.990273960
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3940442190
Short name T456
Test name
Test status
Simulation time 7895597148 ps
CPU time 92.09 seconds
Started Aug 01 06:27:53 PM PDT 24
Finished Aug 01 06:29:25 PM PDT 24
Peak memory 199956 kb
Host smart-dc34e828-be4a-48e1-a530-624746afc620
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940442190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3940442190
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2987396239
Short name T133
Test name
Test status
Simulation time 3130579907 ps
CPU time 14.75 seconds
Started Aug 01 06:27:39 PM PDT 24
Finished Aug 01 06:27:54 PM PDT 24
Peak memory 199984 kb
Host smart-383048d9-d123-4954-9efd-f888a739899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987396239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2987396239
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3700081782
Short name T435
Test name
Test status
Simulation time 1293418675 ps
CPU time 7.95 seconds
Started Aug 01 06:27:39 PM PDT 24
Finished Aug 01 06:27:47 PM PDT 24
Peak memory 199844 kb
Host smart-9812ccc2-74f7-4a68-86d2-9e18c53c94a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700081782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3700081782
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1077576877
Short name T429
Test name
Test status
Simulation time 65966775484 ps
CPU time 2508.44 seconds
Started Aug 01 06:27:52 PM PDT 24
Finished Aug 01 07:09:41 PM PDT 24
Peak memory 770964 kb
Host smart-41d5be1d-3abe-4935-8823-c79cb4d2f8f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077576877 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1077576877
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3093776449
Short name T32
Test name
Test status
Simulation time 2898498128 ps
CPU time 41.35 seconds
Started Aug 01 06:27:53 PM PDT 24
Finished Aug 01 06:28:35 PM PDT 24
Peak memory 200028 kb
Host smart-a0662c9b-8bb5-4cac-be6f-e174774e63ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093776449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3093776449
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3250996430
Short name T428
Test name
Test status
Simulation time 63862412 ps
CPU time 0.61 seconds
Started Aug 01 06:27:52 PM PDT 24
Finished Aug 01 06:27:53 PM PDT 24
Peak memory 195872 kb
Host smart-c5492807-fd02-4a90-985c-10eeaff027c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250996430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3250996430
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.979394794
Short name T313
Test name
Test status
Simulation time 319235183 ps
CPU time 10.44 seconds
Started Aug 01 06:27:55 PM PDT 24
Finished Aug 01 06:28:06 PM PDT 24
Peak memory 199764 kb
Host smart-7c640cfc-550b-49fc-8bef-f4e32d35f1bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979394794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.979394794
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3543189912
Short name T413
Test name
Test status
Simulation time 5730386074 ps
CPU time 39.85 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:28:32 PM PDT 24
Peak memory 200020 kb
Host smart-5f2623fc-d9a0-480f-beb1-36517ec4ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543189912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3543189912
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2898218824
Short name T180
Test name
Test status
Simulation time 14417583065 ps
CPU time 596.64 seconds
Started Aug 01 06:27:52 PM PDT 24
Finished Aug 01 06:37:49 PM PDT 24
Peak memory 686712 kb
Host smart-0ae60e99-5696-4dd0-be1d-c401b54587c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2898218824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2898218824
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.644350027
Short name T245
Test name
Test status
Simulation time 4057102839 ps
CPU time 110.17 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:29:41 PM PDT 24
Peak memory 199992 kb
Host smart-494c1378-2887-4a82-b930-cc624e9178e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644350027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.644350027
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3961022722
Short name T290
Test name
Test status
Simulation time 4439721435 ps
CPU time 164.44 seconds
Started Aug 01 06:27:53 PM PDT 24
Finished Aug 01 06:30:37 PM PDT 24
Peak memory 216376 kb
Host smart-694e444c-e251-4e30-9baf-01871a0af9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961022722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3961022722
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.737429482
Short name T406
Test name
Test status
Simulation time 138326026 ps
CPU time 2.73 seconds
Started Aug 01 06:27:54 PM PDT 24
Finished Aug 01 06:27:57 PM PDT 24
Peak memory 199840 kb
Host smart-af9a3963-8339-4d85-ba43-bbc16d7578fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737429482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.737429482
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1086447323
Short name T83
Test name
Test status
Simulation time 316422260258 ps
CPU time 1390.42 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:51:02 PM PDT 24
Peak memory 529120 kb
Host smart-5a88ec85-804b-4396-831b-622e3f3f16de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086447323 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1086447323
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1468383928
Short name T165
Test name
Test status
Simulation time 1082089232 ps
CPU time 55.84 seconds
Started Aug 01 06:27:49 PM PDT 24
Finished Aug 01 06:28:45 PM PDT 24
Peak memory 199852 kb
Host smart-27cefe88-5983-4cbd-9d21-8151cd79eb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468383928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1468383928
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1806924775
Short name T185
Test name
Test status
Simulation time 15194652 ps
CPU time 0.58 seconds
Started Aug 01 06:26:53 PM PDT 24
Finished Aug 01 06:26:53 PM PDT 24
Peak memory 196580 kb
Host smart-396d48aa-41f0-428e-b865-3a8a8c072558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806924775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1806924775
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1217314567
Short name T252
Test name
Test status
Simulation time 4511986119 ps
CPU time 68.8 seconds
Started Aug 01 06:26:50 PM PDT 24
Finished Aug 01 06:27:59 PM PDT 24
Peak memory 199972 kb
Host smart-83af3df3-95a9-4127-9dec-3e36d03cb03b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217314567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1217314567
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2481538597
Short name T527
Test name
Test status
Simulation time 19877946967 ps
CPU time 67.31 seconds
Started Aug 01 06:26:45 PM PDT 24
Finished Aug 01 06:27:53 PM PDT 24
Peak memory 199976 kb
Host smart-8cbcfb95-68da-4542-afa4-44c4d219d119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481538597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2481538597
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2499839395
Short name T43
Test name
Test status
Simulation time 2038519873 ps
CPU time 168.27 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 06:29:21 PM PDT 24
Peak memory 428268 kb
Host smart-6e069d10-103a-47ed-b18b-0c1c43d27713
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499839395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2499839395
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2911238197
Short name T317
Test name
Test status
Simulation time 6894100214 ps
CPU time 187.94 seconds
Started Aug 01 06:26:32 PM PDT 24
Finished Aug 01 06:29:40 PM PDT 24
Peak memory 199932 kb
Host smart-c279a626-72de-453c-bf4b-79c11bbb8a1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911238197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2911238197
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3659579979
Short name T250
Test name
Test status
Simulation time 24254213116 ps
CPU time 81.95 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 06:27:55 PM PDT 24
Peak memory 199344 kb
Host smart-eee1456a-56ef-4605-80b8-28f9c3d5b012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659579979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3659579979
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.3886094432
Short name T479
Test name
Test status
Simulation time 214961894 ps
CPU time 9.71 seconds
Started Aug 01 06:26:42 PM PDT 24
Finished Aug 01 06:26:52 PM PDT 24
Peak memory 199904 kb
Host smart-23d9e665-53d8-4776-9b37-6a5fedb40f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886094432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3886094432
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3248486575
Short name T80
Test name
Test status
Simulation time 19484886723 ps
CPU time 125.14 seconds
Started Aug 01 06:26:53 PM PDT 24
Finished Aug 01 06:28:58 PM PDT 24
Peak memory 216316 kb
Host smart-b74efd68-cb42-4120-abc6-cc74c71d25f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248486575 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3248486575
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1638449339
Short name T16
Test name
Test status
Simulation time 194733902089 ps
CPU time 934.47 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 06:42:29 PM PDT 24
Peak memory 504908 kb
Host smart-6dce4f39-d988-4b3e-8f54-5f114782721b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638449339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1638449339
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2241846011
Short name T383
Test name
Test status
Simulation time 3802478068 ps
CPU time 50.47 seconds
Started Aug 01 06:26:34 PM PDT 24
Finished Aug 01 06:27:24 PM PDT 24
Peak memory 199908 kb
Host smart-36bb4e70-bc66-4c29-a1a2-d4e9f057f048
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2241846011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2241846011
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.220936690
Short name T480
Test name
Test status
Simulation time 13602525726 ps
CPU time 104.7 seconds
Started Aug 01 06:26:46 PM PDT 24
Finished Aug 01 06:28:31 PM PDT 24
Peak memory 199960 kb
Host smart-9a1fd64a-e3e8-455e-99f5-cb0caec5fb5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=220936690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.220936690
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.826664225
Short name T525
Test name
Test status
Simulation time 17220623839 ps
CPU time 67.74 seconds
Started Aug 01 06:26:57 PM PDT 24
Finished Aug 01 06:28:05 PM PDT 24
Peak memory 199976 kb
Host smart-e4444c80-c639-4cc4-979d-e92bfb40b3e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=826664225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.826664225
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1085637038
Short name T198
Test name
Test status
Simulation time 51665554094 ps
CPU time 660.06 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 06:37:33 PM PDT 24
Peak memory 199924 kb
Host smart-a1719c31-9616-47be-8982-7b32439955c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1085637038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1085637038
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.88781935
Short name T310
Test name
Test status
Simulation time 849109027641 ps
CPU time 2584.99 seconds
Started Aug 01 06:26:33 PM PDT 24
Finished Aug 01 07:09:38 PM PDT 24
Peak memory 215372 kb
Host smart-fd343aa8-8a5b-4494-a2f7-5ae4b1246b99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=88781935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.88781935
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3232755903
Short name T202
Test name
Test status
Simulation time 73225810565 ps
CPU time 2081.13 seconds
Started Aug 01 06:26:39 PM PDT 24
Finished Aug 01 07:01:21 PM PDT 24
Peak memory 215472 kb
Host smart-54dd6b42-298a-41a3-9057-59aaffc874dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3232755903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3232755903
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1367406022
Short name T69
Test name
Test status
Simulation time 9558813331 ps
CPU time 41.49 seconds
Started Aug 01 06:26:46 PM PDT 24
Finished Aug 01 06:27:28 PM PDT 24
Peak memory 199948 kb
Host smart-84fd9ee3-a807-47e5-9f6a-1a2a1d90f6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367406022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1367406022
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4275357637
Short name T210
Test name
Test status
Simulation time 13516094 ps
CPU time 0.58 seconds
Started Aug 01 06:27:52 PM PDT 24
Finished Aug 01 06:27:53 PM PDT 24
Peak memory 195856 kb
Host smart-11d555ed-7b06-49f8-9916-9b041e1f65a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275357637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4275357637
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2999193641
Short name T445
Test name
Test status
Simulation time 982088498 ps
CPU time 54.74 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:28:46 PM PDT 24
Peak memory 199832 kb
Host smart-1230dc87-a498-44e5-a52d-08d6604eabe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999193641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2999193641
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3128220194
Short name T334
Test name
Test status
Simulation time 535060035 ps
CPU time 10.49 seconds
Started Aug 01 06:27:50 PM PDT 24
Finished Aug 01 06:28:01 PM PDT 24
Peak memory 199856 kb
Host smart-d1310cfe-1a80-47d6-8c1a-73bd835dfe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128220194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3128220194
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1340542663
Short name T9
Test name
Test status
Simulation time 1609491806 ps
CPU time 263.72 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:32:15 PM PDT 24
Peak memory 620264 kb
Host smart-a2aa146c-d0f1-4b6f-84b7-3d6b7ee76785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1340542663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1340542663
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3195202034
Short name T55
Test name
Test status
Simulation time 21778471710 ps
CPU time 200.73 seconds
Started Aug 01 06:27:54 PM PDT 24
Finished Aug 01 06:31:14 PM PDT 24
Peak memory 199988 kb
Host smart-0eca9951-029d-4f98-aadc-7524e580a7a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195202034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3195202034
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2363038461
Short name T461
Test name
Test status
Simulation time 9530543657 ps
CPU time 37.29 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:28:28 PM PDT 24
Peak memory 199960 kb
Host smart-e6ce3717-1f6a-44c6-860e-a3cda9e79bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363038461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2363038461
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1413915271
Short name T434
Test name
Test status
Simulation time 1177139679 ps
CPU time 10.46 seconds
Started Aug 01 06:27:55 PM PDT 24
Finished Aug 01 06:28:05 PM PDT 24
Peak memory 199912 kb
Host smart-29f2fa3b-27ae-402d-85fc-b0450be55513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413915271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1413915271
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1071426742
Short name T505
Test name
Test status
Simulation time 120651692197 ps
CPU time 852.9 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:42:05 PM PDT 24
Peak memory 216116 kb
Host smart-1b0e6873-6e90-46c7-90cf-0e0561b71c7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071426742 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1071426742
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1329571876
Short name T283
Test name
Test status
Simulation time 3424462657 ps
CPU time 97.91 seconds
Started Aug 01 06:27:50 PM PDT 24
Finished Aug 01 06:29:28 PM PDT 24
Peak memory 200036 kb
Host smart-241cc9e1-1381-479f-945b-de1ffbad3d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329571876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1329571876
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1079307824
Short name T203
Test name
Test status
Simulation time 33642372 ps
CPU time 0.6 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:27:52 PM PDT 24
Peak memory 195540 kb
Host smart-e91f460c-38f5-47a4-afae-326e5e7ffb77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079307824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1079307824
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3220126312
Short name T387
Test name
Test status
Simulation time 12741147 ps
CPU time 0.68 seconds
Started Aug 01 06:27:52 PM PDT 24
Finished Aug 01 06:27:53 PM PDT 24
Peak memory 196332 kb
Host smart-578809b9-f374-4691-9883-9a7e105e6568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220126312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3220126312
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3206631669
Short name T398
Test name
Test status
Simulation time 27352611445 ps
CPU time 1359.2 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:50:31 PM PDT 24
Peak memory 744348 kb
Host smart-dd7e6d44-3f6a-4f4a-8e4d-a1bba863c80d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3206631669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3206631669
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.830423757
Short name T54
Test name
Test status
Simulation time 26764262 ps
CPU time 0.77 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:27:52 PM PDT 24
Peak memory 196536 kb
Host smart-787cb8ee-5fda-48a0-a43d-b6a9ad17d304
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830423757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.830423757
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3006366357
Short name T485
Test name
Test status
Simulation time 3978884286 ps
CPU time 54.94 seconds
Started Aug 01 06:27:55 PM PDT 24
Finished Aug 01 06:28:50 PM PDT 24
Peak memory 200028 kb
Host smart-3e985c81-8c27-4765-9491-a1f5a3279fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006366357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3006366357
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3510534775
Short name T325
Test name
Test status
Simulation time 368488118 ps
CPU time 7.55 seconds
Started Aug 01 06:27:52 PM PDT 24
Finished Aug 01 06:28:00 PM PDT 24
Peak memory 199852 kb
Host smart-2fded6fb-2bb4-4ffb-ade0-52f249e37d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510534775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3510534775
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1872055110
Short name T236
Test name
Test status
Simulation time 41281870075 ps
CPU time 1589.4 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:54:21 PM PDT 24
Peak memory 730700 kb
Host smart-8a409168-0622-4d4d-8b69-74d8408714c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872055110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1872055110
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.776721703
Short name T147
Test name
Test status
Simulation time 722518520 ps
CPU time 24.69 seconds
Started Aug 01 06:27:51 PM PDT 24
Finished Aug 01 06:28:16 PM PDT 24
Peak memory 199812 kb
Host smart-3f595b46-c803-46a0-97bc-e1ad06c09ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776721703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.776721703
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1287967468
Short name T173
Test name
Test status
Simulation time 28109284 ps
CPU time 0.6 seconds
Started Aug 01 06:28:09 PM PDT 24
Finished Aug 01 06:28:10 PM PDT 24
Peak memory 195592 kb
Host smart-8f3682ae-8b07-4086-bfbc-917e9d13fe5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287967468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1287967468
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1020434839
Short name T37
Test name
Test status
Simulation time 3894392145 ps
CPU time 116.13 seconds
Started Aug 01 06:28:09 PM PDT 24
Finished Aug 01 06:30:06 PM PDT 24
Peak memory 199964 kb
Host smart-b64ec528-b299-423b-b417-443d1cf2cf3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020434839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1020434839
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.571613158
Short name T507
Test name
Test status
Simulation time 6410516976 ps
CPU time 21.07 seconds
Started Aug 01 06:28:07 PM PDT 24
Finished Aug 01 06:28:28 PM PDT 24
Peak memory 199980 kb
Host smart-7c76fd86-aaa2-42ad-96b5-142ffa2c4927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571613158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.571613158
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.386436771
Short name T526
Test name
Test status
Simulation time 12633565394 ps
CPU time 578.09 seconds
Started Aug 01 06:28:09 PM PDT 24
Finished Aug 01 06:37:47 PM PDT 24
Peak memory 641672 kb
Host smart-56dc73e6-3ed9-41e2-aecf-8fddd1fe52ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386436771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.386436771
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3908989702
Short name T382
Test name
Test status
Simulation time 30839736 ps
CPU time 0.83 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:28:10 PM PDT 24
Peak memory 197672 kb
Host smart-cf6c8b53-8f3f-4a63-96ba-5a8c6d84f79d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908989702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3908989702
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3825076338
Short name T417
Test name
Test status
Simulation time 5009847608 ps
CPU time 91.5 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 06:29:41 PM PDT 24
Peak memory 199956 kb
Host smart-ae97cbbc-7352-4358-a00e-db1439324aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825076338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3825076338
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2614774525
Short name T167
Test name
Test status
Simulation time 4038909768 ps
CPU time 12.77 seconds
Started Aug 01 06:27:54 PM PDT 24
Finished Aug 01 06:28:07 PM PDT 24
Peak memory 200036 kb
Host smart-329ac71b-a346-4025-be68-1aa45e9d14fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614774525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2614774525
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2045882971
Short name T400
Test name
Test status
Simulation time 3714815914 ps
CPU time 192.8 seconds
Started Aug 01 06:28:11 PM PDT 24
Finished Aug 01 06:31:24 PM PDT 24
Peak memory 200008 kb
Host smart-0bd66529-1ffd-4f83-bbab-4cd173f3bfc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045882971 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2045882971
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3539462921
Short name T528
Test name
Test status
Simulation time 28571969372 ps
CPU time 124.61 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:30:13 PM PDT 24
Peak memory 200032 kb
Host smart-2fa4c919-a079-4985-b620-050274d5ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539462921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3539462921
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2088746648
Short name T186
Test name
Test status
Simulation time 11566146 ps
CPU time 0.59 seconds
Started Aug 01 06:28:07 PM PDT 24
Finished Aug 01 06:28:08 PM PDT 24
Peak memory 194808 kb
Host smart-4eb76001-641e-4acd-ad3e-9f166b668f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088746648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2088746648
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1290891719
Short name T454
Test name
Test status
Simulation time 1511569423 ps
CPU time 79.15 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:29:27 PM PDT 24
Peak memory 199832 kb
Host smart-80454965-5af2-43ee-93ad-8c4ed16316fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290891719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1290891719
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3855672194
Short name T376
Test name
Test status
Simulation time 10751797306 ps
CPU time 33.56 seconds
Started Aug 01 06:28:11 PM PDT 24
Finished Aug 01 06:28:45 PM PDT 24
Peak memory 199984 kb
Host smart-f1bfd4ab-b049-4fe4-b459-4439b3249ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855672194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3855672194
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1603258280
Short name T477
Test name
Test status
Simulation time 20478394 ps
CPU time 0.85 seconds
Started Aug 01 06:28:07 PM PDT 24
Finished Aug 01 06:28:08 PM PDT 24
Peak memory 215696 kb
Host smart-95ea2c57-353c-4d97-8105-f0caff4d2833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1603258280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1603258280
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2066143892
Short name T156
Test name
Test status
Simulation time 1114360493 ps
CPU time 19.55 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:28:27 PM PDT 24
Peak memory 200052 kb
Host smart-6dcf07f8-9fb8-448a-b885-5ff04f491cb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066143892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2066143892
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1619263187
Short name T49
Test name
Test status
Simulation time 23391653660 ps
CPU time 105.6 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 06:29:56 PM PDT 24
Peak memory 199984 kb
Host smart-94e2fba3-e9e3-4314-9292-3b7280b7a60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619263187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1619263187
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.147608574
Short name T363
Test name
Test status
Simulation time 158836735 ps
CPU time 1.02 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 06:28:11 PM PDT 24
Peak memory 199772 kb
Host smart-b64f21aa-d146-45a7-b884-dee46c25b7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147608574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.147608574
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3066119462
Short name T235
Test name
Test status
Simulation time 106780466017 ps
CPU time 2761.54 seconds
Started Aug 01 06:28:07 PM PDT 24
Finished Aug 01 07:14:09 PM PDT 24
Peak memory 741712 kb
Host smart-a52df62a-102e-412d-a1c2-186a744aba3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066119462 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3066119462
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3065245565
Short name T515
Test name
Test status
Simulation time 7406721668 ps
CPU time 96.42 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:29:45 PM PDT 24
Peak memory 199904 kb
Host smart-85a1e01f-47b6-4eff-86bb-cb95546f9f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065245565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3065245565
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1707882786
Short name T206
Test name
Test status
Simulation time 33843524 ps
CPU time 0.62 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 06:28:11 PM PDT 24
Peak memory 195964 kb
Host smart-5a93ffc8-1b48-4807-99cd-9d2c0919eae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707882786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1707882786
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.542007009
Short name T231
Test name
Test status
Simulation time 2466706660 ps
CPU time 72.58 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 06:29:23 PM PDT 24
Peak memory 199952 kb
Host smart-17c1b1ae-d84d-4466-967c-3ead83df031f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542007009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.542007009
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3230763873
Short name T240
Test name
Test status
Simulation time 536183523 ps
CPU time 22.42 seconds
Started Aug 01 06:28:09 PM PDT 24
Finished Aug 01 06:28:31 PM PDT 24
Peak memory 199836 kb
Host smart-edd00e69-c756-43f4-9652-561719a3f13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230763873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3230763873
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1085207888
Short name T524
Test name
Test status
Simulation time 2365419468 ps
CPU time 201.44 seconds
Started Aug 01 06:28:11 PM PDT 24
Finished Aug 01 06:31:32 PM PDT 24
Peak memory 629076 kb
Host smart-01d6efab-75c5-4aeb-98e7-ce143b4b9fdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085207888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1085207888
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.838930901
Short name T260
Test name
Test status
Simulation time 466201629 ps
CPU time 26.67 seconds
Started Aug 01 06:28:07 PM PDT 24
Finished Aug 01 06:28:33 PM PDT 24
Peak memory 199816 kb
Host smart-e3bedab1-e0b8-42c5-8185-c985d0337cda
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838930901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.838930901
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2364151825
Short name T333
Test name
Test status
Simulation time 3315739614 ps
CPU time 45.82 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:28:54 PM PDT 24
Peak memory 199952 kb
Host smart-fbe5f113-750d-407b-beda-1fe764e7ac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364151825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2364151825
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.67844792
Short name T506
Test name
Test status
Simulation time 2508771028 ps
CPU time 11.02 seconds
Started Aug 01 06:28:09 PM PDT 24
Finished Aug 01 06:28:21 PM PDT 24
Peak memory 199996 kb
Host smart-799fd513-7943-43fd-92ec-4c1d8f67d551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67844792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.67844792
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2805265475
Short name T79
Test name
Test status
Simulation time 134216263127 ps
CPU time 2492.6 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 07:09:43 PM PDT 24
Peak memory 802900 kb
Host smart-49e7c340-9be0-4d44-8cbe-a928cbd723ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805265475 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2805265475
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1624022336
Short name T393
Test name
Test status
Simulation time 915540550 ps
CPU time 38.06 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:28:47 PM PDT 24
Peak memory 199864 kb
Host smart-f21c9c81-2fe9-44b9-91cc-1ad6f77d93c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624022336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1624022336
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2605369846
Short name T64
Test name
Test status
Simulation time 135236096 ps
CPU time 0.62 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 06:28:11 PM PDT 24
Peak memory 196600 kb
Host smart-4ca61e29-7d07-4aa5-a8a3-5d78389f7dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605369846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2605369846
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2886191914
Short name T61
Test name
Test status
Simulation time 1364100034 ps
CPU time 18.54 seconds
Started Aug 01 06:28:11 PM PDT 24
Finished Aug 01 06:28:29 PM PDT 24
Peak memory 199860 kb
Host smart-ffef6a3b-2ff6-4cd2-81dc-f68633a93d87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886191914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2886191914
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.367232650
Short name T302
Test name
Test status
Simulation time 4277855064 ps
CPU time 63.69 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:29:12 PM PDT 24
Peak memory 200012 kb
Host smart-862da32a-f8e5-4bb4-adfb-78dcfc94ef44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367232650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.367232650
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1013182343
Short name T263
Test name
Test status
Simulation time 7932777743 ps
CPU time 919.72 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 06:43:30 PM PDT 24
Peak memory 672556 kb
Host smart-aa065875-86f8-40fe-9138-d045af851e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1013182343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1013182343
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1206476715
Short name T287
Test name
Test status
Simulation time 5332168031 ps
CPU time 106.48 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 06:29:56 PM PDT 24
Peak memory 199988 kb
Host smart-f6c895ca-d655-4d82-89cd-094d95cc1c19
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206476715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1206476715
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.875164825
Short name T357
Test name
Test status
Simulation time 15059916660 ps
CPU time 145.57 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:30:34 PM PDT 24
Peak memory 216380 kb
Host smart-679846ac-8a2d-42bf-887d-faa411f17a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875164825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.875164825
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2393898274
Short name T261
Test name
Test status
Simulation time 130847554 ps
CPU time 6.97 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:28:15 PM PDT 24
Peak memory 199828 kb
Host smart-bca8afee-4552-49ba-b7d6-085c04900572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393898274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2393898274
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2269667573
Short name T87
Test name
Test status
Simulation time 21359292258 ps
CPU time 988.89 seconds
Started Aug 01 06:28:08 PM PDT 24
Finished Aug 01 06:44:37 PM PDT 24
Peak memory 619632 kb
Host smart-78cacc4b-ed21-4167-9351-b2d713a7e01f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269667573 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2269667573
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3099330584
Short name T303
Test name
Test status
Simulation time 824043822 ps
CPU time 47.87 seconds
Started Aug 01 06:28:07 PM PDT 24
Finished Aug 01 06:28:55 PM PDT 24
Peak memory 199820 kb
Host smart-f2252fa3-6b86-4d07-9c03-d3bee8e81723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099330584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3099330584
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.183269035
Short name T486
Test name
Test status
Simulation time 17001607 ps
CPU time 0.59 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:28:25 PM PDT 24
Peak memory 195468 kb
Host smart-84315052-a365-45dc-ab77-5fa06804d2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183269035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.183269035
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.687790854
Short name T13
Test name
Test status
Simulation time 393659635 ps
CPU time 5.6 seconds
Started Aug 01 06:28:11 PM PDT 24
Finished Aug 01 06:28:17 PM PDT 24
Peak memory 199848 kb
Host smart-70e317b1-99d0-4733-a38a-90c5e1975a0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687790854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.687790854
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3933664827
Short name T217
Test name
Test status
Simulation time 6574365945 ps
CPU time 60.92 seconds
Started Aug 01 06:28:22 PM PDT 24
Finished Aug 01 06:29:23 PM PDT 24
Peak memory 200084 kb
Host smart-c752e134-d49a-4ba8-8bae-1da407c208cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933664827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3933664827
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.281700330
Short name T421
Test name
Test status
Simulation time 10920923184 ps
CPU time 1080.12 seconds
Started Aug 01 06:28:22 PM PDT 24
Finished Aug 01 06:46:23 PM PDT 24
Peak memory 714200 kb
Host smart-57c07d67-316f-4fc2-85be-df6696223350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281700330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.281700330
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.599257137
Short name T491
Test name
Test status
Simulation time 2617167523 ps
CPU time 35.37 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:28:59 PM PDT 24
Peak memory 199928 kb
Host smart-b72e05fb-24b7-45b6-b48f-0d184e821b6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599257137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.599257137
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2104132755
Short name T193
Test name
Test status
Simulation time 5240935582 ps
CPU time 98.05 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 06:29:49 PM PDT 24
Peak memory 199972 kb
Host smart-13be8b28-19af-4dd5-8231-c64937c6da33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104132755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2104132755
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.4032333644
Short name T57
Test name
Test status
Simulation time 740119892 ps
CPU time 9.42 seconds
Started Aug 01 06:28:10 PM PDT 24
Finished Aug 01 06:28:19 PM PDT 24
Peak memory 199860 kb
Host smart-6cad30dc-8820-431c-8cd5-097b85dd684f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032333644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.4032333644
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.315425810
Short name T197
Test name
Test status
Simulation time 25019282 ps
CPU time 0.64 seconds
Started Aug 01 06:28:25 PM PDT 24
Finished Aug 01 06:28:26 PM PDT 24
Peak memory 195712 kb
Host smart-17c71ded-a6cd-4a5b-87a0-e43d6fa66ebc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315425810 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.315425810
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1263085391
Short name T471
Test name
Test status
Simulation time 62088356606 ps
CPU time 82.01 seconds
Started Aug 01 06:28:23 PM PDT 24
Finished Aug 01 06:29:46 PM PDT 24
Peak memory 200032 kb
Host smart-2aca1372-3914-4501-9ad4-bab07a547683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263085391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1263085391
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3236737251
Short name T402
Test name
Test status
Simulation time 17043635 ps
CPU time 0.57 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:28:25 PM PDT 24
Peak memory 194884 kb
Host smart-e1e6423b-18fd-4f9e-be2d-70546732f946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236737251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3236737251
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1329377953
Short name T343
Test name
Test status
Simulation time 1206506108 ps
CPU time 64.56 seconds
Started Aug 01 06:28:23 PM PDT 24
Finished Aug 01 06:29:28 PM PDT 24
Peak memory 199812 kb
Host smart-fff21c87-0d47-41a5-bdb3-598209e532fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329377953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1329377953
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2218262476
Short name T484
Test name
Test status
Simulation time 157537802 ps
CPU time 3.22 seconds
Started Aug 01 06:28:25 PM PDT 24
Finished Aug 01 06:28:28 PM PDT 24
Peak memory 199936 kb
Host smart-168a7624-6c25-41c0-9daa-a6f9bdde6e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218262476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2218262476
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.91412827
Short name T207
Test name
Test status
Simulation time 6666880776 ps
CPU time 120.29 seconds
Started Aug 01 06:28:25 PM PDT 24
Finished Aug 01 06:30:26 PM PDT 24
Peak memory 439936 kb
Host smart-861205c8-a1cb-42ed-b56f-c269dc672e69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91412827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.91412827
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.951553837
Short name T157
Test name
Test status
Simulation time 2926075510 ps
CPU time 111.89 seconds
Started Aug 01 06:28:25 PM PDT 24
Finished Aug 01 06:30:17 PM PDT 24
Peak memory 199916 kb
Host smart-673bd338-38cb-4cbd-a92d-3ac0e27c0e8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951553837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.951553837
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1538162164
Short name T344
Test name
Test status
Simulation time 15509053817 ps
CPU time 115.58 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:30:19 PM PDT 24
Peak memory 216208 kb
Host smart-8ba44055-8786-4635-97ef-6e88aeb38e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538162164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1538162164
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2811259050
Short name T503
Test name
Test status
Simulation time 5129911374 ps
CPU time 15.48 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:28:40 PM PDT 24
Peak memory 199988 kb
Host smart-beb186bf-3594-492f-9272-85381bfef7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811259050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2811259050
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.768856570
Short name T114
Test name
Test status
Simulation time 22294266252 ps
CPU time 893.68 seconds
Started Aug 01 06:28:27 PM PDT 24
Finished Aug 01 06:43:21 PM PDT 24
Peak memory 518396 kb
Host smart-0a1ca22d-d379-4e37-aa72-8b04b11833a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768856570 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.768856570
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1083876611
Short name T152
Test name
Test status
Simulation time 1501312054 ps
CPU time 21 seconds
Started Aug 01 06:28:27 PM PDT 24
Finished Aug 01 06:28:48 PM PDT 24
Peak memory 199864 kb
Host smart-a85b7248-69cf-46ed-9bff-8761d2e60513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083876611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1083876611
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3665320918
Short name T500
Test name
Test status
Simulation time 23085178 ps
CPU time 0.59 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:28:25 PM PDT 24
Peak memory 195908 kb
Host smart-852f8181-2d3d-4bf4-8b89-782d4990d9b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665320918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3665320918
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.820144264
Short name T148
Test name
Test status
Simulation time 2378067579 ps
CPU time 67.17 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:29:31 PM PDT 24
Peak memory 200004 kb
Host smart-bab960c6-0a2c-4b19-b6b4-8a432ecd2514
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820144264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.820144264
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3990993678
Short name T134
Test name
Test status
Simulation time 1487370201 ps
CPU time 28.32 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:28:52 PM PDT 24
Peak memory 199800 kb
Host smart-73a0c67c-d8b8-4045-8b40-98099233f7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990993678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3990993678
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3783535341
Short name T401
Test name
Test status
Simulation time 15036150435 ps
CPU time 626.81 seconds
Started Aug 01 06:28:22 PM PDT 24
Finished Aug 01 06:38:49 PM PDT 24
Peak memory 676588 kb
Host smart-c0b7c5af-21b6-4c76-bfac-591c8f641b6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3783535341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3783535341
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1761337071
Short name T450
Test name
Test status
Simulation time 5134913960 ps
CPU time 82.18 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:29:47 PM PDT 24
Peak memory 200008 kb
Host smart-3abd5a41-67fb-41f7-97ba-781c2f535207
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761337071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1761337071
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.777395659
Short name T271
Test name
Test status
Simulation time 4362256191 ps
CPU time 20 seconds
Started Aug 01 06:28:26 PM PDT 24
Finished Aug 01 06:28:46 PM PDT 24
Peak memory 200028 kb
Host smart-f10da109-8f10-47fa-a5b4-57edf6976424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777395659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.777395659
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.615206204
Short name T78
Test name
Test status
Simulation time 300655189 ps
CPU time 3.03 seconds
Started Aug 01 06:28:27 PM PDT 24
Finished Aug 01 06:28:30 PM PDT 24
Peak memory 199888 kb
Host smart-2bb7554a-4090-422d-8b6c-e9daa0edc003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615206204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.615206204
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.26923919
Short name T82
Test name
Test status
Simulation time 369225485828 ps
CPU time 1199.94 seconds
Started Aug 01 06:28:23 PM PDT 24
Finished Aug 01 06:48:23 PM PDT 24
Peak memory 372496 kb
Host smart-98120aa5-ce72-41e4-82ce-613907792723
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923919 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.26923919
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3715987162
Short name T518
Test name
Test status
Simulation time 2341690449 ps
CPU time 27.22 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:28:52 PM PDT 24
Peak memory 199992 kb
Host smart-683b37c0-2e77-4e96-a56f-40a93ab6b1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715987162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3715987162
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3047501461
Short name T170
Test name
Test status
Simulation time 20964748 ps
CPU time 0.6 seconds
Started Aug 01 06:28:28 PM PDT 24
Finished Aug 01 06:28:28 PM PDT 24
Peak memory 195584 kb
Host smart-36345689-22d9-4ddc-8e5a-b28a54f86205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047501461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3047501461
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1175991589
Short name T45
Test name
Test status
Simulation time 1144406869 ps
CPU time 57.63 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:29:22 PM PDT 24
Peak memory 199852 kb
Host smart-4e538eb8-2819-499c-8146-1b65ee488448
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175991589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1175991589
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2406157452
Short name T337
Test name
Test status
Simulation time 3289478035 ps
CPU time 25.95 seconds
Started Aug 01 06:28:23 PM PDT 24
Finished Aug 01 06:28:49 PM PDT 24
Peak memory 199940 kb
Host smart-8e5e82c8-c045-44c0-ab77-8833e8f96a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406157452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2406157452
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3993839626
Short name T244
Test name
Test status
Simulation time 20559780748 ps
CPU time 812.2 seconds
Started Aug 01 06:28:23 PM PDT 24
Finished Aug 01 06:41:55 PM PDT 24
Peak memory 692092 kb
Host smart-868c6334-2c8b-4936-aa94-9b03294c38cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993839626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3993839626
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1163796390
Short name T306
Test name
Test status
Simulation time 93642939 ps
CPU time 1.68 seconds
Started Aug 01 06:28:26 PM PDT 24
Finished Aug 01 06:28:28 PM PDT 24
Peak memory 199884 kb
Host smart-2361a73c-187f-4ad7-81e5-5f716f70c40d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163796390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1163796390
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3998812242
Short name T482
Test name
Test status
Simulation time 440779520 ps
CPU time 11.97 seconds
Started Aug 01 06:28:25 PM PDT 24
Finished Aug 01 06:28:37 PM PDT 24
Peak memory 199832 kb
Host smart-8295ffea-85c9-4c28-81e5-d598c0405054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998812242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3998812242
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_stress_all.4288234359
Short name T496
Test name
Test status
Simulation time 15551910109 ps
CPU time 802.03 seconds
Started Aug 01 06:28:24 PM PDT 24
Finished Aug 01 06:41:46 PM PDT 24
Peak memory 732272 kb
Host smart-254ed688-8035-4f0c-9135-40e31f0de8c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288234359 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.4288234359
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.399316740
Short name T40
Test name
Test status
Simulation time 3694239405 ps
CPU time 45.34 seconds
Started Aug 01 06:28:26 PM PDT 24
Finished Aug 01 06:29:12 PM PDT 24
Peak memory 199992 kb
Host smart-94133c0a-a7e2-4d4d-aedb-593113538626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399316740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.399316740
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.426847337
Short name T386
Test name
Test status
Simulation time 41194650 ps
CPU time 0.62 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:26:57 PM PDT 24
Peak memory 195876 kb
Host smart-564b2ab7-0c6c-46a0-980c-b6e7d40611da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426847337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.426847337
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1563983813
Short name T379
Test name
Test status
Simulation time 1149778026 ps
CPU time 62.21 seconds
Started Aug 01 06:27:02 PM PDT 24
Finished Aug 01 06:28:04 PM PDT 24
Peak memory 199904 kb
Host smart-0d7eda58-03f6-49ce-90c5-90f7bbbe464d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1563983813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1563983813
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2137360092
Short name T223
Test name
Test status
Simulation time 4725785228 ps
CPU time 10.81 seconds
Started Aug 01 06:27:00 PM PDT 24
Finished Aug 01 06:27:11 PM PDT 24
Peak memory 199944 kb
Host smart-f9fd3dfb-e739-4d3e-8509-a4ad1b57ccf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137360092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2137360092
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2658482951
Short name T272
Test name
Test status
Simulation time 21421814047 ps
CPU time 767.63 seconds
Started Aug 01 06:27:07 PM PDT 24
Finished Aug 01 06:39:55 PM PDT 24
Peak memory 729616 kb
Host smart-e2d3fa40-d2ae-4d20-b073-2ce878c91af0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658482951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2658482951
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2023763726
Short name T338
Test name
Test status
Simulation time 14716501572 ps
CPU time 99.25 seconds
Started Aug 01 06:27:00 PM PDT 24
Finished Aug 01 06:28:39 PM PDT 24
Peak memory 199964 kb
Host smart-a9a80316-f256-4eb6-ac9c-573319a9acdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023763726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2023763726
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3645932118
Short name T295
Test name
Test status
Simulation time 3079167453 ps
CPU time 55.63 seconds
Started Aug 01 06:26:48 PM PDT 24
Finished Aug 01 06:27:44 PM PDT 24
Peak memory 200032 kb
Host smart-344409c6-0960-4722-883c-c47ecce376bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645932118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3645932118
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2797294046
Short name T474
Test name
Test status
Simulation time 1013518557 ps
CPU time 12.09 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:27:16 PM PDT 24
Peak memory 199900 kb
Host smart-7890f379-ebbe-4e04-81de-64720790037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797294046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2797294046
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3236004182
Short name T241
Test name
Test status
Simulation time 79081636985 ps
CPU time 959.16 seconds
Started Aug 01 06:26:57 PM PDT 24
Finished Aug 01 06:43:01 PM PDT 24
Peak memory 622824 kb
Host smart-3361c8a4-138f-4375-9ec8-9cf169de1d31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236004182 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3236004182
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3024968946
Short name T29
Test name
Test status
Simulation time 21603464933 ps
CPU time 2016.01 seconds
Started Aug 01 06:27:01 PM PDT 24
Finished Aug 01 07:00:37 PM PDT 24
Peak memory 764308 kb
Host smart-dcce8448-8e86-4121-a2c2-521f6de95cde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024968946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3024968946
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3954892212
Short name T201
Test name
Test status
Simulation time 5163723724 ps
CPU time 90.75 seconds
Started Aug 01 06:27:05 PM PDT 24
Finished Aug 01 06:28:36 PM PDT 24
Peak memory 199988 kb
Host smart-2936f1ea-f7be-4f26-af7c-23ab412c2bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954892212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3954892212
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1723958057
Short name T342
Test name
Test status
Simulation time 34357328 ps
CPU time 0.57 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:26:56 PM PDT 24
Peak memory 194900 kb
Host smart-aaa4838b-2cd6-4031-b470-762660240953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723958057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1723958057
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.579031260
Short name T232
Test name
Test status
Simulation time 1252718769 ps
CPU time 81.18 seconds
Started Aug 01 06:26:54 PM PDT 24
Finished Aug 01 06:28:15 PM PDT 24
Peak memory 199760 kb
Host smart-f8081333-8071-4c60-b5e4-bafb6e049ff8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579031260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.579031260
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1982138592
Short name T129
Test name
Test status
Simulation time 3399431129 ps
CPU time 32.18 seconds
Started Aug 01 06:26:54 PM PDT 24
Finished Aug 01 06:27:26 PM PDT 24
Peak memory 199972 kb
Host smart-09ec9765-571d-4a8e-a962-6d8e3177da83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982138592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1982138592
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1755478937
Short name T309
Test name
Test status
Simulation time 31822801 ps
CPU time 0.69 seconds
Started Aug 01 06:27:06 PM PDT 24
Finished Aug 01 06:27:07 PM PDT 24
Peak memory 198212 kb
Host smart-38989d72-efdb-4486-9542-b8eb15b39293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755478937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1755478937
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2100686698
Short name T190
Test name
Test status
Simulation time 32946478512 ps
CPU time 147.48 seconds
Started Aug 01 06:27:00 PM PDT 24
Finished Aug 01 06:29:27 PM PDT 24
Peak memory 199960 kb
Host smart-bff9cb82-dd4d-458e-9288-ddbedd74e4f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100686698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2100686698
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1369038252
Short name T256
Test name
Test status
Simulation time 176706970 ps
CPU time 9.75 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:27:06 PM PDT 24
Peak memory 199792 kb
Host smart-b07083d2-f20a-4ada-bc30-efbf5c16c432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369038252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1369038252
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2466039286
Short name T308
Test name
Test status
Simulation time 2312670683 ps
CPU time 7.68 seconds
Started Aug 01 06:26:51 PM PDT 24
Finished Aug 01 06:26:59 PM PDT 24
Peak memory 199884 kb
Host smart-d28b7a75-f3da-4975-961f-a3a96e6f655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466039286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2466039286
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1001706448
Short name T390
Test name
Test status
Simulation time 25421950703 ps
CPU time 1038.47 seconds
Started Aug 01 06:27:11 PM PDT 24
Finished Aug 01 06:44:29 PM PDT 24
Peak memory 741480 kb
Host smart-158d0520-e0f1-46eb-ac69-4b659b550d28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001706448 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1001706448
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.4226373072
Short name T77
Test name
Test status
Simulation time 69327668501 ps
CPU time 7211.79 seconds
Started Aug 01 06:26:50 PM PDT 24
Finished Aug 01 08:27:02 PM PDT 24
Peak memory 913680 kb
Host smart-66323989-276f-443b-8a7f-575a45f16732
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226373072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.4226373072
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.52846118
Short name T369
Test name
Test status
Simulation time 1042667023 ps
CPU time 20.27 seconds
Started Aug 01 06:26:58 PM PDT 24
Finished Aug 01 06:27:18 PM PDT 24
Peak memory 199832 kb
Host smart-3568626b-3a93-4563-b218-3c4ee7c2b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52846118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.52846118
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3868809932
Short name T284
Test name
Test status
Simulation time 18285928 ps
CPU time 0.59 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:27:05 PM PDT 24
Peak memory 194848 kb
Host smart-8e8b2502-35a5-4b36-8745-dbebb8dd696e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868809932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3868809932
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1350886377
Short name T276
Test name
Test status
Simulation time 3143474763 ps
CPU time 45.97 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:27:42 PM PDT 24
Peak memory 200032 kb
Host smart-9b1ce59d-ca54-47fe-a751-28612f65b074
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350886377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1350886377
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.143613839
Short name T502
Test name
Test status
Simulation time 2002012176 ps
CPU time 28.95 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:27:25 PM PDT 24
Peak memory 199840 kb
Host smart-3d5cb916-118b-4710-b6a9-cba672f454e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143613839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.143613839
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3030142669
Short name T38
Test name
Test status
Simulation time 25437031259 ps
CPU time 1252.9 seconds
Started Aug 01 06:26:51 PM PDT 24
Finished Aug 01 06:47:44 PM PDT 24
Peak memory 771076 kb
Host smart-b8949824-868d-4049-a2ad-30fa03ba8ba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030142669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3030142669
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.518350087
Short name T53
Test name
Test status
Simulation time 1898449588 ps
CPU time 23.61 seconds
Started Aug 01 06:26:53 PM PDT 24
Finished Aug 01 06:27:17 PM PDT 24
Peak memory 199788 kb
Host smart-b49dd58e-467d-49c8-ab42-d28c3ccda74e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518350087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.518350087
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3398489422
Short name T279
Test name
Test status
Simulation time 4818944010 ps
CPU time 144.89 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:29:29 PM PDT 24
Peak memory 199984 kb
Host smart-f5f1fc78-734c-42d7-b692-aac6962b7de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398489422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3398489422
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.137709856
Short name T215
Test name
Test status
Simulation time 134356520 ps
CPU time 6.1 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 06:27:02 PM PDT 24
Peak memory 199860 kb
Host smart-0c202e47-072d-4cb8-8952-42b0f302e43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137709856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.137709856
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.893674126
Short name T468
Test name
Test status
Simulation time 22302841496 ps
CPU time 2893.01 seconds
Started Aug 01 06:26:57 PM PDT 24
Finished Aug 01 07:15:10 PM PDT 24
Peak memory 755988 kb
Host smart-09018f99-abfc-441d-81ec-4d3af75d1832
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893674126 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.893674126
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2087166775
Short name T366
Test name
Test status
Simulation time 4577125444 ps
CPU time 66.92 seconds
Started Aug 01 06:26:58 PM PDT 24
Finished Aug 01 06:28:05 PM PDT 24
Peak memory 199992 kb
Host smart-9f3606ad-e7e9-4ea4-ae53-d7ca2793971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087166775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2087166775
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3163123169
Short name T320
Test name
Test status
Simulation time 15223115 ps
CPU time 0.59 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 06:26:55 PM PDT 24
Peak memory 196560 kb
Host smart-ecce942a-f080-4caa-bf2d-d4474ec835cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163123169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3163123169
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3228484640
Short name T221
Test name
Test status
Simulation time 1017375837 ps
CPU time 29.33 seconds
Started Aug 01 06:27:00 PM PDT 24
Finished Aug 01 06:27:30 PM PDT 24
Peak memory 199880 kb
Host smart-87477804-1455-423f-adc6-857ea0294412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228484640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3228484640
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1034242297
Short name T410
Test name
Test status
Simulation time 417309064 ps
CPU time 5.57 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 06:27:01 PM PDT 24
Peak memory 199840 kb
Host smart-77f6e583-9c9e-449d-bd18-4e918bc5cf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034242297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1034242297
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3066228769
Short name T339
Test name
Test status
Simulation time 770506778 ps
CPU time 117.04 seconds
Started Aug 01 06:27:00 PM PDT 24
Finished Aug 01 06:28:57 PM PDT 24
Peak memory 591116 kb
Host smart-0d8f0eb5-b6c4-4139-81e5-c612b9f82d92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066228769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3066228769
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2944717543
Short name T151
Test name
Test status
Simulation time 13460391810 ps
CPU time 45.95 seconds
Started Aug 01 06:26:58 PM PDT 24
Finished Aug 01 06:27:44 PM PDT 24
Peak memory 199984 kb
Host smart-2c1e6246-4905-4937-accb-18881cfb6eea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944717543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2944717543
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.657786906
Short name T47
Test name
Test status
Simulation time 7743674462 ps
CPU time 111.81 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:28:48 PM PDT 24
Peak memory 199980 kb
Host smart-44f1f937-526e-4d5b-a1b4-2df845086042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657786906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.657786906
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3105707439
Short name T319
Test name
Test status
Simulation time 361325541 ps
CPU time 16.98 seconds
Started Aug 01 06:26:55 PM PDT 24
Finished Aug 01 06:27:13 PM PDT 24
Peak memory 199848 kb
Host smart-9f9e4303-89e5-4976-b87a-47255b5c3c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105707439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3105707439
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.954781710
Short name T28
Test name
Test status
Simulation time 97542021607 ps
CPU time 2390.94 seconds
Started Aug 01 06:26:54 PM PDT 24
Finished Aug 01 07:06:46 PM PDT 24
Peak memory 747244 kb
Host smart-eb4443be-f949-4360-890f-11b8c69359ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954781710 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.954781710
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.4197931020
Short name T452
Test name
Test status
Simulation time 50478575785 ps
CPU time 143.07 seconds
Started Aug 01 06:26:53 PM PDT 24
Finished Aug 01 06:29:16 PM PDT 24
Peak memory 199972 kb
Host smart-f2cb3f49-2b11-4d1f-a53c-12d0f3100ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197931020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.4197931020
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1330278855
Short name T361
Test name
Test status
Simulation time 87951632 ps
CPU time 0.7 seconds
Started Aug 01 06:26:51 PM PDT 24
Finished Aug 01 06:26:52 PM PDT 24
Peak memory 196516 kb
Host smart-6b95bc86-d24c-4416-9a3c-f7090776ce25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330278855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1330278855
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1155446293
Short name T60
Test name
Test status
Simulation time 1163507334 ps
CPU time 63.24 seconds
Started Aug 01 06:27:04 PM PDT 24
Finished Aug 01 06:28:07 PM PDT 24
Peak memory 199812 kb
Host smart-77694ba4-934f-48c3-986c-8f747e529115
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155446293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1155446293
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2323281066
Short name T327
Test name
Test status
Simulation time 1469853288 ps
CPU time 27.42 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:27:24 PM PDT 24
Peak memory 199920 kb
Host smart-df8da38a-2ec4-4455-936f-06879d7ca313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323281066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2323281066
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1570124142
Short name T297
Test name
Test status
Simulation time 22484432152 ps
CPU time 612.82 seconds
Started Aug 01 06:26:57 PM PDT 24
Finished Aug 01 06:37:10 PM PDT 24
Peak memory 706488 kb
Host smart-baba453a-47db-4bfe-86ea-fa5ebd18093d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570124142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1570124142
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1063125649
Short name T332
Test name
Test status
Simulation time 23166445222 ps
CPU time 162.34 seconds
Started Aug 01 06:27:05 PM PDT 24
Finished Aug 01 06:29:48 PM PDT 24
Peak memory 199956 kb
Host smart-5d85f014-f3b6-4bb2-a0af-dd9caa831f4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063125649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1063125649
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1366380865
Short name T238
Test name
Test status
Simulation time 13616393117 ps
CPU time 85.84 seconds
Started Aug 01 06:26:43 PM PDT 24
Finished Aug 01 06:28:09 PM PDT 24
Peak memory 199996 kb
Host smart-f14391ba-a320-4e63-9ef7-3956dadf74c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366380865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1366380865
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.23133144
Short name T200
Test name
Test status
Simulation time 1310624247 ps
CPU time 17.29 seconds
Started Aug 01 06:26:42 PM PDT 24
Finished Aug 01 06:27:00 PM PDT 24
Peak memory 199828 kb
Host smart-b1cf8eba-5af8-4577-b733-ad78028d1a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23133144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.23133144
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2437989216
Short name T360
Test name
Test status
Simulation time 15387946261 ps
CPU time 399 seconds
Started Aug 01 06:26:59 PM PDT 24
Finished Aug 01 06:33:38 PM PDT 24
Peak memory 215940 kb
Host smart-93597643-6b04-4fd7-badd-0348f82f4814
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437989216 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2437989216
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.3018486384
Short name T12
Test name
Test status
Simulation time 142857312006 ps
CPU time 1280.18 seconds
Started Aug 01 06:26:59 PM PDT 24
Finished Aug 01 06:48:19 PM PDT 24
Peak memory 660748 kb
Host smart-0fc32620-2274-42d5-b1bc-4d02f0a27703
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018486384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3018486384
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3597592655
Short name T189
Test name
Test status
Simulation time 15778391572 ps
CPU time 67.3 seconds
Started Aug 01 06:26:56 PM PDT 24
Finished Aug 01 06:28:04 PM PDT 24
Peak memory 200032 kb
Host smart-8540c76a-3253-4d2a-9d64-e2519ebea946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597592655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3597592655
Directory /workspace/9.hmac_wipe_secret/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%