Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19581780	1			T1	1238		T2	2058		T3	4578
all_values[1]	19581780	1			T1	1238		T2	2058		T3	4578
all_values[2]	19581780	1			T1	1238		T2	2058		T3	4578

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

259498

1

T2

45

T4

4337

T17

407

auto[1]

58485842

1

T1

3714

T2

6129

T3

13734

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49824094

1

T1

3318

T2

5208

T3

12128

auto[1]

8921246

1

T1

396

T2

966

T3

1606

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	79174	1			T4	1139		T18	36		T24	347
all_values[0]	auto[0]	auto[1]	386	1			T4	4		T24	5		T126	2
all_values[0]	auto[1]	auto[0]	19481290	1			T1	1237		T2	2035		T3	4549
all_values[0]	auto[1]	auto[1]	20930	1			T1	1		T2	23		T3	29
all_values[1]	auto[0]	auto[0]	92205	1			T2	45		T4	1230		T24	185
all_values[1]	auto[0]	auto[1]	245	1			T4	2		T8	15		T20	4
all_values[1]	auto[1]	auto[0]	19488964	1			T1	1238		T2	2013		T3	4578
all_values[1]	auto[1]	auto[1]	366	1			T25	2		T8	22		T9	1
all_values[2]	auto[0]	auto[0]	36823	1			T4	3		T17	407		T7	953
all_values[2]	auto[0]	auto[1]	50665	1			T4	1959		T24	2		T132	30
all_values[2]	auto[1]	auto[0]	10645638	1			T1	843		T2	1115		T3	3001
all_values[2]	auto[1]	auto[1]	8848654	1			T1	395		T2	943		T3	1577