Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

142321

1

T1

4

T2

36

T3

2140

auto[1]

159970

1

T2

16

T3

2124

T4

100

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	114662	1			T1	2		T3	1395		T4	95
len_1026_2046	8702	1			T3	70		T6	4		T19	58
len_514_1022	4631	1			T2	1		T3	584		T6	1
len_2_510	3725	1			T2	2		T3	21		T6	3
len_2056	234	1			T2	2		T23	4		T24	4
len_2048	345	1			T2	3		T3	1		T19	2
len_2040	162	1			T24	5		T128	1		T8	12
len_1032	247	1			T2	3		T23	5		T24	9
len_1024	1939	1			T2	4		T3	5		T19	8
len_1016	160	1			T2	1		T24	3		T8	15
len_520	246	1			T24	3		T128	4		T8	9
len_512	364	1			T3	1		T19	4		T23	4
len_504	202	1			T2	1		T6	2		T26	1
len_8	1581	1			T5	24		T140	14		T70	9
len_0	13945	1			T2	9		T3	55		T4	8

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

131

1

T126

1

T141

1

T142

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	55084	1			T1	2		T3	957		T4	51
auto[0]	len_1026_2046	3567	1			T3	29		T6	2		T19	13
auto[0]	len_514_1022	2700	1			T3	24		T7	1		T19	9
auto[0]	len_2_510	2042	1			T2	2		T3	14		T6	1
auto[0]	len_2056	123	1			T2	2		T23	2		T24	1
auto[0]	len_2048	185	1			T2	3		T24	9		T49	1
auto[0]	len_2040	85	1			T24	2		T8	6		T79	3
auto[0]	len_1032	145	1			T2	3		T23	1		T24	7
auto[0]	len_1024	307	1			T2	3		T3	3		T19	2
auto[0]	len_1016	89	1			T24	1		T8	13		T79	4
auto[0]	len_520	107	1			T128	3		T8	4		T9	2
auto[0]	len_512	213	1			T3	1		T19	1		T23	3
auto[0]	len_504	120	1			T2	1		T6	2		T26	1
auto[0]	len_8	265	1			T48	21		T131	1		T143	2
auto[0]	len_0	6128	1			T2	4		T3	42		T4	2
auto[1]	len_2050_plus	59578	1			T3	438		T4	44		T17	3
auto[1]	len_1026_2046	5135	1			T3	41		T6	2		T19	45
auto[1]	len_514_1022	1931	1			T2	1		T3	560		T6	1
auto[1]	len_2_510	1683	1			T3	7		T6	2		T19	28
auto[1]	len_2056	111	1			T23	2		T24	3		T128	3
auto[1]	len_2048	160	1			T3	1		T19	2		T24	3
auto[1]	len_2040	77	1			T24	3		T128	1		T8	6
auto[1]	len_1032	102	1			T23	4		T24	2		T8	5
auto[1]	len_1024	1632	1			T2	1		T3	2		T19	6
auto[1]	len_1016	71	1			T2	1		T24	2		T8	2
auto[1]	len_520	139	1			T24	3		T128	1		T8	5
auto[1]	len_512	151	1			T19	3		T23	1		T24	2
auto[1]	len_504	82	1			T8	6		T20	1		T144	2
auto[1]	len_8	1316	1			T5	24		T140	14		T70	9
auto[1]	len_0	7817	1			T2	5		T3	13		T4	6

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

71

1

T142

2

T48

2

T8

3

auto[1]

len_upper

60

1

T126

1

T141

1

T48

4