Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4881367 1 T1 264 T2 364 T3 2203
auto[1] 3296423 1 T1 343 T2 645 T3 6321


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3341582 1 T1 264 T2 615 T3 5916
auto[1] 4836208 1 T1 343 T2 394 T3 2608


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3442350 1 T1 607 T2 518 T3 4253
auto[1] 4735440 1 T2 491 T3 4271 T4 10128


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4906648 1 T1 607 T2 545 T3 6306
auto[1] 3271142 1 T2 464 T3 2218 T4 16357


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7338682 1 T1 593 T2 1000 T3 8211
fifo_depth[1] 125579 1 T1 10 T2 6 T3 112
fifo_depth[2] 98536 1 T1 4 T2 3 T3 105
fifo_depth[3] 78325 1 T3 34 T4 7 T17 2
fifo_depth[4] 71721 1 T3 38 T4 2 T17 1
fifo_depth[5] 56872 1 T3 11 T4 1 T5 450
fifo_depth[6] 45793 1 T3 10 T5 345 T6 294
fifo_depth[7] 31713 1 T3 1 T5 241 T6 188


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 839108 1 T1 14 T2 9 T3 313
auto[1] 7338682 1 T1 593 T2 1000 T3 8211


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8164567 1 T1 607 T2 1009 T3 8524
auto[1] 13223 1 T25 336 T8 742 T20 598


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 50919 1 T3 33 T4 11 T17 34
auto[0] auto[0] auto[0] auto[0] auto[1] 41105 1 T4 53 T6 381 T7 553
auto[0] auto[0] auto[0] auto[1] auto[0] 37917 1 T3 184 T6 243 T7 56
auto[0] auto[0] auto[0] auto[1] auto[1] 39125 1 T2 2 T3 15 T4 38
auto[0] auto[0] auto[1] auto[0] auto[0] 163407 1 T2 1 T4 12 T17 12
auto[0] auto[0] auto[1] auto[0] auto[1] 35502 1 T2 2 T3 8 T4 36
auto[0] auto[0] auto[1] auto[1] auto[0] 49680 1 T1 14 T3 29 T4 12
auto[0] auto[0] auto[1] auto[1] auto[1] 31140 1 T3 3 T4 54 T6 157
auto[0] auto[1] auto[0] auto[0] auto[0] 48253 1 T3 16 T4 11 T5 445
auto[0] auto[1] auto[0] auto[0] auto[1] 46538 1 T17 9 T5 1167 T6 15
auto[0] auto[1] auto[0] auto[1] auto[0] 48573 1 T2 2 T4 33 T5 672
auto[0] auto[1] auto[0] auto[1] auto[1] 45507 1 T4 58 T5 202 T6 181
auto[0] auto[1] auto[1] auto[0] auto[0] 63592 1 T4 7 T17 21 T5 363
auto[0] auto[1] auto[1] auto[0] auto[1] 42984 1 T3 25 T4 12 T5 400
auto[0] auto[1] auto[1] auto[1] auto[0] 46137 1 T2 2 T6 51 T19 30
auto[0] auto[1] auto[1] auto[1] auto[1] 48729 1 T4 5 T6 338 T7 217
auto[1] auto[0] auto[0] auto[0] auto[0] 189850 1 T1 264 T3 199 T4 2222
auto[1] auto[0] auto[0] auto[0] auto[1] 196415 1 T2 57 T4 3298 T6 1662
auto[1] auto[0] auto[0] auto[1] auto[0] 194514 1 T2 109 T3 2570 T4 660
auto[1] auto[0] auto[0] auto[1] auto[1] 192251 1 T2 136 T3 245 T4 1047
auto[1] auto[0] auto[1] auto[0] auto[0] 1618487 1 T2 48 T4 937 T17 198
auto[1] auto[0] auto[1] auto[0] auto[1] 188005 1 T2 117 T3 51 T4 2698
auto[1] auto[0] auto[1] auto[1] auto[0] 213295 1 T1 329 T2 25 T3 236
auto[1] auto[0] auto[1] auto[1] auto[1] 200738 1 T2 21 T3 680 T4 3488
auto[1] auto[1] auto[0] auto[0] auto[0] 532252 1 T2 62 T3 1647 T4 2379
auto[1] auto[1] auto[0] auto[0] auto[1] 570540 1 T2 23 T4 768 T17 260
auto[1] auto[1] auto[0] auto[1] auto[0] 557479 1 T2 223 T3 54 T4 1692
auto[1] auto[1] auto[0] auto[1] auto[1] 550344 1 T2 1 T3 953 T4 2553
auto[1] auto[1] auto[1] auto[0] auto[0] 586452 1 T2 11 T4 354 T17 367
auto[1] auto[1] auto[1] auto[0] auto[1] 507066 1 T2 43 T3 224 T4 1836
auto[1] auto[1] auto[1] auto[1] auto[0] 505841 1 T2 62 T3 1338 T4 7
auto[1] auto[1] auto[1] auto[1] auto[1] 535153 1 T2 62 T3 14 T4 413


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 239718 1 T1 264 T3 232 T4 2233
auto[0] auto[0] auto[0] auto[0] auto[1] 236896 1 T2 57 T4 3351 T6 2043
auto[0] auto[0] auto[0] auto[1] auto[0] 231497 1 T2 109 T3 2754 T4 660
auto[0] auto[0] auto[0] auto[1] auto[1] 230330 1 T2 138 T3 260 T4 1085
auto[0] auto[0] auto[1] auto[0] auto[0] 1780949 1 T2 49 T4 949 T17 210
auto[0] auto[0] auto[1] auto[0] auto[1] 222369 1 T2 119 T3 59 T4 2734
auto[0] auto[0] auto[1] auto[1] auto[0] 261831 1 T1 343 T2 25 T3 265
auto[0] auto[0] auto[1] auto[1] auto[1] 231409 1 T2 21 T3 683 T4 3542
auto[0] auto[1] auto[0] auto[0] auto[0] 579506 1 T2 62 T3 1663 T4 2390
auto[0] auto[1] auto[0] auto[0] auto[1] 616370 1 T2 23 T4 768 T17 269
auto[0] auto[1] auto[0] auto[1] auto[0] 605559 1 T2 225 T3 54 T4 1725
auto[0] auto[1] auto[0] auto[1] auto[1] 595161 1 T2 1 T3 953 T4 2611
auto[0] auto[1] auto[1] auto[0] auto[0] 648888 1 T2 11 T4 361 T17 388
auto[0] auto[1] auto[1] auto[0] auto[1] 549731 1 T2 43 T3 249 T4 1848
auto[0] auto[1] auto[1] auto[1] auto[0] 551281 1 T2 64 T3 1338 T4 7
auto[0] auto[1] auto[1] auto[1] auto[1] 583072 1 T2 62 T3 14 T4 418
auto[1] auto[0] auto[0] auto[0] auto[0] 1051 1 T25 85 T8 32 T20 44
auto[1] auto[0] auto[0] auto[0] auto[1] 624 1 T25 228 T8 91 T20 17
auto[1] auto[0] auto[0] auto[1] auto[0] 934 1 T25 1 T8 78 T146 6
auto[1] auto[0] auto[0] auto[1] auto[1] 1046 1 T25 19 T8 10 T20 122
auto[1] auto[0] auto[1] auto[0] auto[0] 945 1 T8 11 T20 46 T22 10
auto[1] auto[0] auto[1] auto[0] auto[1] 1138 1 T8 116 T66 11 T146 7
auto[1] auto[0] auto[1] auto[1] auto[0] 1144 1 T8 38 T20 16 T147 1
auto[1] auto[0] auto[1] auto[1] auto[1] 469 1 T8 34 T148 154 T149 41
auto[1] auto[1] auto[0] auto[0] auto[0] 999 1 T8 254 T20 3 T148 7
auto[1] auto[1] auto[0] auto[0] auto[1] 708 1 T150 3 T148 1 T149 42
auto[1] auto[1] auto[0] auto[1] auto[0] 493 1 T25 3 T8 7 T20 22
auto[1] auto[1] auto[0] auto[1] auto[1] 690 1 T8 2 T20 3 T150 50
auto[1] auto[1] auto[1] auto[0] auto[0] 1156 1 T8 38 T20 310 T150 254
auto[1] auto[1] auto[1] auto[0] auto[1] 319 1 T8 15 T148 47 T149 11
auto[1] auto[1] auto[1] auto[1] auto[0] 697 1 T8 16 T150 2 T146 6
auto[1] auto[1] auto[1] auto[1] auto[1] 810 1 T20 15 T148 7 T149 2


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 189850 1 T1 264 T3 199 T4 2222
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 196415 1 T2 57 T4 3298 T6 1662
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 194514 1 T2 109 T3 2570 T4 660
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 192251 1 T2 136 T3 245 T4 1047
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1618487 1 T2 48 T4 937 T17 198
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 188005 1 T2 117 T3 51 T4 2698
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 213295 1 T1 329 T2 25 T3 236
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 200738 1 T2 21 T3 680 T4 3488
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 532252 1 T2 62 T3 1647 T4 2379
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 570540 1 T2 23 T4 768 T17 260
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 557479 1 T2 223 T3 54 T4 1692
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 550344 1 T2 1 T3 953 T4 2553
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 586452 1 T2 11 T4 354 T17 367
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 507066 1 T2 43 T3 224 T4 1836
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 505841 1 T2 62 T3 1338 T4 7
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 535153 1 T2 62 T3 14 T4 413
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 4323 1 T3 4 T4 8 T17 24
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3706 1 T4 39 T6 67 T7 82
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3881 1 T3 80 T6 38 T7 12
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3730 1 T2 1 T3 7 T4 28
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 40729 1 T2 1 T4 9 T17 7
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3770 1 T2 2 T3 3 T4 32
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 4392 1 T1 10 T3 7 T4 10
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3695 1 T4 46 T6 30 T19 18
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 7379 1 T3 11 T4 7 T5 65
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 7274 1 T17 8 T5 171 T6 2
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 7029 1 T2 1 T4 26 T5 111
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6992 1 T4 44 T5 29 T6 29
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 9185 1 T4 5 T17 13 T5 48
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6753 1 T4 10 T5 66 T6 2
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 5788 1 T2 1 T6 9 T19 3
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 6953 1 T4 5 T6 57 T7 28
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3424 1 T3 9 T4 3 T17 10
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2866 1 T4 14 T6 76 T7 83
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3108 1 T3 67 T6 35 T7 8
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2980 1 T2 1 T3 4 T4 8
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 29396 1 T4 2 T17 4 T7 24
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2893 1 T3 2 T4 2 T6 49
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3616 1 T1 4 T3 6 T4 2
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2888 1 T3 3 T4 7 T6 23
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 6266 1 T3 3 T4 3 T5 62
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5924 1 T17 1 T5 192 T6 2
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5848 1 T2 1 T4 6 T5 90
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5794 1 T4 12 T5 26 T6 31
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 7389 1 T4 2 T17 6 T5 51
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5615 1 T3 11 T4 2 T5 58
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4799 1 T2 1 T6 8 T19 26
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 5730 1 T6 58 T7 35 T19 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2749 1 T3 5 T6 57 T7 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2254 1 T6 69 T7 92 T24 12
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2245 1 T3 19 T6 33 T7 10
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2420 1 T3 1 T4 2 T6 75
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 22825 1 T17 1 T7 23 T24 7
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2282 1 T3 2 T6 40 T7 35
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2630 1 T3 6 T6 66 T7 44
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2152 1 T4 1 T6 23 T19 7
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 5213 1 T4 1 T5 64 T24 13
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4779 1 T5 197 T6 3 T7 14
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4856 1 T4 1 T5 104 T6 15
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4824 1 T4 2 T5 33 T6 20
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 6040 1 T17 1 T5 53 T6 52
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 4500 1 T3 1 T5 65 T6 3
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 3970 1 T6 4 T19 1 T23 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 4586 1 T6 65 T7 40 T23 3
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2864 1 T3 7 T6 63 T7 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2449 1 T6 68 T7 94 T19 4
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2386 1 T3 16 T6 28 T7 9
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2528 1 T3 1 T6 63 T24 18
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 17411 1 T4 1 T7 23 T19 17
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2437 1 T4 1 T6 43 T7 43
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2712 1 T3 4 T6 79 T7 46
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2200 1 T6 23 T19 8 T24 8
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4827 1 T3 1 T5 67 T19 3
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4512 1 T5 173 T6 1 T7 18
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4644 1 T5 103 T6 16 T7 32
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4732 1 T5 33 T6 29 T7 15
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5776 1 T17 1 T5 62 T6 47
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4192 1 T3 9 T5 48 T6 4
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 3859 1 T6 6 T23 1 T24 3
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 4192 1 T6 52 T7 30 T23 2
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 2370 1 T3 3 T6 59 T7 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1853 1 T6 52 T7 69 T24 10
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1650 1 T3 2 T6 30 T7 7
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1958 1 T3 2 T6 53 T24 3
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 12278 1 T7 23 T126 21 T49 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1840 1 T3 1 T4 1 T6 49
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 2176 1 T3 3 T6 51 T7 29
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1684 1 T6 19 T19 3 T24 2
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 4056 1 T5 60 T24 1 T140 87
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3789 1 T5 161 T6 1 T7 16
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 4010 1 T5 85 T6 14 T7 24
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 4067 1 T5 30 T6 25 T7 17
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4617 1 T5 56 T6 35 T19 1
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3744 1 T5 58 T7 14 T70 68
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3168 1 T6 8 T23 3 T24 3
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3612 1 T6 45 T7 35 T132 10
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1891 1 T3 4 T6 37 T19 2
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1808 1 T6 29 T7 70 T24 10
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1656 1 T6 27 T7 4 T19 21
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1581 1 T6 36 T24 3 T126 9
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 8757 1 T7 24 T24 2 T126 21
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1498 1 T6 29 T7 26 T23 2
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1878 1 T3 2 T6 26 T7 26
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1391 1 T6 14 T126 7 T49 2
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3405 1 T3 1 T5 56 T24 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3100 1 T5 110 T6 1 T7 7
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3316 1 T5 81 T6 12 T7 18
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3354 1 T5 22 T6 18 T7 11
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3694 1 T5 35 T6 28 T19 1
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2967 1 T3 3 T5 41 T6 2
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2632 1 T6 5 T23 1 T24 5
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2865 1 T6 30 T7 21 T23 1
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1586 1 T3 1 T6 30 T25 22
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1324 1 T6 14 T7 35 T24 13
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1170 1 T6 24 T7 3 T126 2
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1134 1 T6 18 T126 1 T25 5
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 5515 1 T7 15 T126 12 T49 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1157 1 T6 13 T7 8 T48 10
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1411 1 T6 13 T7 21 T48 2
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1040 1 T6 15 T126 1 T25 42
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2339 1 T5 36 T140 46 T8 183
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2145 1 T5 84 T6 2 T7 7
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2159 1 T5 53 T6 9 T7 11
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2346 1 T5 12 T6 11 T7 11
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2499 1 T5 26 T6 19 T19 2
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1917 1 T5 30 T7 3 T70 25
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1752 1 T6 5 T23 1 T24 2
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2219 1 T6 15 T7 19 T23 1

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