Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19581780	1			T1	1238		T2	2058		T3	4578
all_pins[1]	19581780	1			T1	1238		T2	2058		T3	4578
all_pins[2]	19581780	1			T1	1238		T2	2058		T3	4578

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49874483	1			T1	3318		T2	5207		T3	12126
values[0x1]	8870857	1			T1	396		T2	967		T3	1608
transitions[0x0=>0x1]	8870688	1			T1	396		T2	967		T3	1607
transitions[0x1=>0x0]	8870704	1			T1	396		T2	967		T3	1608

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19559976	1			T1	1237		T2	2034		T3	4547
all_pins[0]	values[0x1]	21804	1			T1	1		T2	24		T3	31
all_pins[0]	transitions[0x0=>0x1]	21722	1			T1	1		T2	24		T3	30
all_pins[0]	transitions[0x1=>0x0]	8848588	1			T1	395		T2	943		T3	1577
all_pins[1]	values[0x0]	19581381	1			T1	1238		T2	2058		T3	4578
all_pins[1]	values[0x1]	399	1			T25	2		T8	24		T9	1
all_pins[1]	transitions[0x0=>0x1]	362	1			T25	2		T8	23		T9	1
all_pins[1]	transitions[0x1=>0x0]	21767	1			T1	1		T2	24		T3	31
all_pins[2]	values[0x0]	10733126	1			T1	843		T2	1115		T3	3001
all_pins[2]	values[0x1]	8848654	1			T1	395		T2	943		T3	1577
all_pins[2]	transitions[0x0=>0x1]	8848604	1			T1	395		T2	943		T3	1577
all_pins[2]	transitions[0x1=>0x0]	349	1			T25	2		T8	21		T9	1