Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1063 1 T4 4 T24 4 T8 62
all_values[1] 1063 1 T4 4 T24 4 T8 62
all_values[2] 1063 1 T4 4 T24 4 T8 62


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1590 1 T4 6 T24 5 T8 77
auto[1] 1599 1 T4 6 T24 7 T8 109


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1170 1 T4 3 T24 7 T8 68
auto[1] 2019 1 T4 9 T24 5 T8 118


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1802 1 T4 8 T24 9 T8 112
auto[1] 1387 1 T4 4 T24 3 T8 74


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 221 1 T24 2 T8 16 T9 4
all_values[0] auto[0] auto[0] auto[1] 86 1 T8 4 T20 1 T10 1
all_values[0] auto[0] auto[1] auto[0] 230 1 T24 1 T8 16 T9 2
all_values[0] auto[0] auto[1] auto[1] 80 1 T4 3 T8 6 T20 2
all_values[0] auto[1] auto[0] auto[1] 228 1 T4 1 T24 1 T8 10
all_values[0] auto[1] auto[1] auto[1] 218 1 T8 10 T20 6 T10 3
all_values[1] auto[0] auto[0] auto[0] 175 1 T4 1 T24 1 T8 8
all_values[1] auto[0] auto[0] auto[1] 132 1 T4 1 T8 8 T20 4
all_values[1] auto[0] auto[1] auto[0] 170 1 T24 3 T8 6 T9 2
all_values[1] auto[0] auto[1] auto[1] 129 1 T8 13 T9 1 T20 1
all_values[1] auto[1] auto[0] auto[1] 233 1 T4 2 T8 7 T20 2
all_values[1] auto[1] auto[1] auto[1] 224 1 T8 20 T9 1 T20 4
all_values[2] auto[0] auto[0] auto[0] 166 1 T4 1 T8 8 T9 1
all_values[2] auto[0] auto[0] auto[1] 109 1 T24 1 T8 5 T20 2
all_values[2] auto[0] auto[1] auto[0] 208 1 T4 1 T8 14 T9 3
all_values[2] auto[0] auto[1] auto[1] 96 1 T4 1 T24 1 T8 8
all_values[2] auto[1] auto[0] auto[1] 240 1 T8 11 T9 1 T20 7
all_values[2] auto[1] auto[1] auto[1] 244 1 T4 1 T24 2 T8 16


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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