Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	5030	1			T2	14		T3	7		T4	21
sha2_none	4873	1			T1	1		T2	7		T3	5
sha2_512	7854	1			T2	12		T3	10		T4	28
sha2_384	8062	1			T2	7		T3	10		T4	26
sha2_256	6824	1			T1	1		T2	5		T3	8

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20006

1

T1

1

T2

18

T3

12

auto[1]

13110

1

T1

1

T2

28

T3

28

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12995

1

T1

1

T2

28

T3

26

auto[1]

20121

1

T1

1

T2

18

T3

14

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17548

1

T2

23

T3

17

T4

63

disabled

15568

1

T1

2

T2

23

T3

23

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5377	1			T1	1		T2	14		T3	7
key_none	7825	1			T2	5		T3	6		T4	21
key_1024	4843	1			T2	8		T3	5		T4	17
key_512	4192	1			T2	3		T3	7		T4	12
key_384	3872	1			T1	1		T2	6		T3	7
key_256	3482	1			T2	5		T3	4		T4	16
key_128	3412	1			T2	5		T3	4		T4	19

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20289

1

T1

2

T2

24

T3

26

auto[1]

12827

1

T2

22

T3

14

T4

69

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

32897

1

T1

2

T2

46

T3

40

disabled

219

1

T4

3

T24

2

T48

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1829

1

T2

5

T3

6

T4

7

enabled

auto[0]

auto[0]

auto[1]

1923

1

T2

1

T4

9

T17

1

enabled

auto[0]

auto[1]

auto[0]

1887

1

T2

7

T3

1

T4

10

enabled

auto[0]

auto[1]

auto[1]

1849

1

T2

1

T3

2

T4

10

enabled

auto[1]

auto[0]

auto[0]

4513

1

T2

1

T4

6

T17

1

enabled

auto[1]

auto[0]

auto[1]

1787

1

T2

1

T3

2

T4

9

enabled

auto[1]

auto[1]

auto[0]

1950

1

T2

3

T3

4

T4

7

enabled

auto[1]

auto[1]

auto[1]

1810

1

T2

4

T3

2

T4

5

disabled

auto[0]

auto[0]

auto[0]

1363

1

T1

1

T3

3

T4

11

disabled

auto[0]

auto[0]

auto[1]

1361

1

T2

5

T4

7

T6

7

disabled

auto[0]

auto[1]

auto[0]

1428

1

T2

4

T3

8

T4

12

disabled

auto[0]

auto[1]

auto[1]

1355

1

T2

5

T3

6

T4

9

disabled

auto[1]

auto[0]

auto[0]

5883

1

T2

2

T4

8

T17

1

disabled

auto[1]

auto[0]

auto[1]

1347

1

T2

3

T3

1

T4

10

disabled

auto[1]

auto[1]

auto[0]

1436

1

T1

1

T2

2

T3

4

disabled

auto[1]

auto[1]

auto[1]

1395

1

T2

2

T3

1

T4

10

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17462

1

T2

23

T3

17

T4

62

enabled

disabled

86

1

T4

1

T24

2

T8

3

disabled

disabled

133

1

T4

2

T48

2

T8

7

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15435

1

T1

2

T2

23

T3

23

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1315	1			T2	5		T4	3		T6	2
key_invalid	sha2_none	1005	1			T1	1		T2	2		T4	10
key_invalid	sha2_512	984	1			T2	3		T3	2		T4	4
key_invalid	sha2_384	975	1			T2	2		T3	2		T4	3
key_invalid	sha2_256	984	1			T2	1		T3	3		T4	5
key_none	sha2_invalid	604	1			T2	2		T3	1		T4	6
key_none	sha2_none	642	1			T3	1		T4	4		T6	1
key_none	sha2_512	2256	1			T2	2		T3	2		T4	3
key_none	sha2_384	2621	1			T3	1		T4	4		T18	1
key_none	sha2_256	1652	1			T2	1		T3	1		T4	4
key_1024	sha2_invalid	636	1			T2	3		T4	1		T5	2
key_1024	sha2_none	625	1			T2	1		T3	2		T4	2
key_1024	sha2_512	1787	1			T2	2		T4	8		T5	2
key_1024	sha2_384	1041	1			T2	1		T3	2		T4	5
key_512	sha2_invalid	590	1			T4	3		T5	2		T6	1
key_512	sha2_none	628	1			T2	1		T3	1		T4	1
key_512	sha2_512	705	1			T3	3		T4	2		T6	3
key_512	sha2_384	1323	1			T2	2		T3	3		T4	4
key_512	sha2_256	878	1			T4	2		T6	3		T26	1
key_384	sha2_invalid	624	1			T3	3		T4	4		T6	1
key_384	sha2_none	647	1			T2	1		T4	10		T5	1
key_384	sha2_512	687	1			T2	3		T3	2		T4	4
key_384	sha2_384	715	1			T2	1		T4	1		T5	1
key_384	sha2_256	1132	1			T1	1		T2	1		T3	2
key_256	sha2_invalid	622	1			T2	2		T3	2		T4	2
key_256	sha2_none	604	1			T2	1		T3	1		T4	5
key_256	sha2_512	713	1			T2	2		T4	3		T5	4
key_256	sha2_384	697	1			T3	1		T4	2		T19	2
key_256	sha2_256	793	1			T4	4		T5	2		T6	5
key_128	sha2_invalid	611	1			T2	2		T3	1		T4	2
key_128	sha2_none	699	1			T2	1		T4	4		T5	1
key_128	sha2_512	710	1			T3	1		T4	4		T17	1
key_128	sha2_384	665	1			T2	1		T3	1		T4	7
key_128	sha2_256	671	1			T2	1		T3	1		T4	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

690

1

T2

1

T3

1

T4

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1315	1			T2	5		T4	3		T6	2
key_invalid	sha2_none	1005	1			T1	1		T2	2		T4	10
key_invalid	sha2_512	984	1			T2	3		T3	2		T4	4
key_invalid	sha2_384	975	1			T2	2		T3	2		T4	3
key_invalid	sha2_256	984	1			T2	1		T3	3		T4	5
key_none	sha2_invalid	604	1			T2	2		T3	1		T4	6
key_none	sha2_none	642	1			T3	1		T4	4		T6	1
key_none	sha2_512	2256	1			T2	2		T3	2		T4	3
key_none	sha2_384	2621	1			T3	1		T4	4		T18	1
key_none	sha2_256	1652	1			T2	1		T3	1		T4	4
key_1024	sha2_invalid	636	1			T2	3		T4	1		T5	2
key_1024	sha2_none	625	1			T2	1		T3	2		T4	2
key_1024	sha2_512	1787	1			T2	2		T4	8		T5	2
key_1024	sha2_384	1041	1			T2	1		T3	2		T4	5
key_1024	sha2_256	690	1			T2	1		T3	1		T4	1
key_512	sha2_invalid	590	1			T4	3		T5	2		T6	1
key_512	sha2_none	628	1			T2	1		T3	1		T4	1
key_512	sha2_512	705	1			T3	3		T4	2		T6	3
key_512	sha2_384	1323	1			T2	2		T3	3		T4	4
key_512	sha2_256	878	1			T4	2		T6	3		T26	1
key_384	sha2_invalid	624	1			T3	3		T4	4		T6	1
key_384	sha2_none	647	1			T2	1		T4	10		T5	1
key_384	sha2_512	687	1			T2	3		T3	2		T4	4
key_384	sha2_384	715	1			T2	1		T4	1		T5	1
key_384	sha2_256	1132	1			T1	1		T2	1		T3	2
key_256	sha2_invalid	622	1			T2	2		T3	2		T4	2
key_256	sha2_none	604	1			T2	1		T3	1		T4	5
key_256	sha2_512	713	1			T2	2		T4	3		T5	4
key_256	sha2_384	697	1			T3	1		T4	2		T19	2
key_256	sha2_256	793	1			T4	4		T5	2		T6	5
key_128	sha2_invalid	611	1			T2	2		T3	1		T4	2
key_128	sha2_none	699	1			T2	1		T4	4		T5	1
key_128	sha2_512	710	1			T3	1		T4	4		T17	1
key_128	sha2_384	665	1			T2	1		T3	1		T4	7
key_128	sha2_256	671	1			T2	1		T3	1		T4	2