Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.04 95.40 97.22 100.00 97.06 98.27 98.48 99.85


Total test records in report: 658
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T525 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3991729661 Aug 02 05:03:50 PM PDT 24 Aug 02 05:03:51 PM PDT 24 87401059 ps
T122 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1155163514 Aug 02 05:04:02 PM PDT 24 Aug 02 05:04:03 PM PDT 24 186642125 ps
T526 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1272418882 Aug 02 05:03:44 PM PDT 24 Aug 02 05:03:46 PM PDT 24 40854403 ps
T101 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1911319883 Aug 02 05:04:07 PM PDT 24 Aug 02 05:04:08 PM PDT 24 26359789 ps
T68 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1504718789 Aug 02 05:03:59 PM PDT 24 Aug 02 05:04:01 PM PDT 24 368994793 ps
T527 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1539226923 Aug 02 05:04:16 PM PDT 24 Aug 02 05:04:20 PM PDT 24 866031514 ps
T528 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1326480352 Aug 02 05:03:45 PM PDT 24 Aug 02 05:03:47 PM PDT 24 80936049 ps
T102 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1919877345 Aug 02 05:04:04 PM PDT 24 Aug 02 05:04:05 PM PDT 24 76870535 ps
T529 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3380361676 Aug 02 05:04:07 PM PDT 24 Aug 02 05:04:08 PM PDT 24 70097721 ps
T530 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3624482810 Aug 02 05:03:56 PM PDT 24 Aug 02 05:03:56 PM PDT 24 14236626 ps
T531 /workspace/coverage/cover_reg_top/30.hmac_intr_test.612206356 Aug 02 05:04:03 PM PDT 24 Aug 02 05:04:04 PM PDT 24 41987928 ps
T103 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2933166285 Aug 02 05:04:02 PM PDT 24 Aug 02 05:04:03 PM PDT 24 17149245 ps
T104 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2602373266 Aug 02 05:03:44 PM PDT 24 Aug 02 05:03:45 PM PDT 24 28497947 ps
T105 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3289863178 Aug 02 05:03:55 PM PDT 24 Aug 02 05:03:59 PM PDT 24 497055688 ps
T532 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1188727501 Aug 02 05:04:11 PM PDT 24 Aug 02 05:04:11 PM PDT 24 29526701 ps
T106 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4041884066 Aug 02 05:03:43 PM PDT 24 Aug 02 05:03:44 PM PDT 24 15935881 ps
T533 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1001784721 Aug 02 05:03:45 PM PDT 24 Aug 02 05:03:45 PM PDT 24 42804315 ps
T123 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3286499805 Aug 02 05:04:05 PM PDT 24 Aug 02 05:04:07 PM PDT 24 100603359 ps
T107 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.16109041 Aug 02 05:03:42 PM PDT 24 Aug 02 05:03:43 PM PDT 24 199101970 ps
T534 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2280988363 Aug 02 05:04:02 PM PDT 24 Aug 02 05:04:05 PM PDT 24 200255967 ps
T124 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1780506415 Aug 02 05:03:55 PM PDT 24 Aug 02 05:03:57 PM PDT 24 84920384 ps
T69 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.850838084 Aug 02 05:03:58 PM PDT 24 Aug 02 05:04:00 PM PDT 24 109339197 ps
T125 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3128862855 Aug 02 05:03:53 PM PDT 24 Aug 02 05:03:55 PM PDT 24 84466770 ps
T535 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2685205758 Aug 02 05:04:09 PM PDT 24 Aug 02 05:04:10 PM PDT 24 134594579 ps
T536 /workspace/coverage/cover_reg_top/48.hmac_intr_test.4208514837 Aug 02 05:04:07 PM PDT 24 Aug 02 05:04:08 PM PDT 24 11695924 ps
T537 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4053486667 Aug 02 05:04:01 PM PDT 24 Aug 02 05:04:04 PM PDT 24 51208594 ps
T108 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1679471547 Aug 02 05:04:05 PM PDT 24 Aug 02 05:04:06 PM PDT 24 14975775 ps
T109 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3635124702 Aug 02 05:03:39 PM PDT 24 Aug 02 05:03:53 PM PDT 24 308444809 ps
T538 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3653470218 Aug 02 05:04:09 PM PDT 24 Aug 02 05:04:10 PM PDT 24 12955521 ps
T539 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1575807572 Aug 02 05:04:10 PM PDT 24 Aug 02 05:11:18 PM PDT 24 112635290994 ps
T540 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.989041091 Aug 02 05:03:40 PM PDT 24 Aug 02 05:03:44 PM PDT 24 79213854 ps
T133 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1632784812 Aug 02 05:04:08 PM PDT 24 Aug 02 05:04:13 PM PDT 24 1200292115 ps
T134 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2778823839 Aug 02 05:03:44 PM PDT 24 Aug 02 05:03:46 PM PDT 24 62922002 ps
T541 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3220504563 Aug 02 05:03:49 PM PDT 24 Aug 02 05:03:53 PM PDT 24 423402489 ps
T542 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.949652833 Aug 02 05:03:57 PM PDT 24 Aug 02 05:04:00 PM PDT 24 583977518 ps
T543 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2866874009 Aug 02 05:03:50 PM PDT 24 Aug 02 05:03:52 PM PDT 24 45783955 ps
T544 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2495398075 Aug 02 05:04:07 PM PDT 24 Aug 02 05:04:09 PM PDT 24 299471308 ps
T137 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2739090202 Aug 02 05:04:13 PM PDT 24 Aug 02 05:04:16 PM PDT 24 658695482 ps
T545 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3273960356 Aug 02 05:04:02 PM PDT 24 Aug 02 05:04:06 PM PDT 24 45485596 ps
T546 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3458896309 Aug 02 05:04:11 PM PDT 24 Aug 02 05:04:12 PM PDT 24 69051987 ps
T547 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1221321607 Aug 02 05:03:56 PM PDT 24 Aug 02 05:03:58 PM PDT 24 364972608 ps
T548 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.810580104 Aug 02 05:03:44 PM PDT 24 Aug 02 05:03:46 PM PDT 24 265540826 ps
T549 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2728981491 Aug 02 05:03:55 PM PDT 24 Aug 02 05:03:57 PM PDT 24 38309680 ps
T550 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2002971787 Aug 02 05:03:46 PM PDT 24 Aug 02 05:03:49 PM PDT 24 837696737 ps
T551 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2057720105 Aug 02 05:04:28 PM PDT 24 Aug 02 05:04:29 PM PDT 24 15366602 ps
T552 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2562043105 Aug 02 05:03:59 PM PDT 24 Aug 02 05:03:59 PM PDT 24 113952011 ps
T553 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2955071463 Aug 02 05:04:06 PM PDT 24 Aug 02 05:04:07 PM PDT 24 35909164 ps
T554 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3240952700 Aug 02 05:03:47 PM PDT 24 Aug 02 05:03:48 PM PDT 24 40104678 ps
T110 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2551107904 Aug 02 05:03:58 PM PDT 24 Aug 02 05:03:59 PM PDT 24 110531506 ps
T555 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2004021436 Aug 02 05:03:44 PM PDT 24 Aug 02 05:03:46 PM PDT 24 385044479 ps
T556 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2274399142 Aug 02 05:04:03 PM PDT 24 Aug 02 05:04:05 PM PDT 24 60767680 ps
T557 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2669396550 Aug 02 05:03:53 PM PDT 24 Aug 02 05:03:54 PM PDT 24 101606856 ps
T558 /workspace/coverage/cover_reg_top/19.hmac_intr_test.409877567 Aug 02 05:04:03 PM PDT 24 Aug 02 05:04:03 PM PDT 24 39664015 ps
T559 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1695955573 Aug 02 05:03:44 PM PDT 24 Aug 02 05:03:45 PM PDT 24 43338393 ps
T560 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4049012019 Aug 02 05:03:51 PM PDT 24 Aug 02 05:05:06 PM PDT 24 20573959240 ps
T561 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2948928016 Aug 02 05:04:12 PM PDT 24 Aug 02 05:04:13 PM PDT 24 37152101 ps
T562 /workspace/coverage/cover_reg_top/40.hmac_intr_test.183481701 Aug 02 05:04:09 PM PDT 24 Aug 02 05:04:10 PM PDT 24 54201452 ps
T563 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3230419362 Aug 02 05:03:43 PM PDT 24 Aug 02 05:03:46 PM PDT 24 46658243 ps
T564 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2558680923 Aug 02 05:04:05 PM PDT 24 Aug 02 05:04:05 PM PDT 24 127420082 ps
T565 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1826922450 Aug 02 05:03:56 PM PDT 24 Aug 02 05:03:57 PM PDT 24 13246037 ps
T566 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1202455895 Aug 02 05:03:45 PM PDT 24 Aug 02 05:03:47 PM PDT 24 521041488 ps
T567 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1013641838 Aug 02 05:03:47 PM PDT 24 Aug 02 05:03:49 PM PDT 24 471731586 ps
T568 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1212295238 Aug 02 05:04:12 PM PDT 24 Aug 02 05:04:13 PM PDT 24 35699224 ps
T569 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4289160797 Aug 02 05:03:48 PM PDT 24 Aug 02 05:03:50 PM PDT 24 36920594 ps
T120 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1847355255 Aug 02 05:03:35 PM PDT 24 Aug 02 05:03:47 PM PDT 24 1808912360 ps
T570 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.526141733 Aug 02 05:03:50 PM PDT 24 Aug 02 05:03:51 PM PDT 24 203220336 ps
T571 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1619814522 Aug 02 05:03:55 PM PDT 24 Aug 02 05:03:57 PM PDT 24 97903178 ps
T572 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1440210047 Aug 02 05:03:55 PM PDT 24 Aug 02 05:03:57 PM PDT 24 213763451 ps
T573 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3484967632 Aug 02 05:03:51 PM PDT 24 Aug 02 05:03:52 PM PDT 24 12811336 ps
T574 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.103346751 Aug 02 05:04:15 PM PDT 24 Aug 02 05:04:17 PM PDT 24 249834281 ps
T575 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3640585667 Aug 02 05:04:05 PM PDT 24 Aug 02 05:04:06 PM PDT 24 61221436 ps
T576 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1279755256 Aug 02 05:03:45 PM PDT 24 Aug 02 05:03:51 PM PDT 24 535474946 ps
T577 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3376711409 Aug 02 05:03:51 PM PDT 24 Aug 02 05:03:55 PM PDT 24 289405286 ps
T578 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2165088777 Aug 02 05:04:02 PM PDT 24 Aug 02 05:04:03 PM PDT 24 35617852 ps
T579 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3851297538 Aug 02 05:03:39 PM PDT 24 Aug 02 05:03:42 PM PDT 24 217905544 ps
T580 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1817188801 Aug 02 05:03:58 PM PDT 24 Aug 02 05:03:59 PM PDT 24 37826600 ps
T581 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3553471419 Aug 02 05:04:16 PM PDT 24 Aug 02 05:04:17 PM PDT 24 34994896 ps
T582 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3551192503 Aug 02 05:04:13 PM PDT 24 Aug 02 05:04:14 PM PDT 24 23768902 ps
T583 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1528105244 Aug 02 05:03:45 PM PDT 24 Aug 02 05:03:48 PM PDT 24 47427396 ps
T584 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2766233774 Aug 02 05:04:10 PM PDT 24 Aug 02 05:04:11 PM PDT 24 26777792 ps
T585 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1776180486 Aug 02 05:03:58 PM PDT 24 Aug 02 05:03:58 PM PDT 24 35190735 ps
T586 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1775273195 Aug 02 05:03:57 PM PDT 24 Aug 02 05:03:59 PM PDT 24 52764143 ps
T587 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1510121788 Aug 02 05:04:09 PM PDT 24 Aug 02 05:04:10 PM PDT 24 14246805 ps
T588 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1525160067 Aug 02 05:04:03 PM PDT 24 Aug 02 05:04:06 PM PDT 24 46678174 ps
T589 /workspace/coverage/cover_reg_top/38.hmac_intr_test.65534497 Aug 02 05:04:02 PM PDT 24 Aug 02 05:04:02 PM PDT 24 14423636 ps
T590 /workspace/coverage/cover_reg_top/23.hmac_intr_test.393849419 Aug 02 05:03:58 PM PDT 24 Aug 02 05:03:58 PM PDT 24 15934089 ps
T591 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1008315502 Aug 02 05:03:43 PM PDT 24 Aug 02 05:03:46 PM PDT 24 63335857 ps
T592 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.989287771 Aug 02 05:03:42 PM PDT 24 Aug 02 05:03:44 PM PDT 24 436546704 ps
T593 /workspace/coverage/cover_reg_top/47.hmac_intr_test.410769812 Aug 02 05:04:08 PM PDT 24 Aug 02 05:04:09 PM PDT 24 17210962 ps
T594 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.4058340809 Aug 02 05:04:00 PM PDT 24 Aug 02 05:04:04 PM PDT 24 1328758027 ps
T595 /workspace/coverage/cover_reg_top/0.hmac_intr_test.655694177 Aug 02 05:03:52 PM PDT 24 Aug 02 05:03:53 PM PDT 24 19309255 ps
T596 /workspace/coverage/cover_reg_top/43.hmac_intr_test.487269799 Aug 02 05:04:34 PM PDT 24 Aug 02 05:04:34 PM PDT 24 26419970 ps
T597 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1176289019 Aug 02 05:04:09 PM PDT 24 Aug 02 05:04:09 PM PDT 24 13280460 ps
T598 /workspace/coverage/cover_reg_top/17.hmac_intr_test.231716755 Aug 02 05:04:13 PM PDT 24 Aug 02 05:04:14 PM PDT 24 26356671 ps
T599 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2972909151 Aug 02 05:03:40 PM PDT 24 Aug 02 05:03:40 PM PDT 24 52552235 ps
T600 /workspace/coverage/cover_reg_top/7.hmac_intr_test.157130259 Aug 02 05:04:08 PM PDT 24 Aug 02 05:04:09 PM PDT 24 37197059 ps
T601 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1140198319 Aug 02 05:03:57 PM PDT 24 Aug 02 05:03:57 PM PDT 24 155721456 ps
T602 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3539019032 Aug 02 05:03:59 PM PDT 24 Aug 02 05:04:02 PM PDT 24 608972971 ps
T603 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3378268224 Aug 02 05:03:45 PM PDT 24 Aug 02 05:03:47 PM PDT 24 96466034 ps
T604 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1553982231 Aug 02 05:03:50 PM PDT 24 Aug 02 05:03:55 PM PDT 24 375644620 ps
T605 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1839986363 Aug 02 05:04:10 PM PDT 24 Aug 02 05:04:11 PM PDT 24 179777572 ps
T138 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3523256173 Aug 02 05:04:02 PM PDT 24 Aug 02 05:04:05 PM PDT 24 314338429 ps
T606 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.604670020 Aug 02 05:03:54 PM PDT 24 Aug 02 05:04:02 PM PDT 24 84493196 ps
T607 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3098465169 Aug 02 05:03:50 PM PDT 24 Aug 02 05:03:52 PM PDT 24 47033210 ps
T608 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2219691172 Aug 02 05:03:45 PM PDT 24 Aug 02 05:03:56 PM PDT 24 728517879 ps
T609 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3736215179 Aug 02 05:03:49 PM PDT 24 Aug 02 05:03:51 PM PDT 24 48418547 ps
T610 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.134239652 Aug 02 05:04:15 PM PDT 24 Aug 02 05:04:16 PM PDT 24 151819873 ps
T611 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2345207344 Aug 02 05:04:03 PM PDT 24 Aug 02 05:04:06 PM PDT 24 89151898 ps
T612 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.291068006 Aug 02 05:04:00 PM PDT 24 Aug 02 05:04:01 PM PDT 24 33537213 ps
T139 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2239114118 Aug 02 05:03:50 PM PDT 24 Aug 02 05:03:53 PM PDT 24 310316532 ps
T613 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2822901548 Aug 02 05:03:44 PM PDT 24 Aug 02 05:03:47 PM PDT 24 128631731 ps
T614 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4188963579 Aug 02 05:03:51 PM PDT 24 Aug 02 05:03:52 PM PDT 24 31691274 ps
T615 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3934172021 Aug 02 05:03:59 PM PDT 24 Aug 02 05:03:59 PM PDT 24 14538242 ps
T616 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2700538234 Aug 02 05:03:57 PM PDT 24 Aug 02 05:03:58 PM PDT 24 39084300 ps
T617 /workspace/coverage/cover_reg_top/2.hmac_intr_test.499884705 Aug 02 05:03:57 PM PDT 24 Aug 02 05:03:58 PM PDT 24 61493286 ps
T618 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2235008462 Aug 02 05:03:42 PM PDT 24 Aug 02 05:03:43 PM PDT 24 14461930 ps
T619 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1445599848 Aug 02 05:03:48 PM PDT 24 Aug 02 05:03:57 PM PDT 24 1073522139 ps
T620 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2193937760 Aug 02 05:04:08 PM PDT 24 Aug 02 05:20:07 PM PDT 24 98314343968 ps
T621 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3740363059 Aug 02 05:04:07 PM PDT 24 Aug 02 05:04:12 PM PDT 24 77288105 ps
T622 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2930116508 Aug 02 05:03:46 PM PDT 24 Aug 02 05:03:51 PM PDT 24 274111085 ps
T135 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2492964082 Aug 02 05:03:59 PM PDT 24 Aug 02 05:04:03 PM PDT 24 254971360 ps
T623 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3024823937 Aug 02 05:03:50 PM PDT 24 Aug 02 05:03:51 PM PDT 24 34278678 ps
T624 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3959140797 Aug 02 05:03:40 PM PDT 24 Aug 02 05:03:41 PM PDT 24 18256485 ps
T625 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1160298420 Aug 02 05:03:51 PM PDT 24 Aug 02 05:03:53 PM PDT 24 82416973 ps
T626 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.533136398 Aug 02 05:04:00 PM PDT 24 Aug 02 05:04:04 PM PDT 24 1208452211 ps
T627 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1470221739 Aug 02 05:04:08 PM PDT 24 Aug 02 05:04:09 PM PDT 24 130587225 ps
T628 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.969038748 Aug 02 05:03:45 PM PDT 24 Aug 02 05:03:49 PM PDT 24 1448579079 ps
T629 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3811240151 Aug 02 05:04:11 PM PDT 24 Aug 02 05:04:13 PM PDT 24 175680704 ps
T630 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2580786716 Aug 02 05:04:02 PM PDT 24 Aug 02 05:04:04 PM PDT 24 48415561 ps
T631 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1516758384 Aug 02 05:04:04 PM PDT 24 Aug 02 05:04:05 PM PDT 24 83881287 ps
T632 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1707288257 Aug 02 05:03:49 PM PDT 24 Aug 02 05:03:49 PM PDT 24 13481302 ps
T633 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2321018766 Aug 02 05:04:02 PM PDT 24 Aug 02 05:04:08 PM PDT 24 362729358 ps
T634 /workspace/coverage/cover_reg_top/8.hmac_intr_test.4111099966 Aug 02 05:03:57 PM PDT 24 Aug 02 05:03:58 PM PDT 24 82455667 ps
T635 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2847152737 Aug 02 05:04:05 PM PDT 24 Aug 02 05:04:08 PM PDT 24 176831797 ps
T636 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1064863662 Aug 02 05:04:08 PM PDT 24 Aug 02 05:04:10 PM PDT 24 97681032 ps
T637 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3236502727 Aug 02 05:03:53 PM PDT 24 Aug 02 05:03:56 PM PDT 24 191524091 ps
T638 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4095055441 Aug 02 05:03:41 PM PDT 24 Aug 02 05:03:42 PM PDT 24 70654680 ps
T639 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2258123946 Aug 02 05:03:59 PM PDT 24 Aug 02 05:04:02 PM PDT 24 1218875090 ps
T640 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1536954680 Aug 02 05:03:46 PM PDT 24 Aug 02 05:03:48 PM PDT 24 40416252 ps
T641 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2575354750 Aug 02 05:03:50 PM PDT 24 Aug 02 05:03:52 PM PDT 24 11482884 ps
T642 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1308656979 Aug 02 05:04:05 PM PDT 24 Aug 02 05:04:05 PM PDT 24 30063884 ps
T643 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1363027398 Aug 02 05:04:12 PM PDT 24 Aug 02 05:04:13 PM PDT 24 26609462 ps
T644 /workspace/coverage/cover_reg_top/29.hmac_intr_test.806963638 Aug 02 05:03:57 PM PDT 24 Aug 02 05:03:58 PM PDT 24 137668021 ps
T645 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.599845653 Aug 02 05:04:05 PM PDT 24 Aug 02 05:04:07 PM PDT 24 64745006 ps
T646 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1761254794 Aug 02 05:03:57 PM PDT 24 Aug 02 05:04:00 PM PDT 24 930042699 ps
T647 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3765852393 Aug 02 05:04:05 PM PDT 24 Aug 02 05:04:07 PM PDT 24 61442815 ps
T648 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1755550375 Aug 02 05:03:54 PM PDT 24 Aug 02 05:03:56 PM PDT 24 46136682 ps
T649 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1393562177 Aug 02 05:04:14 PM PDT 24 Aug 02 05:04:15 PM PDT 24 65020889 ps
T650 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1065217210 Aug 02 05:04:01 PM PDT 24 Aug 02 05:04:02 PM PDT 24 58864975 ps
T651 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1709028866 Aug 02 05:04:06 PM PDT 24 Aug 02 05:04:07 PM PDT 24 184590257 ps
T136 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2149895325 Aug 02 05:03:58 PM PDT 24 Aug 02 05:04:01 PM PDT 24 174318458 ps
T652 /workspace/coverage/cover_reg_top/21.hmac_intr_test.4079775764 Aug 02 05:03:58 PM PDT 24 Aug 02 05:03:59 PM PDT 24 14316166 ps
T653 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1450021681 Aug 02 05:03:43 PM PDT 24 Aug 02 05:03:45 PM PDT 24 24566499 ps
T654 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2832754840 Aug 02 05:04:10 PM PDT 24 Aug 02 05:04:11 PM PDT 24 43073212 ps
T655 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3746887232 Aug 02 05:04:09 PM PDT 24 Aug 02 05:04:10 PM PDT 24 19444859 ps
T656 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3636369746 Aug 02 05:03:45 PM PDT 24 Aug 02 05:03:48 PM PDT 24 299338258 ps
T657 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2938524484 Aug 02 05:04:04 PM PDT 24 Aug 02 05:04:07 PM PDT 24 160702102 ps
T658 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2806064580 Aug 02 05:04:02 PM PDT 24 Aug 02 05:04:04 PM PDT 24 89085772 ps

Test location /workspace/coverage/default/29.hmac_burst_wr.3224679805
Short name T19
Test name
Test status
Simulation time 30811418788 ps
CPU time 61.08 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:05:52 PM PDT 24
Peak memory 199984 kb
Host smart-633597e1-e282-4627-a971-b38430b2f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224679805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3224679805
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1026521474
Short name T8
Test name
Test status
Simulation time 211626581226 ps
CPU time 10698.1 seconds
Started Aug 02 05:04:30 PM PDT 24
Finished Aug 02 08:02:50 PM PDT 24
Peak memory 929972 kb
Host smart-08068712-abda-4b06-af2f-d4086a9063f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026521474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1026521474
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2723836330
Short name T4
Test name
Test status
Simulation time 200672218609 ps
CPU time 594.64 seconds
Started Aug 02 05:04:59 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 200008 kb
Host smart-9f978eeb-8d86-41ce-b2b8-ee76158131e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723836330 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2723836330
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2724852886
Short name T9
Test name
Test status
Simulation time 38369661547 ps
CPU time 967.58 seconds
Started Aug 02 05:04:21 PM PDT 24
Finished Aug 02 05:20:29 PM PDT 24
Peak memory 689492 kb
Host smart-26132135-a6d6-4bc5-964f-95f616afac46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724852886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2724852886
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1632784812
Short name T133
Test name
Test status
Simulation time 1200292115 ps
CPU time 4.62 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:04:13 PM PDT 24
Peak memory 200088 kb
Host smart-b02bf5ab-2c40-4a6c-a026-23c9060c2902
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632784812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1632784812
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3140420414
Short name T57
Test name
Test status
Simulation time 860539407 ps
CPU time 0.91 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:04:26 PM PDT 24
Peak memory 218476 kb
Host smart-66ae6b12-31c7-48e2-b27a-bdf05622e796
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140420414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3140420414
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1601392689
Short name T100
Test name
Test status
Simulation time 65549120 ps
CPU time 0.88 seconds
Started Aug 02 05:04:00 PM PDT 24
Finished Aug 02 05:04:01 PM PDT 24
Peak memory 199296 kb
Host smart-0a984d8f-6d47-46b9-9ce9-504e043350b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601392689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1601392689
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1114889705
Short name T21
Test name
Test status
Simulation time 1115657849 ps
CPU time 65.34 seconds
Started Aug 02 05:04:12 PM PDT 24
Finished Aug 02 05:05:17 PM PDT 24
Peak memory 199888 kb
Host smart-874f79c0-1ede-4d2f-912d-7cb26d032687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114889705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1114889705
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3465735291
Short name T53
Test name
Test status
Simulation time 70865662 ps
CPU time 0.59 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:04:34 PM PDT 24
Peak memory 195860 kb
Host smart-4d1266bb-ee33-4aab-a337-a3722099d656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465735291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3465735291
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.705670136
Short name T67
Test name
Test status
Simulation time 556592524 ps
CPU time 3.24 seconds
Started Aug 02 05:03:55 PM PDT 24
Finished Aug 02 05:03:58 PM PDT 24
Peak memory 200132 kb
Host smart-9bccf7b6-fa07-4fe1-b3bf-a9a7cc160167
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705670136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.705670136
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2054846248
Short name T483
Test name
Test status
Simulation time 32618115562 ps
CPU time 1342.91 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:26:48 PM PDT 24
Peak memory 724160 kb
Host smart-437361a2-3012-4072-9a31-52e17bc4a9e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054846248 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2054846248
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2000336087
Short name T12
Test name
Test status
Simulation time 650896766 ps
CPU time 38.24 seconds
Started Aug 02 05:04:42 PM PDT 24
Finished Aug 02 05:05:20 PM PDT 24
Peak memory 199876 kb
Host smart-1cf9ff49-f2ea-4c0d-b282-27822693fbda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000336087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2000336087
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2239114118
Short name T139
Test name
Test status
Simulation time 310316532 ps
CPU time 2.9 seconds
Started Aug 02 05:03:50 PM PDT 24
Finished Aug 02 05:03:53 PM PDT 24
Peak memory 200136 kb
Host smart-ab865b72-42e8-4b7d-847b-547662e55fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239114118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2239114118
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2149895325
Short name T136
Test name
Test status
Simulation time 174318458 ps
CPU time 3.08 seconds
Started Aug 02 05:03:58 PM PDT 24
Finished Aug 02 05:04:01 PM PDT 24
Peak memory 200104 kb
Host smart-13246cc4-fd7d-4845-8b8a-e3a60058bf0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149895325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2149895325
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1709619857
Short name T432
Test name
Test status
Simulation time 75005625064 ps
CPU time 611.91 seconds
Started Aug 02 05:04:23 PM PDT 24
Finished Aug 02 05:14:35 PM PDT 24
Peak memory 199992 kb
Host smart-7437399e-f777-4f02-928f-9dbc9587ec28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1709619857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1709619857
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.37092363
Short name T140
Test name
Test status
Simulation time 33892076702 ps
CPU time 484.81 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:12:19 PM PDT 24
Peak memory 666448 kb
Host smart-cb611144-8aa5-4cf2-8e15-843999ae7cb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37092363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.37092363
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.126490293
Short name T73
Test name
Test status
Simulation time 58314840138 ps
CPU time 1519.82 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:29:39 PM PDT 24
Peak memory 726916 kb
Host smart-3dca8448-dbb3-4a4e-a2bd-c9c43fbc389d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126490293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.126490293
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1008315502
Short name T591
Test name
Test status
Simulation time 63335857 ps
CPU time 3.19 seconds
Started Aug 02 05:03:43 PM PDT 24
Finished Aug 02 05:03:46 PM PDT 24
Peak memory 200056 kb
Host smart-5022afb9-300c-4c32-a104-4f97f6f84d6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008315502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1008315502
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2219691172
Short name T608
Test name
Test status
Simulation time 728517879 ps
CPU time 10.57 seconds
Started Aug 02 05:03:45 PM PDT 24
Finished Aug 02 05:03:56 PM PDT 24
Peak memory 200052 kb
Host smart-5e8fbe8c-1d5a-4a6f-90c0-2e78ec8b92b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219691172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2219691172
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4095055441
Short name T638
Test name
Test status
Simulation time 70654680 ps
CPU time 0.73 seconds
Started Aug 02 05:03:41 PM PDT 24
Finished Aug 02 05:03:42 PM PDT 24
Peak memory 198012 kb
Host smart-486f5fbb-765f-442b-b74b-d108d9a1586b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095055441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4095055441
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2004021436
Short name T555
Test name
Test status
Simulation time 385044479 ps
CPU time 2.18 seconds
Started Aug 02 05:03:44 PM PDT 24
Finished Aug 02 05:03:46 PM PDT 24
Peak memory 200176 kb
Host smart-984bdfc3-aa0c-41c9-a3e4-4f26cbdde427
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004021436 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2004021436
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3991729661
Short name T525
Test name
Test status
Simulation time 87401059 ps
CPU time 0.83 seconds
Started Aug 02 05:03:50 PM PDT 24
Finished Aug 02 05:03:51 PM PDT 24
Peak memory 199396 kb
Host smart-1b823523-5400-498e-98e4-37c78cd12464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991729661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3991729661
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.655694177
Short name T595
Test name
Test status
Simulation time 19309255 ps
CPU time 0.56 seconds
Started Aug 02 05:03:52 PM PDT 24
Finished Aug 02 05:03:53 PM PDT 24
Peak memory 195000 kb
Host smart-b87d1428-cec6-4ae8-8faa-0d124373625e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655694177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.655694177
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3539019032
Short name T602
Test name
Test status
Simulation time 608972971 ps
CPU time 2.25 seconds
Started Aug 02 05:03:59 PM PDT 24
Finished Aug 02 05:04:02 PM PDT 24
Peak memory 200072 kb
Host smart-115ae21e-f0f2-4700-993b-575cda8b515b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539019032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3539019032
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.989041091
Short name T540
Test name
Test status
Simulation time 79213854 ps
CPU time 4.18 seconds
Started Aug 02 05:03:40 PM PDT 24
Finished Aug 02 05:03:44 PM PDT 24
Peak memory 200092 kb
Host smart-967516fc-1fda-4ee0-8b3b-97b1a1de9a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989041091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.989041091
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2345207344
Short name T611
Test name
Test status
Simulation time 89151898 ps
CPU time 2.79 seconds
Started Aug 02 05:04:03 PM PDT 24
Finished Aug 02 05:04:06 PM PDT 24
Peak memory 200140 kb
Host smart-a94d4476-6949-4f4c-85d7-7e1aa979fc11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345207344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2345207344
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.533136398
Short name T626
Test name
Test status
Simulation time 1208452211 ps
CPU time 3.4 seconds
Started Aug 02 05:04:00 PM PDT 24
Finished Aug 02 05:04:04 PM PDT 24
Peak memory 200136 kb
Host smart-218e2ac4-7666-4f37-8732-2d1f82a92a5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533136398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.533136398
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1553982231
Short name T604
Test name
Test status
Simulation time 375644620 ps
CPU time 5.36 seconds
Started Aug 02 05:03:50 PM PDT 24
Finished Aug 02 05:03:55 PM PDT 24
Peak memory 200152 kb
Host smart-94366215-498d-49e6-a763-9f1f25a41900
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553982231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1553982231
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2972909151
Short name T599
Test name
Test status
Simulation time 52552235 ps
CPU time 0.71 seconds
Started Aug 02 05:03:40 PM PDT 24
Finished Aug 02 05:03:40 PM PDT 24
Peak memory 198476 kb
Host smart-3c5d5eaa-57e1-4ce8-a3eb-c9ffae8cf102
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972909151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2972909151
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1536954680
Short name T640
Test name
Test status
Simulation time 40416252 ps
CPU time 1.25 seconds
Started Aug 02 05:03:46 PM PDT 24
Finished Aug 02 05:03:48 PM PDT 24
Peak memory 199984 kb
Host smart-2ecb6cee-75eb-4125-a897-d75dac8b84b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536954680 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1536954680
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2235008462
Short name T618
Test name
Test status
Simulation time 14461930 ps
CPU time 0.71 seconds
Started Aug 02 05:03:42 PM PDT 24
Finished Aug 02 05:03:43 PM PDT 24
Peak memory 198140 kb
Host smart-e1efb025-a0af-477f-8d5d-21356daa5213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235008462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2235008462
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1695955573
Short name T559
Test name
Test status
Simulation time 43338393 ps
CPU time 0.61 seconds
Started Aug 02 05:03:44 PM PDT 24
Finished Aug 02 05:03:45 PM PDT 24
Peak memory 195076 kb
Host smart-728ff99c-825f-471a-b42b-f1560034909b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695955573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1695955573
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2806064580
Short name T658
Test name
Test status
Simulation time 89085772 ps
CPU time 2.19 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:04:04 PM PDT 24
Peak memory 200168 kb
Host smart-34f65e31-36b0-4a94-83fe-2370a2d8f688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806064580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2806064580
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3220504563
Short name T541
Test name
Test status
Simulation time 423402489 ps
CPU time 3.86 seconds
Started Aug 02 05:03:49 PM PDT 24
Finished Aug 02 05:03:53 PM PDT 24
Peak memory 200128 kb
Host smart-c033f064-39f8-40f1-a8c2-8050a0637617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220504563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3220504563
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2193937760
Short name T620
Test name
Test status
Simulation time 98314343968 ps
CPU time 958.93 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:20:07 PM PDT 24
Peak memory 216644 kb
Host smart-419e2412-604d-4ec2-91cf-e21dca9da50e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193937760 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2193937760
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2955071463
Short name T553
Test name
Test status
Simulation time 35909164 ps
CPU time 0.58 seconds
Started Aug 02 05:04:06 PM PDT 24
Finished Aug 02 05:04:07 PM PDT 24
Peak memory 195072 kb
Host smart-d1eae8f8-1b17-431b-9e24-2b2df0081e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955071463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2955071463
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2580786716
Short name T630
Test name
Test status
Simulation time 48415561 ps
CPU time 2.09 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:04:04 PM PDT 24
Peak memory 200148 kb
Host smart-fef422b4-ae3a-4f0a-aae5-c6e997322070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580786716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2580786716
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.969038748
Short name T628
Test name
Test status
Simulation time 1448579079 ps
CPU time 3.11 seconds
Started Aug 02 05:03:45 PM PDT 24
Finished Aug 02 05:03:49 PM PDT 24
Peak memory 200140 kb
Host smart-7af1278a-e85a-450f-b813-a4217c9b1f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969038748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.969038748
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1504718789
Short name T68
Test name
Test status
Simulation time 368994793 ps
CPU time 1.95 seconds
Started Aug 02 05:03:59 PM PDT 24
Finished Aug 02 05:04:01 PM PDT 24
Peak memory 200212 kb
Host smart-be1e41b2-9fe9-43c8-b96b-ca87c9dde7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504718789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1504718789
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.599845653
Short name T645
Test name
Test status
Simulation time 64745006 ps
CPU time 1.83 seconds
Started Aug 02 05:04:05 PM PDT 24
Finished Aug 02 05:04:07 PM PDT 24
Peak memory 199836 kb
Host smart-a35e49ba-27bd-4577-9a88-ac887eb9a9dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599845653 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.599845653
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2948928016
Short name T561
Test name
Test status
Simulation time 37152101 ps
CPU time 0.72 seconds
Started Aug 02 05:04:12 PM PDT 24
Finished Aug 02 05:04:13 PM PDT 24
Peak memory 198080 kb
Host smart-9275feaa-234c-424f-823b-b3951b8d5080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948928016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2948928016
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3959140797
Short name T624
Test name
Test status
Simulation time 18256485 ps
CPU time 0.6 seconds
Started Aug 02 05:03:40 PM PDT 24
Finished Aug 02 05:03:41 PM PDT 24
Peak memory 195068 kb
Host smart-90b37515-0b43-4f99-ad30-5b5389923ae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959140797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3959140797
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1155163514
Short name T122
Test name
Test status
Simulation time 186642125 ps
CPU time 1.22 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:04:03 PM PDT 24
Peak memory 200120 kb
Host smart-d517823e-1732-44ac-adba-05c8f1a4057d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155163514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1155163514
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2274399142
Short name T556
Test name
Test status
Simulation time 60767680 ps
CPU time 1.58 seconds
Started Aug 02 05:04:03 PM PDT 24
Finished Aug 02 05:04:05 PM PDT 24
Peak memory 200068 kb
Host smart-385b1dcc-0185-49ad-a2b7-ce5ffb84cc46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274399142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2274399142
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2930116508
Short name T622
Test name
Test status
Simulation time 274111085 ps
CPU time 4.4 seconds
Started Aug 02 05:03:46 PM PDT 24
Finished Aug 02 05:03:51 PM PDT 24
Peak memory 200140 kb
Host smart-ad5f2a28-1f22-43f6-b7ed-8fa6c7fa90cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930116508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2930116508
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3236502727
Short name T637
Test name
Test status
Simulation time 191524091 ps
CPU time 2.86 seconds
Started Aug 02 05:03:53 PM PDT 24
Finished Aug 02 05:03:56 PM PDT 24
Peak memory 208308 kb
Host smart-41f390d6-43ce-433b-bd7f-cdc277bdd4bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236502727 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3236502727
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.16109041
Short name T107
Test name
Test status
Simulation time 199101970 ps
CPU time 0.91 seconds
Started Aug 02 05:03:42 PM PDT 24
Finished Aug 02 05:03:43 PM PDT 24
Peak memory 199620 kb
Host smart-c6cfab1e-1578-4d61-adf7-00b8d935ce0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16109041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.16109041
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1776180486
Short name T585
Test name
Test status
Simulation time 35190735 ps
CPU time 0.59 seconds
Started Aug 02 05:03:58 PM PDT 24
Finished Aug 02 05:03:58 PM PDT 24
Peak memory 195000 kb
Host smart-761e1cc4-f62a-4a65-b597-662fc70994c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776180486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1776180486
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4289160797
Short name T569
Test name
Test status
Simulation time 36920594 ps
CPU time 1.58 seconds
Started Aug 02 05:03:48 PM PDT 24
Finished Aug 02 05:03:50 PM PDT 24
Peak memory 200140 kb
Host smart-856f51b3-1ad1-4284-9274-f5f6fad0d959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289160797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.4289160797
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3740363059
Short name T621
Test name
Test status
Simulation time 77288105 ps
CPU time 4.04 seconds
Started Aug 02 05:04:07 PM PDT 24
Finished Aug 02 05:04:12 PM PDT 24
Peak memory 200172 kb
Host smart-fdd551b0-0f96-4025-9834-4f06a5f26ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740363059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3740363059
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1525160067
Short name T588
Test name
Test status
Simulation time 46678174 ps
CPU time 3.07 seconds
Started Aug 02 05:04:03 PM PDT 24
Finished Aug 02 05:04:06 PM PDT 24
Peak memory 208400 kb
Host smart-21a8c08f-72c4-403c-b7d8-53d7648cddd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525160067 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1525160067
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1065217210
Short name T650
Test name
Test status
Simulation time 58864975 ps
CPU time 0.69 seconds
Started Aug 02 05:04:01 PM PDT 24
Finished Aug 02 05:04:02 PM PDT 24
Peak memory 197968 kb
Host smart-aee0dcb9-9be7-441c-85e3-ba0f992c9a59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065217210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1065217210
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3380361676
Short name T529
Test name
Test status
Simulation time 70097721 ps
CPU time 0.61 seconds
Started Aug 02 05:04:07 PM PDT 24
Finished Aug 02 05:04:08 PM PDT 24
Peak memory 195120 kb
Host smart-f1c2d6d0-c8c6-4866-820c-4f8a6150ffd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380361676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3380361676
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2495398075
Short name T544
Test name
Test status
Simulation time 299471308 ps
CPU time 1.79 seconds
Started Aug 02 05:04:07 PM PDT 24
Finished Aug 02 05:04:09 PM PDT 24
Peak memory 199872 kb
Host smart-8a4ea4ed-33ac-431e-b60c-98e5c89e32a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495398075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2495398075
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.4058340809
Short name T594
Test name
Test status
Simulation time 1328758027 ps
CPU time 3.89 seconds
Started Aug 02 05:04:00 PM PDT 24
Finished Aug 02 05:04:04 PM PDT 24
Peak memory 200176 kb
Host smart-f3c2239e-03f8-4f72-8b14-0a383a7d0a5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058340809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.4058340809
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3523256173
Short name T138
Test name
Test status
Simulation time 314338429 ps
CPU time 2.99 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:04:05 PM PDT 24
Peak memory 200184 kb
Host smart-0cce158f-f9ed-44ae-897a-a8ddf605d493
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523256173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3523256173
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2728981491
Short name T549
Test name
Test status
Simulation time 38309680 ps
CPU time 2.3 seconds
Started Aug 02 05:03:55 PM PDT 24
Finished Aug 02 05:03:57 PM PDT 24
Peak memory 200060 kb
Host smart-104bb213-8f88-4602-8304-e43b25150e8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728981491 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2728981491
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4188963579
Short name T614
Test name
Test status
Simulation time 31691274 ps
CPU time 0.7 seconds
Started Aug 02 05:03:51 PM PDT 24
Finished Aug 02 05:03:52 PM PDT 24
Peak memory 197744 kb
Host smart-d34b25b3-587d-48ae-b0e4-b3faeb3f246e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188963579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4188963579
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1826922450
Short name T565
Test name
Test status
Simulation time 13246037 ps
CPU time 0.56 seconds
Started Aug 02 05:03:56 PM PDT 24
Finished Aug 02 05:03:57 PM PDT 24
Peak memory 195024 kb
Host smart-acc22ea1-3779-45e1-bb83-af441437b958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826922450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1826922450
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1755550375
Short name T648
Test name
Test status
Simulation time 46136682 ps
CPU time 2.15 seconds
Started Aug 02 05:03:54 PM PDT 24
Finished Aug 02 05:03:56 PM PDT 24
Peak memory 200168 kb
Host smart-e58a0961-6bef-4627-9574-52ba5acaba06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755550375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1755550375
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3458896309
Short name T546
Test name
Test status
Simulation time 69051987 ps
CPU time 1.62 seconds
Started Aug 02 05:04:11 PM PDT 24
Finished Aug 02 05:04:12 PM PDT 24
Peak memory 200052 kb
Host smart-5826c34d-ba58-47a2-a211-29db67ed53b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458896309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3458896309
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.850838084
Short name T69
Test name
Test status
Simulation time 109339197 ps
CPU time 1.9 seconds
Started Aug 02 05:03:58 PM PDT 24
Finished Aug 02 05:04:00 PM PDT 24
Peak memory 200084 kb
Host smart-53fc29b2-4fa5-455c-ac64-4aed7a36daf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850838084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.850838084
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1575807572
Short name T539
Test name
Test status
Simulation time 112635290994 ps
CPU time 428.17 seconds
Started Aug 02 05:04:10 PM PDT 24
Finished Aug 02 05:11:18 PM PDT 24
Peak memory 216676 kb
Host smart-cf44af80-0c76-4481-b77f-dcf44c0ae2bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575807572 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1575807572
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.291068006
Short name T612
Test name
Test status
Simulation time 33537213 ps
CPU time 0.67 seconds
Started Aug 02 05:04:00 PM PDT 24
Finished Aug 02 05:04:01 PM PDT 24
Peak memory 197976 kb
Host smart-0257fe8e-1fcf-4112-be5d-0a0e2f994e55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291068006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.291068006
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1212295238
Short name T568
Test name
Test status
Simulation time 35699224 ps
CPU time 0.6 seconds
Started Aug 02 05:04:12 PM PDT 24
Finished Aug 02 05:04:13 PM PDT 24
Peak memory 194996 kb
Host smart-2125ba7f-4cc9-4240-a578-3eeb116eb9c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212295238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1212295238
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1221321607
Short name T547
Test name
Test status
Simulation time 364972608 ps
CPU time 1.58 seconds
Started Aug 02 05:03:56 PM PDT 24
Finished Aug 02 05:03:58 PM PDT 24
Peak memory 200156 kb
Host smart-fa59db93-76b8-45b4-a6ab-e93b41f1ac1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221321607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1221321607
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1539226923
Short name T527
Test name
Test status
Simulation time 866031514 ps
CPU time 4.04 seconds
Started Aug 02 05:04:16 PM PDT 24
Finished Aug 02 05:04:20 PM PDT 24
Peak memory 200240 kb
Host smart-0b36298d-25b3-473c-99ff-1e575c3d5a80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539226923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1539226923
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.604670020
Short name T606
Test name
Test status
Simulation time 84493196 ps
CPU time 2.17 seconds
Started Aug 02 05:03:54 PM PDT 24
Finished Aug 02 05:04:02 PM PDT 24
Peak memory 200084 kb
Host smart-8e39a4fa-77ec-4a28-8687-a859d905bd63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604670020 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.604670020
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2551107904
Short name T110
Test name
Test status
Simulation time 110531506 ps
CPU time 0.94 seconds
Started Aug 02 05:03:58 PM PDT 24
Finished Aug 02 05:03:59 PM PDT 24
Peak memory 199876 kb
Host smart-4c807806-0262-4b87-bc42-8e7e9a31cf11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551107904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2551107904
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1140198319
Short name T601
Test name
Test status
Simulation time 155721456 ps
CPU time 0.64 seconds
Started Aug 02 05:03:57 PM PDT 24
Finished Aug 02 05:03:57 PM PDT 24
Peak memory 194984 kb
Host smart-fa51e434-f768-4fb6-9343-262cf2841ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140198319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1140198319
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3128862855
Short name T125
Test name
Test status
Simulation time 84466770 ps
CPU time 1.74 seconds
Started Aug 02 05:03:53 PM PDT 24
Finished Aug 02 05:03:55 PM PDT 24
Peak memory 200064 kb
Host smart-87375f1d-5373-4967-a5e5-8c7a0a3296dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128862855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3128862855
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.520278055
Short name T524
Test name
Test status
Simulation time 184665598 ps
CPU time 2.78 seconds
Started Aug 02 05:03:50 PM PDT 24
Finished Aug 02 05:03:54 PM PDT 24
Peak memory 200120 kb
Host smart-fdb662a4-5e2a-42d9-8f50-46bacfdd8ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520278055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.520278055
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1761254794
Short name T646
Test name
Test status
Simulation time 930042699 ps
CPU time 3.09 seconds
Started Aug 02 05:03:57 PM PDT 24
Finished Aug 02 05:04:00 PM PDT 24
Peak memory 200080 kb
Host smart-d527df37-cbda-40dc-bfbd-dac669fc79e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761254794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1761254794
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.103346751
Short name T574
Test name
Test status
Simulation time 249834281 ps
CPU time 1.98 seconds
Started Aug 02 05:04:15 PM PDT 24
Finished Aug 02 05:04:17 PM PDT 24
Peak memory 200200 kb
Host smart-ea7092b3-b240-4200-8e84-d0ebf3ef5c3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103346751 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.103346751
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2933166285
Short name T103
Test name
Test status
Simulation time 17149245 ps
CPU time 0.92 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:04:03 PM PDT 24
Peak memory 199996 kb
Host smart-20fd2f66-9421-4dfd-a950-a1b275dcdddb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933166285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2933166285
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.231716755
Short name T598
Test name
Test status
Simulation time 26356671 ps
CPU time 0.59 seconds
Started Aug 02 05:04:13 PM PDT 24
Finished Aug 02 05:04:14 PM PDT 24
Peak memory 194984 kb
Host smart-0a18c31d-e052-46fd-963b-20db52d2bff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231716755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.231716755
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1064863662
Short name T636
Test name
Test status
Simulation time 97681032 ps
CPU time 1.14 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:04:10 PM PDT 24
Peak memory 200048 kb
Host smart-ee90270a-4912-42a2-a31a-7e409c2347be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064863662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1064863662
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.949652833
Short name T542
Test name
Test status
Simulation time 583977518 ps
CPU time 2.87 seconds
Started Aug 02 05:03:57 PM PDT 24
Finished Aug 02 05:04:00 PM PDT 24
Peak memory 200040 kb
Host smart-2e9cf36f-ac1a-456f-8678-d65d79afc484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949652833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.949652833
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2492964082
Short name T135
Test name
Test status
Simulation time 254971360 ps
CPU time 4.36 seconds
Started Aug 02 05:03:59 PM PDT 24
Finished Aug 02 05:04:03 PM PDT 24
Peak memory 200096 kb
Host smart-03220ce2-87a1-43da-9144-508d3943d87a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492964082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2492964082
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.134239652
Short name T610
Test name
Test status
Simulation time 151819873 ps
CPU time 1.21 seconds
Started Aug 02 05:04:15 PM PDT 24
Finished Aug 02 05:04:16 PM PDT 24
Peak memory 200020 kb
Host smart-c42e18a1-c665-4e28-a011-93a8524b5ce6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134239652 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.134239652
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1919877345
Short name T102
Test name
Test status
Simulation time 76870535 ps
CPU time 0.9 seconds
Started Aug 02 05:04:04 PM PDT 24
Finished Aug 02 05:04:05 PM PDT 24
Peak memory 199992 kb
Host smart-6f4bbc3f-6d8b-4416-8527-052198b07291
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919877345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1919877345
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2558680923
Short name T564
Test name
Test status
Simulation time 127420082 ps
CPU time 0.6 seconds
Started Aug 02 05:04:05 PM PDT 24
Finished Aug 02 05:04:05 PM PDT 24
Peak memory 195020 kb
Host smart-f65cca5f-b1f3-443a-8054-0fc1d8b1963e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558680923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2558680923
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3286499805
Short name T123
Test name
Test status
Simulation time 100603359 ps
CPU time 1.7 seconds
Started Aug 02 05:04:05 PM PDT 24
Finished Aug 02 05:04:07 PM PDT 24
Peak memory 200016 kb
Host smart-95f79bc0-eadb-402b-a0b2-fd2fd1a6c4af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286499805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3286499805
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2258123946
Short name T639
Test name
Test status
Simulation time 1218875090 ps
CPU time 3.39 seconds
Started Aug 02 05:03:59 PM PDT 24
Finished Aug 02 05:04:02 PM PDT 24
Peak memory 200068 kb
Host smart-43d021a4-b083-48bb-953c-0d531031fb92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258123946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2258123946
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2847152737
Short name T635
Test name
Test status
Simulation time 176831797 ps
CPU time 3.11 seconds
Started Aug 02 05:04:05 PM PDT 24
Finished Aug 02 05:04:08 PM PDT 24
Peak memory 200148 kb
Host smart-b44bc510-3cbc-4368-bea2-ad25089793b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847152737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2847152737
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3273960356
Short name T545
Test name
Test status
Simulation time 45485596 ps
CPU time 2.91 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:04:06 PM PDT 24
Peak memory 215624 kb
Host smart-df2249b5-e6e6-4da4-aa09-b064aa37f2a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273960356 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3273960356
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1679471547
Short name T108
Test name
Test status
Simulation time 14975775 ps
CPU time 0.81 seconds
Started Aug 02 05:04:05 PM PDT 24
Finished Aug 02 05:04:06 PM PDT 24
Peak memory 199024 kb
Host smart-1efd9e75-44f6-41a5-b29b-74bc372e33eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679471547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1679471547
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.409877567
Short name T558
Test name
Test status
Simulation time 39664015 ps
CPU time 0.63 seconds
Started Aug 02 05:04:03 PM PDT 24
Finished Aug 02 05:04:03 PM PDT 24
Peak memory 195008 kb
Host smart-66202a03-6b7d-4982-bfb6-43fd53d57826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409877567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.409877567
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3765852393
Short name T647
Test name
Test status
Simulation time 61442815 ps
CPU time 2.27 seconds
Started Aug 02 05:04:05 PM PDT 24
Finished Aug 02 05:04:07 PM PDT 24
Peak memory 199948 kb
Host smart-7c51fbae-c843-491c-9f20-95695cc2d12c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765852393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3765852393
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2280988363
Short name T534
Test name
Test status
Simulation time 200255967 ps
CPU time 3.46 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:04:05 PM PDT 24
Peak memory 200068 kb
Host smart-af9860dc-dde3-453b-afcd-ad68ce844fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280988363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2280988363
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2739090202
Short name T137
Test name
Test status
Simulation time 658695482 ps
CPU time 2.83 seconds
Started Aug 02 05:04:13 PM PDT 24
Finished Aug 02 05:04:16 PM PDT 24
Peak memory 200124 kb
Host smart-e9fe86df-6b2c-4049-aeb7-79b28685bc6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739090202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2739090202
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2321018766
Short name T633
Test name
Test status
Simulation time 362729358 ps
CPU time 6 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:04:08 PM PDT 24
Peak memory 200120 kb
Host smart-046201c8-910b-42d9-8afb-5cfac0cd465b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321018766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2321018766
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3635124702
Short name T109
Test name
Test status
Simulation time 308444809 ps
CPU time 13.64 seconds
Started Aug 02 05:03:39 PM PDT 24
Finished Aug 02 05:03:53 PM PDT 24
Peak memory 200096 kb
Host smart-034ac2ce-9da1-47bc-b996-5b4595e7164a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635124702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3635124702
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3024823937
Short name T623
Test name
Test status
Simulation time 34278678 ps
CPU time 0.83 seconds
Started Aug 02 05:03:50 PM PDT 24
Finished Aug 02 05:03:51 PM PDT 24
Peak memory 199704 kb
Host smart-81d056b2-8977-4753-b952-2083e9f12833
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024823937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3024823937
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4049012019
Short name T560
Test name
Test status
Simulation time 20573959240 ps
CPU time 75.38 seconds
Started Aug 02 05:03:51 PM PDT 24
Finished Aug 02 05:05:06 PM PDT 24
Peak memory 215600 kb
Host smart-cede0cf8-447b-4bbd-8275-696b26ffff35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049012019 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.4049012019
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1450021681
Short name T653
Test name
Test status
Simulation time 24566499 ps
CPU time 0.78 seconds
Started Aug 02 05:03:43 PM PDT 24
Finished Aug 02 05:03:45 PM PDT 24
Peak memory 199088 kb
Host smart-fff2c9fd-99f2-447a-8df6-8f71467bd792
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450021681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1450021681
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.499884705
Short name T617
Test name
Test status
Simulation time 61493286 ps
CPU time 0.61 seconds
Started Aug 02 05:03:57 PM PDT 24
Finished Aug 02 05:03:58 PM PDT 24
Peak memory 195072 kb
Host smart-167fc3b5-a42c-4d90-9122-d114362e3971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499884705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.499884705
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3230419362
Short name T563
Test name
Test status
Simulation time 46658243 ps
CPU time 2.21 seconds
Started Aug 02 05:03:43 PM PDT 24
Finished Aug 02 05:03:46 PM PDT 24
Peak memory 200116 kb
Host smart-fd08dd9a-2e0c-46ad-bffc-e00cef01cce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230419362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3230419362
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3636369746
Short name T656
Test name
Test status
Simulation time 299338258 ps
CPU time 2.97 seconds
Started Aug 02 05:03:45 PM PDT 24
Finished Aug 02 05:03:48 PM PDT 24
Peak memory 200188 kb
Host smart-8f3be855-8c88-42eb-8b73-3bbf22ef0606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636369746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3636369746
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2002971787
Short name T550
Test name
Test status
Simulation time 837696737 ps
CPU time 2.96 seconds
Started Aug 02 05:03:46 PM PDT 24
Finished Aug 02 05:03:49 PM PDT 24
Peak memory 200200 kb
Host smart-1a607d13-ab25-434b-a800-9a9189e7c6cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002971787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2002971787
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3553471419
Short name T581
Test name
Test status
Simulation time 34994896 ps
CPU time 0.63 seconds
Started Aug 02 05:04:16 PM PDT 24
Finished Aug 02 05:04:17 PM PDT 24
Peak memory 195132 kb
Host smart-72cbcf06-0135-43db-8bbf-1102f6821c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553471419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3553471419
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.4079775764
Short name T652
Test name
Test status
Simulation time 14316166 ps
CPU time 0.58 seconds
Started Aug 02 05:03:58 PM PDT 24
Finished Aug 02 05:03:59 PM PDT 24
Peak memory 194940 kb
Host smart-5013e0f5-60bc-41c8-99db-375240dfac16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079775764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.4079775764
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1188727501
Short name T532
Test name
Test status
Simulation time 29526701 ps
CPU time 0.57 seconds
Started Aug 02 05:04:11 PM PDT 24
Finished Aug 02 05:04:11 PM PDT 24
Peak memory 194936 kb
Host smart-f9c451e1-ee90-4dda-80d4-4e2901f88614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188727501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1188727501
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.393849419
Short name T590
Test name
Test status
Simulation time 15934089 ps
CPU time 0.61 seconds
Started Aug 02 05:03:58 PM PDT 24
Finished Aug 02 05:03:58 PM PDT 24
Peak memory 195184 kb
Host smart-b75959ea-50bd-40da-9f59-ae1c78e5165d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393849419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.393849419
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1817188801
Short name T580
Test name
Test status
Simulation time 37826600 ps
CPU time 0.62 seconds
Started Aug 02 05:03:58 PM PDT 24
Finished Aug 02 05:03:59 PM PDT 24
Peak memory 195136 kb
Host smart-0d71423d-8d3e-4f16-9957-01ac069855c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817188801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1817188801
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3624482810
Short name T530
Test name
Test status
Simulation time 14236626 ps
CPU time 0.57 seconds
Started Aug 02 05:03:56 PM PDT 24
Finished Aug 02 05:03:56 PM PDT 24
Peak memory 195016 kb
Host smart-a4361adf-e67c-4534-97c8-07a250d2453d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624482810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3624482810
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2832754840
Short name T654
Test name
Test status
Simulation time 43073212 ps
CPU time 0.56 seconds
Started Aug 02 05:04:10 PM PDT 24
Finished Aug 02 05:04:11 PM PDT 24
Peak memory 194828 kb
Host smart-0ebfeeee-c905-4d09-8057-80086b52de1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832754840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2832754840
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2165088777
Short name T578
Test name
Test status
Simulation time 35617852 ps
CPU time 0.56 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:04:03 PM PDT 24
Peak memory 195000 kb
Host smart-e1df3743-3eab-4039-a0c5-6dde3fa841d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165088777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2165088777
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2700538234
Short name T616
Test name
Test status
Simulation time 39084300 ps
CPU time 0.57 seconds
Started Aug 02 05:03:57 PM PDT 24
Finished Aug 02 05:03:58 PM PDT 24
Peak memory 195032 kb
Host smart-d7510ead-fc71-4ad9-a2ff-0516bfefc6b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700538234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2700538234
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.806963638
Short name T644
Test name
Test status
Simulation time 137668021 ps
CPU time 0.57 seconds
Started Aug 02 05:03:57 PM PDT 24
Finished Aug 02 05:03:58 PM PDT 24
Peak memory 194948 kb
Host smart-643f1c49-1d53-4ad0-96cd-fe70fdc3d86c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806963638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.806963638
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1445599848
Short name T619
Test name
Test status
Simulation time 1073522139 ps
CPU time 8.96 seconds
Started Aug 02 05:03:48 PM PDT 24
Finished Aug 02 05:03:57 PM PDT 24
Peak memory 200076 kb
Host smart-6687441f-b38c-41fe-8202-eecebf215dd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445599848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1445599848
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1847355255
Short name T120
Test name
Test status
Simulation time 1808912360 ps
CPU time 11 seconds
Started Aug 02 05:03:35 PM PDT 24
Finished Aug 02 05:03:47 PM PDT 24
Peak memory 200036 kb
Host smart-c9d5aca9-6ede-4297-81f7-33ecc98dc2d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847355255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1847355255
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2669396550
Short name T557
Test name
Test status
Simulation time 101606856 ps
CPU time 0.9 seconds
Started Aug 02 05:03:53 PM PDT 24
Finished Aug 02 05:03:54 PM PDT 24
Peak memory 199476 kb
Host smart-330d6348-730b-4403-beed-516ecba3480d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669396550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2669396550
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.526141733
Short name T570
Test name
Test status
Simulation time 203220336 ps
CPU time 1.21 seconds
Started Aug 02 05:03:50 PM PDT 24
Finished Aug 02 05:03:51 PM PDT 24
Peak memory 200004 kb
Host smart-c3db9de6-8250-4f9b-add8-03bd7330940c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526141733 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.526141733
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2602373266
Short name T104
Test name
Test status
Simulation time 28497947 ps
CPU time 0.81 seconds
Started Aug 02 05:03:44 PM PDT 24
Finished Aug 02 05:03:45 PM PDT 24
Peak memory 199720 kb
Host smart-9aa6a2af-d0e0-4b1b-a60e-e25e907c1dd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602373266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2602373266
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3484967632
Short name T573
Test name
Test status
Simulation time 12811336 ps
CPU time 0.61 seconds
Started Aug 02 05:03:51 PM PDT 24
Finished Aug 02 05:03:52 PM PDT 24
Peak memory 194980 kb
Host smart-a0aa26e6-b5a5-4797-9bde-20708cb127ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484967632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3484967632
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1440210047
Short name T572
Test name
Test status
Simulation time 213763451 ps
CPU time 1.88 seconds
Started Aug 02 05:03:55 PM PDT 24
Finished Aug 02 05:03:57 PM PDT 24
Peak memory 199992 kb
Host smart-035d8b66-1e09-4d46-96e1-7d9545055fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440210047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1440210047
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3378268224
Short name T603
Test name
Test status
Simulation time 96466034 ps
CPU time 2.57 seconds
Started Aug 02 05:03:45 PM PDT 24
Finished Aug 02 05:03:47 PM PDT 24
Peak memory 200020 kb
Host smart-fe19ed37-c9b7-4a48-8e73-9e51ded62398
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378268224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3378268224
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2778823839
Short name T134
Test name
Test status
Simulation time 62922002 ps
CPU time 1.59 seconds
Started Aug 02 05:03:44 PM PDT 24
Finished Aug 02 05:03:46 PM PDT 24
Peak memory 200136 kb
Host smart-15b9059a-66d0-4f3c-a7ee-2ade79739ead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778823839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2778823839
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.612206356
Short name T531
Test name
Test status
Simulation time 41987928 ps
CPU time 0.61 seconds
Started Aug 02 05:04:03 PM PDT 24
Finished Aug 02 05:04:04 PM PDT 24
Peak memory 195036 kb
Host smart-7053f679-bc78-49f5-a34e-af20f924b329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612206356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.612206356
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3934172021
Short name T615
Test name
Test status
Simulation time 14538242 ps
CPU time 0.6 seconds
Started Aug 02 05:03:59 PM PDT 24
Finished Aug 02 05:03:59 PM PDT 24
Peak memory 195060 kb
Host smart-b1f9265d-a854-4314-ae49-c76acf74f42c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934172021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3934172021
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1363027398
Short name T643
Test name
Test status
Simulation time 26609462 ps
CPU time 0.61 seconds
Started Aug 02 05:04:12 PM PDT 24
Finished Aug 02 05:04:13 PM PDT 24
Peak memory 194832 kb
Host smart-dedd3085-292c-4c8f-811d-de90ce11ecbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363027398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1363027398
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1308656979
Short name T642
Test name
Test status
Simulation time 30063884 ps
CPU time 0.61 seconds
Started Aug 02 05:04:05 PM PDT 24
Finished Aug 02 05:04:05 PM PDT 24
Peak memory 195020 kb
Host smart-d0e98c18-1f47-4dd3-ad27-4fa7b5180010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308656979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1308656979
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3551192503
Short name T582
Test name
Test status
Simulation time 23768902 ps
CPU time 0.64 seconds
Started Aug 02 05:04:13 PM PDT 24
Finished Aug 02 05:04:14 PM PDT 24
Peak memory 194992 kb
Host smart-3599d9ad-a627-45f2-896d-e2acdb88247b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551192503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3551192503
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2784143829
Short name T522
Test name
Test status
Simulation time 38482324 ps
CPU time 0.56 seconds
Started Aug 02 05:04:16 PM PDT 24
Finished Aug 02 05:04:16 PM PDT 24
Peak memory 195144 kb
Host smart-989f0d71-d538-4759-994f-85ccbbc99781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784143829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2784143829
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3640585667
Short name T575
Test name
Test status
Simulation time 61221436 ps
CPU time 0.6 seconds
Started Aug 02 05:04:05 PM PDT 24
Finished Aug 02 05:04:06 PM PDT 24
Peak memory 194932 kb
Host smart-b6d6f31c-5869-4592-a14e-106d514e233e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640585667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3640585667
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2685205758
Short name T535
Test name
Test status
Simulation time 134594579 ps
CPU time 0.61 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:04:10 PM PDT 24
Peak memory 195168 kb
Host smart-d6c15f2b-a809-445b-9e5a-db99a654827d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685205758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2685205758
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.65534497
Short name T589
Test name
Test status
Simulation time 14423636 ps
CPU time 0.61 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:04:02 PM PDT 24
Peak memory 195152 kb
Host smart-930c9aec-02c7-48a6-a7a4-3112962c622d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65534497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.65534497
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1176289019
Short name T597
Test name
Test status
Simulation time 13280460 ps
CPU time 0.57 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:04:09 PM PDT 24
Peak memory 195108 kb
Host smart-515350c1-7d2c-4d92-b3a8-ece013c6befb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176289019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1176289019
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3289863178
Short name T105
Test name
Test status
Simulation time 497055688 ps
CPU time 3.3 seconds
Started Aug 02 05:03:55 PM PDT 24
Finished Aug 02 05:03:59 PM PDT 24
Peak memory 200120 kb
Host smart-09b1b0af-1ff7-4ad5-967d-d6bc3688f48d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289863178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3289863178
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1279755256
Short name T576
Test name
Test status
Simulation time 535474946 ps
CPU time 5.89 seconds
Started Aug 02 05:03:45 PM PDT 24
Finished Aug 02 05:03:51 PM PDT 24
Peak memory 198540 kb
Host smart-646a295b-f313-4ccf-b61c-d7fc61d89273
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279755256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1279755256
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1839986363
Short name T605
Test name
Test status
Simulation time 179777572 ps
CPU time 0.99 seconds
Started Aug 02 05:04:10 PM PDT 24
Finished Aug 02 05:04:11 PM PDT 24
Peak memory 199928 kb
Host smart-7bd26ce9-6585-4244-beb9-caaf467ed2fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839986363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1839986363
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.802693946
Short name T523
Test name
Test status
Simulation time 49496641 ps
CPU time 3.19 seconds
Started Aug 02 05:03:49 PM PDT 24
Finished Aug 02 05:03:52 PM PDT 24
Peak memory 215760 kb
Host smart-f4973fcc-2910-46e8-a601-59b6304f9bdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802693946 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.802693946
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1516758384
Short name T631
Test name
Test status
Simulation time 83881287 ps
CPU time 0.84 seconds
Started Aug 02 05:04:04 PM PDT 24
Finished Aug 02 05:04:05 PM PDT 24
Peak memory 199732 kb
Host smart-b124f136-9bb9-4bea-a577-05d348ce4a56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516758384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1516758384
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2562043105
Short name T552
Test name
Test status
Simulation time 113952011 ps
CPU time 0.56 seconds
Started Aug 02 05:03:59 PM PDT 24
Finished Aug 02 05:03:59 PM PDT 24
Peak memory 194976 kb
Host smart-485cbae6-e673-443e-add2-3e76175e9a36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562043105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2562043105
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3240952700
Short name T554
Test name
Test status
Simulation time 40104678 ps
CPU time 1.12 seconds
Started Aug 02 05:03:47 PM PDT 24
Finished Aug 02 05:03:48 PM PDT 24
Peak memory 198872 kb
Host smart-f9e02d22-bb03-4be5-a1ff-02e7d8ccfae7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240952700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3240952700
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1528105244
Short name T583
Test name
Test status
Simulation time 47427396 ps
CPU time 2.32 seconds
Started Aug 02 05:03:45 PM PDT 24
Finished Aug 02 05:03:48 PM PDT 24
Peak memory 200224 kb
Host smart-fdf5c08e-6649-4f2e-949a-8ff5a2465b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528105244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1528105244
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3811240151
Short name T629
Test name
Test status
Simulation time 175680704 ps
CPU time 1.9 seconds
Started Aug 02 05:04:11 PM PDT 24
Finished Aug 02 05:04:13 PM PDT 24
Peak memory 200136 kb
Host smart-fa5825e2-5027-4e05-84d8-83cbde1eb25a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811240151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3811240151
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.183481701
Short name T562
Test name
Test status
Simulation time 54201452 ps
CPU time 0.58 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:04:10 PM PDT 24
Peak memory 194980 kb
Host smart-fadea697-ec1b-491a-8950-db467e11d433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183481701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.183481701
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2057720105
Short name T551
Test name
Test status
Simulation time 15366602 ps
CPU time 0.58 seconds
Started Aug 02 05:04:28 PM PDT 24
Finished Aug 02 05:04:29 PM PDT 24
Peak memory 194992 kb
Host smart-00a7766c-38d6-41b0-8cb0-5198f8c04bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057720105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2057720105
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1499219014
Short name T521
Test name
Test status
Simulation time 40938692 ps
CPU time 0.6 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:04:10 PM PDT 24
Peak memory 195044 kb
Host smart-968e6ee7-1103-4a71-8956-34e57069808a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499219014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1499219014
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.487269799
Short name T596
Test name
Test status
Simulation time 26419970 ps
CPU time 0.58 seconds
Started Aug 02 05:04:34 PM PDT 24
Finished Aug 02 05:04:34 PM PDT 24
Peak memory 194992 kb
Host smart-2c7c9030-f660-48f9-9a10-7c16681f7a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487269799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.487269799
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1393562177
Short name T649
Test name
Test status
Simulation time 65020889 ps
CPU time 0.65 seconds
Started Aug 02 05:04:14 PM PDT 24
Finished Aug 02 05:04:15 PM PDT 24
Peak memory 195080 kb
Host smart-7e245f7b-4eae-4208-8095-c9ac5e8c6235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393562177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1393562177
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1510121788
Short name T587
Test name
Test status
Simulation time 14246805 ps
CPU time 0.65 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:04:10 PM PDT 24
Peak memory 195108 kb
Host smart-9d9eece7-ba3c-48cb-94db-9c6a7f996709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510121788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1510121788
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3746887232
Short name T655
Test name
Test status
Simulation time 19444859 ps
CPU time 0.67 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:04:10 PM PDT 24
Peak memory 195124 kb
Host smart-a56b1909-e7f5-4975-90a6-9602edfd0eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746887232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3746887232
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.410769812
Short name T593
Test name
Test status
Simulation time 17210962 ps
CPU time 0.56 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:04:09 PM PDT 24
Peak memory 195008 kb
Host smart-d06732b6-52c2-447f-ad1f-ca657afe2fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410769812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.410769812
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.4208514837
Short name T536
Test name
Test status
Simulation time 11695924 ps
CPU time 0.64 seconds
Started Aug 02 05:04:07 PM PDT 24
Finished Aug 02 05:04:08 PM PDT 24
Peak memory 195052 kb
Host smart-be4f0871-f36e-4082-bf6d-d392f9bbae36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208514837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.4208514837
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3653470218
Short name T538
Test name
Test status
Simulation time 12955521 ps
CPU time 0.59 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:04:10 PM PDT 24
Peak memory 194976 kb
Host smart-0eed6135-9df8-4255-b816-bb9ed205fa10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653470218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3653470218
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1160298420
Short name T625
Test name
Test status
Simulation time 82416973 ps
CPU time 1.95 seconds
Started Aug 02 05:03:51 PM PDT 24
Finished Aug 02 05:03:53 PM PDT 24
Peak memory 200076 kb
Host smart-80cadcfb-2edf-489a-a79d-24559bdeb67f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160298420 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1160298420
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4041884066
Short name T106
Test name
Test status
Simulation time 15935881 ps
CPU time 0.8 seconds
Started Aug 02 05:03:43 PM PDT 24
Finished Aug 02 05:03:44 PM PDT 24
Peak memory 199812 kb
Host smart-94c4aefe-c2d1-4551-bcb1-ca42b4c77cc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041884066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.4041884066
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2575354750
Short name T641
Test name
Test status
Simulation time 11482884 ps
CPU time 0.6 seconds
Started Aug 02 05:03:50 PM PDT 24
Finished Aug 02 05:03:52 PM PDT 24
Peak memory 195004 kb
Host smart-e16bf10d-5992-4495-9078-25d0e722991c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575354750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2575354750
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.989287771
Short name T592
Test name
Test status
Simulation time 436546704 ps
CPU time 1.84 seconds
Started Aug 02 05:03:42 PM PDT 24
Finished Aug 02 05:03:44 PM PDT 24
Peak memory 200156 kb
Host smart-caba9722-985e-4c4a-badd-4ca9392fd9ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989287771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.989287771
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3098465169
Short name T607
Test name
Test status
Simulation time 47033210 ps
CPU time 2.18 seconds
Started Aug 02 05:03:50 PM PDT 24
Finished Aug 02 05:03:52 PM PDT 24
Peak memory 200116 kb
Host smart-f8b41644-6bd3-4413-8e54-af571a655a77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098465169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3098465169
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1619814522
Short name T571
Test name
Test status
Simulation time 97903178 ps
CPU time 1.83 seconds
Started Aug 02 05:03:55 PM PDT 24
Finished Aug 02 05:03:57 PM PDT 24
Peak memory 200152 kb
Host smart-f8074b87-de86-4a24-b183-da389075860a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619814522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1619814522
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1013641838
Short name T567
Test name
Test status
Simulation time 471731586 ps
CPU time 2.2 seconds
Started Aug 02 05:03:47 PM PDT 24
Finished Aug 02 05:03:49 PM PDT 24
Peak memory 200212 kb
Host smart-cfa27a06-2b6e-4f5a-98ad-f9a05357eed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013641838 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1013641838
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1709028866
Short name T651
Test name
Test status
Simulation time 184590257 ps
CPU time 0.83 seconds
Started Aug 02 05:04:06 PM PDT 24
Finished Aug 02 05:04:07 PM PDT 24
Peak memory 199900 kb
Host smart-858462e2-329f-42ac-b103-71580fdcca30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709028866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1709028866
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1707288257
Short name T632
Test name
Test status
Simulation time 13481302 ps
CPU time 0.6 seconds
Started Aug 02 05:03:49 PM PDT 24
Finished Aug 02 05:03:49 PM PDT 24
Peak memory 194960 kb
Host smart-f4ae7a33-0511-46bd-9ecc-f6a994a1aa54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707288257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1707288257
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2866874009
Short name T543
Test name
Test status
Simulation time 45783955 ps
CPU time 2.17 seconds
Started Aug 02 05:03:50 PM PDT 24
Finished Aug 02 05:03:52 PM PDT 24
Peak memory 200060 kb
Host smart-3024d3c9-7d68-4f07-ae59-6567d6834861
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866874009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2866874009
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3376711409
Short name T577
Test name
Test status
Simulation time 289405286 ps
CPU time 4.34 seconds
Started Aug 02 05:03:51 PM PDT 24
Finished Aug 02 05:03:55 PM PDT 24
Peak memory 200200 kb
Host smart-6a92ff50-013e-445e-ab0f-88dda42342de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376711409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3376711409
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3851297538
Short name T579
Test name
Test status
Simulation time 217905544 ps
CPU time 2.91 seconds
Started Aug 02 05:03:39 PM PDT 24
Finished Aug 02 05:03:42 PM PDT 24
Peak memory 200100 kb
Host smart-bc751a12-b31c-49ab-93bc-3962754674c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851297538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3851297538
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4053486667
Short name T537
Test name
Test status
Simulation time 51208594 ps
CPU time 3.1 seconds
Started Aug 02 05:04:01 PM PDT 24
Finished Aug 02 05:04:04 PM PDT 24
Peak memory 208368 kb
Host smart-9fb08a63-e00b-4c21-b039-164564abccf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053486667 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4053486667
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2766233774
Short name T584
Test name
Test status
Simulation time 26777792 ps
CPU time 0.89 seconds
Started Aug 02 05:04:10 PM PDT 24
Finished Aug 02 05:04:11 PM PDT 24
Peak memory 199420 kb
Host smart-9eebced6-161f-4022-919a-2926478190de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766233774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2766233774
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.157130259
Short name T600
Test name
Test status
Simulation time 37197059 ps
CPU time 0.59 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:04:09 PM PDT 24
Peak memory 194956 kb
Host smart-2ecb53dd-89be-440d-9153-3ebe0d799cc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157130259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.157130259
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1780506415
Short name T124
Test name
Test status
Simulation time 84920384 ps
CPU time 2.04 seconds
Started Aug 02 05:03:55 PM PDT 24
Finished Aug 02 05:03:57 PM PDT 24
Peak memory 200000 kb
Host smart-26a213ee-4870-4578-adf0-98e7c610e250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780506415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1780506415
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1326480352
Short name T528
Test name
Test status
Simulation time 80936049 ps
CPU time 2.21 seconds
Started Aug 02 05:03:45 PM PDT 24
Finished Aug 02 05:03:47 PM PDT 24
Peak memory 200112 kb
Host smart-a641f63b-39ed-4971-b404-60d0e5e3cdb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326480352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1326480352
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1272418882
Short name T526
Test name
Test status
Simulation time 40854403 ps
CPU time 1.15 seconds
Started Aug 02 05:03:44 PM PDT 24
Finished Aug 02 05:03:46 PM PDT 24
Peak memory 199916 kb
Host smart-2a84f87f-a374-45c4-a0fc-e97518556eb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272418882 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1272418882
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1470221739
Short name T627
Test name
Test status
Simulation time 130587225 ps
CPU time 0.92 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:04:09 PM PDT 24
Peak memory 199976 kb
Host smart-2e02a780-68b2-4f26-8ebf-3594aaf055e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470221739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1470221739
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.4111099966
Short name T634
Test name
Test status
Simulation time 82455667 ps
CPU time 0.61 seconds
Started Aug 02 05:03:57 PM PDT 24
Finished Aug 02 05:03:58 PM PDT 24
Peak memory 194964 kb
Host smart-5ce87717-1790-49d0-ae93-ca8019df57ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111099966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.4111099966
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1202455895
Short name T566
Test name
Test status
Simulation time 521041488 ps
CPU time 2.29 seconds
Started Aug 02 05:03:45 PM PDT 24
Finished Aug 02 05:03:47 PM PDT 24
Peak memory 200064 kb
Host smart-d6469f50-7387-4e67-84bd-a3afb2d80031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202455895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1202455895
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.810580104
Short name T548
Test name
Test status
Simulation time 265540826 ps
CPU time 2.5 seconds
Started Aug 02 05:03:44 PM PDT 24
Finished Aug 02 05:03:46 PM PDT 24
Peak memory 200096 kb
Host smart-398b7551-17aa-4901-8cbc-302a6bfc7f0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810580104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.810580104
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3736215179
Short name T609
Test name
Test status
Simulation time 48418547 ps
CPU time 1.67 seconds
Started Aug 02 05:03:49 PM PDT 24
Finished Aug 02 05:03:51 PM PDT 24
Peak memory 200116 kb
Host smart-b153292e-a789-4f08-aa15-4bf0cf52261f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736215179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3736215179
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2822901548
Short name T613
Test name
Test status
Simulation time 128631731 ps
CPU time 1.94 seconds
Started Aug 02 05:03:44 PM PDT 24
Finished Aug 02 05:03:47 PM PDT 24
Peak memory 200140 kb
Host smart-b135d9bd-7f61-4a6e-bdd6-4be295bf65e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822901548 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2822901548
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1911319883
Short name T101
Test name
Test status
Simulation time 26359789 ps
CPU time 0.82 seconds
Started Aug 02 05:04:07 PM PDT 24
Finished Aug 02 05:04:08 PM PDT 24
Peak memory 199908 kb
Host smart-415a606f-2832-4776-829a-faaa6a5fea7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911319883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1911319883
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1001784721
Short name T533
Test name
Test status
Simulation time 42804315 ps
CPU time 0.63 seconds
Started Aug 02 05:03:45 PM PDT 24
Finished Aug 02 05:03:45 PM PDT 24
Peak memory 195056 kb
Host smart-b2b6b32e-281c-4df9-a7ce-e90f83973670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001784721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1001784721
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.284232275
Short name T121
Test name
Test status
Simulation time 46700960 ps
CPU time 2.12 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:04:10 PM PDT 24
Peak memory 199744 kb
Host smart-ae62dbde-abf2-4afc-8abe-6945525d3e13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284232275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.284232275
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2938524484
Short name T657
Test name
Test status
Simulation time 160702102 ps
CPU time 3.14 seconds
Started Aug 02 05:04:04 PM PDT 24
Finished Aug 02 05:04:07 PM PDT 24
Peak memory 200188 kb
Host smart-807ccf2f-944d-4f5c-aaa3-0e407810acef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938524484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2938524484
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1775273195
Short name T586
Test name
Test status
Simulation time 52764143 ps
CPU time 1.76 seconds
Started Aug 02 05:03:57 PM PDT 24
Finished Aug 02 05:03:59 PM PDT 24
Peak memory 200156 kb
Host smart-1b520c21-2759-4538-9ce0-44dc75c1c3c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775273195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1775273195
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1532599546
Short name T54
Test name
Test status
Simulation time 29500639 ps
CPU time 0.59 seconds
Started Aug 02 05:04:15 PM PDT 24
Finished Aug 02 05:04:16 PM PDT 24
Peak memory 194936 kb
Host smart-7d92f764-41ae-4ba4-8ee4-904db876821f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532599546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1532599546
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1945992227
Short name T334
Test name
Test status
Simulation time 347857805 ps
CPU time 10.15 seconds
Started Aug 02 05:04:17 PM PDT 24
Finished Aug 02 05:04:27 PM PDT 24
Peak memory 199764 kb
Host smart-f8c5952a-0295-4611-ae02-81c076278a88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945992227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1945992227
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.562333282
Short name T518
Test name
Test status
Simulation time 3709332404 ps
CPU time 8.06 seconds
Started Aug 02 05:04:16 PM PDT 24
Finished Aug 02 05:04:24 PM PDT 24
Peak memory 199840 kb
Host smart-fecd2358-8d64-4d86-89e2-280bd17bb87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562333282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.562333282
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_error.1410740870
Short name T419
Test name
Test status
Simulation time 496032187 ps
CPU time 26.42 seconds
Started Aug 02 05:04:03 PM PDT 24
Finished Aug 02 05:04:30 PM PDT 24
Peak memory 199888 kb
Host smart-b5866708-dce1-4f26-8ee6-1ff70c436728
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410740870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1410740870
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3031068809
Short name T257
Test name
Test status
Simulation time 46032185359 ps
CPU time 108.18 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:05:57 PM PDT 24
Peak memory 199956 kb
Host smart-c3a5e883-426d-41c4-bdf2-58d31c0fd969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031068809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3031068809
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3506404689
Short name T60
Test name
Test status
Simulation time 132446818 ps
CPU time 0.86 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:04:09 PM PDT 24
Peak memory 218480 kb
Host smart-b2f35247-2895-4211-960c-b4818dbca574
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506404689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3506404689
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3734056852
Short name T456
Test name
Test status
Simulation time 4024085798 ps
CPU time 8.26 seconds
Started Aug 02 05:04:11 PM PDT 24
Finished Aug 02 05:04:20 PM PDT 24
Peak memory 199968 kb
Host smart-ddb467df-bcc6-4ef2-9f90-3b82ea6eef70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734056852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3734056852
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2831764035
Short name T468
Test name
Test status
Simulation time 76850929681 ps
CPU time 958.13 seconds
Started Aug 02 05:04:14 PM PDT 24
Finished Aug 02 05:20:12 PM PDT 24
Peak memory 200008 kb
Host smart-d304a098-576b-4f82-9a4d-2387c438be56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831764035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2831764035
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.1471962535
Short name T384
Test name
Test status
Simulation time 4768194754 ps
CPU time 69.65 seconds
Started Aug 02 05:04:06 PM PDT 24
Finished Aug 02 05:05:16 PM PDT 24
Peak memory 199944 kb
Host smart-09642cf6-cbd0-4eb6-ab8c-d07c12b3f7a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1471962535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.1471962535
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2257824089
Short name T418
Test name
Test status
Simulation time 5546538741 ps
CPU time 67.72 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:05:17 PM PDT 24
Peak memory 200008 kb
Host smart-03516885-700d-4a22-a698-352d69c943ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2257824089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2257824089
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2759122329
Short name T224
Test name
Test status
Simulation time 7748772304 ps
CPU time 115.5 seconds
Started Aug 02 05:04:11 PM PDT 24
Finished Aug 02 05:06:06 PM PDT 24
Peak memory 199944 kb
Host smart-589641e7-6fe0-443d-a084-ade0f75377d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2759122329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2759122329
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.264514505
Short name T463
Test name
Test status
Simulation time 151542625155 ps
CPU time 692.91 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:15:41 PM PDT 24
Peak memory 199968 kb
Host smart-544d805b-af46-4826-9d23-8ee419f2dc26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=264514505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.264514505
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2541516357
Short name T462
Test name
Test status
Simulation time 38301633648 ps
CPU time 2180.38 seconds
Started Aug 02 05:04:18 PM PDT 24
Finished Aug 02 05:40:39 PM PDT 24
Peak memory 215636 kb
Host smart-4fb36e29-0dec-4809-a0e0-60f2caa858c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2541516357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2541516357
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.2753348524
Short name T488
Test name
Test status
Simulation time 183457048160 ps
CPU time 2132.69 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:39:42 PM PDT 24
Peak memory 215376 kb
Host smart-6fc27eb1-642c-4915-b656-42494d10887c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2753348524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2753348524
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.4186399410
Short name T446
Test name
Test status
Simulation time 221466880 ps
CPU time 4.61 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:04:13 PM PDT 24
Peak memory 199860 kb
Host smart-764b564c-6c7f-4fc2-a8a9-e4e27ad6e218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186399410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.4186399410
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1595484234
Short name T288
Test name
Test status
Simulation time 31322585 ps
CPU time 0.57 seconds
Started Aug 02 05:04:22 PM PDT 24
Finished Aug 02 05:04:23 PM PDT 24
Peak memory 195620 kb
Host smart-f55a552a-8a01-4301-8124-a39f9dc19b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595484234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1595484234
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.568480926
Short name T348
Test name
Test status
Simulation time 1999267759 ps
CPU time 109.36 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:05:59 PM PDT 24
Peak memory 199772 kb
Host smart-67619c3f-a717-47aa-b4d4-b0b90fb98b5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568480926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.568480926
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.778957895
Short name T306
Test name
Test status
Simulation time 2256337914 ps
CPU time 59.43 seconds
Started Aug 02 05:04:10 PM PDT 24
Finished Aug 02 05:05:09 PM PDT 24
Peak memory 199960 kb
Host smart-cfbf844b-d036-47d2-be12-d2098cc2f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778957895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.778957895
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.948365668
Short name T264
Test name
Test status
Simulation time 3347756063 ps
CPU time 132.5 seconds
Started Aug 02 05:04:14 PM PDT 24
Finished Aug 02 05:06:27 PM PDT 24
Peak memory 432264 kb
Host smart-3b54255c-b03f-4737-b671-0d5635f6928c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948365668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.948365668
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3854203103
Short name T403
Test name
Test status
Simulation time 36862654512 ps
CPU time 311.86 seconds
Started Aug 02 05:04:06 PM PDT 24
Finished Aug 02 05:09:19 PM PDT 24
Peak memory 199960 kb
Host smart-a2aba650-9adf-4b5a-9f37-d47a4fc71c35
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854203103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3854203103
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.849087816
Short name T175
Test name
Test status
Simulation time 3884932657 ps
CPU time 52.64 seconds
Started Aug 02 05:04:18 PM PDT 24
Finished Aug 02 05:05:11 PM PDT 24
Peak memory 199960 kb
Host smart-b048f8b1-ba41-428e-9c11-ba8dbba415c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849087816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.849087816
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1401920409
Short name T59
Test name
Test status
Simulation time 216518384 ps
CPU time 0.93 seconds
Started Aug 02 05:04:15 PM PDT 24
Finished Aug 02 05:04:16 PM PDT 24
Peak memory 218624 kb
Host smart-2763277c-1520-4177-b1a4-81107ee2320d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401920409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1401920409
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.528627080
Short name T96
Test name
Test status
Simulation time 1284305448 ps
CPU time 7.26 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:04:16 PM PDT 24
Peak memory 199876 kb
Host smart-0f83b2a4-67d0-4efe-aeae-f87048d54d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528627080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.528627080
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2947305147
Short name T47
Test name
Test status
Simulation time 22202257874 ps
CPU time 1704.05 seconds
Started Aug 02 05:04:21 PM PDT 24
Finished Aug 02 05:32:45 PM PDT 24
Peak memory 749612 kb
Host smart-54d2fe89-c117-4d9f-9ae0-6e9f24c661ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947305147 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2947305147
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1872626264
Short name T15
Test name
Test status
Simulation time 717132910013 ps
CPU time 3543.98 seconds
Started Aug 02 05:04:12 PM PDT 24
Finished Aug 02 06:03:16 PM PDT 24
Peak memory 788748 kb
Host smart-90989235-e820-4d75-bfc6-4d880de9b6c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872626264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.1872626264
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3513422935
Short name T347
Test name
Test status
Simulation time 1119896958 ps
CPU time 36.61 seconds
Started Aug 02 05:04:05 PM PDT 24
Finished Aug 02 05:04:42 PM PDT 24
Peak memory 199852 kb
Host smart-aa0f5dc6-6385-4352-acd2-d60b29d45cc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3513422935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3513422935
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1594377742
Short name T163
Test name
Test status
Simulation time 11339535265 ps
CPU time 94.01 seconds
Started Aug 02 05:04:18 PM PDT 24
Finished Aug 02 05:05:52 PM PDT 24
Peak memory 199912 kb
Host smart-1503c5a0-e14d-4ccf-b1cc-40d3cae05cc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1594377742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1594377742
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.173343646
Short name T115
Test name
Test status
Simulation time 10963936560 ps
CPU time 112.08 seconds
Started Aug 02 05:04:16 PM PDT 24
Finished Aug 02 05:06:09 PM PDT 24
Peak memory 199928 kb
Host smart-1e7ad30c-6a25-46c5-aa4e-047ed72808c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=173343646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.173343646
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3281567433
Short name T511
Test name
Test status
Simulation time 41963677976 ps
CPU time 2280.81 seconds
Started Aug 02 05:04:02 PM PDT 24
Finished Aug 02 05:42:04 PM PDT 24
Peak memory 215520 kb
Host smart-98257bd7-3da2-40d4-b0bf-c2d27a8b0f12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3281567433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3281567433
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.1840429891
Short name T491
Test name
Test status
Simulation time 39082804328 ps
CPU time 2104.91 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:39:15 PM PDT 24
Peak memory 215540 kb
Host smart-1c75e618-8dc5-484f-815d-bf5c8e2b0dda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1840429891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.1840429891
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.997718808
Short name T383
Test name
Test status
Simulation time 524598722 ps
CPU time 27.59 seconds
Started Aug 02 05:04:09 PM PDT 24
Finished Aug 02 05:04:37 PM PDT 24
Peak memory 199752 kb
Host smart-1c48fa25-08d9-4325-b404-2b0d616a4269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997718808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.997718808
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3758456308
Short name T469
Test name
Test status
Simulation time 89631588 ps
CPU time 0.62 seconds
Started Aug 02 05:04:38 PM PDT 24
Finished Aug 02 05:04:39 PM PDT 24
Peak memory 195912 kb
Host smart-3260d82e-e1fb-4f96-a751-f5031d36b0a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758456308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3758456308
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3060790692
Short name T64
Test name
Test status
Simulation time 683361192 ps
CPU time 18.91 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:04:45 PM PDT 24
Peak memory 199828 kb
Host smart-9397d336-25d7-40ea-a473-545853c93c9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3060790692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3060790692
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3631316109
Short name T371
Test name
Test status
Simulation time 268147572 ps
CPU time 4.7 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:04:38 PM PDT 24
Peak memory 199920 kb
Host smart-f70c38fa-b096-43fb-b177-31a9080cb4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631316109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3631316109
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3056518328
Short name T169
Test name
Test status
Simulation time 59246897565 ps
CPU time 851.12 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:18:36 PM PDT 24
Peak memory 753076 kb
Host smart-fb69c780-1b2f-404f-b025-7c1e139750d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3056518328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3056518328
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.376953690
Short name T62
Test name
Test status
Simulation time 4004214649 ps
CPU time 47.68 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:05:13 PM PDT 24
Peak memory 199792 kb
Host smart-d1717c02-497b-40db-bad0-025839c8c176
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376953690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.376953690
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.4258241092
Short name T392
Test name
Test status
Simulation time 53424970894 ps
CPU time 184.95 seconds
Started Aug 02 05:04:40 PM PDT 24
Finished Aug 02 05:07:45 PM PDT 24
Peak memory 208144 kb
Host smart-f3289b25-109b-4efd-8f7e-f9b604639180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258241092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.4258241092
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1556418499
Short name T497
Test name
Test status
Simulation time 464474350 ps
CPU time 5.14 seconds
Started Aug 02 05:04:38 PM PDT 24
Finished Aug 02 05:04:43 PM PDT 24
Peak memory 199784 kb
Host smart-3d29a4f3-e26b-4e00-8555-7dd8fa2d526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556418499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1556418499
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1900467788
Short name T170
Test name
Test status
Simulation time 111733513884 ps
CPU time 2897.38 seconds
Started Aug 02 05:04:32 PM PDT 24
Finished Aug 02 05:52:50 PM PDT 24
Peak memory 801924 kb
Host smart-7f9435e2-6c22-499d-be48-576f34a68150
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900467788 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1900467788
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.4101242445
Short name T112
Test name
Test status
Simulation time 393714921 ps
CPU time 21.73 seconds
Started Aug 02 05:04:22 PM PDT 24
Finished Aug 02 05:04:44 PM PDT 24
Peak memory 199784 kb
Host smart-ba8b9234-6587-42d7-97cf-60424af5a103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101242445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.4101242445
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3820403762
Short name T191
Test name
Test status
Simulation time 9205075934 ps
CPU time 83.5 seconds
Started Aug 02 05:04:31 PM PDT 24
Finished Aug 02 05:05:54 PM PDT 24
Peak memory 199944 kb
Host smart-64cede13-ebea-40db-ad8e-980bb353cbfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820403762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3820403762
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.976595477
Short name T387
Test name
Test status
Simulation time 2856230079 ps
CPU time 57.85 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:05:25 PM PDT 24
Peak memory 200040 kb
Host smart-ff7e460f-8bd9-44af-9c21-31ed7a964851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976595477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.976595477
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2507416046
Short name T168
Test name
Test status
Simulation time 3067156893 ps
CPU time 603.44 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:14:39 PM PDT 24
Peak memory 739308 kb
Host smart-e316abe4-5a8b-4133-8ec9-d70446c1b9d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507416046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2507416046
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.4205472992
Short name T358
Test name
Test status
Simulation time 1302595447 ps
CPU time 67.61 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:05:43 PM PDT 24
Peak memory 199864 kb
Host smart-c93ecea0-a786-43f7-b5c2-2ae99e35ddfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205472992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.4205472992
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3785716329
Short name T513
Test name
Test status
Simulation time 13068873533 ps
CPU time 189.46 seconds
Started Aug 02 05:04:41 PM PDT 24
Finished Aug 02 05:07:51 PM PDT 24
Peak memory 200008 kb
Host smart-83b74c44-b9d8-4a88-abe7-537c2fb23772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785716329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3785716329
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.423923446
Short name T391
Test name
Test status
Simulation time 292258541 ps
CPU time 1.36 seconds
Started Aug 02 05:04:30 PM PDT 24
Finished Aug 02 05:04:31 PM PDT 24
Peak memory 199832 kb
Host smart-d9b30e36-e768-4520-b6e9-75af56aadcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423923446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.423923446
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3500937200
Short name T148
Test name
Test status
Simulation time 342861940114 ps
CPU time 2216.5 seconds
Started Aug 02 05:04:20 PM PDT 24
Finished Aug 02 05:41:17 PM PDT 24
Peak memory 772620 kb
Host smart-6989179a-4c14-4f3e-a70c-7344c1d34d67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500937200 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3500937200
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.216394595
Short name T372
Test name
Test status
Simulation time 2781659795 ps
CPU time 135.56 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:06:42 PM PDT 24
Peak memory 200008 kb
Host smart-1a06e63e-1393-466a-b694-6e5a09439ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216394595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.216394595
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2133041796
Short name T28
Test name
Test status
Simulation time 14115552 ps
CPU time 0.6 seconds
Started Aug 02 05:04:23 PM PDT 24
Finished Aug 02 05:04:23 PM PDT 24
Peak memory 194908 kb
Host smart-3447f3a3-b8b3-48a1-81b5-8c0d7caf8c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133041796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2133041796
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.4039765209
Short name T377
Test name
Test status
Simulation time 2234457668 ps
CPU time 62.79 seconds
Started Aug 02 05:04:27 PM PDT 24
Finished Aug 02 05:05:30 PM PDT 24
Peak memory 199944 kb
Host smart-92f87d88-9799-410f-bd86-a7d08987ebb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039765209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.4039765209
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2323987350
Short name T520
Test name
Test status
Simulation time 3986351578 ps
CPU time 53.75 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:05:21 PM PDT 24
Peak memory 199900 kb
Host smart-4521f0a7-6a48-4595-babf-2f0b12cd14f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323987350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2323987350
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.747291265
Short name T357
Test name
Test status
Simulation time 39826531 ps
CPU time 2.06 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:04:27 PM PDT 24
Peak memory 199864 kb
Host smart-d38b1c99-e9d7-4439-9d8a-d5114446bf2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747291265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.747291265
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2854092079
Short name T236
Test name
Test status
Simulation time 664234634 ps
CPU time 24.4 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:04:59 PM PDT 24
Peak memory 199716 kb
Host smart-d30bd68a-d4b2-43cc-9fe8-fff37081cbdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854092079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2854092079
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3230412581
Short name T183
Test name
Test status
Simulation time 1341576640 ps
CPU time 74.85 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:05:50 PM PDT 24
Peak memory 199904 kb
Host smart-7f4883ea-9bcd-479a-896f-5b61bab16a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230412581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3230412581
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.603607207
Short name T23
Test name
Test status
Simulation time 539626455 ps
CPU time 5.64 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:04:39 PM PDT 24
Peak memory 199796 kb
Host smart-4538742b-7d01-4d97-81a2-ab29cb944ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603607207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.603607207
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1796721054
Short name T150
Test name
Test status
Simulation time 16523775601 ps
CPU time 1087.61 seconds
Started Aug 02 05:04:22 PM PDT 24
Finished Aug 02 05:22:29 PM PDT 24
Peak memory 726824 kb
Host smart-32d6367d-4352-49f4-beef-929332e43866
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796721054 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1796721054
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3730129982
Short name T26
Test name
Test status
Simulation time 8393685050 ps
CPU time 101.17 seconds
Started Aug 02 05:04:23 PM PDT 24
Finished Aug 02 05:06:05 PM PDT 24
Peak memory 200000 kb
Host smart-6d54bb3f-0c4e-46e3-a1f5-8ddf5af80d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730129982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3730129982
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1639878146
Short name T63
Test name
Test status
Simulation time 55382980 ps
CPU time 0.55 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:04:35 PM PDT 24
Peak memory 195568 kb
Host smart-d5ee298f-45fb-4470-b745-3caeb9e964fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639878146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1639878146
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1863601085
Short name T430
Test name
Test status
Simulation time 544984169 ps
CPU time 30.91 seconds
Started Aug 02 05:04:37 PM PDT 24
Finished Aug 02 05:05:08 PM PDT 24
Peak memory 199816 kb
Host smart-36209a13-fe6a-49ef-91f9-ed355bfcb0f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863601085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1863601085
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3396784317
Short name T147
Test name
Test status
Simulation time 719476063 ps
CPU time 10 seconds
Started Aug 02 05:04:44 PM PDT 24
Finished Aug 02 05:04:54 PM PDT 24
Peak memory 199828 kb
Host smart-f90b42db-10df-4889-9b0c-ed236bbefd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396784317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3396784317
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2383480545
Short name T479
Test name
Test status
Simulation time 9300079522 ps
CPU time 780.72 seconds
Started Aug 02 05:04:43 PM PDT 24
Finished Aug 02 05:17:44 PM PDT 24
Peak memory 732708 kb
Host smart-f09fd579-337d-48e4-b874-940a4d95e7c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383480545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2383480545
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2603409479
Short name T210
Test name
Test status
Simulation time 2215259928 ps
CPU time 107.41 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:06:14 PM PDT 24
Peak memory 199844 kb
Host smart-7dc127b4-dce1-4ad3-b6dc-8849e9fac7bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603409479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2603409479
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.546477810
Short name T482
Test name
Test status
Simulation time 12413976635 ps
CPU time 154.32 seconds
Started Aug 02 05:04:27 PM PDT 24
Finished Aug 02 05:07:01 PM PDT 24
Peak memory 216220 kb
Host smart-48dc6070-5f10-4544-a113-05f34385178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546477810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.546477810
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1887007210
Short name T494
Test name
Test status
Simulation time 411175517 ps
CPU time 5.35 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:04:41 PM PDT 24
Peak memory 199832 kb
Host smart-4ae3bead-640d-4328-b01c-d8f468b20638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887007210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1887007210
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2132225721
Short name T338
Test name
Test status
Simulation time 98573478164 ps
CPU time 2164.65 seconds
Started Aug 02 05:04:28 PM PDT 24
Finished Aug 02 05:40:33 PM PDT 24
Peak memory 770696 kb
Host smart-37f6d542-e0c3-46ed-acd3-dba32d8afe1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132225721 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2132225721
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2808505263
Short name T77
Test name
Test status
Simulation time 790389603 ps
CPU time 10.46 seconds
Started Aug 02 05:04:29 PM PDT 24
Finished Aug 02 05:04:39 PM PDT 24
Peak memory 199860 kb
Host smart-09e148be-3085-4769-bc30-87cb5701757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808505263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2808505263
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.530431481
Short name T476
Test name
Test status
Simulation time 57569230 ps
CPU time 0.58 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:04:27 PM PDT 24
Peak memory 195900 kb
Host smart-f9bcf3b5-8b5b-4d5f-bdde-d361dea43f51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530431481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.530431481
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3871153491
Short name T352
Test name
Test status
Simulation time 1375253441 ps
CPU time 79.49 seconds
Started Aug 02 05:04:34 PM PDT 24
Finished Aug 02 05:05:54 PM PDT 24
Peak memory 199884 kb
Host smart-6a8932ec-21ed-40f5-a3f8-3dc3462dc385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871153491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3871153491
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.693705148
Short name T235
Test name
Test status
Simulation time 8142625248 ps
CPU time 24.58 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:04:51 PM PDT 24
Peak memory 199896 kb
Host smart-e5568a2c-9ec3-493f-883b-5ea2a4de0783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693705148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.693705148
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3125914520
Short name T202
Test name
Test status
Simulation time 13640710040 ps
CPU time 593.92 seconds
Started Aug 02 05:04:38 PM PDT 24
Finished Aug 02 05:14:32 PM PDT 24
Peak memory 712364 kb
Host smart-45e85f98-4845-4ba6-9386-aa1a1b5718e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125914520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3125914520
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2430569793
Short name T117
Test name
Test status
Simulation time 42386340607 ps
CPU time 120.87 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:06:59 PM PDT 24
Peak memory 200060 kb
Host smart-3ace20a6-614e-4725-b919-ad717d188b43
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430569793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2430569793
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1569616813
Short name T256
Test name
Test status
Simulation time 27869690781 ps
CPU time 120.86 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:06:28 PM PDT 24
Peak memory 216356 kb
Host smart-357011b3-8a0a-4333-b720-621bd312a2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569616813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1569616813
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3368089533
Short name T359
Test name
Test status
Simulation time 7545417682 ps
CPU time 11.68 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:04:38 PM PDT 24
Peak memory 200028 kb
Host smart-dd2d79b7-3999-4a14-b8f2-40b40943fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368089533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3368089533
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1397931884
Short name T313
Test name
Test status
Simulation time 14261882435 ps
CPU time 463.46 seconds
Started Aug 02 05:04:38 PM PDT 24
Finished Aug 02 05:12:22 PM PDT 24
Peak memory 356596 kb
Host smart-067703f7-5b92-4377-96f7-60b43624daab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397931884 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1397931884
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2406499115
Short name T461
Test name
Test status
Simulation time 32400093649 ps
CPU time 148.68 seconds
Started Aug 02 05:05:01 PM PDT 24
Finished Aug 02 05:07:30 PM PDT 24
Peak memory 200020 kb
Host smart-ac32a903-3c8b-46bb-9ac3-002bc5c996a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406499115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2406499115
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.900318754
Short name T250
Test name
Test status
Simulation time 14856908 ps
CPU time 0.57 seconds
Started Aug 02 05:04:27 PM PDT 24
Finished Aug 02 05:04:27 PM PDT 24
Peak memory 194876 kb
Host smart-35dd7e4c-655b-4d1b-bcda-f5b51941e3b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900318754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.900318754
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2641088301
Short name T248
Test name
Test status
Simulation time 2644149428 ps
CPU time 76.89 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:05:50 PM PDT 24
Peak memory 199964 kb
Host smart-e42b0924-9fce-4e9a-bfdf-cc2e271d4537
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641088301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2641088301
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.882979240
Short name T51
Test name
Test status
Simulation time 269364163 ps
CPU time 2.08 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:04:57 PM PDT 24
Peak memory 199844 kb
Host smart-0b68c29c-d9af-4311-8e6e-471f712b0e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882979240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.882979240
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1892543866
Short name T460
Test name
Test status
Simulation time 6627056402 ps
CPU time 192.08 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:07:37 PM PDT 24
Peak memory 458352 kb
Host smart-7a15480e-6dbb-4c9d-8f43-4083bd771008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892543866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1892543866
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.811934657
Short name T441
Test name
Test status
Simulation time 6911542245 ps
CPU time 91.36 seconds
Started Aug 02 05:04:54 PM PDT 24
Finished Aug 02 05:06:26 PM PDT 24
Peak memory 199976 kb
Host smart-9ee086b1-8e34-4416-94b3-d79fcc0c3774
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811934657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.811934657
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3561405584
Short name T428
Test name
Test status
Simulation time 14555612541 ps
CPU time 269.32 seconds
Started Aug 02 05:04:30 PM PDT 24
Finished Aug 02 05:09:00 PM PDT 24
Peak memory 199988 kb
Host smart-721db46b-d904-460c-a859-f68ad890df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561405584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3561405584
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2186754950
Short name T244
Test name
Test status
Simulation time 563929625 ps
CPU time 6.74 seconds
Started Aug 02 05:04:23 PM PDT 24
Finished Aug 02 05:04:30 PM PDT 24
Peak memory 199892 kb
Host smart-d7614c34-9ed5-41bf-b3ba-478389760c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186754950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2186754950
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.4175677364
Short name T130
Test name
Test status
Simulation time 390436964766 ps
CPU time 3078.54 seconds
Started Aug 02 05:04:43 PM PDT 24
Finished Aug 02 05:56:07 PM PDT 24
Peak memory 752300 kb
Host smart-a138e6d0-ef57-4b46-bb96-6967b9617183
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175677364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.4175677364
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.933582968
Short name T129
Test name
Test status
Simulation time 864423076 ps
CPU time 20.34 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:04:56 PM PDT 24
Peak memory 199756 kb
Host smart-a4ead942-71d2-41b8-9a47-a506aabbeadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933582968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.933582968
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3573903344
Short name T399
Test name
Test status
Simulation time 13908803 ps
CPU time 0.55 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:04:33 PM PDT 24
Peak memory 195552 kb
Host smart-df36eb07-f784-4a6c-a66c-5cc3b17f3ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573903344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3573903344
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3586884844
Short name T216
Test name
Test status
Simulation time 5662896491 ps
CPU time 82.2 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:05:57 PM PDT 24
Peak memory 199944 kb
Host smart-5501c6c9-368b-4e7b-826c-e84cdb486666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586884844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3586884844
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.207869077
Short name T335
Test name
Test status
Simulation time 10813971912 ps
CPU time 34.42 seconds
Started Aug 02 05:04:48 PM PDT 24
Finished Aug 02 05:05:23 PM PDT 24
Peak memory 216332 kb
Host smart-2f209ad2-d560-4531-a288-4c81f05fcde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207869077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.207869077
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1071009517
Short name T501
Test name
Test status
Simulation time 7051833009 ps
CPU time 225.92 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:08:12 PM PDT 24
Peak memory 631784 kb
Host smart-8abc38a3-20d0-4056-904d-c18e051111c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071009517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1071009517
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1410172146
Short name T182
Test name
Test status
Simulation time 31395117522 ps
CPU time 135.84 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:06:42 PM PDT 24
Peak memory 199896 kb
Host smart-21369049-0f7d-4a98-820d-9b538b4b54a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410172146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1410172146
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1032880505
Short name T192
Test name
Test status
Simulation time 34151075647 ps
CPU time 145.87 seconds
Started Aug 02 05:04:31 PM PDT 24
Finished Aug 02 05:06:57 PM PDT 24
Peak memory 200020 kb
Host smart-227d17d5-2643-4402-b01f-43acad91f39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032880505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1032880505
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3484313159
Short name T18
Test name
Test status
Simulation time 253776741 ps
CPU time 1.55 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:04:38 PM PDT 24
Peak memory 199828 kb
Host smart-7e052ac2-3982-4d9f-8262-38ada8fd32e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484313159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3484313159
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3910750168
Short name T380
Test name
Test status
Simulation time 116551895782 ps
CPU time 724.53 seconds
Started Aug 02 05:04:47 PM PDT 24
Finished Aug 02 05:16:51 PM PDT 24
Peak memory 200044 kb
Host smart-804272be-04e3-46db-bb54-ef45a66edca2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910750168 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3910750168
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.734470274
Short name T370
Test name
Test status
Simulation time 2077956875 ps
CPU time 34.41 seconds
Started Aug 02 05:04:30 PM PDT 24
Finished Aug 02 05:05:05 PM PDT 24
Peak memory 199844 kb
Host smart-4ee87c4e-fcf5-49ea-b2a8-634e6b05fb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734470274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.734470274
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.4082858624
Short name T185
Test name
Test status
Simulation time 15630169 ps
CPU time 0.56 seconds
Started Aug 02 05:04:34 PM PDT 24
Finished Aug 02 05:04:35 PM PDT 24
Peak memory 195984 kb
Host smart-b3fe1adf-3efc-4e14-a5b6-ac1b8c8efdc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082858624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4082858624
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2232321044
Short name T208
Test name
Test status
Simulation time 3337182135 ps
CPU time 96.08 seconds
Started Aug 02 05:04:49 PM PDT 24
Finished Aug 02 05:06:25 PM PDT 24
Peak memory 199968 kb
Host smart-d1861485-16f8-40a0-991b-631b3285b24d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232321044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2232321044
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2875749414
Short name T451
Test name
Test status
Simulation time 5622952899 ps
CPU time 58.36 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:05:32 PM PDT 24
Peak memory 216080 kb
Host smart-8c191bb3-abdf-4e4e-a8d8-3c6d7ee39288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875749414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2875749414
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2189787552
Short name T95
Test name
Test status
Simulation time 79863268205 ps
CPU time 1079.31 seconds
Started Aug 02 05:04:39 PM PDT 24
Finished Aug 02 05:22:38 PM PDT 24
Peak memory 760888 kb
Host smart-a37d7963-c442-4fd7-836d-a01545dc6988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2189787552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2189787552
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.900342982
Short name T365
Test name
Test status
Simulation time 58472308542 ps
CPU time 176.98 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:07:30 PM PDT 24
Peak memory 199980 kb
Host smart-c12ca1b4-262b-4f53-bf81-cc2539a0a376
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900342982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.900342982
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1799810801
Short name T326
Test name
Test status
Simulation time 2384066425 ps
CPU time 125.97 seconds
Started Aug 02 05:04:32 PM PDT 24
Finished Aug 02 05:06:38 PM PDT 24
Peak memory 199960 kb
Host smart-a6af9732-1287-4e90-a692-fa8310da462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799810801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1799810801
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.622006935
Short name T79
Test name
Test status
Simulation time 2322471774 ps
CPU time 14.35 seconds
Started Aug 02 05:04:44 PM PDT 24
Finished Aug 02 05:04:59 PM PDT 24
Peak memory 199980 kb
Host smart-20766e4e-90e9-4ce4-b080-7b5b52ebf172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622006935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.622006935
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.608828346
Short name T402
Test name
Test status
Simulation time 7902926466 ps
CPU time 383.02 seconds
Started Aug 02 05:04:32 PM PDT 24
Finished Aug 02 05:10:55 PM PDT 24
Peak memory 199980 kb
Host smart-99c43761-7247-4f35-bb2f-6e6520439065
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608828346 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.608828346
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.294638703
Short name T498
Test name
Test status
Simulation time 7249050680 ps
CPU time 22.97 seconds
Started Aug 02 05:04:37 PM PDT 24
Finished Aug 02 05:05:00 PM PDT 24
Peak memory 199944 kb
Host smart-09298d7e-5a92-40b5-b276-7f7103757fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294638703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.294638703
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.628969284
Short name T214
Test name
Test status
Simulation time 43526130 ps
CPU time 0.6 seconds
Started Aug 02 05:04:43 PM PDT 24
Finished Aug 02 05:04:43 PM PDT 24
Peak memory 195860 kb
Host smart-7be9f0b4-5c7e-4f3b-86e8-027bf96894fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628969284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.628969284
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2481069315
Short name T321
Test name
Test status
Simulation time 3505032051 ps
CPU time 65.59 seconds
Started Aug 02 05:04:37 PM PDT 24
Finished Aug 02 05:05:43 PM PDT 24
Peak memory 199956 kb
Host smart-5c0c46fd-3750-44b9-905c-608a50cbe09e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481069315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2481069315
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.497998892
Short name T237
Test name
Test status
Simulation time 914574582 ps
CPU time 47.57 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:05:23 PM PDT 24
Peak memory 199900 kb
Host smart-88a8b939-56d1-4cbb-a2f6-37490dd61536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497998892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.497998892
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2256223168
Short name T91
Test name
Test status
Simulation time 5925027531 ps
CPU time 897.41 seconds
Started Aug 02 05:04:45 PM PDT 24
Finished Aug 02 05:19:43 PM PDT 24
Peak memory 715896 kb
Host smart-d1a3647a-e3f3-46d4-99d0-a92a9906c0c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256223168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2256223168
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2190583546
Short name T205
Test name
Test status
Simulation time 7658939254 ps
CPU time 126.12 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:06:41 PM PDT 24
Peak memory 199976 kb
Host smart-355f299c-12cb-404c-a3c1-2281cf1ce2a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190583546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2190583546
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1868033553
Short name T382
Test name
Test status
Simulation time 11853155833 ps
CPU time 166.37 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:07:22 PM PDT 24
Peak memory 199936 kb
Host smart-35164b05-43a9-4170-ba2d-2eacb00438a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868033553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1868033553
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.365481332
Short name T296
Test name
Test status
Simulation time 2370230297 ps
CPU time 5.83 seconds
Started Aug 02 05:04:51 PM PDT 24
Finished Aug 02 05:04:57 PM PDT 24
Peak memory 199916 kb
Host smart-2c3fc7eb-7577-4dc1-897c-7849282d0b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365481332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.365481332
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.627621716
Short name T503
Test name
Test status
Simulation time 809396862745 ps
CPU time 543.94 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:13:37 PM PDT 24
Peak memory 199948 kb
Host smart-060e00b2-e98a-4446-a5d0-d03372cd4f49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627621716 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.627621716
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.4070434180
Short name T310
Test name
Test status
Simulation time 20451629222 ps
CPU time 90.59 seconds
Started Aug 02 05:04:29 PM PDT 24
Finished Aug 02 05:06:00 PM PDT 24
Peak memory 200016 kb
Host smart-b1108f36-fc6f-4a8d-a5d6-fe08afa98ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070434180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4070434180
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3720238579
Short name T477
Test name
Test status
Simulation time 41163917 ps
CPU time 0.59 seconds
Started Aug 02 05:04:34 PM PDT 24
Finished Aug 02 05:04:35 PM PDT 24
Peak memory 195892 kb
Host smart-12f6fee7-efe8-4ad7-a74b-ab6760dc0b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720238579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3720238579
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1607255807
Short name T255
Test name
Test status
Simulation time 782923256 ps
CPU time 22.61 seconds
Started Aug 02 05:04:30 PM PDT 24
Finished Aug 02 05:04:52 PM PDT 24
Peak memory 199860 kb
Host smart-75dd792f-030d-4071-9cbc-6ef72290762a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1607255807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1607255807
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3144971109
Short name T273
Test name
Test status
Simulation time 6670984223 ps
CPU time 57.75 seconds
Started Aug 02 05:04:28 PM PDT 24
Finished Aug 02 05:05:25 PM PDT 24
Peak memory 199968 kb
Host smart-583d3d0d-91e2-4894-a5c2-713a5fa8e1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144971109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3144971109
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1627051909
Short name T443
Test name
Test status
Simulation time 2026540923 ps
CPU time 176.64 seconds
Started Aug 02 05:04:32 PM PDT 24
Finished Aug 02 05:07:29 PM PDT 24
Peak memory 446940 kb
Host smart-3b59134a-c45c-4fe3-b7b6-e7191dbd93bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627051909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1627051909
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2558322423
Short name T212
Test name
Test status
Simulation time 5974404172 ps
CPU time 154.35 seconds
Started Aug 02 05:04:41 PM PDT 24
Finished Aug 02 05:07:16 PM PDT 24
Peak memory 199984 kb
Host smart-251b17b0-bb23-4e3c-8b3d-095de1adb890
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558322423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2558322423
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1535108239
Short name T314
Test name
Test status
Simulation time 1175869270 ps
CPU time 62.29 seconds
Started Aug 02 05:04:47 PM PDT 24
Finished Aug 02 05:05:50 PM PDT 24
Peak memory 199832 kb
Host smart-9d73dae3-9e08-42c4-9b1e-f64f3bc07484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535108239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1535108239
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1346147832
Short name T363
Test name
Test status
Simulation time 194693573 ps
CPU time 2.68 seconds
Started Aug 02 05:04:28 PM PDT 24
Finished Aug 02 05:04:31 PM PDT 24
Peak memory 199800 kb
Host smart-0d30c932-5ab8-4ec8-b630-503afda5444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346147832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1346147832
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1117004273
Short name T308
Test name
Test status
Simulation time 10425428646 ps
CPU time 139.54 seconds
Started Aug 02 05:04:27 PM PDT 24
Finished Aug 02 05:06:57 PM PDT 24
Peak memory 199972 kb
Host smart-a8148524-57cc-4697-82db-413a1b53d2fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117004273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1117004273
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3700156804
Short name T327
Test name
Test status
Simulation time 1524412633 ps
CPU time 67.06 seconds
Started Aug 02 05:04:37 PM PDT 24
Finished Aug 02 05:05:44 PM PDT 24
Peak memory 199832 kb
Host smart-a63ecb07-2262-4fa5-95f6-f769013e0b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700156804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3700156804
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3340908149
Short name T490
Test name
Test status
Simulation time 24948218 ps
CPU time 0.57 seconds
Started Aug 02 05:04:23 PM PDT 24
Finished Aug 02 05:04:23 PM PDT 24
Peak memory 195952 kb
Host smart-a77ed2db-ec2b-4df6-b095-d6bdb6128867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340908149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3340908149
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2631490284
Short name T278
Test name
Test status
Simulation time 5936554510 ps
CPU time 80.75 seconds
Started Aug 02 05:04:12 PM PDT 24
Finished Aug 02 05:05:33 PM PDT 24
Peak memory 200024 kb
Host smart-f8c1f3f4-1c9a-4f37-a3d1-be4e299d0764
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2631490284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2631490284
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3367833301
Short name T475
Test name
Test status
Simulation time 1404688695 ps
CPU time 18.11 seconds
Started Aug 02 05:04:24 PM PDT 24
Finished Aug 02 05:04:43 PM PDT 24
Peak memory 199844 kb
Host smart-c629ff04-6751-45ca-8493-9435dda87fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367833301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3367833301
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2753513736
Short name T395
Test name
Test status
Simulation time 9548098136 ps
CPU time 848.25 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:18:17 PM PDT 24
Peak memory 670372 kb
Host smart-62c02beb-873e-4ace-b83c-a313535937c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753513736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2753513736
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1859522160
Short name T116
Test name
Test status
Simulation time 42617103530 ps
CPU time 86.97 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:05:46 PM PDT 24
Peak memory 199944 kb
Host smart-6747f14f-92e8-44c0-a62b-ec55534c6b4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859522160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1859522160
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.429717227
Short name T245
Test name
Test status
Simulation time 2257567871 ps
CPU time 124.63 seconds
Started Aug 02 05:04:11 PM PDT 24
Finished Aug 02 05:06:16 PM PDT 24
Peak memory 199876 kb
Host smart-189c196f-470b-4e27-a5c9-7bfdca38bf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429717227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.429717227
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.909094643
Short name T40
Test name
Test status
Simulation time 277575765 ps
CPU time 0.89 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:04:20 PM PDT 24
Peak memory 218508 kb
Host smart-6ce5e869-5a1a-4493-b3e0-c0c5472c68de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909094643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.909094643
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.220526020
Short name T159
Test name
Test status
Simulation time 187209185 ps
CPU time 7.8 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:04:33 PM PDT 24
Peak memory 199788 kb
Host smart-a623c23b-c8ff-4092-b61a-437ad713b21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220526020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.220526020
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2238175456
Short name T398
Test name
Test status
Simulation time 7841235987 ps
CPU time 95.62 seconds
Started Aug 02 05:04:14 PM PDT 24
Finished Aug 02 05:05:49 PM PDT 24
Peak memory 199920 kb
Host smart-e35d29dc-780a-4edb-a1f4-e9388ac48e49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238175456 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2238175456
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1686839422
Short name T72
Test name
Test status
Simulation time 44601947210 ps
CPU time 227.85 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:08:21 PM PDT 24
Peak memory 208248 kb
Host smart-62e4cb8f-23c4-44a2-9f55-87318e05698a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686839422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1686839422
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2909175344
Short name T259
Test name
Test status
Simulation time 4502649797 ps
CPU time 67.34 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:05:26 PM PDT 24
Peak memory 200040 kb
Host smart-7e457eda-917f-45a7-9c6b-59f95dafeba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2909175344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2909175344
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.2232194061
Short name T478
Test name
Test status
Simulation time 8559155408 ps
CPU time 63.08 seconds
Started Aug 02 05:04:29 PM PDT 24
Finished Aug 02 05:05:32 PM PDT 24
Peak memory 200028 kb
Host smart-efc9b82c-4ef5-4041-b2b3-318ff89dacb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2232194061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2232194061
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.2734465357
Short name T52
Test name
Test status
Simulation time 13957087369 ps
CPU time 87.93 seconds
Started Aug 02 05:04:18 PM PDT 24
Finished Aug 02 05:05:46 PM PDT 24
Peak memory 199976 kb
Host smart-eceb8ee7-e036-457d-92b4-0ee081c74140
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2734465357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2734465357
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.99825776
Short name T213
Test name
Test status
Simulation time 52672233482 ps
CPU time 658.18 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:15:07 PM PDT 24
Peak memory 199932 kb
Host smart-cb0846ec-04c2-4ef5-8507-69a21769cf42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=99825776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.99825776
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3778827269
Short name T260
Test name
Test status
Simulation time 547745085042 ps
CPU time 2314.2 seconds
Started Aug 02 05:04:18 PM PDT 24
Finished Aug 02 05:42:52 PM PDT 24
Peak memory 216284 kb
Host smart-e8b2794a-8afb-4cfd-b49c-9529dfccf012
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3778827269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3778827269
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.839079922
Short name T132
Test name
Test status
Simulation time 650578118 ps
CPU time 27.31 seconds
Started Aug 02 05:04:05 PM PDT 24
Finished Aug 02 05:04:33 PM PDT 24
Peak memory 199904 kb
Host smart-c484323a-d3cf-455c-ad8a-1878ec02c4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839079922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.839079922
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2349730507
Short name T311
Test name
Test status
Simulation time 107319753 ps
CPU time 0.59 seconds
Started Aug 02 05:04:41 PM PDT 24
Finished Aug 02 05:04:42 PM PDT 24
Peak memory 195940 kb
Host smart-46769f21-ee59-4843-bb47-9b646d33d985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349730507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2349730507
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4072314450
Short name T81
Test name
Test status
Simulation time 20795033240 ps
CPU time 68.48 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:05:43 PM PDT 24
Peak memory 216256 kb
Host smart-1b9f3a12-e2f2-4a2a-9611-a94dc3262d56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072314450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4072314450
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3069899156
Short name T226
Test name
Test status
Simulation time 4501711786 ps
CPU time 21.54 seconds
Started Aug 02 05:04:56 PM PDT 24
Finished Aug 02 05:05:18 PM PDT 24
Peak memory 199916 kb
Host smart-f6de7451-7a00-4fac-94c2-ed104b5e0b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069899156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3069899156
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2505747545
Short name T5
Test name
Test status
Simulation time 34362746788 ps
CPU time 1477.15 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:29:13 PM PDT 24
Peak memory 773656 kb
Host smart-e3d5708e-c397-49b1-9a83-c30be81d2ca4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505747545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2505747545
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1988419850
Short name T92
Test name
Test status
Simulation time 9373277253 ps
CPU time 112.83 seconds
Started Aug 02 05:04:35 PM PDT 24
Finished Aug 02 05:06:28 PM PDT 24
Peak memory 199988 kb
Host smart-2820fd8b-a9fb-45bf-983b-6e9176e7b957
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988419850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1988419850
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3399403657
Short name T420
Test name
Test status
Simulation time 819187415 ps
CPU time 42.4 seconds
Started Aug 02 05:04:31 PM PDT 24
Finished Aug 02 05:05:14 PM PDT 24
Peak memory 199848 kb
Host smart-bfd61df2-e497-4534-9684-d5ff0b2b3fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399403657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3399403657
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3214743370
Short name T290
Test name
Test status
Simulation time 351906172 ps
CPU time 8.86 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:04:45 PM PDT 24
Peak memory 199876 kb
Host smart-5c9f386b-d3ec-4d9b-90f5-b9d92805fd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214743370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3214743370
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.324135355
Short name T369
Test name
Test status
Simulation time 1921597355 ps
CPU time 67.34 seconds
Started Aug 02 05:04:34 PM PDT 24
Finished Aug 02 05:05:42 PM PDT 24
Peak memory 199864 kb
Host smart-7ae6d3e2-4ffa-46b2-9dbb-cc80bd4f408e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324135355 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.324135355
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4029991645
Short name T247
Test name
Test status
Simulation time 2367237480 ps
CPU time 103.88 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:06:20 PM PDT 24
Peak memory 199960 kb
Host smart-b877975d-6f42-4130-ae47-caf22aa7db88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029991645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4029991645
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3071888046
Short name T98
Test name
Test status
Simulation time 33594759 ps
CPU time 0.54 seconds
Started Aug 02 05:04:32 PM PDT 24
Finished Aug 02 05:04:33 PM PDT 24
Peak memory 194956 kb
Host smart-6e6daed0-5f67-4e13-9d69-53a9357b858d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071888046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3071888046
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1813583670
Short name T414
Test name
Test status
Simulation time 441885991 ps
CPU time 26.92 seconds
Started Aug 02 05:04:51 PM PDT 24
Finished Aug 02 05:05:18 PM PDT 24
Peak memory 199836 kb
Host smart-d2d06a72-5c1a-4e2a-8fa2-dd87a166e765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813583670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1813583670
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.131989394
Short name T504
Test name
Test status
Simulation time 2794685389 ps
CPU time 35.4 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:05:12 PM PDT 24
Peak memory 199964 kb
Host smart-32de2447-d6a1-4cda-806e-6c7e822858ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131989394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.131989394
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2377433697
Short name T495
Test name
Test status
Simulation time 14773909943 ps
CPU time 1073.95 seconds
Started Aug 02 05:04:38 PM PDT 24
Finished Aug 02 05:22:32 PM PDT 24
Peak memory 763132 kb
Host smart-e3376b29-fffd-4342-bf56-411e54b58619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377433697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2377433697
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1076080941
Short name T265
Test name
Test status
Simulation time 2171464029 ps
CPU time 107.29 seconds
Started Aug 02 05:04:48 PM PDT 24
Finished Aug 02 05:06:35 PM PDT 24
Peak memory 199880 kb
Host smart-9c9f1608-b116-4827-a019-8e94afad0d49
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076080941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1076080941
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1167901383
Short name T241
Test name
Test status
Simulation time 17317788673 ps
CPU time 216.06 seconds
Started Aug 02 05:04:37 PM PDT 24
Finished Aug 02 05:08:14 PM PDT 24
Peak memory 200068 kb
Host smart-bf592fc7-9535-487d-900f-5f4f9d0ce122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167901383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1167901383
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1406459254
Short name T434
Test name
Test status
Simulation time 531091224 ps
CPU time 11.68 seconds
Started Aug 02 05:04:54 PM PDT 24
Finished Aug 02 05:05:06 PM PDT 24
Peak memory 199792 kb
Host smart-0592ec50-3a48-428d-bd4c-e8af9639a4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406459254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1406459254
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1592848552
Short name T86
Test name
Test status
Simulation time 563814187071 ps
CPU time 2629.01 seconds
Started Aug 02 05:04:37 PM PDT 24
Finished Aug 02 05:48:26 PM PDT 24
Peak memory 760920 kb
Host smart-92284153-3918-4779-b634-180631f98b50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592848552 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1592848552
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1840715411
Short name T489
Test name
Test status
Simulation time 3853509279 ps
CPU time 92.49 seconds
Started Aug 02 05:04:54 PM PDT 24
Finished Aug 02 05:06:27 PM PDT 24
Peak memory 199980 kb
Host smart-10ec2bb6-aa47-481a-8372-5800a7b99fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840715411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1840715411
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3919667158
Short name T397
Test name
Test status
Simulation time 29006478 ps
CPU time 0.61 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:04:50 PM PDT 24
Peak memory 196664 kb
Host smart-8160fc6f-1e64-4010-903a-31381e28c18b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919667158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3919667158
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.278267794
Short name T437
Test name
Test status
Simulation time 2368131451 ps
CPU time 62.46 seconds
Started Aug 02 05:04:31 PM PDT 24
Finished Aug 02 05:05:34 PM PDT 24
Peak memory 199984 kb
Host smart-e964d3fa-ec5f-4a8c-9331-2347409919cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278267794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.278267794
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2769277538
Short name T270
Test name
Test status
Simulation time 2905621638 ps
CPU time 40.03 seconds
Started Aug 02 05:04:48 PM PDT 24
Finished Aug 02 05:05:28 PM PDT 24
Peak memory 200000 kb
Host smart-d72a6894-da50-4e3f-b783-bf21de937eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769277538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2769277538
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2452683285
Short name T238
Test name
Test status
Simulation time 5475056136 ps
CPU time 928.79 seconds
Started Aug 02 05:04:40 PM PDT 24
Finished Aug 02 05:20:09 PM PDT 24
Peak memory 698544 kb
Host smart-44159cd9-c853-4292-b96c-dd9b1d0b3f5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452683285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2452683285
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.4284128659
Short name T496
Test name
Test status
Simulation time 42862363774 ps
CPU time 124.09 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:07:02 PM PDT 24
Peak memory 199876 kb
Host smart-2736eb4f-b2d9-47f6-99af-00de7f456316
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284128659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4284128659
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1205821459
Short name T474
Test name
Test status
Simulation time 3289937839 ps
CPU time 53.43 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:05:29 PM PDT 24
Peak memory 199964 kb
Host smart-8dc206f9-f142-4bb7-a379-7d9ce8c2f8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205821459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1205821459
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.60099016
Short name T505
Test name
Test status
Simulation time 322151538 ps
CPU time 13.85 seconds
Started Aug 02 05:04:45 PM PDT 24
Finished Aug 02 05:04:59 PM PDT 24
Peak memory 199824 kb
Host smart-76734c6a-f5e7-46c3-9fe4-e65fecbecc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60099016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.60099016
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3022508997
Short name T87
Test name
Test status
Simulation time 64012139965 ps
CPU time 1185.39 seconds
Started Aug 02 05:04:38 PM PDT 24
Finished Aug 02 05:24:23 PM PDT 24
Peak memory 685680 kb
Host smart-d85df61b-7a70-4bec-9839-fd822b49febd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022508997 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3022508997
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2702434747
Short name T324
Test name
Test status
Simulation time 1131951230 ps
CPU time 48.04 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:05:24 PM PDT 24
Peak memory 199844 kb
Host smart-09e99c10-10bf-4ef5-8ad1-f4bb844f8d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702434747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2702434747
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1044876102
Short name T401
Test name
Test status
Simulation time 12813122 ps
CPU time 0.59 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:04:56 PM PDT 24
Peak memory 195980 kb
Host smart-c8d6c4a8-253e-474d-a755-9719bf34ea75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044876102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1044876102
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.435341306
Short name T473
Test name
Test status
Simulation time 18051792851 ps
CPU time 41.71 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:05:32 PM PDT 24
Peak memory 200032 kb
Host smart-1678d988-49d9-438c-84a6-96572a1c6e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435341306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.435341306
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2703198880
Short name T409
Test name
Test status
Simulation time 2310760786 ps
CPU time 331.58 seconds
Started Aug 02 05:04:43 PM PDT 24
Finished Aug 02 05:10:14 PM PDT 24
Peak memory 674096 kb
Host smart-4c485c57-545b-4a24-9bd5-34c7eae7ab57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703198880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2703198880
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3943695371
Short name T36
Test name
Test status
Simulation time 11475285774 ps
CPU time 194.34 seconds
Started Aug 02 05:04:39 PM PDT 24
Finished Aug 02 05:07:54 PM PDT 24
Peak memory 199956 kb
Host smart-106de01f-977f-4019-a278-a4bac1c6e8cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943695371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3943695371
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.90197549
Short name T166
Test name
Test status
Simulation time 6732656864 ps
CPU time 58.44 seconds
Started Aug 02 05:04:38 PM PDT 24
Finished Aug 02 05:05:37 PM PDT 24
Peak memory 199924 kb
Host smart-b14b8321-da39-4fb7-95eb-95c53e381b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90197549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.90197549
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2770552118
Short name T292
Test name
Test status
Simulation time 1123992079 ps
CPU time 15.28 seconds
Started Aug 02 05:04:46 PM PDT 24
Finished Aug 02 05:05:01 PM PDT 24
Peak memory 199920 kb
Host smart-d90718c8-eb4f-4a89-a071-8c376ec038f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770552118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2770552118
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3399656436
Short name T215
Test name
Test status
Simulation time 78240462631 ps
CPU time 2355.18 seconds
Started Aug 02 05:04:41 PM PDT 24
Finished Aug 02 05:43:57 PM PDT 24
Peak memory 773056 kb
Host smart-03885dfe-e9c3-46be-b793-d5ed0e628644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399656436 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3399656436
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.4180063442
Short name T381
Test name
Test status
Simulation time 7648081388 ps
CPU time 131.39 seconds
Started Aug 02 05:04:40 PM PDT 24
Finished Aug 02 05:06:51 PM PDT 24
Peak memory 199968 kb
Host smart-6c12f28f-f5bf-4e29-86ce-eebd12447b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180063442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.4180063442
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2646891372
Short name T444
Test name
Test status
Simulation time 16028598 ps
CPU time 0.59 seconds
Started Aug 02 05:04:54 PM PDT 24
Finished Aug 02 05:04:54 PM PDT 24
Peak memory 195908 kb
Host smart-75e1094d-d23d-4a36-82e4-686ed7a674dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646891372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2646891372
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.442160072
Short name T349
Test name
Test status
Simulation time 2936846346 ps
CPU time 15.7 seconds
Started Aug 02 05:04:52 PM PDT 24
Finished Aug 02 05:05:08 PM PDT 24
Peak memory 199948 kb
Host smart-72c039d0-2f3b-4465-9ed6-30c3dd0c1430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442160072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.442160072
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1856325529
Short name T230
Test name
Test status
Simulation time 4295114115 ps
CPU time 54.38 seconds
Started Aug 02 05:04:39 PM PDT 24
Finished Aug 02 05:05:33 PM PDT 24
Peak memory 200024 kb
Host smart-2622f1bf-3a23-4893-8b5c-a98b94b26801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856325529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1856325529
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.74802706
Short name T424
Test name
Test status
Simulation time 3190280016 ps
CPU time 494.3 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:13:04 PM PDT 24
Peak memory 501136 kb
Host smart-27751c0a-25d5-4b86-bcf5-dd3a6502cb0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74802706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.74802706
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1729250693
Short name T400
Test name
Test status
Simulation time 3873849667 ps
CPU time 71.31 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:06:01 PM PDT 24
Peak memory 199972 kb
Host smart-0f0f4f70-3074-4bba-8cde-697a4c0fc7f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729250693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1729250693
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1944831519
Short name T283
Test name
Test status
Simulation time 1408076346 ps
CPU time 27.84 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:05:18 PM PDT 24
Peak memory 199828 kb
Host smart-28b9de5a-4523-4296-98e4-7546ebb11604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944831519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1944831519
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2493361546
Short name T222
Test name
Test status
Simulation time 19869425 ps
CPU time 0.89 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:04:56 PM PDT 24
Peak memory 198964 kb
Host smart-c4b3832d-83dd-4bf4-8fd1-af5ce288eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493361546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2493361546
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3393969998
Short name T85
Test name
Test status
Simulation time 29927801532 ps
CPU time 385 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:11:20 PM PDT 24
Peak memory 200004 kb
Host smart-5e75ef40-5698-43d9-a5c7-7ab597b36dec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393969998 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3393969998
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.91352766
Short name T76
Test name
Test status
Simulation time 43029584624 ps
CPU time 116.69 seconds
Started Aug 02 05:04:56 PM PDT 24
Finished Aug 02 05:06:53 PM PDT 24
Peak memory 200008 kb
Host smart-3a4a35d7-a415-4224-ba82-6bb4115b3db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91352766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.91352766
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4139127909
Short name T416
Test name
Test status
Simulation time 40766366 ps
CPU time 0.57 seconds
Started Aug 02 05:04:51 PM PDT 24
Finished Aug 02 05:04:52 PM PDT 24
Peak memory 196624 kb
Host smart-7082775b-ddfa-4aa7-99b7-47aac453ed11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139127909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4139127909
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1458725098
Short name T38
Test name
Test status
Simulation time 230566294 ps
CPU time 12.04 seconds
Started Aug 02 05:04:51 PM PDT 24
Finished Aug 02 05:05:03 PM PDT 24
Peak memory 199812 kb
Host smart-ee966459-b065-4a17-b6f5-44f50b919bc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458725098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1458725098
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2257156229
Short name T339
Test name
Test status
Simulation time 15129882135 ps
CPU time 28.02 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:05:04 PM PDT 24
Peak memory 200036 kb
Host smart-12cd520a-68c1-498a-a5f1-7f4421794c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257156229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2257156229
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.298287975
Short name T386
Test name
Test status
Simulation time 10088236528 ps
CPU time 523.19 seconds
Started Aug 02 05:04:40 PM PDT 24
Finished Aug 02 05:13:23 PM PDT 24
Peak memory 692428 kb
Host smart-5791ef02-0eb9-4114-8b65-aa377ae83f57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=298287975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.298287975
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1278939964
Short name T29
Test name
Test status
Simulation time 4282999787 ps
CPU time 73.33 seconds
Started Aug 02 05:04:54 PM PDT 24
Finished Aug 02 05:06:08 PM PDT 24
Peak memory 199980 kb
Host smart-18f3afaa-b973-4b93-93f6-47229f8dd3db
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278939964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1278939964
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2956679657
Short name T322
Test name
Test status
Simulation time 16205025260 ps
CPU time 108.25 seconds
Started Aug 02 05:04:38 PM PDT 24
Finished Aug 02 05:06:26 PM PDT 24
Peak memory 208196 kb
Host smart-11dea97f-b9c4-452d-99f0-93d1f2918a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956679657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2956679657
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2470199875
Short name T172
Test name
Test status
Simulation time 73091864 ps
CPU time 3.16 seconds
Started Aug 02 05:04:42 PM PDT 24
Finished Aug 02 05:04:45 PM PDT 24
Peak memory 199928 kb
Host smart-24325a67-f9d3-4612-8ff6-9a7763aab96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470199875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2470199875
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1514710600
Short name T450
Test name
Test status
Simulation time 15251807650 ps
CPU time 65.8 seconds
Started Aug 02 05:04:39 PM PDT 24
Finished Aug 02 05:05:45 PM PDT 24
Peak memory 199992 kb
Host smart-1ff5f251-d4e4-4c0a-b6f1-8cf23e92e7e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514710600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1514710600
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1954506610
Short name T345
Test name
Test status
Simulation time 2342439751 ps
CPU time 59.2 seconds
Started Aug 02 05:04:53 PM PDT 24
Finished Aug 02 05:05:52 PM PDT 24
Peak memory 199928 kb
Host smart-87de14cf-7b7e-4836-b5a4-2f579ecaadeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954506610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1954506610
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4170167555
Short name T221
Test name
Test status
Simulation time 50545261 ps
CPU time 0.57 seconds
Started Aug 02 05:04:49 PM PDT 24
Finished Aug 02 05:04:50 PM PDT 24
Peak memory 194920 kb
Host smart-1bec6484-11ad-4f60-b9e5-6df951a678cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170167555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4170167555
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3605813148
Short name T433
Test name
Test status
Simulation time 873297647 ps
CPU time 23.97 seconds
Started Aug 02 05:04:53 PM PDT 24
Finished Aug 02 05:05:17 PM PDT 24
Peak memory 199880 kb
Host smart-cf36f103-ca6a-47c4-8cc1-1a366e85d2d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605813148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3605813148
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.4228663217
Short name T66
Test name
Test status
Simulation time 326943020 ps
CPU time 4.07 seconds
Started Aug 02 05:04:41 PM PDT 24
Finished Aug 02 05:04:45 PM PDT 24
Peak memory 199768 kb
Host smart-e5dbdce4-2ca4-4b51-bf36-5ce5f7271770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228663217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.4228663217
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4180494649
Short name T366
Test name
Test status
Simulation time 6570980252 ps
CPU time 1201.8 seconds
Started Aug 02 05:04:42 PM PDT 24
Finished Aug 02 05:24:44 PM PDT 24
Peak memory 708760 kb
Host smart-1b5c130a-0fa7-40f5-9c8d-274be83263f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180494649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4180494649
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1908675925
Short name T439
Test name
Test status
Simulation time 33439656402 ps
CPU time 100.37 seconds
Started Aug 02 05:04:38 PM PDT 24
Finished Aug 02 05:06:19 PM PDT 24
Peak memory 200000 kb
Host smart-fb2aee77-e752-4c32-ae54-cb0338d99a83
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908675925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1908675925
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3050167765
Short name T295
Test name
Test status
Simulation time 2363978052 ps
CPU time 35.2 seconds
Started Aug 02 05:04:37 PM PDT 24
Finished Aug 02 05:05:13 PM PDT 24
Peak memory 199976 kb
Host smart-23985c08-43ab-4a68-ace7-0faeebc5d9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050167765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3050167765
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1945168907
Short name T368
Test name
Test status
Simulation time 6792202591 ps
CPU time 7.47 seconds
Started Aug 02 05:04:39 PM PDT 24
Finished Aug 02 05:04:47 PM PDT 24
Peak memory 199980 kb
Host smart-c2890dd7-47fd-44d3-b7ac-f38cf0576c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945168907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1945168907
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3270721642
Short name T385
Test name
Test status
Simulation time 181319676359 ps
CPU time 4386.82 seconds
Started Aug 02 05:04:45 PM PDT 24
Finished Aug 02 06:17:52 PM PDT 24
Peak memory 839440 kb
Host smart-a60d439f-bb1b-4cee-b8bd-2b9a921c9960
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270721642 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3270721642
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3324125144
Short name T304
Test name
Test status
Simulation time 4357496532 ps
CPU time 55.13 seconds
Started Aug 02 05:04:49 PM PDT 24
Finished Aug 02 05:05:45 PM PDT 24
Peak memory 199944 kb
Host smart-74e67514-eb84-4264-829b-c8a819bd4ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324125144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3324125144
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2985938475
Short name T251
Test name
Test status
Simulation time 20782298 ps
CPU time 0.55 seconds
Started Aug 02 05:04:40 PM PDT 24
Finished Aug 02 05:04:41 PM PDT 24
Peak memory 195564 kb
Host smart-14983860-7cd7-4e77-9f82-7f6c3e309fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985938475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2985938475
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3074348671
Short name T195
Test name
Test status
Simulation time 2774391997 ps
CPU time 39.01 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:05:29 PM PDT 24
Peak memory 199948 kb
Host smart-9cbfe27a-5a58-47eb-98a1-6cd47a17a55d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074348671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3074348671
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3716343559
Short name T253
Test name
Test status
Simulation time 987524020 ps
CPU time 9.78 seconds
Started Aug 02 05:04:34 PM PDT 24
Finished Aug 02 05:04:44 PM PDT 24
Peak memory 199864 kb
Host smart-ad9d1063-d6b1-4c25-8a9c-b0532db6f3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716343559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3716343559
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3790330293
Short name T160
Test name
Test status
Simulation time 2773473409 ps
CPU time 172.9 seconds
Started Aug 02 05:04:51 PM PDT 24
Finished Aug 02 05:07:44 PM PDT 24
Peak memory 372660 kb
Host smart-77f7b44e-3024-4858-b996-2ed0c0b30b61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790330293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3790330293
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1542366757
Short name T164
Test name
Test status
Simulation time 8935295395 ps
CPU time 80.18 seconds
Started Aug 02 05:04:54 PM PDT 24
Finished Aug 02 05:06:14 PM PDT 24
Peak memory 200012 kb
Host smart-6fef0645-e334-4fa9-ad1e-6b698c653bfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542366757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1542366757
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.260815546
Short name T197
Test name
Test status
Simulation time 118867283786 ps
CPU time 162.99 seconds
Started Aug 02 05:04:49 PM PDT 24
Finished Aug 02 05:07:32 PM PDT 24
Peak memory 208112 kb
Host smart-c11a8ffa-9865-4dfd-9c52-4ee6e86c2507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260815546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.260815546
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.902464583
Short name T233
Test name
Test status
Simulation time 45991105 ps
CPU time 0.86 seconds
Started Aug 02 05:04:43 PM PDT 24
Finished Aug 02 05:04:43 PM PDT 24
Peak memory 199016 kb
Host smart-9c01798a-1421-487e-a569-3940d3f41e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902464583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.902464583
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2810652845
Short name T449
Test name
Test status
Simulation time 123896386512 ps
CPU time 3461.15 seconds
Started Aug 02 05:04:51 PM PDT 24
Finished Aug 02 06:02:33 PM PDT 24
Peak memory 800868 kb
Host smart-60722f7a-7868-4263-8110-610dae1868a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810652845 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2810652845
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.656645058
Short name T89
Test name
Test status
Simulation time 42780075530 ps
CPU time 99.27 seconds
Started Aug 02 05:04:47 PM PDT 24
Finished Aug 02 05:06:26 PM PDT 24
Peak memory 199992 kb
Host smart-374b0057-bacd-4440-adfb-141718a9f4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656645058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.656645058
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2009738222
Short name T97
Test name
Test status
Simulation time 70754749 ps
CPU time 0.56 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:04:51 PM PDT 24
Peak memory 195556 kb
Host smart-80de5b67-6c53-4462-9686-d362d382ed46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009738222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2009738222
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2483958602
Short name T486
Test name
Test status
Simulation time 1734927805 ps
CPU time 25.66 seconds
Started Aug 02 05:04:45 PM PDT 24
Finished Aug 02 05:05:11 PM PDT 24
Peak memory 199832 kb
Host smart-5869c773-8880-41d2-9386-08be085f351c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483958602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2483958602
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.530154330
Short name T289
Test name
Test status
Simulation time 385103739 ps
CPU time 6.57 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:05:04 PM PDT 24
Peak memory 199784 kb
Host smart-d832347f-44ae-4855-bf41-5062001635f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530154330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.530154330
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3825284974
Short name T242
Test name
Test status
Simulation time 8737294065 ps
CPU time 272.1 seconds
Started Aug 02 05:04:53 PM PDT 24
Finished Aug 02 05:09:25 PM PDT 24
Peak memory 375772 kb
Host smart-381c3585-26c5-4f98-9a55-5c7204a32c09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825284974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3825284974
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1725899466
Short name T227
Test name
Test status
Simulation time 4724090526 ps
CPU time 79.14 seconds
Started Aug 02 05:04:39 PM PDT 24
Finished Aug 02 05:06:03 PM PDT 24
Peak memory 199944 kb
Host smart-6c9773db-da6f-4a95-8e78-14a13f8b8283
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725899466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1725899466
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1851340308
Short name T114
Test name
Test status
Simulation time 2790450237 ps
CPU time 154.86 seconds
Started Aug 02 05:04:37 PM PDT 24
Finished Aug 02 05:07:12 PM PDT 24
Peak memory 199972 kb
Host smart-1168275d-3e8b-478c-a505-3f8e485a5efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851340308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1851340308
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1153498941
Short name T417
Test name
Test status
Simulation time 71693314 ps
CPU time 3.48 seconds
Started Aug 02 05:04:38 PM PDT 24
Finished Aug 02 05:04:42 PM PDT 24
Peak memory 199888 kb
Host smart-b8fe8c26-5e87-411a-99b4-81c9452e8236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153498941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1153498941
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2527894374
Short name T84
Test name
Test status
Simulation time 60361102196 ps
CPU time 1007.33 seconds
Started Aug 02 05:04:40 PM PDT 24
Finished Aug 02 05:21:27 PM PDT 24
Peak memory 434888 kb
Host smart-ea1846ed-3bfc-4bc0-85e5-ddcef99de5a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527894374 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2527894374
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1593355770
Short name T286
Test name
Test status
Simulation time 5363229149 ps
CPU time 50.71 seconds
Started Aug 02 05:04:36 PM PDT 24
Finished Aug 02 05:05:27 PM PDT 24
Peak memory 199984 kb
Host smart-c543c004-ef88-4753-ab1b-6eb6761d9e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593355770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1593355770
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.586781988
Short name T203
Test name
Test status
Simulation time 36360144 ps
CPU time 0.58 seconds
Started Aug 02 05:04:56 PM PDT 24
Finished Aug 02 05:04:56 PM PDT 24
Peak memory 195936 kb
Host smart-990cb593-fbeb-4287-9c94-e7c28cac9454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586781988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.586781988
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1611842300
Short name T13
Test name
Test status
Simulation time 6930748443 ps
CPU time 115.68 seconds
Started Aug 02 05:04:59 PM PDT 24
Finished Aug 02 05:06:55 PM PDT 24
Peak memory 208200 kb
Host smart-a7ac167e-2800-4452-94ae-f92d2036d96c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611842300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1611842300
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2395691642
Short name T220
Test name
Test status
Simulation time 3700542712 ps
CPU time 670.07 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:16:10 PM PDT 24
Peak memory 712744 kb
Host smart-28ccc595-f8bd-4180-a1d2-2779679ac083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2395691642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2395691642
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.624730118
Short name T378
Test name
Test status
Simulation time 10219247133 ps
CPU time 27.68 seconds
Started Aug 02 05:05:01 PM PDT 24
Finished Aug 02 05:05:29 PM PDT 24
Peak memory 199948 kb
Host smart-cd2853ea-b874-47bc-bcca-bde142dfb342
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624730118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.624730118
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1378515895
Short name T154
Test name
Test status
Simulation time 2058428366 ps
CPU time 38.23 seconds
Started Aug 02 05:04:51 PM PDT 24
Finished Aug 02 05:05:29 PM PDT 24
Peak memory 199824 kb
Host smart-2ccb7539-1153-485a-b2d8-2bf28815dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378515895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1378515895
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3635882128
Short name T342
Test name
Test status
Simulation time 1877615635 ps
CPU time 14.52 seconds
Started Aug 02 05:04:57 PM PDT 24
Finished Aug 02 05:05:12 PM PDT 24
Peak memory 199936 kb
Host smart-9cb8feb9-9781-449f-a399-41707067fd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635882128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3635882128
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2795638062
Short name T24
Test name
Test status
Simulation time 44529378436 ps
CPU time 716.89 seconds
Started Aug 02 05:04:56 PM PDT 24
Finished Aug 02 05:16:53 PM PDT 24
Peak memory 216340 kb
Host smart-5e45b19c-693b-448f-a7c5-d7bac3360a3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795638062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2795638062
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.686384902
Short name T151
Test name
Test status
Simulation time 4036503532 ps
CPU time 71.46 seconds
Started Aug 02 05:04:51 PM PDT 24
Finished Aug 02 05:06:02 PM PDT 24
Peak memory 199968 kb
Host smart-9d73a79f-6886-4db1-8a51-4c0547111559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686384902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.686384902
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.584284508
Short name T300
Test name
Test status
Simulation time 13376854 ps
CPU time 0.59 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:04:20 PM PDT 24
Peak memory 195868 kb
Host smart-34595b60-d47e-45e4-a65b-01146985beef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584284508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.584284508
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3917720568
Short name T406
Test name
Test status
Simulation time 19297421767 ps
CPU time 54.58 seconds
Started Aug 02 05:04:11 PM PDT 24
Finished Aug 02 05:05:06 PM PDT 24
Peak memory 199928 kb
Host smart-f3d2adbe-5585-4dcf-a7c1-b0d3b059cd6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3917720568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3917720568
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2591446119
Short name T317
Test name
Test status
Simulation time 5874569072 ps
CPU time 18.72 seconds
Started Aug 02 05:04:14 PM PDT 24
Finished Aug 02 05:04:33 PM PDT 24
Peak memory 199864 kb
Host smart-7f8b3105-61e1-4261-8dec-c46b0e230174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591446119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2591446119
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1864030934
Short name T343
Test name
Test status
Simulation time 2952504062 ps
CPU time 437.73 seconds
Started Aug 02 05:04:16 PM PDT 24
Finished Aug 02 05:11:34 PM PDT 24
Peak memory 644864 kb
Host smart-3a2b06c9-c083-4fb6-9c58-0125cff76174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864030934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1864030934
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3759524002
Short name T436
Test name
Test status
Simulation time 6405135664 ps
CPU time 108.01 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:06:14 PM PDT 24
Peak memory 200020 kb
Host smart-ded4c91f-7376-4785-9e17-0d4b33a5bce8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759524002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3759524002
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3289576731
Short name T309
Test name
Test status
Simulation time 86852091359 ps
CPU time 200.65 seconds
Started Aug 02 05:04:16 PM PDT 24
Finished Aug 02 05:07:37 PM PDT 24
Peak memory 199988 kb
Host smart-ec4101a0-6f7e-43bc-bd80-b6737fb0d80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289576731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3289576731
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.38639814
Short name T281
Test name
Test status
Simulation time 991870982 ps
CPU time 8.85 seconds
Started Aug 02 05:04:08 PM PDT 24
Finished Aug 02 05:04:17 PM PDT 24
Peak memory 199892 kb
Host smart-b547c9df-2553-46a2-ba9e-55b09810e3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38639814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.38639814
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2409608021
Short name T6
Test name
Test status
Simulation time 4984910209 ps
CPU time 237.94 seconds
Started Aug 02 05:04:17 PM PDT 24
Finished Aug 02 05:08:15 PM PDT 24
Peak memory 200024 kb
Host smart-4342ef99-9596-4dee-8e7d-f2401eab7bc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409608021 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2409608021
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3669933897
Short name T74
Test name
Test status
Simulation time 53990408995 ps
CPU time 1582.92 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:30:43 PM PDT 24
Peak memory 744108 kb
Host smart-d10dc99e-81fe-429f-a6db-810e7adfee01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3669933897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3669933897
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1438963120
Short name T509
Test name
Test status
Simulation time 5398310891 ps
CPU time 45.27 seconds
Started Aug 02 05:04:22 PM PDT 24
Finished Aug 02 05:05:07 PM PDT 24
Peak memory 200040 kb
Host smart-0621da35-addc-41bd-8eb8-b51372cf355e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1438963120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1438963120
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1631016322
Short name T442
Test name
Test status
Simulation time 19535785906 ps
CPU time 72.39 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:05:32 PM PDT 24
Peak memory 200000 kb
Host smart-d56b52f1-69fc-4d18-a676-58115672044d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1631016322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1631016322
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1321476373
Short name T56
Test name
Test status
Simulation time 8611517739 ps
CPU time 135.83 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:06:35 PM PDT 24
Peak memory 200048 kb
Host smart-8a1830ce-be77-45ba-ae5b-4df6bd3d1d5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1321476373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1321476373
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3119205597
Short name T143
Test name
Test status
Simulation time 164084019665 ps
CPU time 585.75 seconds
Started Aug 02 05:04:11 PM PDT 24
Finished Aug 02 05:13:57 PM PDT 24
Peak memory 199984 kb
Host smart-0a76ad11-0cc0-4c99-bba7-69b347559d99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3119205597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3119205597
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2952062517
Short name T113
Test name
Test status
Simulation time 317781038581 ps
CPU time 2259.76 seconds
Started Aug 02 05:04:07 PM PDT 24
Finished Aug 02 05:41:47 PM PDT 24
Peak memory 215488 kb
Host smart-a406a936-8370-48fa-bebe-e80c1bcfcb06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2952062517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2952062517
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1844179761
Short name T93
Test name
Test status
Simulation time 191513502350 ps
CPU time 2397.51 seconds
Started Aug 02 05:04:23 PM PDT 24
Finished Aug 02 05:44:21 PM PDT 24
Peak memory 216108 kb
Host smart-18e4bd6a-ef9e-4b17-af12-92c08278982b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1844179761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1844179761
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1537586825
Short name T336
Test name
Test status
Simulation time 700218586 ps
CPU time 6.88 seconds
Started Aug 02 05:04:18 PM PDT 24
Finished Aug 02 05:04:25 PM PDT 24
Peak memory 199836 kb
Host smart-4521faa3-668d-4379-91d2-74029f5cfa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537586825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1537586825
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1341417855
Short name T455
Test name
Test status
Simulation time 53664675 ps
CPU time 0.6 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:05:00 PM PDT 24
Peak memory 195828 kb
Host smart-44c14929-48f2-413a-9cd5-6cfda311fb52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341417855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1341417855
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.4157504331
Short name T465
Test name
Test status
Simulation time 4294262907 ps
CPU time 69.73 seconds
Started Aug 02 05:04:57 PM PDT 24
Finished Aug 02 05:06:07 PM PDT 24
Peak memory 199912 kb
Host smart-7f6c9e3b-2c83-440b-b127-8d6f2ec5777a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157504331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.4157504331
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3549451987
Short name T111
Test name
Test status
Simulation time 8199213044 ps
CPU time 51.84 seconds
Started Aug 02 05:04:54 PM PDT 24
Finished Aug 02 05:05:46 PM PDT 24
Peak memory 215568 kb
Host smart-23f34b37-6bae-45f9-9c0e-859467355fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549451987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3549451987
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1425059185
Short name T70
Test name
Test status
Simulation time 4313036577 ps
CPU time 232.19 seconds
Started Aug 02 05:04:52 PM PDT 24
Finished Aug 02 05:08:44 PM PDT 24
Peak memory 642388 kb
Host smart-1009f80c-0b61-4b3d-867d-c417d4ac88f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425059185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1425059185
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.688681939
Short name T393
Test name
Test status
Simulation time 34523621823 ps
CPU time 136.07 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:07:11 PM PDT 24
Peak memory 199904 kb
Host smart-1a642a4e-8891-41da-aae6-5ccfecb830b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688681939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.688681939
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2156051690
Short name T277
Test name
Test status
Simulation time 5614778623 ps
CPU time 81.33 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:06:16 PM PDT 24
Peak memory 216264 kb
Host smart-d7cc18cb-4b46-4450-9e1e-b88edaf9a76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156051690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2156051690
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1962105819
Short name T196
Test name
Test status
Simulation time 185171831 ps
CPU time 8.08 seconds
Started Aug 02 05:04:45 PM PDT 24
Finished Aug 02 05:04:53 PM PDT 24
Peak memory 199912 kb
Host smart-5ec3d126-fb81-4ebd-a228-f1eaf42bb5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962105819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1962105819
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1236117536
Short name T82
Test name
Test status
Simulation time 111948993856 ps
CPU time 2525.05 seconds
Started Aug 02 05:04:47 PM PDT 24
Finished Aug 02 05:46:57 PM PDT 24
Peak memory 762744 kb
Host smart-82a13421-0574-4eee-b217-03d78ed93813
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236117536 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1236117536
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1902450952
Short name T454
Test name
Test status
Simulation time 2308004100 ps
CPU time 32.63 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:05:23 PM PDT 24
Peak memory 199988 kb
Host smart-fa4ab0ca-5f62-454a-8062-65053d98bc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902450952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1902450952
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2084715710
Short name T178
Test name
Test status
Simulation time 28678568 ps
CPU time 0.61 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:04:59 PM PDT 24
Peak memory 195944 kb
Host smart-5daf92b1-fb92-40b7-bf63-5cc4de3a405f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084715710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2084715710
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.131696744
Short name T186
Test name
Test status
Simulation time 49866077 ps
CPU time 2.78 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:05:01 PM PDT 24
Peak memory 199828 kb
Host smart-9339641b-1bc1-4e4c-b211-377925d3155d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131696744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.131696744
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2155449910
Short name T161
Test name
Test status
Simulation time 7140109258 ps
CPU time 48.44 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:05:47 PM PDT 24
Peak memory 199868 kb
Host smart-96defc61-3ce6-405b-b4fd-91e488d09104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155449910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2155449910
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3584399325
Short name T459
Test name
Test status
Simulation time 9502605043 ps
CPU time 912.1 seconds
Started Aug 02 05:04:53 PM PDT 24
Finished Aug 02 05:20:05 PM PDT 24
Peak memory 737256 kb
Host smart-e702256c-d95e-4970-8c42-aea39b7b77b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584399325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3584399325
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3922980918
Short name T181
Test name
Test status
Simulation time 2906681734 ps
CPU time 159.62 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:07:40 PM PDT 24
Peak memory 199936 kb
Host smart-7826cde7-ebf6-4e4d-8d33-c59c2739d1e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922980918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3922980918
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3034371326
Short name T452
Test name
Test status
Simulation time 5086156193 ps
CPU time 38.24 seconds
Started Aug 02 05:04:44 PM PDT 24
Finished Aug 02 05:05:22 PM PDT 24
Peak memory 199948 kb
Host smart-6b26a546-c598-4145-a7e0-6ec2cc54dfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034371326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3034371326
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3855027038
Short name T448
Test name
Test status
Simulation time 10059916076 ps
CPU time 9.77 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:05:00 PM PDT 24
Peak memory 199980 kb
Host smart-ce8a3e5c-b6e4-4f3c-a899-8214ce02f249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855027038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3855027038
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.4046014753
Short name T447
Test name
Test status
Simulation time 69466286823 ps
CPU time 1527.49 seconds
Started Aug 02 05:05:01 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 677360 kb
Host smart-0658e71b-c1b2-4c83-b5b0-747aa103d798
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046014753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.4046014753
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1799554412
Short name T88
Test name
Test status
Simulation time 5014821274 ps
CPU time 104 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:06:44 PM PDT 24
Peak memory 199928 kb
Host smart-3c0427e4-9f50-4ff3-bafc-54725fb0cdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799554412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1799554412
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2794298037
Short name T284
Test name
Test status
Simulation time 28067379 ps
CPU time 0.61 seconds
Started Aug 02 05:04:56 PM PDT 24
Finished Aug 02 05:04:57 PM PDT 24
Peak memory 196628 kb
Host smart-fbdc9a5c-360c-4e07-a81f-10775a280c6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794298037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2794298037
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3015675137
Short name T32
Test name
Test status
Simulation time 504797459 ps
CPU time 14.04 seconds
Started Aug 02 05:04:53 PM PDT 24
Finished Aug 02 05:05:07 PM PDT 24
Peak memory 199852 kb
Host smart-bd206b1d-c57e-4368-8644-a0dd3828dea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015675137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3015675137
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1110263611
Short name T302
Test name
Test status
Simulation time 9438630928 ps
CPU time 66.84 seconds
Started Aug 02 05:04:53 PM PDT 24
Finished Aug 02 05:06:00 PM PDT 24
Peak memory 208220 kb
Host smart-e26e220c-3fec-4f18-a7de-3183d1af7eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110263611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1110263611
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3778365848
Short name T80
Test name
Test status
Simulation time 2772944928 ps
CPU time 550.92 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 719020 kb
Host smart-7bb01e25-68ca-40b7-9aa1-02f6dcb00327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778365848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3778365848
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3161449810
Short name T307
Test name
Test status
Simulation time 36603944353 ps
CPU time 150.68 seconds
Started Aug 02 05:04:59 PM PDT 24
Finished Aug 02 05:07:29 PM PDT 24
Peak memory 199936 kb
Host smart-79794e28-b434-4b4b-bff3-ff21b721058b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161449810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3161449810
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3662204391
Short name T153
Test name
Test status
Simulation time 465291030 ps
CPU time 9.35 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:05:05 PM PDT 24
Peak memory 199884 kb
Host smart-225cfcc2-f390-446d-8db9-621f3a92f49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662204391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3662204391
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4276543992
Short name T355
Test name
Test status
Simulation time 3022470566 ps
CPU time 11.26 seconds
Started Aug 02 05:04:56 PM PDT 24
Finished Aug 02 05:05:07 PM PDT 24
Peak memory 199980 kb
Host smart-cc21aa8d-d8e3-48d8-a384-7db2b1d90d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276543992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4276543992
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.167625494
Short name T90
Test name
Test status
Simulation time 8196869088 ps
CPU time 408.25 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:11:47 PM PDT 24
Peak memory 634312 kb
Host smart-6c6afa5b-b557-4fed-99cb-543697114803
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167625494 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.167625494
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2910193069
Short name T340
Test name
Test status
Simulation time 348455121 ps
CPU time 16.72 seconds
Started Aug 02 05:04:54 PM PDT 24
Finished Aug 02 05:05:10 PM PDT 24
Peak memory 199800 kb
Host smart-a00d60a0-f3e0-4c2e-b20e-2ed763186fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910193069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2910193069
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4209536434
Short name T464
Test name
Test status
Simulation time 28002605 ps
CPU time 0.55 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:04:56 PM PDT 24
Peak memory 195516 kb
Host smart-005b51ff-658e-4e95-9e6d-da7cd05df925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209536434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4209536434
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1235728611
Short name T193
Test name
Test status
Simulation time 3555407057 ps
CPU time 18.29 seconds
Started Aug 02 05:04:59 PM PDT 24
Finished Aug 02 05:05:17 PM PDT 24
Peak memory 199996 kb
Host smart-b6f2dc35-a328-4809-a86a-6ee7abb2c464
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235728611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1235728611
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1645583502
Short name T45
Test name
Test status
Simulation time 1203289753 ps
CPU time 67.03 seconds
Started Aug 02 05:04:56 PM PDT 24
Finished Aug 02 05:06:03 PM PDT 24
Peak memory 199904 kb
Host smart-8fe88f0a-f6bb-4fad-9ecd-5db1d7035d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645583502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1645583502
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2848164592
Short name T507
Test name
Test status
Simulation time 20155521360 ps
CPU time 889.81 seconds
Started Aug 02 05:04:51 PM PDT 24
Finished Aug 02 05:19:41 PM PDT 24
Peak memory 714040 kb
Host smart-a9e6952a-a4a3-42eb-9aeb-e2c75a55a4bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2848164592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2848164592
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.860200851
Short name T438
Test name
Test status
Simulation time 19394191905 ps
CPU time 157.12 seconds
Started Aug 02 05:04:49 PM PDT 24
Finished Aug 02 05:07:27 PM PDT 24
Peak memory 200008 kb
Host smart-50dab88e-9f00-4b12-8129-27f657e4bf54
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860200851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.860200851
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2299393331
Short name T361
Test name
Test status
Simulation time 6490076925 ps
CPU time 184.5 seconds
Started Aug 02 05:04:56 PM PDT 24
Finished Aug 02 05:08:01 PM PDT 24
Peak memory 200024 kb
Host smart-5153fbe7-b53a-4c22-a691-0f9b6a4a22f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299393331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2299393331
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3137787608
Short name T470
Test name
Test status
Simulation time 1031759829 ps
CPU time 6.88 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:05:05 PM PDT 24
Peak memory 199892 kb
Host smart-5ea9e522-2db4-4492-b489-f23b2eaca98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137787608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3137787608
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.4135604959
Short name T487
Test name
Test status
Simulation time 36742110223 ps
CPU time 460.49 seconds
Started Aug 02 05:05:01 PM PDT 24
Finished Aug 02 05:12:42 PM PDT 24
Peak memory 215924 kb
Host smart-2b27d1a0-0d12-4738-a46b-309e42b574d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135604959 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.4135604959
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.578402572
Short name T514
Test name
Test status
Simulation time 3955843756 ps
CPU time 13.33 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:05:13 PM PDT 24
Peak memory 199968 kb
Host smart-cbdb1150-9124-4ce7-80bc-f609a4031626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578402572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.578402572
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2612394741
Short name T199
Test name
Test status
Simulation time 72509430 ps
CPU time 0.56 seconds
Started Aug 02 05:05:02 PM PDT 24
Finished Aug 02 05:05:02 PM PDT 24
Peak memory 195472 kb
Host smart-915cfb1d-c470-491d-8d1a-2a188e194736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612394741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2612394741
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.661097028
Short name T318
Test name
Test status
Simulation time 488166358 ps
CPU time 13.84 seconds
Started Aug 02 05:05:03 PM PDT 24
Finished Aug 02 05:05:17 PM PDT 24
Peak memory 199836 kb
Host smart-4038d745-7f3d-4b63-a820-eef3fda701af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661097028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.661097028
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1346523025
Short name T219
Test name
Test status
Simulation time 19178897 ps
CPU time 0.71 seconds
Started Aug 02 05:04:53 PM PDT 24
Finished Aug 02 05:04:54 PM PDT 24
Peak memory 197288 kb
Host smart-42465e73-29e4-4433-ae69-040f6bcd627d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346523025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1346523025
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2081026764
Short name T246
Test name
Test status
Simulation time 2776805924 ps
CPU time 448 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:12:23 PM PDT 24
Peak memory 635168 kb
Host smart-ee863ad8-e656-40ce-9c7f-294aa3a74b8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081026764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2081026764
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2692490220
Short name T119
Test name
Test status
Simulation time 2497155615 ps
CPU time 38.13 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:05:38 PM PDT 24
Peak memory 199972 kb
Host smart-b0793937-0a01-4fc4-ac80-e88ea6b5e470
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692490220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2692490220
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3381938228
Short name T184
Test name
Test status
Simulation time 3869045895 ps
CPU time 55.84 seconds
Started Aug 02 05:04:50 PM PDT 24
Finished Aug 02 05:05:46 PM PDT 24
Peak memory 199988 kb
Host smart-6e99a0a5-c01b-45bc-bee8-2590fb4c6b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381938228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3381938228
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.4118429844
Short name T276
Test name
Test status
Simulation time 835442429 ps
CPU time 9.91 seconds
Started Aug 02 05:05:01 PM PDT 24
Finished Aug 02 05:05:11 PM PDT 24
Peak memory 199896 kb
Host smart-76c7b855-1b78-4fff-9431-1a8a47c448f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118429844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.4118429844
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3087863948
Short name T20
Test name
Test status
Simulation time 11445891649 ps
CPU time 1189.53 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:24:44 PM PDT 24
Peak memory 714408 kb
Host smart-c22224db-91c9-47f4-9f45-44e87aff5789
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087863948 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3087863948
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3425069255
Short name T516
Test name
Test status
Simulation time 385438289 ps
CPU time 3.81 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:05:02 PM PDT 24
Peak memory 199836 kb
Host smart-8a37b48e-2e86-4cac-97b4-8fb149cc9e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425069255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3425069255
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3940772456
Short name T445
Test name
Test status
Simulation time 11457011 ps
CPU time 0.59 seconds
Started Aug 02 05:04:59 PM PDT 24
Finished Aug 02 05:05:00 PM PDT 24
Peak memory 194848 kb
Host smart-964e2956-fd3a-4a5a-9bea-ad1aedd3e7e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940772456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3940772456
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.882471540
Short name T46
Test name
Test status
Simulation time 1441441237 ps
CPU time 44 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:05:44 PM PDT 24
Peak memory 199904 kb
Host smart-b1bf529e-40b9-4207-aea4-148a2dd290c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=882471540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.882471540
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2757284796
Short name T341
Test name
Test status
Simulation time 521881585 ps
CPU time 10.13 seconds
Started Aug 02 05:05:04 PM PDT 24
Finished Aug 02 05:05:14 PM PDT 24
Peak memory 199840 kb
Host smart-add11a3e-63a2-4b43-813b-3019fc5d8194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757284796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2757284796
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2390865505
Short name T231
Test name
Test status
Simulation time 3276089812 ps
CPU time 536.32 seconds
Started Aug 02 05:04:57 PM PDT 24
Finished Aug 02 05:13:53 PM PDT 24
Peak memory 678660 kb
Host smart-95d43ddc-a94f-436b-ae06-30c1ca7f9111
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390865505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2390865505
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2264135324
Short name T467
Test name
Test status
Simulation time 9619170620 ps
CPU time 173.41 seconds
Started Aug 02 05:05:05 PM PDT 24
Finished Aug 02 05:07:59 PM PDT 24
Peak memory 200060 kb
Host smart-9dabf4ad-a6ce-41cf-9fa9-277fbf7562cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264135324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2264135324
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.167745634
Short name T408
Test name
Test status
Simulation time 12103807233 ps
CPU time 220.55 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:08:41 PM PDT 24
Peak memory 199980 kb
Host smart-0594f876-464f-4107-9a60-60f45fcc74f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167745634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.167745634
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1174187369
Short name T266
Test name
Test status
Simulation time 895750183 ps
CPU time 2.03 seconds
Started Aug 02 05:05:04 PM PDT 24
Finished Aug 02 05:05:07 PM PDT 24
Peak memory 199852 kb
Host smart-0d5db76b-608b-4d79-a437-70945ab6ca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174187369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1174187369
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2488717925
Short name T34
Test name
Test status
Simulation time 5925812783 ps
CPU time 69.83 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:06:08 PM PDT 24
Peak memory 199908 kb
Host smart-633e1c9c-ecda-4ca8-874e-74bb4d3a2685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488717925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2488717925
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3414778865
Short name T225
Test name
Test status
Simulation time 23441619 ps
CPU time 0.63 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:04:56 PM PDT 24
Peak memory 195948 kb
Host smart-f047d4e8-0412-474e-9c68-65e15bd97a0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414778865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3414778865
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2635447463
Short name T272
Test name
Test status
Simulation time 1258837787 ps
CPU time 73.13 seconds
Started Aug 02 05:05:03 PM PDT 24
Finished Aug 02 05:06:17 PM PDT 24
Peak memory 199876 kb
Host smart-7e864e42-8a9b-45f1-a5c6-b2bc2c6a1681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2635447463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2635447463
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2206659128
Short name T75
Test name
Test status
Simulation time 4934350638 ps
CPU time 24.03 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:05:24 PM PDT 24
Peak memory 200008 kb
Host smart-246ce02e-3b7b-4bb2-a248-91c70128c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206659128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2206659128
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1336398394
Short name T429
Test name
Test status
Simulation time 3976547258 ps
CPU time 338.07 seconds
Started Aug 02 05:04:54 PM PDT 24
Finished Aug 02 05:10:32 PM PDT 24
Peak memory 504208 kb
Host smart-d2959970-f790-4528-88b0-40eaf44244b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1336398394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1336398394
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3443940863
Short name T269
Test name
Test status
Simulation time 5302712936 ps
CPU time 59.88 seconds
Started Aug 02 05:05:05 PM PDT 24
Finished Aug 02 05:06:05 PM PDT 24
Peak memory 200068 kb
Host smart-9c9bcfd2-3f76-4188-9f1e-9aead44f6589
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443940863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3443940863
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2258808371
Short name T162
Test name
Test status
Simulation time 4080484275 ps
CPU time 54.33 seconds
Started Aug 02 05:05:09 PM PDT 24
Finished Aug 02 05:06:03 PM PDT 24
Peak memory 199928 kb
Host smart-4c46218d-86ee-41fe-bd15-7f19a0c1fae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258808371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2258808371
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.4065945192
Short name T330
Test name
Test status
Simulation time 74565993 ps
CPU time 1.29 seconds
Started Aug 02 05:04:56 PM PDT 24
Finished Aug 02 05:04:58 PM PDT 24
Peak memory 199808 kb
Host smart-82140ce8-85a6-4587-b676-89c146d181cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065945192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.4065945192
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.291761497
Short name T144
Test name
Test status
Simulation time 89684985309 ps
CPU time 1371.44 seconds
Started Aug 02 05:05:01 PM PDT 24
Finished Aug 02 05:27:53 PM PDT 24
Peak memory 731384 kb
Host smart-f2d095eb-fae8-44b7-b1be-9525fb5113bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291761497 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.291761497
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.4268191430
Short name T333
Test name
Test status
Simulation time 2655922743 ps
CPU time 26.07 seconds
Started Aug 02 05:04:55 PM PDT 24
Finished Aug 02 05:05:22 PM PDT 24
Peak memory 199884 kb
Host smart-fed991df-3ce5-40e2-876f-d1bfb5f2414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268191430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.4268191430
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.123318123
Short name T471
Test name
Test status
Simulation time 50869371 ps
CPU time 0.59 seconds
Started Aug 02 05:05:03 PM PDT 24
Finished Aug 02 05:05:03 PM PDT 24
Peak memory 195564 kb
Host smart-bccf0834-80c2-4d1c-90be-723521b6d331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123318123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.123318123
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1964928651
Short name T187
Test name
Test status
Simulation time 894507812 ps
CPU time 53.79 seconds
Started Aug 02 05:05:03 PM PDT 24
Finished Aug 02 05:05:57 PM PDT 24
Peak memory 199748 kb
Host smart-b03bebe7-500b-4ee5-a245-f3ef182c59c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964928651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1964928651
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.696697147
Short name T291
Test name
Test status
Simulation time 9144815023 ps
CPU time 44.15 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:05:44 PM PDT 24
Peak memory 200064 kb
Host smart-5f489fb8-1f98-48e1-96c0-52b31940e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696697147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.696697147
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3016748042
Short name T354
Test name
Test status
Simulation time 418767758 ps
CPU time 94.97 seconds
Started Aug 02 05:04:59 PM PDT 24
Finished Aug 02 05:06:34 PM PDT 24
Peak memory 439520 kb
Host smart-c6f9d106-03cd-48a4-9620-ef3bd3dbb625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3016748042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3016748042
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2421237246
Short name T229
Test name
Test status
Simulation time 4835426636 ps
CPU time 199.91 seconds
Started Aug 02 05:05:01 PM PDT 24
Finished Aug 02 05:08:21 PM PDT 24
Peak memory 199884 kb
Host smart-49c5a4c9-6904-4014-a7e6-31bc2b8960c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421237246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2421237246
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1882559744
Short name T145
Test name
Test status
Simulation time 54098057233 ps
CPU time 170.02 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:07:50 PM PDT 24
Peak memory 200036 kb
Host smart-0c7bb87a-aa81-4088-a116-3ad7aa159560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882559744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1882559744
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.105921550
Short name T458
Test name
Test status
Simulation time 190684643 ps
CPU time 9.41 seconds
Started Aug 02 05:05:02 PM PDT 24
Finished Aug 02 05:05:12 PM PDT 24
Peak memory 199820 kb
Host smart-325b4cea-7d59-49d0-b312-06b219db1dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105921550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.105921550
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2129419891
Short name T149
Test name
Test status
Simulation time 28888478242 ps
CPU time 3141.05 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:57:22 PM PDT 24
Peak memory 784816 kb
Host smart-96390672-9ce8-4f0c-b9be-c0942a166532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129419891 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2129419891
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.585810853
Short name T174
Test name
Test status
Simulation time 35390706869 ps
CPU time 109.24 seconds
Started Aug 02 05:04:59 PM PDT 24
Finished Aug 02 05:06:49 PM PDT 24
Peak memory 200060 kb
Host smart-20d07b89-c59a-4b14-aeb2-89acd2d3c941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585810853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.585810853
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2630568167
Short name T155
Test name
Test status
Simulation time 11449349 ps
CPU time 0.58 seconds
Started Aug 02 05:04:59 PM PDT 24
Finished Aug 02 05:05:00 PM PDT 24
Peak memory 194908 kb
Host smart-22c25949-5f9b-4229-93af-072804a6866f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630568167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2630568167
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.323163501
Short name T268
Test name
Test status
Simulation time 1672514151 ps
CPU time 99.37 seconds
Started Aug 02 05:05:02 PM PDT 24
Finished Aug 02 05:06:42 PM PDT 24
Peak memory 199776 kb
Host smart-06438edf-a93e-49dc-9654-e7c0d0d1b767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323163501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.323163501
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3833175743
Short name T49
Test name
Test status
Simulation time 10832392901 ps
CPU time 34.8 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:05:35 PM PDT 24
Peak memory 200008 kb
Host smart-5adf2fef-e421-4da8-94f9-264d4b8b9bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833175743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3833175743
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.351111645
Short name T35
Test name
Test status
Simulation time 3699816285 ps
CPU time 617.74 seconds
Started Aug 02 05:05:01 PM PDT 24
Finished Aug 02 05:15:19 PM PDT 24
Peak memory 670448 kb
Host smart-08f0a03d-58bf-4f7c-b39e-7855ddcd80a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351111645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.351111645
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.720872732
Short name T303
Test name
Test status
Simulation time 15899366967 ps
CPU time 206.15 seconds
Started Aug 02 05:04:54 PM PDT 24
Finished Aug 02 05:08:21 PM PDT 24
Peak memory 200000 kb
Host smart-b03d3f96-444d-48b2-b2ed-af450b04e3ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720872732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.720872732
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2230388470
Short name T373
Test name
Test status
Simulation time 14696397801 ps
CPU time 197.72 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:08:16 PM PDT 24
Peak memory 200044 kb
Host smart-bb8b3897-34d8-490d-88d0-a6ebb9f2f4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230388470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2230388470
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3656694485
Short name T200
Test name
Test status
Simulation time 48755487 ps
CPU time 0.94 seconds
Started Aug 02 05:04:59 PM PDT 24
Finished Aug 02 05:05:00 PM PDT 24
Peak memory 199772 kb
Host smart-e1ccd0a9-ef8e-42f6-a33c-5e920aca2147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656694485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3656694485
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3440268739
Short name T48
Test name
Test status
Simulation time 127152841412 ps
CPU time 5356.11 seconds
Started Aug 02 05:05:01 PM PDT 24
Finished Aug 02 06:34:17 PM PDT 24
Peak memory 884520 kb
Host smart-a19e95eb-ca7a-41b4-81f6-649558144c9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440268739 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3440268739
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2959727580
Short name T152
Test name
Test status
Simulation time 399289971 ps
CPU time 4.76 seconds
Started Aug 02 05:04:58 PM PDT 24
Finished Aug 02 05:05:03 PM PDT 24
Peak memory 199820 kb
Host smart-7299cde8-91e9-4e79-997b-fd3d7c525edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959727580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2959727580
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1649419306
Short name T194
Test name
Test status
Simulation time 14640286 ps
CPU time 0.61 seconds
Started Aug 02 05:05:05 PM PDT 24
Finished Aug 02 05:05:06 PM PDT 24
Peak memory 195936 kb
Host smart-c2fbdb8b-573e-4523-9331-6dfc8dd22215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649419306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1649419306
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.4040149846
Short name T360
Test name
Test status
Simulation time 164265983 ps
CPU time 9.27 seconds
Started Aug 02 05:04:59 PM PDT 24
Finished Aug 02 05:05:08 PM PDT 24
Peak memory 199744 kb
Host smart-abafdc52-1fd5-4fd0-b320-97b158b92931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040149846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.4040149846
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1440927257
Short name T282
Test name
Test status
Simulation time 4079452340 ps
CPU time 58.99 seconds
Started Aug 02 05:05:02 PM PDT 24
Finished Aug 02 05:06:02 PM PDT 24
Peak memory 200008 kb
Host smart-bd4de6c7-c450-4d62-9f21-757a1b6f86cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440927257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1440927257
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.323728815
Short name T367
Test name
Test status
Simulation time 1088414313 ps
CPU time 199.72 seconds
Started Aug 02 05:05:02 PM PDT 24
Finished Aug 02 05:08:21 PM PDT 24
Peak memory 474528 kb
Host smart-3ada4ab9-d007-4e91-8265-93719a2fe520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323728815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.323728815
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1988900327
Short name T312
Test name
Test status
Simulation time 3099746763 ps
CPU time 135.47 seconds
Started Aug 02 05:05:02 PM PDT 24
Finished Aug 02 05:07:18 PM PDT 24
Peak memory 199976 kb
Host smart-c88840bc-f7c3-4b52-bf6a-6c13f5f1760a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988900327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1988900327
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3721695430
Short name T356
Test name
Test status
Simulation time 17429850160 ps
CPU time 71.5 seconds
Started Aug 02 05:05:00 PM PDT 24
Finished Aug 02 05:06:11 PM PDT 24
Peak memory 200232 kb
Host smart-55e98b64-46ba-4c41-8d7b-afc05411a92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721695430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3721695430
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1209007832
Short name T394
Test name
Test status
Simulation time 859564606 ps
CPU time 14.49 seconds
Started Aug 02 05:05:03 PM PDT 24
Finished Aug 02 05:05:17 PM PDT 24
Peak memory 199820 kb
Host smart-19641f24-108a-423a-a717-0a84e9e05ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209007832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1209007832
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1382917775
Short name T204
Test name
Test status
Simulation time 1063199703 ps
CPU time 17.68 seconds
Started Aug 02 05:05:04 PM PDT 24
Finished Aug 02 05:05:21 PM PDT 24
Peak memory 199868 kb
Host smart-de2ad278-4bfd-43e5-902a-1fbe8c135331
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382917775 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1382917775
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3531219078
Short name T502
Test name
Test status
Simulation time 6656637111 ps
CPU time 56.57 seconds
Started Aug 02 05:05:05 PM PDT 24
Finished Aug 02 05:06:01 PM PDT 24
Peak memory 199984 kb
Host smart-dbfeb395-0cc0-47d3-8557-22bf25e383d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531219078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3531219078
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3536252061
Short name T55
Test name
Test status
Simulation time 50092667 ps
CPU time 0.56 seconds
Started Aug 02 05:04:30 PM PDT 24
Finished Aug 02 05:04:31 PM PDT 24
Peak memory 194848 kb
Host smart-c90d376e-321a-4a8d-b808-a6738cdda1fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536252061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3536252061
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3799454639
Short name T301
Test name
Test status
Simulation time 2401145985 ps
CPU time 43.65 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:05:03 PM PDT 24
Peak memory 200016 kb
Host smart-b5c2bfe5-d1ff-4a52-a961-040411f040ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799454639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3799454639
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2471995767
Short name T217
Test name
Test status
Simulation time 6224304941 ps
CPU time 253.04 seconds
Started Aug 02 05:04:11 PM PDT 24
Finished Aug 02 05:08:24 PM PDT 24
Peak memory 604344 kb
Host smart-2f1db7c8-7271-48bb-ae60-7c1c1fd4fc2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2471995767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2471995767
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.4006760477
Short name T364
Test name
Test status
Simulation time 78321263019 ps
CPU time 251.53 seconds
Started Aug 02 05:04:23 PM PDT 24
Finished Aug 02 05:08:35 PM PDT 24
Peak memory 200036 kb
Host smart-c4df1a64-21fb-4c01-b9f4-afe3eb706c47
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006760477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.4006760477
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2791025470
Short name T190
Test name
Test status
Simulation time 3425519106 ps
CPU time 54.98 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:05:28 PM PDT 24
Peak memory 216144 kb
Host smart-3e0f75dd-26c7-40b1-bdf6-ae868a7e1ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791025470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2791025470
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1897720579
Short name T58
Test name
Test status
Simulation time 83947234 ps
CPU time 1.02 seconds
Started Aug 02 05:04:14 PM PDT 24
Finished Aug 02 05:04:15 PM PDT 24
Peak memory 219608 kb
Host smart-bee7b8ad-acfc-4560-a540-3196663d07b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897720579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1897720579
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3872292630
Short name T128
Test name
Test status
Simulation time 2266492342 ps
CPU time 9.82 seconds
Started Aug 02 05:04:15 PM PDT 24
Finished Aug 02 05:04:24 PM PDT 24
Peak memory 199924 kb
Host smart-78dcfea7-229b-4d29-a035-a0661652e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872292630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3872292630
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3501626502
Short name T506
Test name
Test status
Simulation time 323422145938 ps
CPU time 4209.15 seconds
Started Aug 02 05:04:23 PM PDT 24
Finished Aug 02 06:14:33 PM PDT 24
Peak memory 833552 kb
Host smart-bbed48cd-39d0-48fd-a90e-2b09b7590305
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501626502 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3501626502
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3315684999
Short name T14
Test name
Test status
Simulation time 189971255907 ps
CPU time 719.29 seconds
Started Aug 02 05:04:22 PM PDT 24
Finished Aug 02 05:16:21 PM PDT 24
Peak memory 216148 kb
Host smart-20a380b6-9347-4ada-a6bf-42af004fbe8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3315684999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3315684999
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.996285261
Short name T179
Test name
Test status
Simulation time 1659345115 ps
CPU time 69.91 seconds
Started Aug 02 05:04:20 PM PDT 24
Finished Aug 02 05:05:30 PM PDT 24
Peak memory 199876 kb
Host smart-1d184043-3211-4f52-8a9e-8fb6bbbabe76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=996285261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.996285261
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.3509847534
Short name T165
Test name
Test status
Simulation time 13567667511 ps
CPU time 70.12 seconds
Started Aug 02 05:04:21 PM PDT 24
Finished Aug 02 05:05:31 PM PDT 24
Peak memory 200008 kb
Host smart-03f7e5a8-04d7-4a7b-897c-f6a8d37f69a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3509847534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3509847534
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2184892296
Short name T425
Test name
Test status
Simulation time 3102023968 ps
CPU time 119.52 seconds
Started Aug 02 05:04:24 PM PDT 24
Finished Aug 02 05:06:24 PM PDT 24
Peak memory 199912 kb
Host smart-d84d5300-00e0-4a7e-a581-fa159af4ec26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2184892296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2184892296
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.4036367028
Short name T481
Test name
Test status
Simulation time 421168731042 ps
CPU time 706.19 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:16:12 PM PDT 24
Peak memory 199936 kb
Host smart-11f698ca-2474-487f-8105-8ade55406a37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4036367028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.4036367028
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.802703955
Short name T453
Test name
Test status
Simulation time 473330144756 ps
CPU time 2324.98 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:43:04 PM PDT 24
Peak memory 216412 kb
Host smart-7dd6bf61-acea-4094-bc7d-99f3c23416be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=802703955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.802703955
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.175220210
Short name T493
Test name
Test status
Simulation time 836458313605 ps
CPU time 2535.33 seconds
Started Aug 02 05:04:24 PM PDT 24
Finished Aug 02 05:46:40 PM PDT 24
Peak memory 216080 kb
Host smart-557ee683-bfd3-42e9-9801-e88a124fad9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=175220210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.175220210
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2219137172
Short name T78
Test name
Test status
Simulation time 20791187567 ps
CPU time 84.66 seconds
Started Aug 02 05:04:22 PM PDT 24
Finished Aug 02 05:05:47 PM PDT 24
Peak memory 199984 kb
Host smart-23565cf3-7554-40e8-82fc-763685d29718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219137172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2219137172
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1102477853
Short name T254
Test name
Test status
Simulation time 105175827 ps
CPU time 0.58 seconds
Started Aug 02 05:05:04 PM PDT 24
Finished Aug 02 05:05:05 PM PDT 24
Peak memory 195564 kb
Host smart-2aa69d52-3ae0-45f5-a358-a0820bb242c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102477853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1102477853
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.117676266
Short name T337
Test name
Test status
Simulation time 1503856254 ps
CPU time 85.56 seconds
Started Aug 02 05:05:07 PM PDT 24
Finished Aug 02 05:06:33 PM PDT 24
Peak memory 199888 kb
Host smart-c1debb3f-eb1e-4419-bd7d-84573a9bcc24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117676266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.117676266
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3612575363
Short name T3
Test name
Test status
Simulation time 4914406815 ps
CPU time 59.82 seconds
Started Aug 02 05:05:05 PM PDT 24
Finished Aug 02 05:06:05 PM PDT 24
Peak memory 199940 kb
Host smart-48747bd9-8975-445c-9510-5a26d11dbc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612575363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3612575363
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3753207972
Short name T499
Test name
Test status
Simulation time 745189394 ps
CPU time 17.44 seconds
Started Aug 02 05:05:04 PM PDT 24
Finished Aug 02 05:05:22 PM PDT 24
Peak memory 229316 kb
Host smart-16848794-c66c-487f-9c21-8ca30f1af84d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753207972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3753207972
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2693495096
Short name T239
Test name
Test status
Simulation time 12348253007 ps
CPU time 26.61 seconds
Started Aug 02 05:05:02 PM PDT 24
Finished Aug 02 05:05:29 PM PDT 24
Peak memory 199916 kb
Host smart-d755412c-5769-4116-81b3-4a3fd643a25c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693495096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2693495096
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2057335293
Short name T274
Test name
Test status
Simulation time 10711451215 ps
CPU time 67.09 seconds
Started Aug 02 05:05:06 PM PDT 24
Finished Aug 02 05:06:14 PM PDT 24
Peak memory 200200 kb
Host smart-b135f3c4-c10a-4ba4-80a9-8a2e5fc816fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057335293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2057335293
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.268356788
Short name T31
Test name
Test status
Simulation time 1782464581 ps
CPU time 5.26 seconds
Started Aug 02 05:05:08 PM PDT 24
Finished Aug 02 05:05:13 PM PDT 24
Peak memory 199852 kb
Host smart-8f404f39-e41c-45bc-a218-86a8a44db50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268356788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.268356788
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3103690429
Short name T492
Test name
Test status
Simulation time 19066748497 ps
CPU time 858.91 seconds
Started Aug 02 05:05:12 PM PDT 24
Finished Aug 02 05:19:31 PM PDT 24
Peak memory 713284 kb
Host smart-57ab67d7-9b73-4c16-b02e-bfdf965e75d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103690429 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3103690429
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.4088634326
Short name T17
Test name
Test status
Simulation time 1047816669 ps
CPU time 19.02 seconds
Started Aug 02 05:05:05 PM PDT 24
Finished Aug 02 05:05:24 PM PDT 24
Peak memory 199888 kb
Host smart-7b7317d6-c70d-4ff3-900e-b90f020fa357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088634326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.4088634326
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1111095348
Short name T188
Test name
Test status
Simulation time 32319640 ps
CPU time 0.57 seconds
Started Aug 02 05:05:06 PM PDT 24
Finished Aug 02 05:05:06 PM PDT 24
Peak memory 194944 kb
Host smart-75726770-7a73-4dbb-91f4-67159c7ddebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111095348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1111095348
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1719749172
Short name T33
Test name
Test status
Simulation time 1201236243 ps
CPU time 35.4 seconds
Started Aug 02 05:05:12 PM PDT 24
Finished Aug 02 05:05:48 PM PDT 24
Peak memory 199852 kb
Host smart-0a0d513a-88e3-419a-80ba-1acf89fdf9e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719749172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1719749172
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2304267020
Short name T263
Test name
Test status
Simulation time 24061146585 ps
CPU time 1065.77 seconds
Started Aug 02 05:05:15 PM PDT 24
Finished Aug 02 05:23:01 PM PDT 24
Peak memory 597600 kb
Host smart-9753502e-b269-4c61-b018-94ec908c52ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304267020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2304267020
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2551892654
Short name T232
Test name
Test status
Simulation time 6156167652 ps
CPU time 52.31 seconds
Started Aug 02 05:05:04 PM PDT 24
Finished Aug 02 05:05:57 PM PDT 24
Peak memory 199992 kb
Host smart-d1f278a0-7519-47cb-a14c-8494b9bf4fb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551892654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2551892654
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.4278754908
Short name T211
Test name
Test status
Simulation time 1365358208 ps
CPU time 16.62 seconds
Started Aug 02 05:05:07 PM PDT 24
Finished Aug 02 05:05:24 PM PDT 24
Peak memory 199912 kb
Host smart-87241c2e-da23-4e2a-84e4-86e0a69748f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278754908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.4278754908
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.991867935
Short name T218
Test name
Test status
Simulation time 2564006284 ps
CPU time 8.54 seconds
Started Aug 02 05:05:03 PM PDT 24
Finished Aug 02 05:05:12 PM PDT 24
Peak memory 199900 kb
Host smart-41cfc9da-f0ff-4cce-a0fd-c57b63f84d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991867935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.991867935
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1221658340
Short name T405
Test name
Test status
Simulation time 19552307 ps
CPU time 0.6 seconds
Started Aug 02 05:05:09 PM PDT 24
Finished Aug 02 05:05:10 PM PDT 24
Peak memory 195712 kb
Host smart-6c95cf16-eab7-4e1d-aa8c-303246ea1c53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221658340 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1221658340
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3577055918
Short name T271
Test name
Test status
Simulation time 2612739682 ps
CPU time 18.62 seconds
Started Aug 02 05:05:02 PM PDT 24
Finished Aug 02 05:05:21 PM PDT 24
Peak memory 200060 kb
Host smart-1f703a48-7a23-4f09-b3f0-040a37940069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577055918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3577055918
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2953670384
Short name T228
Test name
Test status
Simulation time 40428567 ps
CPU time 0.58 seconds
Started Aug 02 05:05:09 PM PDT 24
Finished Aug 02 05:05:10 PM PDT 24
Peak memory 195852 kb
Host smart-5bfa8c15-6500-4bfe-9754-72546c5c39db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953670384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2953670384
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3879687869
Short name T379
Test name
Test status
Simulation time 548921476 ps
CPU time 33.93 seconds
Started Aug 02 05:05:07 PM PDT 24
Finished Aug 02 05:05:41 PM PDT 24
Peak memory 199912 kb
Host smart-8889c7d0-7f72-4d3d-a0f9-7ebf3c33c6d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3879687869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3879687869
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3790443386
Short name T431
Test name
Test status
Simulation time 5492790252 ps
CPU time 18.15 seconds
Started Aug 02 05:05:09 PM PDT 24
Finished Aug 02 05:05:27 PM PDT 24
Peak memory 199908 kb
Host smart-166380e2-2427-4098-adce-cd5eafa97484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790443386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3790443386
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.154196505
Short name T207
Test name
Test status
Simulation time 11604474641 ps
CPU time 1034.33 seconds
Started Aug 02 05:05:09 PM PDT 24
Finished Aug 02 05:22:24 PM PDT 24
Peak memory 688500 kb
Host smart-e9a10cd5-22bf-4de1-9690-abd0fd075c94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154196505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.154196505
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1850949288
Short name T519
Test name
Test status
Simulation time 1627287707 ps
CPU time 43.43 seconds
Started Aug 02 05:05:06 PM PDT 24
Finished Aug 02 05:05:50 PM PDT 24
Peak memory 199732 kb
Host smart-e5983f00-3bf6-4690-9892-71e481611da5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850949288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1850949288
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2443083134
Short name T329
Test name
Test status
Simulation time 2623545076 ps
CPU time 31.22 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:05:46 PM PDT 24
Peak memory 199836 kb
Host smart-09ad4d18-a88d-42ea-ad53-845c9343ef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443083134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2443083134
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1883615405
Short name T42
Test name
Test status
Simulation time 310848520 ps
CPU time 1.08 seconds
Started Aug 02 05:05:04 PM PDT 24
Finished Aug 02 05:05:06 PM PDT 24
Peak memory 199720 kb
Host smart-6a63c873-5d1e-4e59-8f28-09e069550da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883615405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1883615405
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.794389683
Short name T515
Test name
Test status
Simulation time 34710405814 ps
CPU time 927.84 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:20:42 PM PDT 24
Peak memory 653788 kb
Host smart-4ed7d39f-0433-49a6-86e2-416d177e61f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794389683 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.794389683
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3451330461
Short name T374
Test name
Test status
Simulation time 165086950 ps
CPU time 6.39 seconds
Started Aug 02 05:05:07 PM PDT 24
Finished Aug 02 05:05:13 PM PDT 24
Peak memory 199896 kb
Host smart-0d8d5a57-ee36-4849-b715-64eb8f421d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451330461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3451330461
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.4172912561
Short name T50
Test name
Test status
Simulation time 17080156 ps
CPU time 0.64 seconds
Started Aug 02 05:05:11 PM PDT 24
Finished Aug 02 05:05:11 PM PDT 24
Peak memory 196604 kb
Host smart-43de37ce-236f-4154-a1ad-28c79ebf0eae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172912561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.4172912561
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.4082696867
Short name T299
Test name
Test status
Simulation time 112237842 ps
CPU time 6.57 seconds
Started Aug 02 05:05:13 PM PDT 24
Finished Aug 02 05:05:20 PM PDT 24
Peak memory 199856 kb
Host smart-6f4a4bf2-cb96-40f1-bc22-23c9a9641d88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082696867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.4082696867
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2001688524
Short name T142
Test name
Test status
Simulation time 1468063006 ps
CPU time 26.54 seconds
Started Aug 02 05:05:10 PM PDT 24
Finished Aug 02 05:05:37 PM PDT 24
Peak memory 199956 kb
Host smart-9a05a770-e7f4-4296-9bdc-13b07b40c9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001688524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2001688524
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3247991953
Short name T485
Test name
Test status
Simulation time 3504582460 ps
CPU time 181.65 seconds
Started Aug 02 05:05:16 PM PDT 24
Finished Aug 02 05:08:18 PM PDT 24
Peak memory 459244 kb
Host smart-2e202c46-3064-474b-a21e-5af51c660cfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247991953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3247991953
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1198500901
Short name T346
Test name
Test status
Simulation time 6134435950 ps
CPU time 104.87 seconds
Started Aug 02 05:05:11 PM PDT 24
Finished Aug 02 05:06:56 PM PDT 24
Peak memory 200020 kb
Host smart-9b1df5ca-4cde-4c87-aca8-620eb823d5ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198500901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1198500901
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.237754542
Short name T177
Test name
Test status
Simulation time 5799054968 ps
CPU time 100.06 seconds
Started Aug 02 05:05:05 PM PDT 24
Finished Aug 02 05:06:45 PM PDT 24
Peak memory 216288 kb
Host smart-9396a521-6450-4d79-b686-ccbdbc05f620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237754542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.237754542
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.395554811
Short name T404
Test name
Test status
Simulation time 951856615 ps
CPU time 16.34 seconds
Started Aug 02 05:05:05 PM PDT 24
Finished Aug 02 05:05:21 PM PDT 24
Peak memory 199848 kb
Host smart-83230ece-172a-43c3-a888-f7f3dbe76fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395554811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.395554811
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2101647905
Short name T209
Test name
Test status
Simulation time 20033328566 ps
CPU time 235.56 seconds
Started Aug 02 05:05:17 PM PDT 24
Finished Aug 02 05:09:13 PM PDT 24
Peak memory 199904 kb
Host smart-d430d479-b35b-4de2-b904-ceea021a57e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101647905 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2101647905
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2230906814
Short name T189
Test name
Test status
Simulation time 36360834666 ps
CPU time 110.29 seconds
Started Aug 02 05:05:07 PM PDT 24
Finished Aug 02 05:06:57 PM PDT 24
Peak memory 199972 kb
Host smart-b211f2f8-4d4d-4624-9e27-a8fd6af237e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230906814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2230906814
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1843048304
Short name T156
Test name
Test status
Simulation time 13211181 ps
CPU time 0.61 seconds
Started Aug 02 05:05:11 PM PDT 24
Finished Aug 02 05:05:12 PM PDT 24
Peak memory 195988 kb
Host smart-6dcb7de5-0c9f-4c0e-a177-841f107c24aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843048304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1843048304
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3401951842
Short name T332
Test name
Test status
Simulation time 2358137769 ps
CPU time 68.01 seconds
Started Aug 02 05:05:07 PM PDT 24
Finished Aug 02 05:06:15 PM PDT 24
Peak memory 200016 kb
Host smart-4f29b503-5352-4dd6-b184-d2c731541107
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401951842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3401951842
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.350568953
Short name T22
Test name
Test status
Simulation time 2462285831 ps
CPU time 32.2 seconds
Started Aug 02 05:05:07 PM PDT 24
Finished Aug 02 05:05:39 PM PDT 24
Peak memory 200016 kb
Host smart-43aadf26-84bd-4c26-b1c3-e5419d017fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350568953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.350568953
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.493533198
Short name T410
Test name
Test status
Simulation time 5386388430 ps
CPU time 920.35 seconds
Started Aug 02 05:05:12 PM PDT 24
Finished Aug 02 05:20:32 PM PDT 24
Peak memory 733076 kb
Host smart-7a1710a6-c5c0-44c3-8220-88ec5a5a5584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=493533198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.493533198
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2740300964
Short name T353
Test name
Test status
Simulation time 6949859114 ps
CPU time 120.51 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:07:15 PM PDT 24
Peak memory 200060 kb
Host smart-bcbb1bd7-4699-47d2-a17b-478bd9582e0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740300964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2740300964
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4024678719
Short name T457
Test name
Test status
Simulation time 8832788764 ps
CPU time 150.9 seconds
Started Aug 02 05:05:13 PM PDT 24
Finished Aug 02 05:07:44 PM PDT 24
Peak memory 199944 kb
Host smart-4806fb59-0801-43f0-89eb-84671ad3feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024678719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4024678719
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.242393659
Short name T118
Test name
Test status
Simulation time 184225785 ps
CPU time 8.29 seconds
Started Aug 02 05:05:11 PM PDT 24
Finished Aug 02 05:05:19 PM PDT 24
Peak memory 199788 kb
Host smart-9c316bc2-b437-4ec3-9356-782b65833ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242393659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.242393659
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1056462101
Short name T223
Test name
Test status
Simulation time 97520819711 ps
CPU time 874.54 seconds
Started Aug 02 05:05:13 PM PDT 24
Finished Aug 02 05:19:48 PM PDT 24
Peak memory 199904 kb
Host smart-69ff1f34-54bf-4fcf-821c-99a4a011a509
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056462101 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1056462101
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2099914073
Short name T279
Test name
Test status
Simulation time 13308685062 ps
CPU time 38.5 seconds
Started Aug 02 05:05:12 PM PDT 24
Finished Aug 02 05:05:51 PM PDT 24
Peak memory 199904 kb
Host smart-0176648b-b679-408f-8bc3-c8b5ed732e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099914073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2099914073
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3910752380
Short name T167
Test name
Test status
Simulation time 23358626 ps
CPU time 0.54 seconds
Started Aug 02 05:05:18 PM PDT 24
Finished Aug 02 05:05:19 PM PDT 24
Peak memory 194796 kb
Host smart-30566b39-d5b6-4e66-95bf-e403d63e65af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910752380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3910752380
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2156371438
Short name T305
Test name
Test status
Simulation time 1127664736 ps
CPU time 69.01 seconds
Started Aug 02 05:05:13 PM PDT 24
Finished Aug 02 05:06:22 PM PDT 24
Peak memory 199836 kb
Host smart-fee0e278-3298-49bf-a72a-2d01c500348c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156371438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2156371438
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.36489350
Short name T267
Test name
Test status
Simulation time 281871017 ps
CPU time 14.69 seconds
Started Aug 02 05:05:11 PM PDT 24
Finished Aug 02 05:05:26 PM PDT 24
Peak memory 199828 kb
Host smart-5bbccabb-2020-47eb-8cd7-49ed12b5fabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36489350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.36489350
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.500575962
Short name T285
Test name
Test status
Simulation time 5876418839 ps
CPU time 1045.71 seconds
Started Aug 02 05:05:12 PM PDT 24
Finished Aug 02 05:22:38 PM PDT 24
Peak memory 766464 kb
Host smart-fc8b442f-8246-49a5-9577-e12e401f0c13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500575962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.500575962
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.11856760
Short name T407
Test name
Test status
Simulation time 18870668413 ps
CPU time 41.14 seconds
Started Aug 02 05:05:10 PM PDT 24
Finished Aug 02 05:05:51 PM PDT 24
Peak memory 200060 kb
Host smart-77807a02-3545-447b-b117-a16fa3fb2bd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11856760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.11856760
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3343916767
Short name T7
Test name
Test status
Simulation time 4512895215 ps
CPU time 132.01 seconds
Started Aug 02 05:05:10 PM PDT 24
Finished Aug 02 05:07:22 PM PDT 24
Peak memory 199996 kb
Host smart-7e65e6b4-9a74-4aa0-a4bb-b9351a845f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343916767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3343916767
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2067527898
Short name T396
Test name
Test status
Simulation time 1073613944 ps
CPU time 12.24 seconds
Started Aug 02 05:05:09 PM PDT 24
Finished Aug 02 05:05:21 PM PDT 24
Peak memory 199832 kb
Host smart-47f6658e-3266-43df-b4de-661f6a00245c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067527898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2067527898
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1486176911
Short name T261
Test name
Test status
Simulation time 39799685368 ps
CPU time 594.09 seconds
Started Aug 02 05:05:13 PM PDT 24
Finished Aug 02 05:15:07 PM PDT 24
Peak memory 242004 kb
Host smart-75071f70-64da-4881-ba2b-37e28dba4213
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486176911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1486176911
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2058132603
Short name T41
Test name
Test status
Simulation time 29219540879 ps
CPU time 91.43 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:06:46 PM PDT 24
Peak memory 200060 kb
Host smart-c9b18778-f1bf-47b3-9494-1cfcb92d2e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058132603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2058132603
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2075279354
Short name T280
Test name
Test status
Simulation time 12222479 ps
CPU time 0.57 seconds
Started Aug 02 05:05:18 PM PDT 24
Finished Aug 02 05:05:19 PM PDT 24
Peak memory 194948 kb
Host smart-7f5d5c23-9c81-44b2-b55f-1b4e0788d025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075279354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2075279354
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1840628346
Short name T27
Test name
Test status
Simulation time 445508851 ps
CPU time 13.08 seconds
Started Aug 02 05:05:18 PM PDT 24
Finished Aug 02 05:05:31 PM PDT 24
Peak memory 199804 kb
Host smart-094629ec-f824-4bf1-91bd-09f3eca40257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840628346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1840628346
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3980757103
Short name T126
Test name
Test status
Simulation time 2291519209 ps
CPU time 42.7 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:05:57 PM PDT 24
Peak memory 199904 kb
Host smart-c608c2b6-6325-41a0-9789-8d8165c61985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980757103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3980757103
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2835838496
Short name T423
Test name
Test status
Simulation time 64105185777 ps
CPU time 963.22 seconds
Started Aug 02 05:05:15 PM PDT 24
Finished Aug 02 05:21:18 PM PDT 24
Peak memory 709484 kb
Host smart-cc78ac31-9d2b-4a50-bede-2a1c5576b45f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835838496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2835838496
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3972297660
Short name T171
Test name
Test status
Simulation time 5383243889 ps
CPU time 152.19 seconds
Started Aug 02 05:05:13 PM PDT 24
Finished Aug 02 05:07:46 PM PDT 24
Peak memory 199956 kb
Host smart-fca34072-432f-4d67-82d4-b6ccf6fa4b35
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972297660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3972297660
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1992536440
Short name T252
Test name
Test status
Simulation time 14078053481 ps
CPU time 85.91 seconds
Started Aug 02 05:05:17 PM PDT 24
Finished Aug 02 05:06:43 PM PDT 24
Peak memory 200036 kb
Host smart-9d01fc7e-404f-4d5d-bc03-0135721ad4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992536440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1992536440
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3215842308
Short name T331
Test name
Test status
Simulation time 513897961 ps
CPU time 9.03 seconds
Started Aug 02 05:05:13 PM PDT 24
Finished Aug 02 05:05:22 PM PDT 24
Peak memory 199860 kb
Host smart-3baea547-e909-496c-880d-21ff23bc8f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215842308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3215842308
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1469684893
Short name T293
Test name
Test status
Simulation time 167847040721 ps
CPU time 3043.53 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:55:58 PM PDT 24
Peak memory 785496 kb
Host smart-5ff0b5cf-5968-4ca8-8938-9c55f359d51e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469684893 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1469684893
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1319526157
Short name T413
Test name
Test status
Simulation time 3248173622 ps
CPU time 46.51 seconds
Started Aug 02 05:05:17 PM PDT 24
Finished Aug 02 05:06:04 PM PDT 24
Peak memory 199976 kb
Host smart-4a66d804-4e28-4f01-b44c-a04257923b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319526157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1319526157
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3709037773
Short name T30
Test name
Test status
Simulation time 32735560 ps
CPU time 0.58 seconds
Started Aug 02 05:05:17 PM PDT 24
Finished Aug 02 05:05:18 PM PDT 24
Peak memory 194868 kb
Host smart-f9744495-a1c7-4f5d-918e-4f6d89324824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709037773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3709037773
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.957300552
Short name T206
Test name
Test status
Simulation time 59343753 ps
CPU time 3.27 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:05:17 PM PDT 24
Peak memory 199724 kb
Host smart-fea127e1-7a8a-4eb0-8cff-e4f7f34daeca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957300552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.957300552
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2612500522
Short name T412
Test name
Test status
Simulation time 6167287545 ps
CPU time 32.16 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:05:46 PM PDT 24
Peak memory 200032 kb
Host smart-48e353e5-cc7e-4586-84bc-da70cc264cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612500522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2612500522
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2227695570
Short name T480
Test name
Test status
Simulation time 16443092523 ps
CPU time 785.22 seconds
Started Aug 02 05:05:16 PM PDT 24
Finished Aug 02 05:18:21 PM PDT 24
Peak memory 717404 kb
Host smart-f5bb1652-253b-4add-8238-de4c268a46b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227695570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2227695570
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3614217456
Short name T173
Test name
Test status
Simulation time 10070222645 ps
CPU time 11.95 seconds
Started Aug 02 05:05:16 PM PDT 24
Finished Aug 02 05:05:28 PM PDT 24
Peak memory 199976 kb
Host smart-b383d703-04e7-445b-b562-9b96723bfc82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614217456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3614217456
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1838730350
Short name T176
Test name
Test status
Simulation time 58811292224 ps
CPU time 204.24 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:08:38 PM PDT 24
Peak memory 200220 kb
Host smart-95a5de8d-6b75-4317-90ab-e1db3ad60b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838730350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1838730350
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2827293297
Short name T43
Test name
Test status
Simulation time 3005490014 ps
CPU time 10.33 seconds
Started Aug 02 05:05:20 PM PDT 24
Finished Aug 02 05:05:30 PM PDT 24
Peak memory 200072 kb
Host smart-05e8d9b0-1b92-4046-99ad-89d969dcabe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827293297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2827293297
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3425122500
Short name T344
Test name
Test status
Simulation time 209721445466 ps
CPU time 1687.72 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:33:22 PM PDT 24
Peak memory 766392 kb
Host smart-7dab480d-ef25-47d1-ba46-69c184dc95c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425122500 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3425122500
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3094304387
Short name T1
Test name
Test status
Simulation time 1444458767 ps
CPU time 7.74 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:05:22 PM PDT 24
Peak memory 199884 kb
Host smart-ff9986cc-ba1f-45c4-92bb-e6bbe54ae9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094304387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3094304387
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1130365206
Short name T466
Test name
Test status
Simulation time 21758480 ps
CPU time 0.59 seconds
Started Aug 02 05:05:24 PM PDT 24
Finished Aug 02 05:05:25 PM PDT 24
Peak memory 195916 kb
Host smart-c2c2b68f-d879-4ff4-ac91-e3b8c7dc57d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130365206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1130365206
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2559160515
Short name T11
Test name
Test status
Simulation time 7430163912 ps
CPU time 106.53 seconds
Started Aug 02 05:05:13 PM PDT 24
Finished Aug 02 05:07:00 PM PDT 24
Peak memory 200048 kb
Host smart-10486bd6-eb46-4336-8f6b-b9a3042bddca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559160515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2559160515
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3823446964
Short name T411
Test name
Test status
Simulation time 283786487 ps
CPU time 7.49 seconds
Started Aug 02 05:05:19 PM PDT 24
Finished Aug 02 05:05:27 PM PDT 24
Peak memory 199880 kb
Host smart-c24f3b3b-efbe-44d3-a6df-0bc75059e781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823446964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3823446964
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2382858785
Short name T61
Test name
Test status
Simulation time 5275258228 ps
CPU time 920.84 seconds
Started Aug 02 05:05:23 PM PDT 24
Finished Aug 02 05:20:44 PM PDT 24
Peak memory 678884 kb
Host smart-5bd57a36-460f-4764-806c-e522f091addc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382858785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2382858785
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3085671822
Short name T315
Test name
Test status
Simulation time 12904533383 ps
CPU time 91.47 seconds
Started Aug 02 05:05:23 PM PDT 24
Finished Aug 02 05:06:54 PM PDT 24
Peak memory 199972 kb
Host smart-ca2a2417-a865-4cf7-b5e6-5bbf2a422ab8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085671822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3085671822
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.593883552
Short name T421
Test name
Test status
Simulation time 28433382235 ps
CPU time 109.48 seconds
Started Aug 02 05:05:18 PM PDT 24
Finished Aug 02 05:07:08 PM PDT 24
Peak memory 199924 kb
Host smart-bb8b0d1f-404a-4212-9a4a-479f35c8c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593883552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.593883552
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2748067908
Short name T2
Test name
Test status
Simulation time 9405459841 ps
CPU time 14.64 seconds
Started Aug 02 05:05:14 PM PDT 24
Finished Aug 02 05:05:28 PM PDT 24
Peak memory 199932 kb
Host smart-574f006c-5eb3-4114-91e2-a236cefc215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748067908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2748067908
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3450480146
Short name T83
Test name
Test status
Simulation time 33881980102 ps
CPU time 351 seconds
Started Aug 02 05:05:20 PM PDT 24
Finished Aug 02 05:11:11 PM PDT 24
Peak memory 200036 kb
Host smart-c5e680b8-389d-4a6e-9960-03c78478de3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450480146 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3450480146
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2119468918
Short name T472
Test name
Test status
Simulation time 28540049192 ps
CPU time 84.12 seconds
Started Aug 02 05:05:20 PM PDT 24
Finished Aug 02 05:06:44 PM PDT 24
Peak memory 199980 kb
Host smart-400c5b50-106f-480c-8dbb-7808c22dd867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119468918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2119468918
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2667241992
Short name T508
Test name
Test status
Simulation time 41531193 ps
CPU time 0.61 seconds
Started Aug 02 05:05:23 PM PDT 24
Finished Aug 02 05:05:24 PM PDT 24
Peak memory 194868 kb
Host smart-19f2f0c3-1f30-4535-bf65-bfd09218461a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667241992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2667241992
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3891091374
Short name T440
Test name
Test status
Simulation time 137367102 ps
CPU time 7.74 seconds
Started Aug 02 05:05:20 PM PDT 24
Finished Aug 02 05:05:28 PM PDT 24
Peak memory 199840 kb
Host smart-8abac564-992d-4c1d-a8ab-eefc66ee0ea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891091374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3891091374
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.137903716
Short name T328
Test name
Test status
Simulation time 5438194527 ps
CPU time 72.87 seconds
Started Aug 02 05:05:20 PM PDT 24
Finished Aug 02 05:06:33 PM PDT 24
Peak memory 199980 kb
Host smart-55877079-6946-4c74-b273-bb71ec90a5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137903716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.137903716
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.97851691
Short name T234
Test name
Test status
Simulation time 4210474580 ps
CPU time 783.02 seconds
Started Aug 02 05:05:21 PM PDT 24
Finished Aug 02 05:18:24 PM PDT 24
Peak memory 703260 kb
Host smart-ceaac3e1-1dac-4d83-b339-98533ed98dea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97851691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.97851691
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2496043020
Short name T390
Test name
Test status
Simulation time 882564762 ps
CPU time 46.9 seconds
Started Aug 02 05:05:22 PM PDT 24
Finished Aug 02 05:06:09 PM PDT 24
Peak memory 199832 kb
Host smart-6276fd96-25c1-4ac8-b6ea-55ee6edefb9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496043020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2496043020
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1767959096
Short name T141
Test name
Test status
Simulation time 97880997765 ps
CPU time 154.8 seconds
Started Aug 02 05:05:23 PM PDT 24
Finished Aug 02 05:07:58 PM PDT 24
Peak memory 199952 kb
Host smart-ea3144b5-a23c-4035-9c94-73025d34e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767959096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1767959096
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2729966697
Short name T500
Test name
Test status
Simulation time 547804649 ps
CPU time 10.91 seconds
Started Aug 02 05:05:20 PM PDT 24
Finished Aug 02 05:05:31 PM PDT 24
Peak memory 199796 kb
Host smart-343bd691-f9e9-41ff-bdc4-ce87f8c8ee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729966697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2729966697
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3669637574
Short name T262
Test name
Test status
Simulation time 35371524964 ps
CPU time 344.45 seconds
Started Aug 02 05:05:21 PM PDT 24
Finished Aug 02 05:11:05 PM PDT 24
Peak memory 333304 kb
Host smart-895631bc-e46c-4c41-966e-4bbacd4d41a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669637574 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3669637574
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.4161796623
Short name T388
Test name
Test status
Simulation time 2506352753 ps
CPU time 32.13 seconds
Started Aug 02 05:05:25 PM PDT 24
Finished Aug 02 05:05:57 PM PDT 24
Peak memory 199948 kb
Host smart-7188e367-e23b-4024-b882-7520acf0321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161796623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4161796623
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2485951572
Short name T180
Test name
Test status
Simulation time 13649232 ps
CPU time 0.62 seconds
Started Aug 02 05:04:21 PM PDT 24
Finished Aug 02 05:04:21 PM PDT 24
Peak memory 195916 kb
Host smart-ee3c013c-ebee-4cc9-8251-c491a863ddd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485951572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2485951572
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3556332953
Short name T323
Test name
Test status
Simulation time 2710199026 ps
CPU time 78.47 seconds
Started Aug 02 05:04:29 PM PDT 24
Finished Aug 02 05:05:47 PM PDT 24
Peak memory 199904 kb
Host smart-53569e41-8e84-459b-ab86-45cb5d9be970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556332953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3556332953
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3679132023
Short name T146
Test name
Test status
Simulation time 5440769453 ps
CPU time 73.45 seconds
Started Aug 02 05:04:24 PM PDT 24
Finished Aug 02 05:05:38 PM PDT 24
Peak memory 200036 kb
Host smart-01d944de-403d-4a87-968a-ddf848e08836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679132023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3679132023
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3075547046
Short name T427
Test name
Test status
Simulation time 15037501832 ps
CPU time 364.43 seconds
Started Aug 02 05:04:27 PM PDT 24
Finished Aug 02 05:10:31 PM PDT 24
Peak memory 616904 kb
Host smart-1d29a1e0-9440-4aaf-b693-89448375463a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075547046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3075547046
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3098969668
Short name T157
Test name
Test status
Simulation time 223856785 ps
CPU time 12.1 seconds
Started Aug 02 05:04:24 PM PDT 24
Finished Aug 02 05:04:36 PM PDT 24
Peak memory 199784 kb
Host smart-36348115-0bc4-427d-9f7f-0438319764b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098969668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3098969668
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.488531858
Short name T127
Test name
Test status
Simulation time 11605223430 ps
CPU time 102.59 seconds
Started Aug 02 05:04:28 PM PDT 24
Finished Aug 02 05:06:10 PM PDT 24
Peak memory 199968 kb
Host smart-6a339f64-fd95-413b-95f4-1dabab6331e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488531858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.488531858
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1948058876
Short name T297
Test name
Test status
Simulation time 2589804443 ps
CPU time 13.79 seconds
Started Aug 02 05:04:31 PM PDT 24
Finished Aug 02 05:04:45 PM PDT 24
Peak memory 199992 kb
Host smart-027446cf-cfa0-4f1f-a9dc-ffc470227f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948058876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1948058876
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2112151013
Short name T351
Test name
Test status
Simulation time 18400906429 ps
CPU time 2391.42 seconds
Started Aug 02 05:04:10 PM PDT 24
Finished Aug 02 05:44:02 PM PDT 24
Peak memory 770284 kb
Host smart-eda5f696-4b82-4227-858b-d4f3664a9002
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112151013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2112151013
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1278148397
Short name T16
Test name
Test status
Simulation time 45434029707 ps
CPU time 494.39 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:12:48 PM PDT 24
Peak memory 610608 kb
Host smart-da59a3f1-4b57-460b-bf55-1241d640467b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1278148397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1278148397
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1444572558
Short name T389
Test name
Test status
Simulation time 3070919360 ps
CPU time 38.96 seconds
Started Aug 02 05:04:19 PM PDT 24
Finished Aug 02 05:04:58 PM PDT 24
Peak memory 200056 kb
Host smart-397a70fd-4f87-4544-b002-4824b592f062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444572558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1444572558
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1249198302
Short name T316
Test name
Test status
Simulation time 12857027 ps
CPU time 0.58 seconds
Started Aug 02 05:04:24 PM PDT 24
Finished Aug 02 05:04:25 PM PDT 24
Peak memory 195876 kb
Host smart-a7e59820-eafc-4c9e-8160-350eacb2eccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249198302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1249198302
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.893432066
Short name T44
Test name
Test status
Simulation time 105801489 ps
CPU time 5.95 seconds
Started Aug 02 05:04:14 PM PDT 24
Finished Aug 02 05:04:20 PM PDT 24
Peak memory 199816 kb
Host smart-2076ee30-5d98-4f75-9040-f5063e12baaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893432066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.893432066
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1033965598
Short name T25
Test name
Test status
Simulation time 3129548308 ps
CPU time 29.35 seconds
Started Aug 02 05:04:29 PM PDT 24
Finished Aug 02 05:04:59 PM PDT 24
Peak memory 199976 kb
Host smart-a4f2a41a-91dd-44f4-89c8-898d4b3eefe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033965598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1033965598
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2372681449
Short name T158
Test name
Test status
Simulation time 24026767127 ps
CPU time 1165.8 seconds
Started Aug 02 05:04:15 PM PDT 24
Finished Aug 02 05:23:41 PM PDT 24
Peak memory 746608 kb
Host smart-df8d8fa8-3b17-404e-915b-cf9d5a325f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372681449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2372681449
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3009320614
Short name T325
Test name
Test status
Simulation time 40568360863 ps
CPU time 185.1 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:07:31 PM PDT 24
Peak memory 199832 kb
Host smart-11e83e96-10de-49ed-b0a4-ea37c8ed7857
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009320614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3009320614
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3978931494
Short name T435
Test name
Test status
Simulation time 64424240694 ps
CPU time 220.56 seconds
Started Aug 02 05:04:27 PM PDT 24
Finished Aug 02 05:08:07 PM PDT 24
Peak memory 199972 kb
Host smart-bffc0e5f-941b-4c10-bb52-dc1e2af5b7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978931494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3978931494
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1582128793
Short name T37
Test name
Test status
Simulation time 1078594999 ps
CPU time 12.74 seconds
Started Aug 02 05:04:27 PM PDT 24
Finished Aug 02 05:04:40 PM PDT 24
Peak memory 199792 kb
Host smart-b7aa4ab8-4cbf-4bea-8e9c-d65840d0eca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582128793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1582128793
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2687689228
Short name T376
Test name
Test status
Simulation time 66310284047 ps
CPU time 1839.69 seconds
Started Aug 02 05:04:24 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 720716 kb
Host smart-e053a52b-72fa-43f1-8816-4452c1df05d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687689228 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2687689228
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.3632164911
Short name T10
Test name
Test status
Simulation time 91494448627 ps
CPU time 2794.95 seconds
Started Aug 02 05:04:20 PM PDT 24
Finished Aug 02 05:50:55 PM PDT 24
Peak memory 741392 kb
Host smart-a4166e4c-e9ec-4a7d-a8bd-f1b648ba85cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3632164911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3632164911
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2656508616
Short name T320
Test name
Test status
Simulation time 3842481979 ps
CPU time 93.52 seconds
Started Aug 02 05:04:21 PM PDT 24
Finished Aug 02 05:05:55 PM PDT 24
Peak memory 199888 kb
Host smart-44287593-318f-4aed-b1d5-17eae3f85e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656508616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2656508616
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1898045583
Short name T362
Test name
Test status
Simulation time 22289597 ps
CPU time 0.56 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:04:25 PM PDT 24
Peak memory 195984 kb
Host smart-6feaa1ba-f886-4a32-a557-e39e2b7b79c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898045583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1898045583
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.977597714
Short name T99
Test name
Test status
Simulation time 397551237 ps
CPU time 15.21 seconds
Started Aug 02 05:04:14 PM PDT 24
Finished Aug 02 05:04:30 PM PDT 24
Peak memory 199796 kb
Host smart-2cc6860b-925b-4b0f-a583-84ea34dd51bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977597714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.977597714
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.735621009
Short name T94
Test name
Test status
Simulation time 2663299137 ps
CPU time 47.38 seconds
Started Aug 02 05:04:24 PM PDT 24
Finished Aug 02 05:05:12 PM PDT 24
Peak memory 199860 kb
Host smart-2789e34c-a3bb-4fef-9162-8a48f9be229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735621009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.735621009
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.4246261338
Short name T415
Test name
Test status
Simulation time 2623147811 ps
CPU time 168.41 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:07:15 PM PDT 24
Peak memory 439708 kb
Host smart-5926ba67-6d87-45a0-a5ea-8aeaf0ca92f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246261338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.4246261338
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2060861036
Short name T65
Test name
Test status
Simulation time 191277315155 ps
CPU time 173.53 seconds
Started Aug 02 05:04:23 PM PDT 24
Finished Aug 02 05:07:17 PM PDT 24
Peak memory 200016 kb
Host smart-5168dee0-480e-4d71-a86a-92a668b4c575
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060861036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2060861036
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2937145914
Short name T510
Test name
Test status
Simulation time 37613009905 ps
CPU time 142.81 seconds
Started Aug 02 05:04:24 PM PDT 24
Finished Aug 02 05:06:47 PM PDT 24
Peak memory 199980 kb
Host smart-c40926fd-9b8e-472f-9117-dfae8f5810c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937145914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2937145914
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1153115000
Short name T249
Test name
Test status
Simulation time 546528418 ps
CPU time 4.03 seconds
Started Aug 02 05:04:21 PM PDT 24
Finished Aug 02 05:04:25 PM PDT 24
Peak memory 199928 kb
Host smart-30271de6-1bb8-459f-859d-2e86cf9eba39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153115000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1153115000
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2844833693
Short name T131
Test name
Test status
Simulation time 745104913411 ps
CPU time 1207 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:24:41 PM PDT 24
Peak memory 748368 kb
Host smart-97285a41-ea11-4bc5-ae5b-03729113a20c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844833693 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2844833693
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2273880017
Short name T517
Test name
Test status
Simulation time 15980287267 ps
CPU time 151.46 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:07:05 PM PDT 24
Peak memory 199896 kb
Host smart-881ca39c-5a26-4c84-8a41-825f0b1b0e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273880017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2273880017
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2261672999
Short name T426
Test name
Test status
Simulation time 23027114 ps
CPU time 0.55 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:04:26 PM PDT 24
Peak memory 195484 kb
Host smart-fcfe8f68-247b-48ce-9f3c-8f283ab85624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261672999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2261672999
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2430976243
Short name T287
Test name
Test status
Simulation time 1195182730 ps
CPU time 70.13 seconds
Started Aug 02 05:04:27 PM PDT 24
Finished Aug 02 05:05:37 PM PDT 24
Peak memory 199872 kb
Host smart-f8d86510-1f11-4c06-bc8f-b223b11526e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430976243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2430976243
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.745126146
Short name T294
Test name
Test status
Simulation time 4056163747 ps
CPU time 50.42 seconds
Started Aug 02 05:04:20 PM PDT 24
Finished Aug 02 05:05:11 PM PDT 24
Peak memory 199972 kb
Host smart-359e6d9a-75ae-4efb-a808-ca104837648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745126146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.745126146
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1911033719
Short name T375
Test name
Test status
Simulation time 8051691162 ps
CPU time 649.66 seconds
Started Aug 02 05:04:27 PM PDT 24
Finished Aug 02 05:15:17 PM PDT 24
Peak memory 728724 kb
Host smart-79c056b8-c707-4a8a-9715-f7126e4f29df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911033719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1911033719
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.259114552
Short name T298
Test name
Test status
Simulation time 14228734043 ps
CPU time 119.25 seconds
Started Aug 02 05:04:27 PM PDT 24
Finished Aug 02 05:06:27 PM PDT 24
Peak memory 199956 kb
Host smart-d934d799-a39c-4416-b334-0296c5907743
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259114552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.259114552
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.728106552
Short name T319
Test name
Test status
Simulation time 25524729090 ps
CPU time 123.92 seconds
Started Aug 02 05:04:20 PM PDT 24
Finished Aug 02 05:06:24 PM PDT 24
Peak memory 199996 kb
Host smart-c62b977e-5d75-47f4-a070-5ac8ec8940f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728106552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.728106552
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1981073571
Short name T275
Test name
Test status
Simulation time 220378792 ps
CPU time 2.6 seconds
Started Aug 02 05:04:25 PM PDT 24
Finished Aug 02 05:04:27 PM PDT 24
Peak memory 199728 kb
Host smart-68b781a2-a214-4564-ae44-081911c828f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981073571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1981073571
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1518358215
Short name T71
Test name
Test status
Simulation time 82305642056 ps
CPU time 5292.94 seconds
Started Aug 02 05:04:24 PM PDT 24
Finished Aug 02 06:32:38 PM PDT 24
Peak memory 816856 kb
Host smart-aa76f51d-2ccf-46ad-890c-040962ccff36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518358215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1518358215
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3187322674
Short name T258
Test name
Test status
Simulation time 22656714402 ps
CPU time 25.3 seconds
Started Aug 02 05:04:28 PM PDT 24
Finished Aug 02 05:04:54 PM PDT 24
Peak memory 200044 kb
Host smart-ddf8fa9e-ef2d-4a81-b7c4-f43c2ddb0bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187322674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3187322674
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.901858525
Short name T39
Test name
Test status
Simulation time 46424856 ps
CPU time 0.59 seconds
Started Aug 02 05:04:32 PM PDT 24
Finished Aug 02 05:04:33 PM PDT 24
Peak memory 194840 kb
Host smart-42516bdc-dca5-4408-b88e-4c30d661e250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901858525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.901858525
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1980386027
Short name T198
Test name
Test status
Simulation time 1109170538 ps
CPU time 67.33 seconds
Started Aug 02 05:04:43 PM PDT 24
Finished Aug 02 05:05:51 PM PDT 24
Peak memory 199780 kb
Host smart-05f55039-aaca-4704-a39d-16fe14388abc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980386027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1980386027
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3174746541
Short name T350
Test name
Test status
Simulation time 953610838 ps
CPU time 51.23 seconds
Started Aug 02 05:04:34 PM PDT 24
Finished Aug 02 05:05:25 PM PDT 24
Peak memory 199864 kb
Host smart-1f54e952-a46f-4fb3-8016-661c80ae2570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174746541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3174746541
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3862294208
Short name T240
Test name
Test status
Simulation time 3886193157 ps
CPU time 277.72 seconds
Started Aug 02 05:04:45 PM PDT 24
Finished Aug 02 05:09:23 PM PDT 24
Peak memory 443576 kb
Host smart-6a3154e6-47d7-4d03-ae21-778c4b7809f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3862294208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3862294208
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2170499533
Short name T422
Test name
Test status
Simulation time 1362529734 ps
CPU time 74.71 seconds
Started Aug 02 05:04:26 PM PDT 24
Finished Aug 02 05:05:41 PM PDT 24
Peak memory 199932 kb
Host smart-5027b3de-5ab3-407f-b10f-3992c9348ffb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170499533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2170499533
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2880332423
Short name T512
Test name
Test status
Simulation time 20352984075 ps
CPU time 124.35 seconds
Started Aug 02 05:04:40 PM PDT 24
Finished Aug 02 05:06:44 PM PDT 24
Peak memory 200068 kb
Host smart-5c3b365e-4961-40a2-ad55-0425e1769888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880332423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2880332423
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3851033431
Short name T243
Test name
Test status
Simulation time 352294833 ps
CPU time 4.4 seconds
Started Aug 02 05:04:32 PM PDT 24
Finished Aug 02 05:04:37 PM PDT 24
Peak memory 199868 kb
Host smart-e4a2186a-1416-4840-8bc2-a4c93f5bbe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851033431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3851033431
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1457088706
Short name T484
Test name
Test status
Simulation time 351272483412 ps
CPU time 3019.49 seconds
Started Aug 02 05:04:34 PM PDT 24
Finished Aug 02 05:54:54 PM PDT 24
Peak memory 833556 kb
Host smart-021e9ceb-968c-430b-9823-623dae7835a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457088706 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1457088706
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3800200576
Short name T201
Test name
Test status
Simulation time 18323794583 ps
CPU time 81.75 seconds
Started Aug 02 05:04:33 PM PDT 24
Finished Aug 02 05:05:54 PM PDT 24
Peak memory 200052 kb
Host smart-d66fceb6-5c2d-434e-8bcc-d92dae7dab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800200576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3800200576
Directory /workspace/9.hmac_wipe_secret/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%