Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17144066	1			T1	205995		T2	226		T3	16576
all_values[1]	17144066	1			T1	205995		T2	226		T3	16576
all_values[2]	17144066	1			T1	205995		T2	226		T3	16576

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245730

1

T1

1754

T2

54

T6

110

auto[1]

51186468

1

T1

616231

T2

624

T3

49728

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43808786

1

T1

503362

T2

629

T3

41444

auto[1]

7623412

1

T1

114623

T2

49

T3

8284

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	93099	1			T1	715		T2	54		T6	53
all_values[0]	auto[0]	auto[1]	383	1			T1	1		T6	2		T4	5
all_values[0]	auto[1]	auto[0]	17030824	1			T1	205084		T2	168		T3	16396
all_values[0]	auto[1]	auto[1]	19760	1			T1	195		T2	4		T3	180
all_values[1]	auto[0]	auto[0]	74258	1			T1	5		T6	55		T4	142
all_values[1]	auto[0]	auto[1]	225	1			T1	2		T4	1		T43	3
all_values[1]	auto[1]	auto[0]	17069248	1			T1	205987		T2	226		T3	16576
all_values[1]	auto[1]	auto[1]	335	1			T1	1		T4	1		T43	2
all_values[2]	auto[0]	auto[0]	36017	1			T1	263		T4	219		T5	4
all_values[2]	auto[0]	auto[1]	41748	1			T1	768		T5	87		T43	780
all_values[2]	auto[1]	auto[0]	9505340	1			T1	91308		T2	181		T3	8472
all_values[2]	auto[1]	auto[1]	7560961	1			T1	113656		T2	45		T3	8104