Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125359

1

T1

1164

T2

104

T6

6

auto[1]

113656

1

T1

1826

T2

26

T3

182

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	90733	1			T1	897		T2	46		T4	575
len_1026_2046	6107	1			T1	52		T2	2		T6	1
len_514_1022	2983	1			T1	36		T2	2		T4	13
len_2_510	3175	1			T1	22		T2	1		T4	14
len_2056	178	1			T1	2		T4	5		T143	1
len_2048	381	1			T1	3		T4	16		T17	1
len_2040	188	1			T1	13		T4	7		T43	5
len_1032	207	1			T1	2		T6	2		T18	3
len_1024	1813	1			T1	11		T2	1		T3	91
len_1016	190	1			T1	4		T4	8		T18	3
len_520	206	1			T1	4		T4	2		T18	1
len_512	413	1			T1	2		T4	7		T17	2
len_504	200	1			T1	5		T4	1		T18	2
len_8	1309	1			T4	20		T7	6		T43	39
len_0	11424	1			T1	442		T2	13		T4	42

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

106

1

T5

1

T43

2

T59

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	49679	1			T1	477		T2	46		T4	282
auto[0]	len_1026_2046	2415	1			T1	24		T2	2		T6	1
auto[0]	len_514_1022	2077	1			T1	20		T2	2		T4	6
auto[0]	len_2_510	2087	1			T1	6		T2	1		T4	9
auto[0]	len_2056	83	1			T1	1		T4	2		T43	3
auto[0]	len_2048	218	1			T1	1		T4	9		T17	1
auto[0]	len_2040	115	1			T1	7		T4	4		T62	2
auto[0]	len_1032	105	1			T1	2		T6	2		T144	1
auto[0]	len_1024	247	1			T1	4		T2	1		T4	3
auto[0]	len_1016	110	1			T1	3		T4	3		T18	2
auto[0]	len_520	114	1			T1	3		T143	1		T43	1
auto[0]	len_512	243	1			T1	1		T4	5		T17	2
auto[0]	len_504	109	1			T1	3		T4	1		T143	1
auto[0]	len_8	52	1			T51	1		T81	1		T8	1
auto[0]	len_0	5025	1			T1	30		T4	34		T17	206
auto[1]	len_2050_plus	41054	1			T1	420		T4	293		T7	5
auto[1]	len_1026_2046	3692	1			T1	28		T4	93		T18	5
auto[1]	len_514_1022	906	1			T1	16		T4	7		T43	9
auto[1]	len_2_510	1088	1			T1	16		T4	5		T5	1
auto[1]	len_2056	95	1			T1	1		T4	3		T143	1
auto[1]	len_2048	163	1			T1	2		T4	7		T24	1
auto[1]	len_2040	73	1			T1	6		T4	3		T43	5
auto[1]	len_1032	102	1			T18	3		T43	1		T88	2
auto[1]	len_1024	1566	1			T1	7		T3	91		T4	1
auto[1]	len_1016	80	1			T1	1		T4	5		T18	1
auto[1]	len_520	92	1			T1	1		T4	2		T18	1
auto[1]	len_512	170	1			T1	1		T4	2		T43	1
auto[1]	len_504	91	1			T1	2		T18	2		T143	3
auto[1]	len_8	1257	1			T4	20		T7	6		T43	39
auto[1]	len_0	6399	1			T1	412		T2	13		T4	8

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

56

1

T5

1

T43

2

T59

2

auto[1]

len_upper

50

1

T80

1

T81

4

T11

2