Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4250090 1 T1 36984 T2 301 T3 4269
auto[1] 2600969 1 T1 39927 T6 63 T4 22657


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2539855 1 T1 33916 T2 16 T6 38
auto[1] 4311204 1 T1 42995 T2 285 T3 4269


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3207677 1 T1 39497 T2 237 T6 63
auto[1] 3643382 1 T1 37414 T2 64 T3 4269


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4272262 1 T1 34739 T2 16 T3 4269
auto[1] 2578797 1 T1 42172 T2 285 T6 40


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6280832 1 T1 60361 T2 267 T3 4118
fifo_depth[1] 111594 1 T1 1552 T2 8 T3 112
fifo_depth[2] 82423 1 T1 1531 T2 6 T3 36
fifo_depth[3] 62774 1 T1 1415 T2 6 T3 3
fifo_depth[4] 55528 1 T1 1355 T2 6 T4 95
fifo_depth[5] 42947 1 T1 1057 T2 4 T6 1
fifo_depth[6] 33686 1 T1 854 T2 4 T4 16
fifo_depth[7] 21896 1 T1 575 T4 18 T17 1


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 570227 1 T1 16550 T2 34 T3 151
auto[1] 6280832 1 T1 60361 T2 267 T3 4118


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6841990 1 T1 76262 T2 301 T3 4269
auto[1] 9069 1 T1 649 T5 809 T19 189


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 22265 1 T1 9 T4 64 T18 1
auto[0] auto[0] auto[0] auto[0] auto[1] 22578 1 T1 900 T4 125 T5 402
auto[0] auto[0] auto[0] auto[1] auto[0] 24889 1 T1 1820 T6 3 T4 44
auto[0] auto[0] auto[0] auto[1] auto[1] 30792 1 T1 1987 T4 26 T5 240
auto[0] auto[0] auto[1] auto[0] auto[0] 148282 1 T1 1154 T4 103 T5 860
auto[0] auto[0] auto[1] auto[0] auto[1] 15426 1 T1 1469 T2 34 T4 91
auto[0] auto[0] auto[1] auto[1] auto[0] 21557 1 T1 1481 T4 88 T43 178
auto[0] auto[0] auto[1] auto[1] auto[1] 33607 1 T1 2112 T6 5 T4 85
auto[0] auto[1] auto[0] auto[0] auto[0] 31553 1 T1 373 T4 279 T7 315
auto[0] auto[1] auto[0] auto[0] auto[1] 32933 1 T1 923 T4 176 T18 1
auto[0] auto[1] auto[0] auto[1] auto[0] 35884 1 T1 777 T4 82 T7 592
auto[0] auto[1] auto[0] auto[1] auto[1] 32013 1 T1 1047 T4 42 T24 324
auto[0] auto[1] auto[1] auto[0] auto[0] 30201 1 T1 274 T3 151 T4 262
auto[0] auto[1] auto[1] auto[0] auto[1] 30485 1 T1 933 T4 98 T18 4
auto[0] auto[1] auto[1] auto[1] auto[0] 24717 1 T1 945 T4 119 T18 2
auto[0] auto[1] auto[1] auto[1] auto[1] 33045 1 T1 346 T4 129 T18 1
auto[1] auto[0] auto[0] auto[0] auto[0] 161220 1 T1 2920 T2 16 T4 2103
auto[1] auto[0] auto[0] auto[0] auto[1] 165555 1 T1 1673 T4 2229 T17 85
auto[1] auto[0] auto[0] auto[1] auto[0] 160084 1 T1 4987 T6 20 T4 805
auto[1] auto[0] auto[0] auto[1] auto[1] 178047 1 T1 4209 T6 15 T4 755
auto[1] auto[0] auto[1] auto[0] auto[0] 1716805 1 T1 3000 T4 3079 T5 695
auto[1] auto[0] auto[1] auto[0] auto[1] 153044 1 T1 5181 T2 187 T4 2649
auto[1] auto[0] auto[1] auto[1] auto[0] 176293 1 T1 4108 T4 1826 T5 46
auto[1] auto[0] auto[1] auto[1] auto[1] 177233 1 T1 2487 T6 20 T4 1505
auto[1] auto[1] auto[0] auto[0] auto[0] 412554 1 T1 2033 T4 7984 T7 4348
auto[1] auto[1] auto[0] auto[0] auto[1] 400046 1 T1 4650 T4 3742 T7 5819
auto[1] auto[1] auto[0] auto[1] auto[0] 413325 1 T1 2684 T4 5046 T7 1045
auto[1] auto[1] auto[0] auto[1] auto[1] 416117 1 T1 2924 T4 2886 T7 1079
auto[1] auto[1] auto[1] auto[0] auto[0] 458398 1 T1 4512 T3 4118 T6 24
auto[1] auto[1] auto[1] auto[0] auto[1] 448745 1 T1 6980 T2 64 T4 5529
auto[1] auto[1] auto[1] auto[1] auto[0] 434235 1 T1 3662 T4 4029 T17 65
auto[1] auto[1] auto[1] auto[1] auto[1] 409131 1 T1 4351 T4 5190 T7 2


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 183178 1 T1 2929 T2 16 T4 2167
auto[0] auto[0] auto[0] auto[0] auto[1] 187582 1 T1 2365 T4 2354 T17 85
auto[0] auto[0] auto[0] auto[1] auto[0] 183570 1 T1 6791 T6 23 T4 849
auto[0] auto[0] auto[0] auto[1] auto[1] 207309 1 T1 5997 T6 15 T4 781
auto[0] auto[0] auto[1] auto[0] auto[0] 1864879 1 T1 4153 T4 3182 T5 1465
auto[0] auto[0] auto[1] auto[0] auto[1] 168277 1 T1 6635 T2 221 T4 2740
auto[0] auto[0] auto[1] auto[1] auto[0] 196977 1 T1 5539 T4 1914 T5 46
auto[0] auto[0] auto[1] auto[1] auto[1] 209660 1 T1 4453 T6 25 T4 1590
auto[0] auto[1] auto[0] auto[0] auto[0] 443959 1 T1 2406 T4 8263 T7 4663
auto[0] auto[1] auto[0] auto[0] auto[1] 432162 1 T1 5573 T4 3918 T7 5819
auto[0] auto[1] auto[0] auto[1] auto[0] 449034 1 T1 3458 T4 5128 T7 1637
auto[0] auto[1] auto[0] auto[1] auto[1] 447783 1 T1 3971 T4 2928 T7 1079
auto[0] auto[1] auto[1] auto[0] auto[0] 487899 1 T1 4786 T3 4269 T6 24
auto[0] auto[1] auto[1] auto[0] auto[1] 479061 1 T1 7913 T2 64 T4 5627
auto[0] auto[1] auto[1] auto[1] auto[0] 458718 1 T1 4596 T4 4148 T17 65
auto[0] auto[1] auto[1] auto[1] auto[1] 441942 1 T1 4697 T4 5319 T7 2
auto[1] auto[0] auto[0] auto[0] auto[0] 307 1 T9 4 T147 10 T148 55
auto[1] auto[0] auto[0] auto[0] auto[1] 551 1 T1 208 T5 240 T8 5
auto[1] auto[0] auto[0] auto[1] auto[0] 1403 1 T1 16 T5 3 T8 11
auto[1] auto[0] auto[0] auto[1] auto[1] 1530 1 T1 199 T20 585 T8 14
auto[1] auto[0] auto[1] auto[0] auto[0] 208 1 T1 1 T5 90 T8 4
auto[1] auto[0] auto[1] auto[0] auto[1] 193 1 T1 15 T20 170 T149 5
auto[1] auto[0] auto[1] auto[1] auto[0] 873 1 T1 50 T20 36 T47 7
auto[1] auto[0] auto[1] auto[1] auto[1] 1180 1 T1 146 T5 470 T20 6
auto[1] auto[1] auto[0] auto[0] auto[0] 148 1 T5 4 T147 20 T150 8
auto[1] auto[1] auto[0] auto[0] auto[1] 817 1 T8 26 T47 42 T9 3
auto[1] auto[1] auto[0] auto[1] auto[0] 175 1 T1 3 T9 7 T151 72
auto[1] auto[1] auto[0] auto[1] auto[1] 347 1 T47 10 T147 6 T150 304
auto[1] auto[1] auto[1] auto[0] auto[0] 700 1 T5 2 T19 180 T149 4
auto[1] auto[1] auto[1] auto[0] auto[1] 169 1 T20 2 T8 94 T152 2
auto[1] auto[1] auto[1] auto[1] auto[0] 234 1 T1 11 T8 84 T149 3
auto[1] auto[1] auto[1] auto[1] auto[1] 234 1 T19 9 T20 82 T8 17


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 161220 1 T1 2920 T2 16 T4 2103
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 165555 1 T1 1673 T4 2229 T17 85
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 160084 1 T1 4987 T6 20 T4 805
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 178047 1 T1 4209 T6 15 T4 755
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1716805 1 T1 3000 T4 3079 T5 695
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 153044 1 T1 5181 T2 187 T4 2649
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 176293 1 T1 4108 T4 1826 T5 46
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 177233 1 T1 2487 T6 20 T4 1505
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 412554 1 T1 2033 T4 7984 T7 4348
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 400046 1 T1 4650 T4 3742 T7 5819
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 413325 1 T1 2684 T4 5046 T7 1045
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 416117 1 T1 2924 T4 2886 T7 1079
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 458398 1 T1 4512 T3 4118 T6 24
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 448745 1 T1 6980 T2 64 T4 5529
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 434235 1 T1 3662 T4 4029 T17 65
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 409131 1 T1 4351 T4 5190 T7 2
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 2841 1 T1 2 T4 35 T18 1
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3259 1 T1 46 T4 71 T5 1
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3413 1 T1 157 T4 30 T5 9
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3509 1 T1 164 T4 12 T5 3
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 44190 1 T1 152 T4 66 T5 29
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 2934 1 T1 151 T2 8 T4 48
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3374 1 T1 114 T4 54 T43 49
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3783 1 T1 23 T6 2 T4 50
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 4978 1 T1 72 T4 186 T7 48
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 5458 1 T1 159 T4 83 T18 1
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 5732 1 T1 70 T4 28 T7 123
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 5862 1 T1 103 T4 14 T24 47
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 6202 1 T1 54 T3 112 T4 127
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 5723 1 T1 154 T4 30 T18 3
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 4697 1 T1 60 T4 64 T18 1
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5639 1 T1 71 T4 66 T18 1
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 1993 1 T1 1 T4 17 T43 9
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2458 1 T1 54 T4 26 T5 1
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2643 1 T1 163 T6 1 T4 11
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2567 1 T1 152 T4 10 T5 1
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 29626 1 T1 148 T4 29 T5 29
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2090 1 T1 174 T2 6 T4 21
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2435 1 T1 113 T4 23 T43 46
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3076 1 T1 30 T6 1 T4 13
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 3745 1 T1 69 T4 65 T7 38
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 4254 1 T1 149 T4 46 T24 104
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5102 1 T1 79 T4 29 T7 100
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4774 1 T1 92 T4 13 T24 61
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 4673 1 T1 43 T3 36 T4 75
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 4608 1 T1 141 T4 21 T18 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 3675 1 T1 53 T4 46 T18 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4704 1 T1 70 T4 43 T24 11
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 1492 1 T1 2 T4 8 T43 5
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1793 1 T1 41 T4 10 T5 3
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1909 1 T1 121 T6 1 T4 3
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 1938 1 T1 169 T4 3 T24 22
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 21567 1 T1 140 T4 6 T5 28
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 1413 1 T1 131 T2 6 T4 6
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1824 1 T1 110 T4 10 T43 23
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2250 1 T1 39 T6 2 T4 7
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 2787 1 T1 66 T4 25 T7 49
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 3423 1 T1 148 T4 20 T24 97
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4406 1 T1 63 T4 11 T7 113
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 3916 1 T1 90 T4 2 T24 37
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 3558 1 T1 50 T3 3 T4 22
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 3790 1 T1 128 T4 10 T24 30
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 2796 1 T1 48 T4 6 T24 16
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3912 1 T1 69 T4 16 T24 5
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 1563 1 T1 1 T4 1 T43 5
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1871 1 T1 39 T4 8 T24 9
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 1771 1 T1 135 T5 3 T24 32
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2012 1 T1 177 T4 1 T5 3
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 15868 1 T1 180 T4 2 T5 31
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 1359 1 T1 109 T2 6 T4 8
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 1789 1 T1 92 T4 1 T43 19
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2295 1 T1 34 T4 3 T25 18
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 2906 1 T1 63 T4 2 T7 46
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 3298 1 T1 129 T4 10 T24 85
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 3999 1 T1 65 T4 5 T7 94
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3706 1 T1 79 T4 4 T24 54
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 3257 1 T1 42 T4 29 T5 1
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 3496 1 T1 115 T4 15 T24 23
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 2685 1 T1 51 T4 2 T24 14
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3653 1 T1 44 T4 4 T24 9
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1140 1 T25 13 T44 25 T61 7
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1433 1 T1 34 T4 4 T24 10
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1506 1 T1 71 T6 1 T5 18
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1491 1 T1 147 T5 4 T24 16
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 10810 1 T1 117 T5 30 T24 3
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 985 1 T1 103 T2 4 T4 2
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1315 1 T1 66 T43 10 T61 19
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1670 1 T1 40 T4 2 T43 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 2124 1 T1 38 T7 43 T5 11
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 2789 1 T1 119 T4 8 T24 70
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3647 1 T1 68 T4 3 T7 94
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3155 1 T1 62 T4 2 T24 53
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 2631 1 T1 30 T5 4 T143 1
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 2901 1 T1 82 T4 4 T24 26
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 2139 1 T1 41 T4 1 T24 14
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3211 1 T1 39 T24 7 T44 13
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 961 1 T1 1 T43 3 T25 10
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1159 1 T1 31 T4 3 T24 6
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1033 1 T1 87 T5 1 T24 16
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1175 1 T1 119 T5 5 T24 16
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 7617 1 T1 109 T5 27 T24 6
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 830 1 T1 51 T2 4 T24 23
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1104 1 T1 45 T43 13 T61 17
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1576 1 T1 25 T4 2 T25 13
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2059 1 T1 31 T7 34 T24 20
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2140 1 T1 94 T4 6 T24 41
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2927 1 T1 47 T4 1 T7 48
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2517 1 T1 61 T24 28 T44 21
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 2036 1 T1 23 T143 1 T25 1
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2217 1 T1 73 T4 4 T24 20
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 1811 1 T1 31 T24 10 T59 3
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2524 1 T1 26 T24 4 T44 8
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 731 1 T1 2 T43 1 T25 3
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 817 1 T1 17 T4 2 T24 8
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 781 1 T1 58 T5 18 T24 5
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 801 1 T1 91 T5 5 T24 9
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4551 1 T1 40 T5 3 T24 7
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 472 1 T1 18 T17 1 T5 15
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 764 1 T1 28 T43 5 T61 5
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 973 1 T1 33 T4 2 T25 3
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1203 1 T1 20 T4 1 T7 24
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1463 1 T1 58 T4 3 T24 22
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2035 1 T1 35 T4 3 T7 17
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1704 1 T1 43 T4 3 T24 17
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 1350 1 T1 14 T4 1 T44 9
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1425 1 T1 70 T4 3 T24 6
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1161 1 T1 32 T24 12 T59 2
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1665 1 T1 16 T24 2 T44 6

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