Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17144066	1			T1	205995		T2	226		T3	16576
all_pins[1]	17144066	1			T1	205995		T2	226		T3	16576
all_pins[2]	17144066	1			T1	205995		T2	226		T3	16576

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43850397	1			T1	504125		T2	629		T3	41444
values[0x1]	7581801	1			T1	113860		T2	49		T3	8284
transitions[0x0=>0x1]	7581610	1			T1	113860		T2	49		T3	8284
transitions[0x1=>0x0]	7581623	1			T1	113860		T2	49		T3	8284

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17123578	1			T1	205792		T2	222		T3	16396
all_pins[0]	values[0x1]	20488	1			T1	203		T2	4		T3	180
all_pins[0]	transitions[0x0=>0x1]	20416	1			T1	203		T2	4		T3	180
all_pins[0]	transitions[0x1=>0x0]	7560902	1			T1	113656		T2	45		T3	8104
all_pins[1]	values[0x0]	17143714	1			T1	205994		T2	226		T3	16576
all_pins[1]	values[0x1]	352	1			T1	1		T4	1		T43	2
all_pins[1]	transitions[0x0=>0x1]	299	1			T1	1		T4	1		T43	2
all_pins[1]	transitions[0x1=>0x0]	20435	1			T1	203		T2	4		T3	180
all_pins[2]	values[0x0]	9583105	1			T1	92339		T2	181		T3	8472
all_pins[2]	values[0x1]	7560961	1			T1	113656		T2	45		T3	8104
all_pins[2]	transitions[0x0=>0x1]	7560895	1			T1	113656		T2	45		T3	8104
all_pins[2]	transitions[0x1=>0x0]	286	1			T1	1		T43	2		T19	2