Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1046 1 T1 7 T4 8 T43 10
all_values[1] 1046 1 T1 7 T4 8 T43 10
all_values[2] 1046 1 T1 7 T4 8 T43 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1563 1 T1 14 T4 7 T43 15
auto[1] 1575 1 T1 7 T4 17 T43 15


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1091 1 T1 9 T4 14 T43 12
auto[1] 2047 1 T1 12 T4 10 T43 18


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1757 1 T1 14 T4 17 T43 16
auto[1] 1381 1 T1 7 T4 7 T43 14


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 190 1 T1 2 T4 1 T43 4
all_values[0] auto[0] auto[0] auto[1] 88 1 T1 1 T80 5 T8 3
all_values[0] auto[0] auto[1] auto[0] 176 1 T4 4 T43 2 T80 3
all_values[0] auto[0] auto[1] auto[1] 114 1 T1 2 T81 1 T8 3
all_values[0] auto[1] auto[0] auto[1] 243 1 T4 1 T43 2 T80 9
all_values[0] auto[1] auto[1] auto[1] 235 1 T1 2 T4 2 T43 2
all_values[1] auto[0] auto[0] auto[0] 163 1 T1 3 T4 3 T43 2
all_values[1] auto[0] auto[0] auto[1] 133 1 T1 2 T4 1 T43 1
all_values[1] auto[0] auto[1] auto[0] 142 1 T4 1 T43 1 T8 7
all_values[1] auto[0] auto[1] auto[1] 139 1 T4 1 T43 1 T80 3
all_values[1] auto[1] auto[0] auto[1] 246 1 T1 2 T43 2 T80 6
all_values[1] auto[1] auto[1] auto[1] 223 1 T4 2 T43 3 T80 7
all_values[2] auto[0] auto[0] auto[0] 206 1 T1 4 T43 1 T80 2
all_values[2] auto[0] auto[0] auto[1] 77 1 T80 3 T81 2 T8 2
all_values[2] auto[0] auto[1] auto[0] 214 1 T4 5 T43 2 T80 6
all_values[2] auto[0] auto[1] auto[1] 115 1 T4 1 T43 2 T80 3
all_values[2] auto[1] auto[0] auto[1] 217 1 T4 1 T43 3 T80 7
all_values[2] auto[1] auto[1] auto[1] 217 1 T1 3 T4 1 T43 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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