Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3988	1			T1	67		T6	2		T4	69
sha2_none	4186	1			T1	79		T2	1		T4	77
sha2_512	7479	1			T1	81		T2	2		T6	1
sha2_384	7321	1			T1	74		T2	2		T3	180
sha2_256	6225	1			T1	86		T6	1		T4	74

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18504

1

T1

183

T2

5

T3

180

auto[1]

11063

1

T1

206

T6

3

T4

161

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10995

1

T1

191

T2

1

T6

2

auto[1]

18572

1

T1

198

T2

4

T3

180

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15102

1

T1

188

T2

2

T3

180

disabled

14465

1

T1

201

T2

3

T6

3

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4438	1			T1	71		T6	1		T4	69
key_none	7687	1			T1	56		T4	45		T17	2
key_1024	4286	1			T1	42		T3	60		T6	1
key_512	3731	1			T1	54		T2	1		T3	120
key_384	3353	1			T1	59		T2	3		T4	49
key_256	3034	1			T1	42		T2	1		T6	1
key_128	2950	1			T1	62		T6	1		T4	50

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18651

1

T1

189

T2

1

T3

180

auto[1]

10916

1

T1

200

T2

4

T6

2

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29385

1

T1

379

T2

5

T3

180

disabled

182

1

T1

10

T4

1

T50

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1578

1

T1

26

T4

25

T7

2

enabled

auto[0]

auto[0]

auto[1]

1552

1

T1

24

T4

21

T7

7

enabled

auto[0]

auto[1]

auto[0]

1473

1

T1

19

T4

20

T7

2

enabled

auto[0]

auto[1]

auto[1]

1530

1

T1

27

T4

25

T7

2

enabled

auto[1]

auto[0]

auto[0]

4233

1

T1

22

T3

180

T6

1

enabled

auto[1]

auto[0]

auto[1]

1533

1

T1

20

T2

2

T4

30

enabled

auto[1]

auto[1]

auto[0]

1727

1

T1

24

T4

30

T17

1

enabled

auto[1]

auto[1]

auto[1]

1476

1

T1

26

T4

19

T7

1

disabled

auto[0]

auto[0]

auto[0]

1207

1

T1

17

T2

1

T4

24

disabled

auto[0]

auto[0]

auto[1]

1249

1

T1

22

T4

25

T17

1

disabled

auto[0]

auto[1]

auto[0]

1209

1

T1

28

T6

1

T4

16

disabled

auto[0]

auto[1]

auto[1]

1197

1

T1

28

T6

1

T4

14

disabled

auto[1]

auto[0]

auto[0]

6021

1

T1

25

T4

27

T5

4

disabled

auto[1]

auto[0]

auto[1]

1131

1

T1

27

T2

2

T4

16

disabled

auto[1]

auto[1]

auto[0]

1203

1

T1

28

T4

17

T17

1

disabled

auto[1]

auto[1]

auto[1]

1248

1

T1

26

T6

1

T4

20

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15028

1

T1

186

T2

2

T3

180

enabled

disabled

74

1

T1

2

T50

2

T81

1

disabled

disabled

108

1

T1

8

T4

1

T142

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14357

1

T1

193

T2

3

T6

3

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	969	1			T1	22		T6	1		T4	10
key_invalid	sha2_none	806	1			T1	17		T4	17		T17	2
key_invalid	sha2_512	851	1			T1	9		T4	13		T7	2
key_invalid	sha2_384	847	1			T1	10		T4	9		T7	1
key_invalid	sha2_256	868	1			T1	13		T4	17		T7	2
key_none	sha2_invalid	489	1			T1	4		T4	8		T7	1
key_none	sha2_none	570	1			T1	10		T4	16		T18	1
key_none	sha2_512	2496	1			T1	10		T4	8		T17	1
key_none	sha2_384	2522	1			T1	15		T4	7		T17	1
key_none	sha2_256	1557	1			T1	16		T4	6		T5	4
key_1024	sha2_invalid	506	1			T1	6		T4	14		T7	1
key_1024	sha2_none	526	1			T1	9		T4	9		T7	1
key_1024	sha2_512	1725	1			T1	6		T6	1		T4	3
key_1024	sha2_384	897	1			T1	9		T3	60		T4	9
key_512	sha2_invalid	528	1			T1	7		T4	5		T7	1
key_512	sha2_none	589	1			T1	12		T2	1		T4	15
key_512	sha2_512	599	1			T1	14		T4	5		T17	1
key_512	sha2_384	1165	1			T1	10		T3	120		T4	8
key_512	sha2_256	808	1			T1	11		T4	11		T5	1
key_384	sha2_invalid	465	1			T1	8		T4	11		T7	1
key_384	sha2_none	570	1			T1	19		T4	7		T7	1
key_384	sha2_512	604	1			T1	13		T2	1		T4	8
key_384	sha2_384	607	1			T1	10		T2	2		T4	11
key_384	sha2_256	1058	1			T1	8		T4	12		T7	1
key_256	sha2_invalid	514	1			T1	5		T4	10		T5	1
key_256	sha2_none	539	1			T1	7		T4	6		T7	2
key_256	sha2_512	607	1			T1	17		T2	1		T4	14
key_256	sha2_384	614	1			T1	3		T4	12		T7	2
key_256	sha2_256	719	1			T1	10		T6	1		T4	8
key_128	sha2_invalid	492	1			T1	14		T6	1		T4	11
key_128	sha2_none	576	1			T1	4		T4	7		T24	2
key_128	sha2_512	576	1			T1	12		T4	9		T5	1
key_128	sha2_384	653	1			T1	16		T4	11		T7	1
key_128	sha2_256	606	1			T1	16		T4	11		T18	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

595

1

T1

12

T4

9

T5

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	969	1			T1	22		T6	1		T4	10
key_invalid	sha2_none	806	1			T1	17		T4	17		T17	2
key_invalid	sha2_512	851	1			T1	9		T4	13		T7	2
key_invalid	sha2_384	847	1			T1	10		T4	9		T7	1
key_invalid	sha2_256	868	1			T1	13		T4	17		T7	2
key_none	sha2_invalid	489	1			T1	4		T4	8		T7	1
key_none	sha2_none	570	1			T1	10		T4	16		T18	1
key_none	sha2_512	2496	1			T1	10		T4	8		T17	1
key_none	sha2_384	2522	1			T1	15		T4	7		T17	1
key_none	sha2_256	1557	1			T1	16		T4	6		T5	4
key_1024	sha2_invalid	506	1			T1	6		T4	14		T7	1
key_1024	sha2_none	526	1			T1	9		T4	9		T7	1
key_1024	sha2_512	1725	1			T1	6		T6	1		T4	3
key_1024	sha2_384	897	1			T1	9		T3	60		T4	9
key_1024	sha2_256	595	1			T1	12		T4	9		T5	1
key_512	sha2_invalid	528	1			T1	7		T4	5		T7	1
key_512	sha2_none	589	1			T1	12		T2	1		T4	15
key_512	sha2_512	599	1			T1	14		T4	5		T17	1
key_512	sha2_384	1165	1			T1	10		T3	120		T4	8
key_512	sha2_256	808	1			T1	11		T4	11		T5	1
key_384	sha2_invalid	465	1			T1	8		T4	11		T7	1
key_384	sha2_none	570	1			T1	19		T4	7		T7	1
key_384	sha2_512	604	1			T1	13		T2	1		T4	8
key_384	sha2_384	607	1			T1	10		T2	2		T4	11
key_384	sha2_256	1058	1			T1	8		T4	12		T7	1
key_256	sha2_invalid	514	1			T1	5		T4	10		T5	1
key_256	sha2_none	539	1			T1	7		T4	6		T7	2
key_256	sha2_512	607	1			T1	17		T2	1		T4	14
key_256	sha2_384	614	1			T1	3		T4	12		T7	2
key_256	sha2_256	719	1			T1	10		T6	1		T4	8
key_128	sha2_invalid	492	1			T1	14		T6	1		T4	11
key_128	sha2_none	576	1			T1	4		T4	7		T24	2
key_128	sha2_512	576	1			T1	12		T4	9		T5	1
key_128	sha2_384	653	1			T1	16		T4	11		T7	1
key_128	sha2_256	606	1			T1	16		T4	11		T18	1