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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.45 95.40 97.17 100.00 100.00 98.27 98.48 99.85


Total test records in report: 658
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T124 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2232392910 Aug 03 04:35:24 PM PDT 24 Aug 03 04:35:26 PM PDT 24 62106229 ps
T534 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3660201279 Aug 03 04:35:15 PM PDT 24 Aug 03 04:35:17 PM PDT 24 122769173 ps
T535 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2847790247 Aug 03 04:35:42 PM PDT 24 Aug 03 04:35:42 PM PDT 24 28630206 ps
T125 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2283838125 Aug 03 04:35:18 PM PDT 24 Aug 03 04:35:19 PM PDT 24 108768448 ps
T536 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1321645128 Aug 03 04:35:25 PM PDT 24 Aug 03 04:35:28 PM PDT 24 279742171 ps
T537 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1770758658 Aug 03 04:35:17 PM PDT 24 Aug 03 04:35:27 PM PDT 24 734790714 ps
T538 /workspace/coverage/cover_reg_top/14.hmac_intr_test.37273062 Aug 03 04:35:27 PM PDT 24 Aug 03 04:35:28 PM PDT 24 21556778 ps
T539 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.685179741 Aug 03 04:35:11 PM PDT 24 Aug 03 04:35:11 PM PDT 24 53820275 ps
T540 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3235769745 Aug 03 04:35:29 PM PDT 24 Aug 03 04:35:29 PM PDT 24 14741010 ps
T541 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3044685669 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:21 PM PDT 24 16694767 ps
T65 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.988854265 Aug 03 04:35:18 PM PDT 24 Aug 03 04:35:22 PM PDT 24 260958987 ps
T542 /workspace/coverage/cover_reg_top/8.hmac_intr_test.336099071 Aug 03 04:35:16 PM PDT 24 Aug 03 04:35:17 PM PDT 24 71869166 ps
T543 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3565721773 Aug 03 04:35:19 PM PDT 24 Aug 03 04:51:13 PM PDT 24 129965768342 ps
T544 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.4262050615 Aug 03 04:35:27 PM PDT 24 Aug 03 04:35:28 PM PDT 24 226361523 ps
T109 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.182544899 Aug 03 04:35:30 PM PDT 24 Aug 03 04:35:34 PM PDT 24 16098600 ps
T545 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1984612029 Aug 03 04:35:18 PM PDT 24 Aug 03 04:35:20 PM PDT 24 22694858 ps
T126 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3979086241 Aug 03 04:35:21 PM PDT 24 Aug 03 04:35:23 PM PDT 24 175218610 ps
T546 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2764851921 Aug 03 04:35:23 PM PDT 24 Aug 03 04:35:25 PM PDT 24 477878814 ps
T127 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2597339342 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:10 PM PDT 24 400886479 ps
T547 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3275994031 Aug 03 04:35:22 PM PDT 24 Aug 03 04:35:25 PM PDT 24 227077738 ps
T548 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.707683049 Aug 03 04:35:30 PM PDT 24 Aug 03 04:35:35 PM PDT 24 62490906 ps
T128 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.807381557 Aug 03 04:35:18 PM PDT 24 Aug 03 04:35:20 PM PDT 24 1178371530 ps
T549 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2119398229 Aug 03 04:35:38 PM PDT 24 Aug 03 04:35:39 PM PDT 24 14804916 ps
T110 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2425126374 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:17 PM PDT 24 613672278 ps
T550 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3444998981 Aug 03 04:35:24 PM PDT 24 Aug 03 04:35:28 PM PDT 24 171828024 ps
T66 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.700813549 Aug 03 04:35:22 PM PDT 24 Aug 03 04:35:25 PM PDT 24 617734532 ps
T551 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4049428560 Aug 03 04:35:23 PM PDT 24 Aug 03 04:41:35 PM PDT 24 163612199231 ps
T136 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3415279951 Aug 03 04:35:23 PM PDT 24 Aug 03 04:35:27 PM PDT 24 194373472 ps
T552 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2227552534 Aug 03 04:35:41 PM PDT 24 Aug 03 04:35:42 PM PDT 24 45269784 ps
T553 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1692407442 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:21 PM PDT 24 29728464 ps
T554 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3206726648 Aug 03 04:35:27 PM PDT 24 Aug 03 04:35:29 PM PDT 24 151652661 ps
T111 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4102303365 Aug 03 04:35:08 PM PDT 24 Aug 03 04:35:25 PM PDT 24 1631244293 ps
T555 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.126407889 Aug 03 04:35:23 PM PDT 24 Aug 03 04:35:24 PM PDT 24 26202274 ps
T556 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.784655923 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:22 PM PDT 24 48269598 ps
T557 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2336509763 Aug 03 04:35:44 PM PDT 24 Aug 03 04:35:45 PM PDT 24 44400347 ps
T558 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4141892432 Aug 03 04:35:16 PM PDT 24 Aug 03 04:35:19 PM PDT 24 59767703 ps
T559 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1916063640 Aug 03 04:35:14 PM PDT 24 Aug 03 04:35:17 PM PDT 24 443083158 ps
T112 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1728799430 Aug 03 04:35:19 PM PDT 24 Aug 03 04:35:25 PM PDT 24 209741652 ps
T560 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1492996824 Aug 03 04:35:25 PM PDT 24 Aug 03 04:35:26 PM PDT 24 35812788 ps
T129 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2707330430 Aug 03 04:35:19 PM PDT 24 Aug 03 04:35:22 PM PDT 24 451936414 ps
T130 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.548306051 Aug 03 04:35:24 PM PDT 24 Aug 03 04:35:26 PM PDT 24 155679960 ps
T561 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1311754193 Aug 03 04:35:43 PM PDT 24 Aug 03 04:35:43 PM PDT 24 65955009 ps
T562 /workspace/coverage/cover_reg_top/37.hmac_intr_test.4276085967 Aug 03 04:35:43 PM PDT 24 Aug 03 04:35:44 PM PDT 24 11519953 ps
T131 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1810252749 Aug 03 04:35:23 PM PDT 24 Aug 03 04:35:25 PM PDT 24 112718844 ps
T113 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.563314643 Aug 03 04:35:18 PM PDT 24 Aug 03 04:35:19 PM PDT 24 270684274 ps
T563 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3972995945 Aug 03 04:35:40 PM PDT 24 Aug 03 04:35:40 PM PDT 24 14116819 ps
T564 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3252140984 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:10 PM PDT 24 71509835 ps
T565 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3834940442 Aug 03 04:35:44 PM PDT 24 Aug 03 04:35:46 PM PDT 24 115148961 ps
T114 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3224016089 Aug 03 04:35:14 PM PDT 24 Aug 03 04:35:23 PM PDT 24 1147213303 ps
T566 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.145147702 Aug 03 04:35:30 PM PDT 24 Aug 03 04:35:32 PM PDT 24 94065858 ps
T133 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.55730242 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:25 PM PDT 24 576011783 ps
T567 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1472534202 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:21 PM PDT 24 17188429 ps
T568 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1074722585 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:22 PM PDT 24 563093101 ps
T569 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1504891074 Aug 03 04:35:50 PM PDT 24 Aug 03 04:35:50 PM PDT 24 97619557 ps
T134 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1373580123 Aug 03 04:35:22 PM PDT 24 Aug 03 04:35:25 PM PDT 24 302882913 ps
T570 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.592614214 Aug 03 04:35:31 PM PDT 24 Aug 03 04:35:32 PM PDT 24 19009767 ps
T115 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2173841673 Aug 03 04:35:16 PM PDT 24 Aug 03 04:35:17 PM PDT 24 77426423 ps
T571 /workspace/coverage/cover_reg_top/3.hmac_intr_test.266297777 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:10 PM PDT 24 17133724 ps
T572 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2234699595 Aug 03 04:35:16 PM PDT 24 Aug 03 04:35:19 PM PDT 24 45433034 ps
T573 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2164548306 Aug 03 04:35:40 PM PDT 24 Aug 03 04:35:41 PM PDT 24 12187577 ps
T574 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1551342898 Aug 03 04:35:27 PM PDT 24 Aug 03 04:35:28 PM PDT 24 137753374 ps
T575 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3240903603 Aug 03 04:35:37 PM PDT 24 Aug 03 04:35:38 PM PDT 24 137282194 ps
T576 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.846750192 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:21 PM PDT 24 38664772 ps
T577 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1391701465 Aug 03 04:35:36 PM PDT 24 Aug 03 04:35:36 PM PDT 24 25557033 ps
T578 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.545512277 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:21 PM PDT 24 30226989 ps
T116 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2118921071 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:26 PM PDT 24 1730247337 ps
T579 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1694651695 Aug 03 04:35:23 PM PDT 24 Aug 03 04:35:26 PM PDT 24 375272412 ps
T580 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1644373630 Aug 03 04:35:31 PM PDT 24 Aug 03 04:35:31 PM PDT 24 13432285 ps
T581 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1544041537 Aug 03 04:35:24 PM PDT 24 Aug 03 04:35:26 PM PDT 24 109869899 ps
T582 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1466945178 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:14 PM PDT 24 220254218 ps
T583 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2360164752 Aug 03 04:35:14 PM PDT 24 Aug 03 04:35:14 PM PDT 24 31461133 ps
T117 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3771683904 Aug 03 04:35:19 PM PDT 24 Aug 03 04:35:20 PM PDT 24 35511878 ps
T584 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.687266813 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:12 PM PDT 24 58473185 ps
T118 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1367820006 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:13 PM PDT 24 983907835 ps
T585 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3628981297 Aug 03 04:35:08 PM PDT 24 Aug 03 04:35:12 PM PDT 24 215829244 ps
T135 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1661086996 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:23 PM PDT 24 379673907 ps
T586 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4040626604 Aug 03 04:35:06 PM PDT 24 Aug 03 04:35:07 PM PDT 24 16910808 ps
T587 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3865294776 Aug 03 04:35:11 PM PDT 24 Aug 03 04:35:15 PM PDT 24 17109451 ps
T588 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.982065253 Aug 03 04:35:14 PM PDT 24 Aug 03 04:35:15 PM PDT 24 74006598 ps
T137 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3556831485 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:14 PM PDT 24 543886585 ps
T589 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2371010415 Aug 03 04:35:22 PM PDT 24 Aug 03 04:35:24 PM PDT 24 250743367 ps
T590 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2152469818 Aug 03 04:35:17 PM PDT 24 Aug 03 04:35:18 PM PDT 24 181436772 ps
T119 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.60952544 Aug 03 04:35:14 PM PDT 24 Aug 03 04:35:15 PM PDT 24 49144700 ps
T591 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3634299095 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:12 PM PDT 24 46051525 ps
T592 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4059858897 Aug 03 04:35:38 PM PDT 24 Aug 03 04:35:40 PM PDT 24 358255672 ps
T593 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1083878992 Aug 03 04:35:19 PM PDT 24 Aug 03 04:35:20 PM PDT 24 52791614 ps
T594 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4001260492 Aug 03 04:35:19 PM PDT 24 Aug 03 04:35:21 PM PDT 24 29733962 ps
T595 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2867194987 Aug 03 04:35:35 PM PDT 24 Aug 03 04:35:36 PM PDT 24 49778237 ps
T596 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1636422537 Aug 03 04:35:34 PM PDT 24 Aug 03 04:35:35 PM PDT 24 53982073 ps
T597 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2238710733 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:11 PM PDT 24 82478425 ps
T598 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2637949434 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:10 PM PDT 24 30670868 ps
T599 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3401309104 Aug 03 04:35:46 PM PDT 24 Aug 03 04:35:47 PM PDT 24 12145237 ps
T140 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4171892643 Aug 03 04:35:16 PM PDT 24 Aug 03 04:35:20 PM PDT 24 358591730 ps
T600 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2809659570 Aug 03 04:35:14 PM PDT 24 Aug 03 04:35:17 PM PDT 24 59932281 ps
T601 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1093071174 Aug 03 04:35:44 PM PDT 24 Aug 03 04:35:44 PM PDT 24 12639684 ps
T602 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1895239978 Aug 03 04:35:45 PM PDT 24 Aug 03 04:35:46 PM PDT 24 29327584 ps
T603 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3102822938 Aug 03 04:35:17 PM PDT 24 Aug 03 04:35:19 PM PDT 24 26157999 ps
T604 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2311557721 Aug 03 04:35:23 PM PDT 24 Aug 03 04:45:10 PM PDT 24 115781021036 ps
T605 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2610833232 Aug 03 04:35:31 PM PDT 24 Aug 03 04:35:32 PM PDT 24 15750252 ps
T606 /workspace/coverage/cover_reg_top/32.hmac_intr_test.326322000 Aug 03 04:35:48 PM PDT 24 Aug 03 04:35:49 PM PDT 24 16085804 ps
T607 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1452719679 Aug 03 04:35:44 PM PDT 24 Aug 03 04:35:45 PM PDT 24 49590290 ps
T608 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1244094936 Aug 03 04:35:13 PM PDT 24 Aug 03 04:35:15 PM PDT 24 659653082 ps
T609 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1777239141 Aug 03 04:35:14 PM PDT 24 Aug 03 04:35:15 PM PDT 24 41462511 ps
T610 /workspace/coverage/cover_reg_top/33.hmac_intr_test.65157438 Aug 03 04:35:44 PM PDT 24 Aug 03 04:35:45 PM PDT 24 15111921 ps
T611 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2087326825 Aug 03 04:35:08 PM PDT 24 Aug 03 04:35:12 PM PDT 24 74213382 ps
T612 /workspace/coverage/cover_reg_top/34.hmac_intr_test.769356939 Aug 03 04:35:44 PM PDT 24 Aug 03 04:35:45 PM PDT 24 23830733 ps
T120 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2722930517 Aug 03 04:35:18 PM PDT 24 Aug 03 04:35:19 PM PDT 24 44681531 ps
T141 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1473803650 Aug 03 04:35:19 PM PDT 24 Aug 03 04:35:23 PM PDT 24 366267207 ps
T613 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2984839048 Aug 03 04:35:26 PM PDT 24 Aug 03 04:35:27 PM PDT 24 74515073 ps
T614 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4194245222 Aug 03 04:35:22 PM PDT 24 Aug 03 04:35:24 PM PDT 24 99559439 ps
T615 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3417879526 Aug 03 04:35:21 PM PDT 24 Aug 03 04:45:24 PM PDT 24 61211369258 ps
T616 /workspace/coverage/cover_reg_top/11.hmac_intr_test.833618683 Aug 03 04:35:15 PM PDT 24 Aug 03 04:35:16 PM PDT 24 48846649 ps
T617 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3189291921 Aug 03 04:35:23 PM PDT 24 Aug 03 04:35:25 PM PDT 24 164069331 ps
T618 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.448025535 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:22 PM PDT 24 244705504 ps
T619 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3323219359 Aug 03 04:35:48 PM PDT 24 Aug 03 04:35:48 PM PDT 24 15678841 ps
T620 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2024474971 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:21 PM PDT 24 38491429 ps
T621 /workspace/coverage/cover_reg_top/30.hmac_intr_test.999224170 Aug 03 04:35:39 PM PDT 24 Aug 03 04:35:39 PM PDT 24 16895453 ps
T622 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3779409367 Aug 03 04:35:14 PM PDT 24 Aug 03 04:51:56 PM PDT 24 279183842137 ps
T623 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3468457466 Aug 03 04:35:19 PM PDT 24 Aug 03 04:35:20 PM PDT 24 115859506 ps
T138 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2377374311 Aug 03 04:35:24 PM PDT 24 Aug 03 04:35:28 PM PDT 24 506067476 ps
T624 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2321718264 Aug 03 04:35:30 PM PDT 24 Aug 03 04:35:31 PM PDT 24 30799646 ps
T625 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2548180684 Aug 03 04:35:19 PM PDT 24 Aug 03 04:35:25 PM PDT 24 229797505 ps
T626 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.21394183 Aug 03 04:35:20 PM PDT 24 Aug 03 04:35:22 PM PDT 24 149100151 ps
T627 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2369184878 Aug 03 04:35:15 PM PDT 24 Aug 03 04:35:19 PM PDT 24 121052540 ps
T628 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1312326880 Aug 03 04:35:24 PM PDT 24 Aug 03 04:35:26 PM PDT 24 768773266 ps
T629 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3670894167 Aug 03 04:35:32 PM PDT 24 Aug 03 04:35:33 PM PDT 24 13379735 ps
T630 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1960242021 Aug 03 04:35:08 PM PDT 24 Aug 03 04:35:09 PM PDT 24 23994412 ps
T631 /workspace/coverage/cover_reg_top/13.hmac_intr_test.694671900 Aug 03 04:35:24 PM PDT 24 Aug 03 04:35:25 PM PDT 24 48552231 ps
T632 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.796981346 Aug 03 04:35:47 PM PDT 24 Aug 03 04:49:14 PM PDT 24 76607154611 ps
T139 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3318579913 Aug 03 04:35:30 PM PDT 24 Aug 03 04:35:33 PM PDT 24 89388718 ps
T633 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1344094748 Aug 03 04:35:30 PM PDT 24 Aug 03 04:35:34 PM PDT 24 94105308 ps
T634 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.4049555130 Aug 03 04:35:36 PM PDT 24 Aug 03 04:35:38 PM PDT 24 80855010 ps
T635 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4283660769 Aug 03 04:35:18 PM PDT 24 Aug 03 04:35:21 PM PDT 24 717691489 ps
T636 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3134070211 Aug 03 04:35:34 PM PDT 24 Aug 03 04:35:34 PM PDT 24 16269838 ps
T637 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3710670080 Aug 03 04:35:23 PM PDT 24 Aug 03 04:35:24 PM PDT 24 29832417 ps
T638 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4180119535 Aug 03 04:35:15 PM PDT 24 Aug 03 04:35:19 PM PDT 24 816947433 ps
T639 /workspace/coverage/cover_reg_top/48.hmac_intr_test.595811400 Aug 03 04:35:38 PM PDT 24 Aug 03 04:35:39 PM PDT 24 25310066 ps
T640 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2725818545 Aug 03 04:35:43 PM PDT 24 Aug 03 04:35:44 PM PDT 24 14058309 ps
T641 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3227434734 Aug 03 04:35:22 PM PDT 24 Aug 03 04:35:23 PM PDT 24 175312676 ps
T642 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2766065334 Aug 03 04:35:14 PM PDT 24 Aug 03 04:35:14 PM PDT 24 57700142 ps
T643 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3135674814 Aug 03 04:35:16 PM PDT 24 Aug 03 04:35:26 PM PDT 24 209628704 ps
T644 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.984309516 Aug 03 04:35:20 PM PDT 24 Aug 03 04:50:13 PM PDT 24 66950929238 ps
T645 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2833254721 Aug 03 04:35:16 PM PDT 24 Aug 03 04:35:18 PM PDT 24 33760748 ps
T121 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1141214033 Aug 03 04:35:28 PM PDT 24 Aug 03 04:35:29 PM PDT 24 31089906 ps
T646 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.218811382 Aug 03 04:35:16 PM PDT 24 Aug 03 04:35:20 PM PDT 24 198474488 ps
T647 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1355548904 Aug 03 04:35:44 PM PDT 24 Aug 03 04:35:45 PM PDT 24 18012690 ps
T648 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2536186454 Aug 03 04:35:10 PM PDT 24 Aug 03 04:35:11 PM PDT 24 173740271 ps
T649 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2192120661 Aug 03 04:35:33 PM PDT 24 Aug 03 04:35:34 PM PDT 24 37414424 ps
T650 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.686152297 Aug 03 04:35:18 PM PDT 24 Aug 03 04:35:22 PM PDT 24 95636918 ps
T651 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2021271523 Aug 03 04:35:18 PM PDT 24 Aug 03 04:35:20 PM PDT 24 22056103 ps
T652 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1532422518 Aug 03 04:35:12 PM PDT 24 Aug 03 04:35:15 PM PDT 24 601280895 ps
T122 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1715672865 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:10 PM PDT 24 97127817 ps
T653 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2795500091 Aug 03 04:35:47 PM PDT 24 Aug 03 04:35:47 PM PDT 24 56668583 ps
T654 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3322753104 Aug 03 04:35:42 PM PDT 24 Aug 03 04:35:43 PM PDT 24 14142656 ps
T655 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3917778347 Aug 03 04:35:21 PM PDT 24 Aug 03 04:35:23 PM PDT 24 108810685 ps
T656 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2651442663 Aug 03 04:35:19 PM PDT 24 Aug 03 04:35:20 PM PDT 24 28715956 ps
T657 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1587107858 Aug 03 04:35:09 PM PDT 24 Aug 03 04:35:10 PM PDT 24 29136910 ps
T658 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1888621295 Aug 03 04:35:30 PM PDT 24 Aug 03 04:35:32 PM PDT 24 375906386 ps

Test location /workspace/coverage/default/47.hmac_stress_all.1386501049
Short name T4
Test name
Test status
Simulation time 74872172059 ps
CPU time 1398.66 seconds
Started Aug 03 04:42:56 PM PDT 24
Finished Aug 03 05:06:15 PM PDT 24
Peak memory 690276 kb
Host smart-b1729a0d-c187-414f-9f90-c8c5d0c57054
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386501049 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1386501049
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2452247165
Short name T43
Test name
Test status
Simulation time 222097090284 ps
CPU time 1901.75 seconds
Started Aug 03 04:42:04 PM PDT 24
Finished Aug 03 05:13:46 PM PDT 24
Peak memory 771584 kb
Host smart-db101258-9691-4779-993f-4184f1ac908e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452247165 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2452247165
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.823604737
Short name T8
Test name
Test status
Simulation time 45313383285 ps
CPU time 3004.05 seconds
Started Aug 03 04:42:17 PM PDT 24
Finished Aug 03 05:32:21 PM PDT 24
Peak memory 780568 kb
Host smart-1178ddb2-17d7-49c1-a242-084496913925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823604737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.823604737
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.55730242
Short name T133
Test name
Test status
Simulation time 576011783 ps
CPU time 4.72 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 200000 kb
Host smart-7a9f8f56-baee-4716-9bfa-ea79fec830b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55730242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.55730242
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3748660299
Short name T14
Test name
Test status
Simulation time 66524554377 ps
CPU time 882.16 seconds
Started Aug 03 04:41:53 PM PDT 24
Finished Aug 03 04:56:35 PM PDT 24
Peak memory 453748 kb
Host smart-0f5a74d3-1682-487b-8b70-f1d483946936
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748660299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3748660299
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1392746597
Short name T22
Test name
Test status
Simulation time 64551701113 ps
CPU time 728.64 seconds
Started Aug 03 04:42:10 PM PDT 24
Finished Aug 03 04:54:19 PM PDT 24
Peak memory 363504 kb
Host smart-3c37e0ed-ea71-42e7-bf65-8b9ec5f9df60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392746597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1392746597
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2113483682
Short name T54
Test name
Test status
Simulation time 61267793 ps
CPU time 0.8 seconds
Started Aug 03 04:41:58 PM PDT 24
Finished Aug 03 04:41:59 PM PDT 24
Peak memory 218568 kb
Host smart-0e7a604a-03e6-4565-9a37-ee64e13a6398
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113483682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2113483682
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3971623682
Short name T1
Test name
Test status
Simulation time 84543066821 ps
CPU time 1037.19 seconds
Started Aug 03 04:42:48 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 199980 kb
Host smart-6824063a-aaeb-43c7-9afa-f7db80997e76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971623682 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3971623682
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.187373804
Short name T26
Test name
Test status
Simulation time 6049915231 ps
CPU time 94.08 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:43:51 PM PDT 24
Peak memory 199888 kb
Host smart-acde0bd4-8219-40a9-9e7c-b383c894b5c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187373804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.187373804
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4102303365
Short name T111
Test name
Test status
Simulation time 1631244293 ps
CPU time 16.35 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 200144 kb
Host smart-f1f68a58-76c5-4327-9f55-73069686248e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102303365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4102303365
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/39.hmac_stress_all.224503422
Short name T147
Test name
Test status
Simulation time 8738778336 ps
CPU time 463.03 seconds
Started Aug 03 04:42:48 PM PDT 24
Finished Aug 03 04:50:32 PM PDT 24
Peak memory 200016 kb
Host smart-36748ee0-7b56-4dcc-8242-18889d78f9c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224503422 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.224503422
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2844719345
Short name T53
Test name
Test status
Simulation time 13230081 ps
CPU time 0.58 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:42:09 PM PDT 24
Peak memory 195908 kb
Host smart-7fb7bfd8-6417-4cbd-ab99-d60aa40ffb98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844719345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2844719345
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3658958378
Short name T21
Test name
Test status
Simulation time 637373827 ps
CPU time 35.74 seconds
Started Aug 03 04:42:00 PM PDT 24
Finished Aug 03 04:42:36 PM PDT 24
Peak memory 199860 kb
Host smart-a0e5f1b8-af26-44f3-b6ab-9d8a381c0304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658958378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3658958378
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.4049555130
Short name T634
Test name
Test status
Simulation time 80855010 ps
CPU time 1.89 seconds
Started Aug 03 04:35:36 PM PDT 24
Finished Aug 03 04:35:38 PM PDT 24
Peak memory 200072 kb
Host smart-7f1c5cc1-3da9-4483-9774-fe7203c70c83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049555130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.4049555130
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.988854265
Short name T65
Test name
Test status
Simulation time 260958987 ps
CPU time 4.12 seconds
Started Aug 03 04:35:18 PM PDT 24
Finished Aug 03 04:35:22 PM PDT 24
Peak memory 200108 kb
Host smart-0050b950-173e-4ab5-ab63-182ba503e0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988854265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.988854265
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2283838125
Short name T125
Test name
Test status
Simulation time 108768448 ps
CPU time 1.1 seconds
Started Aug 03 04:35:18 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 199964 kb
Host smart-0831566d-e473-4494-a97b-c90dd63fff04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283838125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2283838125
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3415279951
Short name T136
Test name
Test status
Simulation time 194373472 ps
CPU time 3.21 seconds
Started Aug 03 04:35:23 PM PDT 24
Finished Aug 03 04:35:27 PM PDT 24
Peak memory 200088 kb
Host smart-61e61cf8-6200-42e7-84a1-de662762bc97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415279951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3415279951
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1757570380
Short name T204
Test name
Test status
Simulation time 1868358777 ps
CPU time 72.8 seconds
Started Aug 03 04:41:50 PM PDT 24
Finished Aug 03 04:43:03 PM PDT 24
Peak memory 199884 kb
Host smart-7a85102d-1d2a-407b-b2e1-98cc389414d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757570380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1757570380
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3743511924
Short name T45
Test name
Test status
Simulation time 972850913 ps
CPU time 49.92 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:43:05 PM PDT 24
Peak memory 199828 kb
Host smart-bd1f4276-f0b5-4356-9558-3281e2551805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743511924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3743511924
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2809659570
Short name T600
Test name
Test status
Simulation time 59932281 ps
CPU time 2.74 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 199704 kb
Host smart-3e896ca7-a8b0-4991-a9c0-ec8a280aa596
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809659570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2809659570
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1228822783
Short name T530
Test name
Test status
Simulation time 286668059 ps
CPU time 0.89 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 199132 kb
Host smart-37707f2a-2c89-43ab-874a-e4319e1936da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228822783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1228822783
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3779409367
Short name T622
Test name
Test status
Simulation time 279183842137 ps
CPU time 1001.31 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:51:56 PM PDT 24
Peak memory 216520 kb
Host smart-ec4e612d-121a-430b-a55f-c6385bb1e836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779409367 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3779409367
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4040626604
Short name T586
Test name
Test status
Simulation time 16910808 ps
CPU time 0.92 seconds
Started Aug 03 04:35:06 PM PDT 24
Finished Aug 03 04:35:07 PM PDT 24
Peak memory 199904 kb
Host smart-2124d2a9-e0ea-4f21-8dc3-8c8862740fab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040626604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4040626604
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2360164752
Short name T583
Test name
Test status
Simulation time 31461133 ps
CPU time 0.58 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 194972 kb
Host smart-d55eef53-67ff-4cdc-8c6e-47cdb49122ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360164752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2360164752
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1244094936
Short name T608
Test name
Test status
Simulation time 659653082 ps
CPU time 2.22 seconds
Started Aug 03 04:35:13 PM PDT 24
Finished Aug 03 04:35:15 PM PDT 24
Peak memory 199992 kb
Host smart-cda8c7b5-5ea0-4baa-a1c6-16749e2aadb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244094936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1244094936
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3634299095
Short name T591
Test name
Test status
Simulation time 46051525 ps
CPU time 2.28 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:12 PM PDT 24
Peak memory 200076 kb
Host smart-aa375bf1-36a3-496a-b9fc-08019c33a613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634299095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3634299095
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1532422518
Short name T652
Test name
Test status
Simulation time 601280895 ps
CPU time 2.91 seconds
Started Aug 03 04:35:12 PM PDT 24
Finished Aug 03 04:35:15 PM PDT 24
Peak memory 199944 kb
Host smart-fe0a7127-b784-444f-8af1-af84ac41b918
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532422518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1532422518
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1728799430
Short name T112
Test name
Test status
Simulation time 209741652 ps
CPU time 5.69 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 199968 kb
Host smart-32eef752-4a80-4c60-9ce4-8cc24ad680af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728799430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1728799430
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2548180684
Short name T625
Test name
Test status
Simulation time 229797505 ps
CPU time 5.11 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 199944 kb
Host smart-20be8ea1-4c93-45ad-9291-9fee6cdfb1a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548180684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2548180684
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1777239141
Short name T609
Test name
Test status
Simulation time 41462511 ps
CPU time 0.75 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:35:15 PM PDT 24
Peak memory 197960 kb
Host smart-d96e4c23-eb9f-44b7-9917-793d6fb91a00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777239141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1777239141
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1916063640
Short name T559
Test name
Test status
Simulation time 443083158 ps
CPU time 2.31 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 200096 kb
Host smart-9213a185-0002-4423-8d0d-cee9059b00a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916063640 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1916063640
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1587107858
Short name T657
Test name
Test status
Simulation time 29136910 ps
CPU time 0.74 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 198132 kb
Host smart-9caf5ba3-bef7-4b87-82a9-3078ef426cec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587107858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1587107858
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2766065334
Short name T642
Test name
Test status
Simulation time 57700142 ps
CPU time 0.58 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 195112 kb
Host smart-63552d66-fda8-469b-b3a7-f825556e6ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766065334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2766065334
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2536186454
Short name T648
Test name
Test status
Simulation time 173740271 ps
CPU time 1.19 seconds
Started Aug 03 04:35:10 PM PDT 24
Finished Aug 03 04:35:11 PM PDT 24
Peak memory 198472 kb
Host smart-fe84771b-2e6b-45d8-95e7-41a602fa03de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536186454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2536186454
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1466945178
Short name T582
Test name
Test status
Simulation time 220254218 ps
CPU time 4.02 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 200116 kb
Host smart-100271e5-66e0-4eb2-926d-9ab50ce5da40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466945178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1466945178
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3556831485
Short name T137
Test name
Test status
Simulation time 543886585 ps
CPU time 4.53 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:14 PM PDT 24
Peak memory 200000 kb
Host smart-7ab443f3-4f9f-47c5-83bf-331b31cecdfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556831485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3556831485
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.984309516
Short name T644
Test name
Test status
Simulation time 66950929238 ps
CPU time 892.16 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:50:13 PM PDT 24
Peak memory 216484 kb
Host smart-a86a3202-4931-4e24-b96b-a6fa93c94a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984309516 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.984309516
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3771683904
Short name T117
Test name
Test status
Simulation time 35511878 ps
CPU time 0.94 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 199828 kb
Host smart-e3c6d1a5-2187-416c-846a-ba2b8f53083f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771683904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3771683904
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1692407442
Short name T553
Test name
Test status
Simulation time 29728464 ps
CPU time 0.58 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 194960 kb
Host smart-637936d4-e87f-4a4d-b3ff-c9b7eec9c30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692407442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1692407442
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4283660769
Short name T635
Test name
Test status
Simulation time 717691489 ps
CPU time 2.71 seconds
Started Aug 03 04:35:18 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 200000 kb
Host smart-09254d6c-566d-4c64-9964-e3caddb8fe83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283660769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.4283660769
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.21394183
Short name T626
Test name
Test status
Simulation time 149100151 ps
CPU time 1.74 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:22 PM PDT 24
Peak memory 200132 kb
Host smart-9b4ebcf1-52e1-4f56-9ce3-816ef937dad5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21394183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.21394183
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3660201279
Short name T534
Test name
Test status
Simulation time 122769173 ps
CPU time 1.87 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 199980 kb
Host smart-e7978946-d723-434c-ba1b-4324586c769a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660201279 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3660201279
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3468457466
Short name T623
Test name
Test status
Simulation time 115859506 ps
CPU time 0.91 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 199496 kb
Host smart-531d52c3-e22c-490f-95fb-76b3533f6fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468457466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3468457466
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.833618683
Short name T616
Test name
Test status
Simulation time 48846649 ps
CPU time 0.55 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:16 PM PDT 24
Peak memory 194952 kb
Host smart-e37b819d-027d-4597-8f42-3fdcdf968caa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833618683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.833618683
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1074722585
Short name T568
Test name
Test status
Simulation time 563093101 ps
CPU time 2.37 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:22 PM PDT 24
Peak memory 200004 kb
Host smart-980950a0-43f6-47b5-9604-34d952b1b7c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074722585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1074722585
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3102822938
Short name T603
Test name
Test status
Simulation time 26157999 ps
CPU time 1.26 seconds
Started Aug 03 04:35:17 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 200028 kb
Host smart-8b988f90-17fc-4414-8baf-d87546c7de1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102822938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3102822938
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.448025535
Short name T618
Test name
Test status
Simulation time 244705504 ps
CPU time 1.82 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:22 PM PDT 24
Peak memory 200192 kb
Host smart-92dc63fb-ea1e-4748-8aff-889cf0026403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448025535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.448025535
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3444998981
Short name T550
Test name
Test status
Simulation time 171828024 ps
CPU time 2.82 seconds
Started Aug 03 04:35:24 PM PDT 24
Finished Aug 03 04:35:28 PM PDT 24
Peak memory 215596 kb
Host smart-98ef6339-42d9-4bb6-8cb7-59713b586da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444998981 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3444998981
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.846750192
Short name T576
Test name
Test status
Simulation time 38664772 ps
CPU time 0.68 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 197992 kb
Host smart-3fbb4d34-1ae3-4be0-b325-8fc99555c077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846750192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.846750192
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1472534202
Short name T567
Test name
Test status
Simulation time 17188429 ps
CPU time 0.64 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 195024 kb
Host smart-53ecc2c9-e6f1-4262-8b50-42c4bff7e619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472534202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1472534202
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2152469818
Short name T590
Test name
Test status
Simulation time 181436772 ps
CPU time 1.05 seconds
Started Aug 03 04:35:17 PM PDT 24
Finished Aug 03 04:35:18 PM PDT 24
Peak memory 200088 kb
Host smart-09e2eaa8-b04a-445b-9116-ab828fe56a80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152469818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2152469818
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3275994031
Short name T547
Test name
Test status
Simulation time 227077738 ps
CPU time 3.73 seconds
Started Aug 03 04:35:22 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 200000 kb
Host smart-180e7b96-ddff-42a4-ac0e-d2bf70e44bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275994031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3275994031
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.686152297
Short name T650
Test name
Test status
Simulation time 95636918 ps
CPU time 2.73 seconds
Started Aug 03 04:35:18 PM PDT 24
Finished Aug 03 04:35:22 PM PDT 24
Peak memory 200152 kb
Host smart-6fa292de-11b4-40c8-8cad-c16553ad31b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686152297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.686152297
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.707683049
Short name T548
Test name
Test status
Simulation time 62490906 ps
CPU time 1.6 seconds
Started Aug 03 04:35:30 PM PDT 24
Finished Aug 03 04:35:35 PM PDT 24
Peak memory 200212 kb
Host smart-2a7be42a-4560-4394-af8f-c5b0b60014fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707683049 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.707683049
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.126407889
Short name T555
Test name
Test status
Simulation time 26202274 ps
CPU time 0.8 seconds
Started Aug 03 04:35:23 PM PDT 24
Finished Aug 03 04:35:24 PM PDT 24
Peak memory 199812 kb
Host smart-00b2d0e1-0f84-4126-a6a8-be8278457c10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126407889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.126407889
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.694671900
Short name T631
Test name
Test status
Simulation time 48552231 ps
CPU time 0.62 seconds
Started Aug 03 04:35:24 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 195008 kb
Host smart-b654c7b6-2b34-4a85-85f5-201807717547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694671900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.694671900
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.145147702
Short name T566
Test name
Test status
Simulation time 94065858 ps
CPU time 1.65 seconds
Started Aug 03 04:35:30 PM PDT 24
Finished Aug 03 04:35:32 PM PDT 24
Peak memory 200228 kb
Host smart-3646c3a2-2f5a-4415-a5a6-e812dfc15120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145147702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.145147702
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3206726648
Short name T554
Test name
Test status
Simulation time 151652661 ps
CPU time 2.17 seconds
Started Aug 03 04:35:27 PM PDT 24
Finished Aug 03 04:35:29 PM PDT 24
Peak memory 200060 kb
Host smart-e8f442e3-323e-479a-81f9-2456dd6ba8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206726648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3206726648
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1473803650
Short name T141
Test name
Test status
Simulation time 366267207 ps
CPU time 3.09 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:35:23 PM PDT 24
Peak memory 200176 kb
Host smart-f8dd1d81-4604-483e-9a3e-3d4fe3fa7a22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473803650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1473803650
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2311557721
Short name T604
Test name
Test status
Simulation time 115781021036 ps
CPU time 586.9 seconds
Started Aug 03 04:35:23 PM PDT 24
Finished Aug 03 04:45:10 PM PDT 24
Peak memory 216588 kb
Host smart-8a064ae5-96cb-4824-bda4-a1beb13c6f8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311557721 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2311557721
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2321718264
Short name T624
Test name
Test status
Simulation time 30799646 ps
CPU time 0.8 seconds
Started Aug 03 04:35:30 PM PDT 24
Finished Aug 03 04:35:31 PM PDT 24
Peak memory 199404 kb
Host smart-21c0a11a-4341-4c1d-81c8-6e558872f439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321718264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2321718264
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.37273062
Short name T538
Test name
Test status
Simulation time 21556778 ps
CPU time 0.61 seconds
Started Aug 03 04:35:27 PM PDT 24
Finished Aug 03 04:35:28 PM PDT 24
Peak memory 194992 kb
Host smart-f00d4e27-711f-4b35-9556-9c5b004ff126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37273062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.37273062
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1544041537
Short name T581
Test name
Test status
Simulation time 109869899 ps
CPU time 2.29 seconds
Started Aug 03 04:35:24 PM PDT 24
Finished Aug 03 04:35:26 PM PDT 24
Peak memory 200164 kb
Host smart-e8ea7da0-1f38-4ffe-b6ef-0036e43d6193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544041537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1544041537
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.197448712
Short name T70
Test name
Test status
Simulation time 809451189 ps
CPU time 4.01 seconds
Started Aug 03 04:35:23 PM PDT 24
Finished Aug 03 04:35:27 PM PDT 24
Peak memory 200132 kb
Host smart-142c7bb8-d8ae-429c-9e76-d36a48fa64b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197448712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.197448712
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4049428560
Short name T551
Test name
Test status
Simulation time 163612199231 ps
CPU time 372.54 seconds
Started Aug 03 04:35:23 PM PDT 24
Finished Aug 03 04:41:35 PM PDT 24
Peak memory 216612 kb
Host smart-3a083c7d-7cf8-4f38-a454-1a821e037f8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049428560 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.4049428560
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.182544899
Short name T109
Test name
Test status
Simulation time 16098600 ps
CPU time 0.68 seconds
Started Aug 03 04:35:30 PM PDT 24
Finished Aug 03 04:35:34 PM PDT 24
Peak memory 198152 kb
Host smart-8cf96cb7-5e3a-482d-a67b-3112860446be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182544899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.182544899
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2610833232
Short name T605
Test name
Test status
Simulation time 15750252 ps
CPU time 0.58 seconds
Started Aug 03 04:35:31 PM PDT 24
Finished Aug 03 04:35:32 PM PDT 24
Peak memory 195060 kb
Host smart-ed4d7deb-e8df-489d-88ce-05066d5b234c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610833232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2610833232
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1810252749
Short name T131
Test name
Test status
Simulation time 112718844 ps
CPU time 1.07 seconds
Started Aug 03 04:35:23 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 198648 kb
Host smart-a013c3b1-d596-42bf-8803-1b8e64702f5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810252749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1810252749
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1694651695
Short name T579
Test name
Test status
Simulation time 375272412 ps
CPU time 3.24 seconds
Started Aug 03 04:35:23 PM PDT 24
Finished Aug 03 04:35:26 PM PDT 24
Peak memory 200020 kb
Host smart-c6b59efc-8b98-49bb-af66-6942f50fcf5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694651695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1694651695
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1373580123
Short name T134
Test name
Test status
Simulation time 302882913 ps
CPU time 2.96 seconds
Started Aug 03 04:35:22 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 200008 kb
Host smart-8e6c8224-16f0-4cef-a163-e0ef1b527100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373580123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1373580123
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4059858897
Short name T592
Test name
Test status
Simulation time 358255672 ps
CPU time 2.59 seconds
Started Aug 03 04:35:38 PM PDT 24
Finished Aug 03 04:35:40 PM PDT 24
Peak memory 200132 kb
Host smart-6e3ce8f0-b85b-4e40-b586-45283cda61a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059858897 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4059858897
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1141214033
Short name T121
Test name
Test status
Simulation time 31089906 ps
CPU time 0.96 seconds
Started Aug 03 04:35:28 PM PDT 24
Finished Aug 03 04:35:29 PM PDT 24
Peak memory 199620 kb
Host smart-89168a25-efef-4fa4-a014-1844de053ba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141214033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1141214033
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1492996824
Short name T560
Test name
Test status
Simulation time 35812788 ps
CPU time 0.57 seconds
Started Aug 03 04:35:25 PM PDT 24
Finished Aug 03 04:35:26 PM PDT 24
Peak memory 194992 kb
Host smart-fbd03131-4b8d-430a-9110-c4246d9b4d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492996824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1492996824
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1312326880
Short name T628
Test name
Test status
Simulation time 768773266 ps
CPU time 1.28 seconds
Started Aug 03 04:35:24 PM PDT 24
Finished Aug 03 04:35:26 PM PDT 24
Peak memory 199552 kb
Host smart-5ddcb8e1-38b9-4a0d-826d-b0f79bbabc16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312326880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1312326880
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3189291921
Short name T617
Test name
Test status
Simulation time 164069331 ps
CPU time 2.41 seconds
Started Aug 03 04:35:23 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 200108 kb
Host smart-211cd0ad-845b-469b-95bb-4c26161f190e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189291921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3189291921
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.592614214
Short name T570
Test name
Test status
Simulation time 19009767 ps
CPU time 1.15 seconds
Started Aug 03 04:35:31 PM PDT 24
Finished Aug 03 04:35:32 PM PDT 24
Peak memory 199888 kb
Host smart-128a206d-0085-488b-81ba-3975bb64254c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592614214 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.592614214
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2984839048
Short name T613
Test name
Test status
Simulation time 74515073 ps
CPU time 0.69 seconds
Started Aug 03 04:35:26 PM PDT 24
Finished Aug 03 04:35:27 PM PDT 24
Peak memory 198124 kb
Host smart-db275b0b-7d38-4975-8a09-1d988c060363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984839048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2984839048
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3710670080
Short name T637
Test name
Test status
Simulation time 29832417 ps
CPU time 0.62 seconds
Started Aug 03 04:35:23 PM PDT 24
Finished Aug 03 04:35:24 PM PDT 24
Peak memory 194980 kb
Host smart-4a15321f-d579-4aec-85c7-a6a87d609366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710670080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3710670080
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2232392910
Short name T124
Test name
Test status
Simulation time 62106229 ps
CPU time 1.63 seconds
Started Aug 03 04:35:24 PM PDT 24
Finished Aug 03 04:35:26 PM PDT 24
Peak memory 200056 kb
Host smart-aa8363af-9d37-45a4-8fde-f230cf5b9efb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232392910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2232392910
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1888621295
Short name T658
Test name
Test status
Simulation time 375906386 ps
CPU time 1.91 seconds
Started Aug 03 04:35:30 PM PDT 24
Finished Aug 03 04:35:32 PM PDT 24
Peak memory 200036 kb
Host smart-6f8cc531-8157-47c8-9e0e-e8f7dcddca45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888621295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1888621295
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3318579913
Short name T139
Test name
Test status
Simulation time 89388718 ps
CPU time 2.91 seconds
Started Aug 03 04:35:30 PM PDT 24
Finished Aug 03 04:35:33 PM PDT 24
Peak memory 200000 kb
Host smart-d0ecb3c5-382a-4ed8-a47d-386ba6c13b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318579913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3318579913
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2371010415
Short name T589
Test name
Test status
Simulation time 250743367 ps
CPU time 1.89 seconds
Started Aug 03 04:35:22 PM PDT 24
Finished Aug 03 04:35:24 PM PDT 24
Peak memory 200076 kb
Host smart-1bb88fb3-af21-4ace-9647-de4c474bb2c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371010415 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2371010415
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3227434734
Short name T641
Test name
Test status
Simulation time 175312676 ps
CPU time 0.67 seconds
Started Aug 03 04:35:22 PM PDT 24
Finished Aug 03 04:35:23 PM PDT 24
Peak memory 198124 kb
Host smart-e6aef3ec-becc-4e99-81c3-7e222f025689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227434734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3227434734
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3235769745
Short name T540
Test name
Test status
Simulation time 14741010 ps
CPU time 0.6 seconds
Started Aug 03 04:35:29 PM PDT 24
Finished Aug 03 04:35:29 PM PDT 24
Peak memory 194920 kb
Host smart-83e5fb8f-1528-44df-a0a2-85dc124ad898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235769745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3235769745
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.548306051
Short name T130
Test name
Test status
Simulation time 155679960 ps
CPU time 2.17 seconds
Started Aug 03 04:35:24 PM PDT 24
Finished Aug 03 04:35:26 PM PDT 24
Peak memory 200040 kb
Host smart-cfa11dcd-2c26-4abf-8b07-456461f9d5aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548306051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.548306051
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1321645128
Short name T536
Test name
Test status
Simulation time 279742171 ps
CPU time 3.27 seconds
Started Aug 03 04:35:25 PM PDT 24
Finished Aug 03 04:35:28 PM PDT 24
Peak memory 200116 kb
Host smart-f73eaa84-bf39-4660-9e13-63515ab38448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321645128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1321645128
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2377374311
Short name T138
Test name
Test status
Simulation time 506067476 ps
CPU time 2.83 seconds
Started Aug 03 04:35:24 PM PDT 24
Finished Aug 03 04:35:28 PM PDT 24
Peak memory 200016 kb
Host smart-9264044e-1253-40e4-b449-3c158ec69af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377374311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2377374311
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.796981346
Short name T632
Test name
Test status
Simulation time 76607154611 ps
CPU time 807.13 seconds
Started Aug 03 04:35:47 PM PDT 24
Finished Aug 03 04:49:14 PM PDT 24
Peak memory 224644 kb
Host smart-51b2abca-6cff-42c3-8869-d68a42f06adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796981346 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.796981346
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1344094748
Short name T633
Test name
Test status
Simulation time 94105308 ps
CPU time 0.84 seconds
Started Aug 03 04:35:30 PM PDT 24
Finished Aug 03 04:35:34 PM PDT 24
Peak memory 199920 kb
Host smart-b23f1589-f64a-49cd-bbed-b8f77c712ab3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344094748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1344094748
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1644373630
Short name T580
Test name
Test status
Simulation time 13432285 ps
CPU time 0.63 seconds
Started Aug 03 04:35:31 PM PDT 24
Finished Aug 03 04:35:31 PM PDT 24
Peak memory 194956 kb
Host smart-02082d33-7b6e-4970-8fc5-cce7ff669331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644373630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1644373630
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3834940442
Short name T565
Test name
Test status
Simulation time 115148961 ps
CPU time 1.83 seconds
Started Aug 03 04:35:44 PM PDT 24
Finished Aug 03 04:35:46 PM PDT 24
Peak memory 200132 kb
Host smart-b3aec641-6141-4e1c-bfa2-f5bd51858127
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834940442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3834940442
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.4262050615
Short name T544
Test name
Test status
Simulation time 226361523 ps
CPU time 1.34 seconds
Started Aug 03 04:35:27 PM PDT 24
Finished Aug 03 04:35:28 PM PDT 24
Peak memory 200128 kb
Host smart-f5155ca9-d79f-43bc-b245-3200986f9851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262050615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.4262050615
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4194245222
Short name T614
Test name
Test status
Simulation time 99559439 ps
CPU time 1.76 seconds
Started Aug 03 04:35:22 PM PDT 24
Finished Aug 03 04:35:24 PM PDT 24
Peak memory 200140 kb
Host smart-42d7cb0e-e6a6-46d4-bee8-3697fad1f63e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194245222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4194245222
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2425126374
Short name T110
Test name
Test status
Simulation time 613672278 ps
CPU time 7.67 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 200060 kb
Host smart-e9bd54c6-e29f-4bb7-8dff-5ccc5ac50074
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425126374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2425126374
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2118921071
Short name T116
Test name
Test status
Simulation time 1730247337 ps
CPU time 16.95 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:26 PM PDT 24
Peak memory 200072 kb
Host smart-222ced1c-a59c-4c9b-9071-0ad45c3673e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118921071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2118921071
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.685179741
Short name T539
Test name
Test status
Simulation time 53820275 ps
CPU time 0.83 seconds
Started Aug 03 04:35:11 PM PDT 24
Finished Aug 03 04:35:11 PM PDT 24
Peak memory 199192 kb
Host smart-39e95a59-48c6-4c4a-a676-2cc5c8112794
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685179741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.685179741
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2238710733
Short name T597
Test name
Test status
Simulation time 82478425 ps
CPU time 2.3 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:11 PM PDT 24
Peak memory 200184 kb
Host smart-028d0bbc-73c0-4903-8fb2-1612a6590573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238710733 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2238710733
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3252140984
Short name T564
Test name
Test status
Simulation time 71509835 ps
CPU time 0.83 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 199692 kb
Host smart-6de55ed2-295b-4a89-b798-50df8e8e374e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252140984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3252140984
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1960242021
Short name T630
Test name
Test status
Simulation time 23994412 ps
CPU time 0.64 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:09 PM PDT 24
Peak memory 194980 kb
Host smart-ccb57d64-0e26-4293-b281-aec4d6ad2b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960242021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1960242021
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.982065253
Short name T588
Test name
Test status
Simulation time 74006598 ps
CPU time 1.09 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:35:15 PM PDT 24
Peak memory 200004 kb
Host smart-ba71713f-6bb2-4064-beff-060a3090b29a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982065253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.982065253
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.687266813
Short name T584
Test name
Test status
Simulation time 58473185 ps
CPU time 2.99 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:12 PM PDT 24
Peak memory 200176 kb
Host smart-a2d34cc5-39dd-4120-9be4-7fe3c492bc55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687266813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.687266813
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4038240675
Short name T64
Test name
Test status
Simulation time 151097162 ps
CPU time 3.04 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:11 PM PDT 24
Peak memory 200080 kb
Host smart-53b6e222-1db1-4fff-bdaf-77a8b5f71666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038240675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.4038240675
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3322753104
Short name T654
Test name
Test status
Simulation time 14142656 ps
CPU time 0.6 seconds
Started Aug 03 04:35:42 PM PDT 24
Finished Aug 03 04:35:43 PM PDT 24
Peak memory 195020 kb
Host smart-9177ca0a-1495-4949-be80-fc34a8ce6b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322753104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3322753104
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1636422537
Short name T596
Test name
Test status
Simulation time 53982073 ps
CPU time 0.63 seconds
Started Aug 03 04:35:34 PM PDT 24
Finished Aug 03 04:35:35 PM PDT 24
Peak memory 195040 kb
Host smart-083a2159-f6a5-450d-a0fe-305813536390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636422537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1636422537
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1093071174
Short name T601
Test name
Test status
Simulation time 12639684 ps
CPU time 0.62 seconds
Started Aug 03 04:35:44 PM PDT 24
Finished Aug 03 04:35:44 PM PDT 24
Peak memory 194972 kb
Host smart-77a051ad-cea9-49e5-a98a-5b15e96feac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093071174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1093071174
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1311754193
Short name T561
Test name
Test status
Simulation time 65955009 ps
CPU time 0.58 seconds
Started Aug 03 04:35:43 PM PDT 24
Finished Aug 03 04:35:43 PM PDT 24
Peak memory 194956 kb
Host smart-e7fd3a07-dad5-4344-a20f-c483dbcfe24d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311754193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1311754193
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3972995945
Short name T563
Test name
Test status
Simulation time 14116819 ps
CPU time 0.63 seconds
Started Aug 03 04:35:40 PM PDT 24
Finished Aug 03 04:35:40 PM PDT 24
Peak memory 195020 kb
Host smart-fb43aa34-3382-4be1-ac6a-c2ee27943db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972995945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3972995945
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2867194987
Short name T595
Test name
Test status
Simulation time 49778237 ps
CPU time 0.62 seconds
Started Aug 03 04:35:35 PM PDT 24
Finished Aug 03 04:35:36 PM PDT 24
Peak memory 195024 kb
Host smart-09bf5b3f-2377-4036-9968-0fa81a971ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867194987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2867194987
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3401309104
Short name T599
Test name
Test status
Simulation time 12145237 ps
CPU time 0.62 seconds
Started Aug 03 04:35:46 PM PDT 24
Finished Aug 03 04:35:47 PM PDT 24
Peak memory 195032 kb
Host smart-8c94aacb-2614-4522-9a6b-fab6fd6f9e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401309104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3401309104
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2192120661
Short name T649
Test name
Test status
Simulation time 37414424 ps
CPU time 0.64 seconds
Started Aug 03 04:35:33 PM PDT 24
Finished Aug 03 04:35:34 PM PDT 24
Peak memory 195068 kb
Host smart-ebc9968b-bcf0-453c-8ed4-8e1efda7f174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192120661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2192120661
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1895239978
Short name T602
Test name
Test status
Simulation time 29327584 ps
CPU time 0.58 seconds
Started Aug 03 04:35:45 PM PDT 24
Finished Aug 03 04:35:46 PM PDT 24
Peak memory 194984 kb
Host smart-c1645b9b-a88b-4d51-b2b3-3276a1e8471b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895239978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1895239978
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3240903603
Short name T575
Test name
Test status
Simulation time 137282194 ps
CPU time 0.61 seconds
Started Aug 03 04:35:37 PM PDT 24
Finished Aug 03 04:35:38 PM PDT 24
Peak memory 194876 kb
Host smart-b6ceb24e-c18a-43d6-aee8-44d95a62fb1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240903603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3240903603
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1367820006
Short name T118
Test name
Test status
Simulation time 983907835 ps
CPU time 3.4 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 200080 kb
Host smart-55f67782-8b20-49bc-80bf-f24cf7e9c4d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367820006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1367820006
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1770758658
Short name T537
Test name
Test status
Simulation time 734790714 ps
CPU time 10.4 seconds
Started Aug 03 04:35:17 PM PDT 24
Finished Aug 03 04:35:27 PM PDT 24
Peak memory 200040 kb
Host smart-2465e9b2-65fb-420d-a7a8-600bf99cf856
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770758658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1770758658
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.60952544
Short name T119
Test name
Test status
Simulation time 49144700 ps
CPU time 0.84 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:35:15 PM PDT 24
Peak memory 199176 kb
Host smart-680d26ad-d0c6-4539-bbb7-10e266ce8bd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60952544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.60952544
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2833254721
Short name T645
Test name
Test status
Simulation time 33760748 ps
CPU time 2.11 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:18 PM PDT 24
Peak memory 200124 kb
Host smart-f654c5d8-4610-40ff-a648-f55eeaa44df3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833254721 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2833254721
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2173841673
Short name T115
Test name
Test status
Simulation time 77426423 ps
CPU time 0.91 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 199924 kb
Host smart-5d4c0e1e-bd13-498c-b264-82b36568ba27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173841673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2173841673
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.266297777
Short name T571
Test name
Test status
Simulation time 17133724 ps
CPU time 0.61 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 195004 kb
Host smart-b5e9fbb7-b219-4fd5-918b-156e2a011101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266297777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.266297777
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2597339342
Short name T127
Test name
Test status
Simulation time 400886479 ps
CPU time 1.09 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 198692 kb
Host smart-0d6ed163-4557-4d95-9950-bc3d6158d735
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597339342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2597339342
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2087326825
Short name T611
Test name
Test status
Simulation time 74213382 ps
CPU time 3.73 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:12 PM PDT 24
Peak memory 200152 kb
Host smart-d0b769e2-7436-4cfc-ac59-2fd0125241b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087326825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2087326825
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2369184878
Short name T627
Test name
Test status
Simulation time 121052540 ps
CPU time 3.95 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 200148 kb
Host smart-c4fa2274-5df5-4e94-86d3-3aa9de30eb4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369184878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2369184878
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.999224170
Short name T621
Test name
Test status
Simulation time 16895453 ps
CPU time 0.69 seconds
Started Aug 03 04:35:39 PM PDT 24
Finished Aug 03 04:35:39 PM PDT 24
Peak memory 194956 kb
Host smart-e30f02cd-a599-47b3-8831-3aa65c04f6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999224170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.999224170
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1452719679
Short name T607
Test name
Test status
Simulation time 49590290 ps
CPU time 0.6 seconds
Started Aug 03 04:35:44 PM PDT 24
Finished Aug 03 04:35:45 PM PDT 24
Peak memory 195060 kb
Host smart-8cac20a3-8b34-4268-bd52-ae1771e68ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452719679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1452719679
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.326322000
Short name T606
Test name
Test status
Simulation time 16085804 ps
CPU time 0.65 seconds
Started Aug 03 04:35:48 PM PDT 24
Finished Aug 03 04:35:49 PM PDT 24
Peak memory 195104 kb
Host smart-39812391-1c96-4805-aba7-a27d5a6b5844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326322000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.326322000
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.65157438
Short name T610
Test name
Test status
Simulation time 15111921 ps
CPU time 0.6 seconds
Started Aug 03 04:35:44 PM PDT 24
Finished Aug 03 04:35:45 PM PDT 24
Peak memory 195048 kb
Host smart-0a053ddd-5af3-4985-a547-0ca315557bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65157438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.65157438
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.769356939
Short name T612
Test name
Test status
Simulation time 23830733 ps
CPU time 0.61 seconds
Started Aug 03 04:35:44 PM PDT 24
Finished Aug 03 04:35:45 PM PDT 24
Peak memory 195160 kb
Host smart-e1bdec85-11a5-4c09-8d59-408fb2faea5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769356939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.769356939
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2725818545
Short name T640
Test name
Test status
Simulation time 14058309 ps
CPU time 0.65 seconds
Started Aug 03 04:35:43 PM PDT 24
Finished Aug 03 04:35:44 PM PDT 24
Peak memory 195064 kb
Host smart-b5ed5c88-1975-44c2-9d47-cc5dec421b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725818545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2725818545
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2164548306
Short name T573
Test name
Test status
Simulation time 12187577 ps
CPU time 0.62 seconds
Started Aug 03 04:35:40 PM PDT 24
Finished Aug 03 04:35:41 PM PDT 24
Peak memory 195120 kb
Host smart-d0691890-cead-4dbe-8892-a5f2fccb7c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164548306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2164548306
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.4276085967
Short name T562
Test name
Test status
Simulation time 11519953 ps
CPU time 0.6 seconds
Started Aug 03 04:35:43 PM PDT 24
Finished Aug 03 04:35:44 PM PDT 24
Peak memory 194900 kb
Host smart-549930c4-8fe5-472d-aea2-e5f45ee35df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276085967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.4276085967
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1504891074
Short name T569
Test name
Test status
Simulation time 97619557 ps
CPU time 0.6 seconds
Started Aug 03 04:35:50 PM PDT 24
Finished Aug 03 04:35:50 PM PDT 24
Peak memory 194912 kb
Host smart-1d1fd689-0f2a-4f6c-a2f1-27e78db08111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504891074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1504891074
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2119398229
Short name T549
Test name
Test status
Simulation time 14804916 ps
CPU time 0.61 seconds
Started Aug 03 04:35:38 PM PDT 24
Finished Aug 03 04:35:39 PM PDT 24
Peak memory 194924 kb
Host smart-1e843e72-37c5-42ac-a213-2a4ef9fc7ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119398229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2119398229
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3224016089
Short name T114
Test name
Test status
Simulation time 1147213303 ps
CPU time 8.94 seconds
Started Aug 03 04:35:14 PM PDT 24
Finished Aug 03 04:35:23 PM PDT 24
Peak memory 199968 kb
Host smart-16b0877f-ce61-462c-a642-dc2e5b0b52e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224016089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3224016089
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3135674814
Short name T643
Test name
Test status
Simulation time 209628704 ps
CPU time 9.4 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:26 PM PDT 24
Peak memory 200088 kb
Host smart-a662b986-322a-4cf0-9fa6-765c459618a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135674814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3135674814
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3865294776
Short name T587
Test name
Test status
Simulation time 17109451 ps
CPU time 0.76 seconds
Started Aug 03 04:35:11 PM PDT 24
Finished Aug 03 04:35:15 PM PDT 24
Peak memory 198272 kb
Host smart-f83b4cdf-99e1-4e14-b26c-0d3d2db8e74b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865294776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3865294776
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3417879526
Short name T615
Test name
Test status
Simulation time 61211369258 ps
CPU time 603.06 seconds
Started Aug 03 04:35:21 PM PDT 24
Finished Aug 03 04:45:24 PM PDT 24
Peak memory 215972 kb
Host smart-b18636f4-92a4-4a3c-ac36-bea77cc6e46c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417879526 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3417879526
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1715672865
Short name T122
Test name
Test status
Simulation time 97127817 ps
CPU time 0.85 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 199296 kb
Host smart-9c2169eb-3eeb-419e-9660-e2c5055b0142
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715672865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1715672865
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2637949434
Short name T598
Test name
Test status
Simulation time 30670868 ps
CPU time 0.62 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 195092 kb
Host smart-55a50a7a-619c-4b49-b004-c53f8241b97d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637949434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2637949434
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1404030668
Short name T123
Test name
Test status
Simulation time 262182975 ps
CPU time 2.27 seconds
Started Aug 03 04:35:09 PM PDT 24
Finished Aug 03 04:35:11 PM PDT 24
Peak memory 200096 kb
Host smart-dfc08792-3421-4a29-9804-3e8d2d10e707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404030668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1404030668
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3628981297
Short name T585
Test name
Test status
Simulation time 215829244 ps
CPU time 3.73 seconds
Started Aug 03 04:35:08 PM PDT 24
Finished Aug 03 04:35:12 PM PDT 24
Peak memory 200104 kb
Host smart-57e6c82d-21a2-41e5-99ec-f12a1c2d928a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628981297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3628981297
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4180119535
Short name T638
Test name
Test status
Simulation time 816947433 ps
CPU time 4.23 seconds
Started Aug 03 04:35:15 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 200004 kb
Host smart-0b737961-b75d-4141-9842-2f7c87a25ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180119535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4180119535
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3323219359
Short name T619
Test name
Test status
Simulation time 15678841 ps
CPU time 0.63 seconds
Started Aug 03 04:35:48 PM PDT 24
Finished Aug 03 04:35:48 PM PDT 24
Peak memory 195148 kb
Host smart-caca160c-5169-4c08-b186-4adbd6e592e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323219359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3323219359
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2227552534
Short name T552
Test name
Test status
Simulation time 45269784 ps
CPU time 0.57 seconds
Started Aug 03 04:35:41 PM PDT 24
Finished Aug 03 04:35:42 PM PDT 24
Peak memory 195016 kb
Host smart-442e748d-d5e3-441b-81de-ebe9ced8a7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227552534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2227552534
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2847790247
Short name T535
Test name
Test status
Simulation time 28630206 ps
CPU time 0.6 seconds
Started Aug 03 04:35:42 PM PDT 24
Finished Aug 03 04:35:42 PM PDT 24
Peak memory 194988 kb
Host smart-530e96b8-5f0e-412b-b329-f9ebb6b3f6dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847790247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2847790247
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2336509763
Short name T557
Test name
Test status
Simulation time 44400347 ps
CPU time 0.57 seconds
Started Aug 03 04:35:44 PM PDT 24
Finished Aug 03 04:35:45 PM PDT 24
Peak memory 195100 kb
Host smart-3222b3a4-eca0-4046-8eab-639ca8e96c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336509763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2336509763
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2795500091
Short name T653
Test name
Test status
Simulation time 56668583 ps
CPU time 0.6 seconds
Started Aug 03 04:35:47 PM PDT 24
Finished Aug 03 04:35:47 PM PDT 24
Peak memory 194992 kb
Host smart-1d471176-2aac-4616-afc2-18adb7fbbc16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795500091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2795500091
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1391701465
Short name T577
Test name
Test status
Simulation time 25557033 ps
CPU time 0.63 seconds
Started Aug 03 04:35:36 PM PDT 24
Finished Aug 03 04:35:36 PM PDT 24
Peak memory 195180 kb
Host smart-263c5189-a204-4278-949d-8d8f4866b2c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391701465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1391701465
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3134070211
Short name T636
Test name
Test status
Simulation time 16269838 ps
CPU time 0.63 seconds
Started Aug 03 04:35:34 PM PDT 24
Finished Aug 03 04:35:34 PM PDT 24
Peak memory 194988 kb
Host smart-14e45892-f5be-4d15-8db9-ab22d3e6e599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134070211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3134070211
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3670894167
Short name T629
Test name
Test status
Simulation time 13379735 ps
CPU time 0.63 seconds
Started Aug 03 04:35:32 PM PDT 24
Finished Aug 03 04:35:33 PM PDT 24
Peak memory 195016 kb
Host smart-91ffb2a4-4d8c-44f7-a778-0e13d0a08923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670894167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3670894167
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.595811400
Short name T639
Test name
Test status
Simulation time 25310066 ps
CPU time 0.62 seconds
Started Aug 03 04:35:38 PM PDT 24
Finished Aug 03 04:35:39 PM PDT 24
Peak memory 194908 kb
Host smart-3bf53093-3bdd-4ece-babb-81ee94254098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595811400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.595811400
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1355548904
Short name T647
Test name
Test status
Simulation time 18012690 ps
CPU time 0.62 seconds
Started Aug 03 04:35:44 PM PDT 24
Finished Aug 03 04:35:45 PM PDT 24
Peak memory 195080 kb
Host smart-8e1ff536-61d6-453a-9e74-86147a6c3a73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355548904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1355548904
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1551342898
Short name T574
Test name
Test status
Simulation time 137753374 ps
CPU time 1.19 seconds
Started Aug 03 04:35:27 PM PDT 24
Finished Aug 03 04:35:28 PM PDT 24
Peak memory 199920 kb
Host smart-7e4ac1eb-0265-4322-a4e5-bb949847e777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551342898 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1551342898
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.563314643
Short name T113
Test name
Test status
Simulation time 270684274 ps
CPU time 0.95 seconds
Started Aug 03 04:35:18 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 199816 kb
Host smart-7baab154-901a-4b63-ac80-f496b672d76c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563314643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.563314643
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.4209031645
Short name T533
Test name
Test status
Simulation time 24998504 ps
CPU time 0.6 seconds
Started Aug 03 04:35:27 PM PDT 24
Finished Aug 03 04:35:28 PM PDT 24
Peak memory 195000 kb
Host smart-eef09b48-6c1a-4eb4-9753-d6b607cda362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209031645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.4209031645
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2021271523
Short name T651
Test name
Test status
Simulation time 22056103 ps
CPU time 1.08 seconds
Started Aug 03 04:35:18 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 200148 kb
Host smart-e12f7fec-f942-465c-8067-9023260160ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021271523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2021271523
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.218811382
Short name T646
Test name
Test status
Simulation time 198474488 ps
CPU time 3.56 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 200184 kb
Host smart-bec0bf41-3af7-475a-b171-6c43b9eb2b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218811382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.218811382
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2891879716
Short name T532
Test name
Test status
Simulation time 41494861 ps
CPU time 1.15 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 199964 kb
Host smart-00c563c7-b216-4108-b5de-e07f53ad99e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891879716 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2891879716
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1083878992
Short name T593
Test name
Test status
Simulation time 52791614 ps
CPU time 0.67 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 197644 kb
Host smart-35b16e2e-8aec-4ade-b74b-5f59049fd38c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083878992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1083878992
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3044685669
Short name T541
Test name
Test status
Simulation time 16694767 ps
CPU time 0.61 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 195064 kb
Host smart-9ef55385-9281-4ffa-8b9b-b0f42a1a52b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044685669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3044685669
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2234699595
Short name T572
Test name
Test status
Simulation time 45433034 ps
CPU time 2.29 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 199984 kb
Host smart-2820f133-a64c-4579-8c7f-de50dc6ecf61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234699595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2234699595
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.784655923
Short name T556
Test name
Test status
Simulation time 48269598 ps
CPU time 2.33 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:22 PM PDT 24
Peak memory 200072 kb
Host smart-e0abb231-e474-478f-9200-6a4b7c89c203
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784655923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.784655923
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1661086996
Short name T135
Test name
Test status
Simulation time 379673907 ps
CPU time 2.71 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:23 PM PDT 24
Peak memory 200064 kb
Host smart-e7afc77f-9997-4720-a77b-574c52a3b4a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661086996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1661086996
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1743035497
Short name T531
Test name
Test status
Simulation time 1145145677 ps
CPU time 2.3 seconds
Started Aug 03 04:35:18 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 200052 kb
Host smart-5b8d783a-e9fa-458c-8c70-135a1a5cff5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743035497 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1743035497
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2024474971
Short name T620
Test name
Test status
Simulation time 38491429 ps
CPU time 0.97 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 199432 kb
Host smart-10c91f2a-e0f1-4ba2-a407-452bcffc9f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024474971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2024474971
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2651442663
Short name T656
Test name
Test status
Simulation time 28715956 ps
CPU time 0.58 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 194968 kb
Host smart-69b71994-5b19-436f-bd0d-03459e59adbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651442663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2651442663
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.807381557
Short name T128
Test name
Test status
Simulation time 1178371530 ps
CPU time 2.13 seconds
Started Aug 03 04:35:18 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 200164 kb
Host smart-e55bb8d1-f420-430d-a37f-996c8506ae1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807381557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.807381557
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4001260492
Short name T594
Test name
Test status
Simulation time 29733962 ps
CPU time 1.48 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 200128 kb
Host smart-3b82931c-fc61-43e7-9751-b70c08c65f24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001260492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.4001260492
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.700813549
Short name T66
Test name
Test status
Simulation time 617734532 ps
CPU time 2.93 seconds
Started Aug 03 04:35:22 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 200052 kb
Host smart-b6164c3f-a09f-43bc-b717-54ec9b51cdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700813549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.700813549
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2764851921
Short name T546
Test name
Test status
Simulation time 477878814 ps
CPU time 1.69 seconds
Started Aug 03 04:35:23 PM PDT 24
Finished Aug 03 04:35:25 PM PDT 24
Peak memory 200240 kb
Host smart-0c73d82b-44bf-4d52-aa1a-79629f87a45c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764851921 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2764851921
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2722930517
Short name T120
Test name
Test status
Simulation time 44681531 ps
CPU time 0.79 seconds
Started Aug 03 04:35:18 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 199972 kb
Host smart-41fb82b5-b701-44a0-b25f-4fc3a67750dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722930517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2722930517
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.336099071
Short name T542
Test name
Test status
Simulation time 71869166 ps
CPU time 0.59 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:17 PM PDT 24
Peak memory 195044 kb
Host smart-1cf2b321-85e6-49e7-9e70-8e0ac2d98a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336099071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.336099071
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2707330430
Short name T129
Test name
Test status
Simulation time 451936414 ps
CPU time 2.33 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:35:22 PM PDT 24
Peak memory 200148 kb
Host smart-4ab69a2e-9240-47ef-a2a8-acae8f2cf73e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707330430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2707330430
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4141892432
Short name T558
Test name
Test status
Simulation time 59767703 ps
CPU time 3.06 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 200148 kb
Host smart-376ff580-c926-499c-9417-74933b30c8f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141892432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4141892432
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4171892643
Short name T140
Test name
Test status
Simulation time 358591730 ps
CPU time 4.43 seconds
Started Aug 03 04:35:16 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 200172 kb
Host smart-b9cda584-fb5c-45a2-a5d8-4978806d9e77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171892643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4171892643
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3565721773
Short name T543
Test name
Test status
Simulation time 129965768342 ps
CPU time 954.06 seconds
Started Aug 03 04:35:19 PM PDT 24
Finished Aug 03 04:51:13 PM PDT 24
Peak memory 216596 kb
Host smart-498f1592-5911-4fe8-993b-e65dc21688ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565721773 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3565721773
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.545512277
Short name T578
Test name
Test status
Simulation time 30226989 ps
CPU time 0.96 seconds
Started Aug 03 04:35:20 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 199944 kb
Host smart-5fd448e2-d219-4816-81e5-0e7afb2107f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545512277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.545512277
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1984612029
Short name T545
Test name
Test status
Simulation time 22694858 ps
CPU time 0.58 seconds
Started Aug 03 04:35:18 PM PDT 24
Finished Aug 03 04:35:20 PM PDT 24
Peak memory 194972 kb
Host smart-67ab5b37-e34d-49d1-8b98-876bd271dfa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984612029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1984612029
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3979086241
Short name T126
Test name
Test status
Simulation time 175218610 ps
CPU time 2.11 seconds
Started Aug 03 04:35:21 PM PDT 24
Finished Aug 03 04:35:23 PM PDT 24
Peak memory 200124 kb
Host smart-ff3b2755-e337-4ea8-a06a-ddf04a9ac418
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979086241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3979086241
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3917778347
Short name T655
Test name
Test status
Simulation time 108810685 ps
CPU time 2.24 seconds
Started Aug 03 04:35:21 PM PDT 24
Finished Aug 03 04:35:23 PM PDT 24
Peak memory 200084 kb
Host smart-63da89d8-3d06-41d7-b9e6-a3a8e27f352c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917778347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3917778347
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2631846627
Short name T298
Test name
Test status
Simulation time 12332881 ps
CPU time 0.62 seconds
Started Aug 03 04:41:49 PM PDT 24
Finished Aug 03 04:41:50 PM PDT 24
Peak memory 195544 kb
Host smart-4a28966b-4ce4-4a55-9c38-c179ee952a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631846627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2631846627
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3672188077
Short name T476
Test name
Test status
Simulation time 2612268792 ps
CPU time 74.36 seconds
Started Aug 03 04:41:41 PM PDT 24
Finished Aug 03 04:42:56 PM PDT 24
Peak memory 199936 kb
Host smart-ae8ad018-ad53-4027-81d6-6617bc730948
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672188077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3672188077
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1466621700
Short name T256
Test name
Test status
Simulation time 2702592085 ps
CPU time 25.77 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:42:29 PM PDT 24
Peak memory 200000 kb
Host smart-04cc03b9-c3d6-4962-b371-b746387769b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466621700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1466621700
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1719225101
Short name T286
Test name
Test status
Simulation time 2183537456 ps
CPU time 377.87 seconds
Started Aug 03 04:42:01 PM PDT 24
Finished Aug 03 04:48:19 PM PDT 24
Peak memory 605788 kb
Host smart-6fe1252a-0956-444f-aba9-ba187e92b15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719225101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1719225101
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.645492428
Short name T233
Test name
Test status
Simulation time 1569385012 ps
CPU time 20.57 seconds
Started Aug 03 04:41:46 PM PDT 24
Finished Aug 03 04:42:07 PM PDT 24
Peak memory 199696 kb
Host smart-865ab962-0a9c-4662-8fc3-60b67416b4f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645492428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.645492428
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3482883574
Short name T457
Test name
Test status
Simulation time 310564366 ps
CPU time 16.36 seconds
Started Aug 03 04:41:55 PM PDT 24
Finished Aug 03 04:42:12 PM PDT 24
Peak memory 199812 kb
Host smart-3aca7e3e-7bc3-456d-b8dc-bb4bc50ae5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482883574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3482883574
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.4164810358
Short name T90
Test name
Test status
Simulation time 560270148 ps
CPU time 6.23 seconds
Started Aug 03 04:41:51 PM PDT 24
Finished Aug 03 04:41:57 PM PDT 24
Peak memory 199816 kb
Host smart-65cdead0-d84c-4db8-acd8-1b903b107c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164810358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.4164810358
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.445235541
Short name T289
Test name
Test status
Simulation time 87192871755 ps
CPU time 1958.62 seconds
Started Aug 03 04:41:48 PM PDT 24
Finished Aug 03 05:14:27 PM PDT 24
Peak memory 774072 kb
Host smart-b1b27b37-447e-4b48-8c5d-0e8cc4199ce8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445235541 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.445235541
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2042694560
Short name T15
Test name
Test status
Simulation time 108685324034 ps
CPU time 1921.42 seconds
Started Aug 03 04:41:53 PM PDT 24
Finished Aug 03 05:13:55 PM PDT 24
Peak memory 650184 kb
Host smart-cf78a0cf-6ffa-4fb5-bad2-da1ae79906ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2042694560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2042694560
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2346121874
Short name T489
Test name
Test status
Simulation time 10529880560 ps
CPU time 39.79 seconds
Started Aug 03 04:41:44 PM PDT 24
Finished Aug 03 04:42:24 PM PDT 24
Peak memory 199968 kb
Host smart-54e0126a-1d4f-4794-a1ea-d85f7351855d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2346121874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2346121874
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.4114030304
Short name T3
Test name
Test status
Simulation time 12421195485 ps
CPU time 94.23 seconds
Started Aug 03 04:41:43 PM PDT 24
Finished Aug 03 04:43:17 PM PDT 24
Peak memory 199988 kb
Host smart-c1bc196b-82c0-42a3-8314-7fee04b9f701
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4114030304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.4114030304
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1367044272
Short name T395
Test name
Test status
Simulation time 19344459450 ps
CPU time 75.43 seconds
Started Aug 03 04:41:45 PM PDT 24
Finished Aug 03 04:43:00 PM PDT 24
Peak memory 199940 kb
Host smart-c296e996-484e-48e0-ba2c-489af8596d46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1367044272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1367044272
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3211509143
Short name T321
Test name
Test status
Simulation time 36273115733 ps
CPU time 608.31 seconds
Started Aug 03 04:41:41 PM PDT 24
Finished Aug 03 04:51:50 PM PDT 24
Peak memory 199964 kb
Host smart-0d26c822-ee37-4a9c-b0a1-ac89e7d82a09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3211509143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3211509143
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1286438324
Short name T191
Test name
Test status
Simulation time 292926687441 ps
CPU time 2328.55 seconds
Started Aug 03 04:41:55 PM PDT 24
Finished Aug 03 05:20:44 PM PDT 24
Peak memory 215484 kb
Host smart-b1fa0e0e-67a9-44b8-8eb9-f8d19c33d2c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1286438324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1286438324
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.29463999
Short name T315
Test name
Test status
Simulation time 142542831817 ps
CPU time 2451.35 seconds
Started Aug 03 04:41:59 PM PDT 24
Finished Aug 03 05:22:51 PM PDT 24
Peak memory 216280 kb
Host smart-1573ff20-64e0-42cd-bdf7-066228b76f9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=29463999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.29463999
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1341121995
Short name T528
Test name
Test status
Simulation time 411853427 ps
CPU time 18.7 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 04:42:23 PM PDT 24
Peak memory 199832 kb
Host smart-ba2642ed-60e0-4f3d-986c-765f99711298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341121995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1341121995
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1749807923
Short name T203
Test name
Test status
Simulation time 23238964 ps
CPU time 0.59 seconds
Started Aug 03 04:41:57 PM PDT 24
Finished Aug 03 04:41:58 PM PDT 24
Peak memory 195844 kb
Host smart-a5a4540a-cb75-4db9-8723-ac5d6feb293a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749807923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1749807923
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2643558185
Short name T326
Test name
Test status
Simulation time 3801278899 ps
CPU time 13.68 seconds
Started Aug 03 04:41:46 PM PDT 24
Finished Aug 03 04:42:00 PM PDT 24
Peak memory 199880 kb
Host smart-80884be8-6d9d-4be3-a3ac-cdafed8d9569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643558185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2643558185
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1105606135
Short name T526
Test name
Test status
Simulation time 4238635921 ps
CPU time 813.11 seconds
Started Aug 03 04:41:54 PM PDT 24
Finished Aug 03 04:55:27 PM PDT 24
Peak memory 667864 kb
Host smart-16f25ef7-c07a-4ad1-be38-cb813d825520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1105606135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1105606135
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2673113925
Short name T30
Test name
Test status
Simulation time 346854280 ps
CPU time 4.65 seconds
Started Aug 03 04:41:53 PM PDT 24
Finished Aug 03 04:41:58 PM PDT 24
Peak memory 199796 kb
Host smart-02ad1cde-3ffb-4b85-9a10-6b17be72569a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673113925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2673113925
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.99693595
Short name T287
Test name
Test status
Simulation time 14278805990 ps
CPU time 56.16 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:43:03 PM PDT 24
Peak memory 199948 kb
Host smart-b6751fb1-aa65-404a-8f93-3218373f0d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99693595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.99693595
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4181563985
Short name T56
Test name
Test status
Simulation time 392829993 ps
CPU time 0.98 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:42:07 PM PDT 24
Peak memory 218444 kb
Host smart-1f8daa8a-350b-415b-a812-896a079865ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181563985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4181563985
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1700493419
Short name T207
Test name
Test status
Simulation time 477380479 ps
CPU time 3.81 seconds
Started Aug 03 04:42:02 PM PDT 24
Finished Aug 03 04:42:06 PM PDT 24
Peak memory 199836 kb
Host smart-3c1cb879-f662-4636-847e-3422c3faa444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700493419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1700493419
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.4211192600
Short name T84
Test name
Test status
Simulation time 124181759087 ps
CPU time 3634.46 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 05:42:38 PM PDT 24
Peak memory 804108 kb
Host smart-82ca4637-052f-4d42-9356-7b46f696a813
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211192600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4211192600
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3532918390
Short name T67
Test name
Test status
Simulation time 62678071867 ps
CPU time 329.86 seconds
Started Aug 03 04:41:58 PM PDT 24
Finished Aug 03 04:47:28 PM PDT 24
Peak memory 216464 kb
Host smart-1ea2aa9e-7ef9-48b4-8aed-730db7bac12a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3532918390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3532918390
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.644851407
Short name T280
Test name
Test status
Simulation time 4700283891 ps
CPU time 75.64 seconds
Started Aug 03 04:41:48 PM PDT 24
Finished Aug 03 04:43:04 PM PDT 24
Peak memory 199940 kb
Host smart-2dbdcb09-1d58-414d-aa87-75ead928115d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=644851407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.644851407
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1869200056
Short name T472
Test name
Test status
Simulation time 14020995960 ps
CPU time 93.97 seconds
Started Aug 03 04:41:48 PM PDT 24
Finished Aug 03 04:43:22 PM PDT 24
Peak memory 199972 kb
Host smart-2f23aca8-0703-4f4a-b904-646b9ca3d0ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1869200056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1869200056
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.2628894699
Short name T156
Test name
Test status
Simulation time 5028336621 ps
CPU time 75.3 seconds
Started Aug 03 04:41:37 PM PDT 24
Finished Aug 03 04:42:53 PM PDT 24
Peak memory 199956 kb
Host smart-5b516749-0dd4-4212-a1ad-65235d224398
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2628894699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2628894699
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3837797288
Short name T155
Test name
Test status
Simulation time 45744914338 ps
CPU time 569.68 seconds
Started Aug 03 04:41:52 PM PDT 24
Finished Aug 03 04:51:22 PM PDT 24
Peak memory 199984 kb
Host smart-866dc933-97e2-4b20-90b6-5c8df6af5090
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3837797288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3837797288
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3238815108
Short name T51
Test name
Test status
Simulation time 577216665673 ps
CPU time 2370.08 seconds
Started Aug 03 04:41:52 PM PDT 24
Finished Aug 03 05:21:22 PM PDT 24
Peak memory 216300 kb
Host smart-cace8e01-e2aa-4ef3-98ee-8d8abbf6b121
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3238815108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3238815108
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.159503656
Short name T511
Test name
Test status
Simulation time 99348041112 ps
CPU time 2172.68 seconds
Started Aug 03 04:42:00 PM PDT 24
Finished Aug 03 05:18:13 PM PDT 24
Peak memory 216420 kb
Host smart-e5585d38-650b-4d1b-845b-4571b53efcf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=159503656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.159503656
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.4101847353
Short name T132
Test name
Test status
Simulation time 9683651608 ps
CPU time 120.68 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:44:09 PM PDT 24
Peak memory 199904 kb
Host smart-4f5c159f-7d8e-47f3-8c86-60ec11d2aef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101847353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.4101847353
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1836579694
Short name T278
Test name
Test status
Simulation time 96413569 ps
CPU time 0.62 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:42:03 PM PDT 24
Peak memory 195900 kb
Host smart-7686854b-1cf4-4616-b558-fda3b5ef3f65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836579694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1836579694
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1485694864
Short name T318
Test name
Test status
Simulation time 991055796 ps
CPU time 60.61 seconds
Started Aug 03 04:42:19 PM PDT 24
Finished Aug 03 04:43:20 PM PDT 24
Peak memory 199844 kb
Host smart-11d40d98-7341-493e-9e48-1bdb8e39bdcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485694864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1485694864
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.149217037
Short name T445
Test name
Test status
Simulation time 184282825 ps
CPU time 2.1 seconds
Started Aug 03 04:42:14 PM PDT 24
Finished Aug 03 04:42:17 PM PDT 24
Peak memory 199796 kb
Host smart-76ec770e-b77d-4877-a060-646baebb7c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149217037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.149217037
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.21483227
Short name T282
Test name
Test status
Simulation time 1261488104 ps
CPU time 226.81 seconds
Started Aug 03 04:42:12 PM PDT 24
Finished Aug 03 04:45:59 PM PDT 24
Peak memory 655656 kb
Host smart-90e4c2a1-6fd2-4329-9825-cc46517d06c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21483227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.21483227
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3707814584
Short name T308
Test name
Test status
Simulation time 3177260964 ps
CPU time 150.06 seconds
Started Aug 03 04:42:13 PM PDT 24
Finished Aug 03 04:44:43 PM PDT 24
Peak memory 199988 kb
Host smart-e48946fa-d8f3-40c6-9f1b-85e8231f4196
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707814584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3707814584
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3699360487
Short name T159
Test name
Test status
Simulation time 104133215516 ps
CPU time 96.07 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:43:45 PM PDT 24
Peak memory 199924 kb
Host smart-81df03f1-8c8f-41bd-980f-36d0684e3643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699360487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3699360487
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2097611056
Short name T348
Test name
Test status
Simulation time 530943067 ps
CPU time 6.07 seconds
Started Aug 03 04:42:27 PM PDT 24
Finished Aug 03 04:42:33 PM PDT 24
Peak memory 199824 kb
Host smart-6843348d-0324-4b33-a577-56a940505e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097611056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2097611056
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3583714031
Short name T299
Test name
Test status
Simulation time 256961876 ps
CPU time 3.53 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:42:13 PM PDT 24
Peak memory 199848 kb
Host smart-fb76a82b-d4b7-42ac-9a05-ae9b5b1ef2dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583714031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3583714031
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3372765277
Short name T96
Test name
Test status
Simulation time 30970582398 ps
CPU time 130.13 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:44:26 PM PDT 24
Peak memory 199976 kb
Host smart-e193ce5c-89c1-47e1-b7c2-cce86f69d911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372765277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3372765277
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.4147561493
Short name T228
Test name
Test status
Simulation time 15690104 ps
CPU time 0.58 seconds
Started Aug 03 04:42:02 PM PDT 24
Finished Aug 03 04:42:03 PM PDT 24
Peak memory 196620 kb
Host smart-acb17e85-f8c0-4d21-9118-125a6da56c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147561493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.4147561493
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2954716183
Short name T338
Test name
Test status
Simulation time 7906088167 ps
CPU time 54.88 seconds
Started Aug 03 04:42:17 PM PDT 24
Finished Aug 03 04:43:12 PM PDT 24
Peak memory 199964 kb
Host smart-30ac997c-1b4f-4401-b12e-80ad4f45ab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954716183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2954716183
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1214377737
Short name T158
Test name
Test status
Simulation time 724623579 ps
CPU time 118.57 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:44:07 PM PDT 24
Peak memory 438196 kb
Host smart-ebca543d-fdba-4d71-bfa3-09545cadf6bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214377737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1214377737
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1863254069
Short name T340
Test name
Test status
Simulation time 15120146232 ps
CPU time 136.23 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:44:32 PM PDT 24
Peak memory 199912 kb
Host smart-6fdb3dc0-7958-493b-980f-e34b65ed8526
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863254069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1863254069
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3054487497
Short name T177
Test name
Test status
Simulation time 46914411323 ps
CPU time 154.33 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:44:42 PM PDT 24
Peak memory 208152 kb
Host smart-15dd7b91-f9da-4967-87a9-2cc8e3fffc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054487497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3054487497
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2273496594
Short name T194
Test name
Test status
Simulation time 194411663 ps
CPU time 3.54 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:42:20 PM PDT 24
Peak memory 199860 kb
Host smart-80905905-6fb4-4eec-b906-6fc426a83be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273496594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2273496594
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.746351740
Short name T418
Test name
Test status
Simulation time 127217045270 ps
CPU time 1477.19 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 05:06:53 PM PDT 24
Peak memory 717920 kb
Host smart-1c3f97c0-ad09-43d9-a7be-34add608f2c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746351740 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.746351740
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2416584166
Short name T235
Test name
Test status
Simulation time 1648289663 ps
CPU time 75.74 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:43:22 PM PDT 24
Peak memory 199820 kb
Host smart-be0befa6-4697-47d1-a344-2b2caf822de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416584166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2416584166
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1135422297
Short name T182
Test name
Test status
Simulation time 18899943 ps
CPU time 0.56 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:42:21 PM PDT 24
Peak memory 195692 kb
Host smart-b000638d-96dc-4fd4-82b6-c18e941a159d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135422297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1135422297
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.134489574
Short name T417
Test name
Test status
Simulation time 296476039 ps
CPU time 4.76 seconds
Started Aug 03 04:42:17 PM PDT 24
Finished Aug 03 04:42:21 PM PDT 24
Peak memory 199776 kb
Host smart-ff86ac46-ba7d-47ce-8818-6d62b0f422f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134489574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.134489574
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1867743238
Short name T242
Test name
Test status
Simulation time 357580562 ps
CPU time 3.37 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:42:09 PM PDT 24
Peak memory 199648 kb
Host smart-bd5fd576-080d-413a-9ac1-1813523430a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867743238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1867743238
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2681297792
Short name T92
Test name
Test status
Simulation time 15004318 ps
CPU time 0.71 seconds
Started Aug 03 04:42:02 PM PDT 24
Finished Aug 03 04:42:03 PM PDT 24
Peak memory 198456 kb
Host smart-86a87ab9-dd45-4fcb-bcaf-c750c6b30444
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2681297792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2681297792
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1470360858
Short name T28
Test name
Test status
Simulation time 28032246062 ps
CPU time 35.19 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:42:38 PM PDT 24
Peak memory 199876 kb
Host smart-7c621a0d-c40a-4574-8ee5-3a86870db341
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470360858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1470360858
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3211083123
Short name T454
Test name
Test status
Simulation time 2719564084 ps
CPU time 146.85 seconds
Started Aug 03 04:42:13 PM PDT 24
Finished Aug 03 04:44:40 PM PDT 24
Peak memory 200032 kb
Host smart-de3b6462-3c0b-4047-be1d-d1fcc02b821d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211083123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3211083123
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3298867414
Short name T434
Test name
Test status
Simulation time 956299432 ps
CPU time 6.22 seconds
Started Aug 03 04:42:14 PM PDT 24
Finished Aug 03 04:42:21 PM PDT 24
Peak memory 199792 kb
Host smart-78dd21e2-4401-42c7-943c-3118f2b480a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298867414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3298867414
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3993437981
Short name T150
Test name
Test status
Simulation time 94334531249 ps
CPU time 3160.59 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 05:34:50 PM PDT 24
Peak memory 818608 kb
Host smart-5255a7c2-8be0-4bc6-897c-39cecc749a47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993437981 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3993437981
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.924288302
Short name T87
Test name
Test status
Simulation time 1347458984 ps
CPU time 27.16 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:42:36 PM PDT 24
Peak memory 199892 kb
Host smart-89356603-e02e-41ae-b42a-72edd0b54ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924288302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.924288302
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2853749110
Short name T488
Test name
Test status
Simulation time 15146577 ps
CPU time 0.6 seconds
Started Aug 03 04:42:11 PM PDT 24
Finished Aug 03 04:42:11 PM PDT 24
Peak memory 195916 kb
Host smart-bb3558fc-6335-4f48-a244-77950a900bf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853749110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2853749110
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.567120488
Short name T196
Test name
Test status
Simulation time 2154682193 ps
CPU time 28.36 seconds
Started Aug 03 04:42:11 PM PDT 24
Finished Aug 03 04:42:39 PM PDT 24
Peak memory 199892 kb
Host smart-d84007b7-2d9d-42fa-9e8c-7e95e52358b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567120488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.567120488
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1303850082
Short name T519
Test name
Test status
Simulation time 11713882590 ps
CPU time 475.39 seconds
Started Aug 03 04:42:18 PM PDT 24
Finished Aug 03 04:50:13 PM PDT 24
Peak memory 666508 kb
Host smart-fa9b5857-2bf3-452a-b6c0-2994954abfd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1303850082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1303850082
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2827046717
Short name T237
Test name
Test status
Simulation time 75235160646 ps
CPU time 232.15 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:46:00 PM PDT 24
Peak memory 199940 kb
Host smart-4caab6cd-683f-4151-b937-e9e79a7f02bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827046717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2827046717
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1565454883
Short name T369
Test name
Test status
Simulation time 46845139115 ps
CPU time 154.81 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:44:50 PM PDT 24
Peak memory 200180 kb
Host smart-0a6a9aab-6ec9-41ac-9df0-ee379adc58e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565454883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1565454883
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.53467064
Short name T40
Test name
Test status
Simulation time 1085837436 ps
CPU time 9.48 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:42:30 PM PDT 24
Peak memory 199836 kb
Host smart-2600e5f1-4359-40c4-9e78-4033c1b58a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53467064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.53467064
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3122533037
Short name T29
Test name
Test status
Simulation time 446344837 ps
CPU time 13.4 seconds
Started Aug 03 04:42:17 PM PDT 24
Finished Aug 03 04:42:30 PM PDT 24
Peak memory 199864 kb
Host smart-58cd457c-5ec4-4103-b541-b990bd977665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122533037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3122533037
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1370298092
Short name T437
Test name
Test status
Simulation time 60033901 ps
CPU time 0.58 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:42:15 PM PDT 24
Peak memory 196584 kb
Host smart-433f5884-cef3-4d69-b5e0-509f51a2aee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370298092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1370298092
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.80205519
Short name T334
Test name
Test status
Simulation time 1525780781 ps
CPU time 39.76 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:42:46 PM PDT 24
Peak memory 199880 kb
Host smart-54a6be26-5285-42ae-b786-37c7aa301b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80205519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.80205519
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2148997971
Short name T311
Test name
Test status
Simulation time 399121130 ps
CPU time 21.56 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:42:31 PM PDT 24
Peak memory 199724 kb
Host smart-4a90dd35-45aa-4a14-a027-610ab49edd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148997971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2148997971
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1334061955
Short name T241
Test name
Test status
Simulation time 13597482378 ps
CPU time 547.4 seconds
Started Aug 03 04:42:19 PM PDT 24
Finished Aug 03 04:51:26 PM PDT 24
Peak memory 714976 kb
Host smart-4134598f-4ff9-419c-95a9-14983018e177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334061955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1334061955
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1488863361
Short name T214
Test name
Test status
Simulation time 3121473383 ps
CPU time 78.58 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:43:34 PM PDT 24
Peak memory 199944 kb
Host smart-28b7dbef-df10-42d5-a2f3-7b3575b3ed8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488863361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1488863361
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3757093319
Short name T351
Test name
Test status
Simulation time 403989407 ps
CPU time 24.21 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:42:33 PM PDT 24
Peak memory 199760 kb
Host smart-d852f471-c53e-42bb-8a5f-04733faf4f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757093319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3757093319
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2338834355
Short name T431
Test name
Test status
Simulation time 278996571 ps
CPU time 12.16 seconds
Started Aug 03 04:42:19 PM PDT 24
Finished Aug 03 04:42:31 PM PDT 24
Peak memory 199848 kb
Host smart-b56934ff-1a9a-4b6e-ac39-f5dd02c97ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338834355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2338834355
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2355107010
Short name T192
Test name
Test status
Simulation time 174934766346 ps
CPU time 829.02 seconds
Started Aug 03 04:42:13 PM PDT 24
Finished Aug 03 04:56:02 PM PDT 24
Peak memory 408444 kb
Host smart-e72ef7d3-a4b6-4576-bb71-ea427c71f226
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355107010 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2355107010
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2713547472
Short name T339
Test name
Test status
Simulation time 528028112 ps
CPU time 23.03 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:42:29 PM PDT 24
Peak memory 199840 kb
Host smart-c723bc6b-b08c-40be-9d20-0224b6cc3626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713547472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2713547472
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4128032046
Short name T244
Test name
Test status
Simulation time 15258706 ps
CPU time 0.6 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:42:08 PM PDT 24
Peak memory 195920 kb
Host smart-63d092f8-bd8a-4c79-8e70-591caf9906b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128032046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4128032046
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3110237102
Short name T146
Test name
Test status
Simulation time 1168350421 ps
CPU time 33.76 seconds
Started Aug 03 04:42:14 PM PDT 24
Finished Aug 03 04:42:48 PM PDT 24
Peak memory 199856 kb
Host smart-b37d4a2d-d56f-4d9d-8d72-6be90a9b19f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110237102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3110237102
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.254583548
Short name T439
Test name
Test status
Simulation time 567270114 ps
CPU time 28.94 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:42:49 PM PDT 24
Peak memory 199800 kb
Host smart-20b0e1c7-9d57-4552-ada1-2f2e57523d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254583548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.254583548
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2309759253
Short name T267
Test name
Test status
Simulation time 619977855 ps
CPU time 106.32 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:44:08 PM PDT 24
Peak memory 453076 kb
Host smart-c26bcb64-c562-4bc6-b196-140a20944f98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309759253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2309759253
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.86981923
Short name T250
Test name
Test status
Simulation time 3570821959 ps
CPU time 16.94 seconds
Started Aug 03 04:42:14 PM PDT 24
Finished Aug 03 04:42:31 PM PDT 24
Peak memory 199844 kb
Host smart-13fac4c8-11bd-433f-9dbb-85ebbe81b8dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86981923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.86981923
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1227364195
Short name T48
Test name
Test status
Simulation time 22478788957 ps
CPU time 77.19 seconds
Started Aug 03 04:42:11 PM PDT 24
Finished Aug 03 04:43:28 PM PDT 24
Peak memory 199968 kb
Host smart-a40180c1-3e31-43c1-a9c2-be10b7592842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227364195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1227364195
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2402654625
Short name T269
Test name
Test status
Simulation time 3118356132 ps
CPU time 11.83 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:42:35 PM PDT 24
Peak memory 199948 kb
Host smart-33dec851-23c6-4bcf-8269-7324bfa1e2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402654625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2402654625
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2049208765
Short name T25
Test name
Test status
Simulation time 2472516641 ps
CPU time 35.35 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 04:43:00 PM PDT 24
Peak memory 199904 kb
Host smart-cfdc1dcc-9964-4fae-a306-9efed85ffd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049208765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2049208765
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.872176282
Short name T427
Test name
Test status
Simulation time 2080760093 ps
CPU time 41.98 seconds
Started Aug 03 04:42:19 PM PDT 24
Finished Aug 03 04:43:01 PM PDT 24
Peak memory 199812 kb
Host smart-3a2c1c61-9b1f-4bc0-8fda-e676c4697421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872176282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.872176282
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2467142695
Short name T105
Test name
Test status
Simulation time 597850901 ps
CPU time 30.24 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:42:36 PM PDT 24
Peak memory 199708 kb
Host smart-af807633-60a6-41a7-b3e6-722739b751bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467142695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2467142695
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3719639580
Short name T49
Test name
Test status
Simulation time 25717549673 ps
CPU time 1185.87 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 05:02:12 PM PDT 24
Peak memory 707276 kb
Host smart-b75d81c8-a0bd-477a-a6e2-001fdc5b9aeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719639580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3719639580
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2059285984
Short name T213
Test name
Test status
Simulation time 13993862270 ps
CPU time 127.46 seconds
Started Aug 03 04:42:12 PM PDT 24
Finished Aug 03 04:44:19 PM PDT 24
Peak memory 200032 kb
Host smart-2e51aa4b-3492-4413-80f2-257537e78832
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059285984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2059285984
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2899551014
Short name T285
Test name
Test status
Simulation time 13487055344 ps
CPU time 121.57 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:44:22 PM PDT 24
Peak memory 199948 kb
Host smart-74b57e00-698c-4c67-8437-5ddce39b46b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899551014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2899551014
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3841011211
Short name T483
Test name
Test status
Simulation time 3614522007 ps
CPU time 7.58 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:42:16 PM PDT 24
Peak memory 199964 kb
Host smart-ad74bca6-7349-4d8a-bc3a-ac275fa2f799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841011211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3841011211
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1696697197
Short name T97
Test name
Test status
Simulation time 89017182058 ps
CPU time 2781.08 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 05:28:26 PM PDT 24
Peak memory 775476 kb
Host smart-cf6a5f37-c89f-4a4d-bd85-b151771a27ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696697197 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1696697197
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3061727599
Short name T61
Test name
Test status
Simulation time 2237891601 ps
CPU time 59 seconds
Started Aug 03 04:42:22 PM PDT 24
Finished Aug 03 04:43:21 PM PDT 24
Peak memory 199972 kb
Host smart-1a9527a7-01eb-4cf7-8d52-fe2b41af22e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061727599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3061727599
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2267192926
Short name T161
Test name
Test status
Simulation time 23308422 ps
CPU time 0.62 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:42:22 PM PDT 24
Peak memory 194832 kb
Host smart-23228a52-a44f-4730-a352-e50266a41753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267192926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2267192926
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.651694203
Short name T322
Test name
Test status
Simulation time 751623840 ps
CPU time 40.23 seconds
Started Aug 03 04:42:12 PM PDT 24
Finished Aug 03 04:42:52 PM PDT 24
Peak memory 199868 kb
Host smart-0a57a846-5204-4c3f-859c-212f00a8dfab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651694203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.651694203
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2143656219
Short name T394
Test name
Test status
Simulation time 10715598306 ps
CPU time 35.76 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:42:42 PM PDT 24
Peak memory 208176 kb
Host smart-f28251e8-4aea-461e-9d87-457a320d7cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143656219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2143656219
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.4146069195
Short name T408
Test name
Test status
Simulation time 16114048174 ps
CPU time 320.88 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:47:36 PM PDT 24
Peak memory 596424 kb
Host smart-c35311b1-2586-49b4-b809-a3fb229dbc23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146069195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.4146069195
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.776510147
Short name T521
Test name
Test status
Simulation time 24410149242 ps
CPU time 156.14 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:44:56 PM PDT 24
Peak memory 199936 kb
Host smart-70d16834-c628-4764-94dd-243a37300b8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776510147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.776510147
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.231847295
Short name T101
Test name
Test status
Simulation time 313658343 ps
CPU time 18.35 seconds
Started Aug 03 04:42:24 PM PDT 24
Finished Aug 03 04:42:42 PM PDT 24
Peak memory 199848 kb
Host smart-0201bae5-1299-4911-a222-977900a70641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231847295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.231847295
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3049929829
Short name T400
Test name
Test status
Simulation time 3253307998 ps
CPU time 9.7 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:42:19 PM PDT 24
Peak memory 199972 kb
Host smart-db04c983-0a9f-48b3-b54d-10dfa6c843cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049929829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3049929829
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3729619106
Short name T148
Test name
Test status
Simulation time 543223727 ps
CPU time 25.48 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:42:40 PM PDT 24
Peak memory 199824 kb
Host smart-51633846-6d9e-43bc-bf22-dd97c1561e7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729619106 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3729619106
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3682749837
Short name T510
Test name
Test status
Simulation time 2308172428 ps
CPU time 62.38 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:43:10 PM PDT 24
Peak memory 199968 kb
Host smart-0c9c6688-1ab1-4287-ab74-fcaf4a0132b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682749837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3682749837
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2456569563
Short name T484
Test name
Test status
Simulation time 50069870 ps
CPU time 0.6 seconds
Started Aug 03 04:42:13 PM PDT 24
Finished Aug 03 04:42:14 PM PDT 24
Peak memory 195916 kb
Host smart-09420095-7f0f-4496-9fef-5a9f032972a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456569563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2456569563
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1402149260
Short name T238
Test name
Test status
Simulation time 2935274224 ps
CPU time 85.05 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:43:34 PM PDT 24
Peak memory 199960 kb
Host smart-9310689c-5005-4fa8-809e-7fb49872e7a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402149260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1402149260
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1587542392
Short name T435
Test name
Test status
Simulation time 18055914196 ps
CPU time 61.64 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:43:25 PM PDT 24
Peak memory 216332 kb
Host smart-189b4766-0eaa-41dd-b7c9-ca2a6d3f2398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587542392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1587542392
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.20422451
Short name T157
Test name
Test status
Simulation time 14291511202 ps
CPU time 664.92 seconds
Started Aug 03 04:42:12 PM PDT 24
Finished Aug 03 04:53:17 PM PDT 24
Peak memory 685320 kb
Host smart-3d07ed3b-188d-453c-8079-7bd4190e0d62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20422451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.20422451
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1416171123
Short name T447
Test name
Test status
Simulation time 16634628076 ps
CPU time 47.75 seconds
Started Aug 03 04:42:11 PM PDT 24
Finished Aug 03 04:42:59 PM PDT 24
Peak memory 199956 kb
Host smart-8f0dd6ce-499a-4e41-8851-7ad0627d6400
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416171123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1416171123
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2662968223
Short name T169
Test name
Test status
Simulation time 14392507862 ps
CPU time 92.67 seconds
Started Aug 03 04:42:13 PM PDT 24
Finished Aug 03 04:43:45 PM PDT 24
Peak memory 199968 kb
Host smart-61f66db2-d7ba-44de-92da-c6a7d80acae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662968223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2662968223
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1001262105
Short name T324
Test name
Test status
Simulation time 55994190 ps
CPU time 2.23 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:42:22 PM PDT 24
Peak memory 199808 kb
Host smart-ca5bc2f9-0621-4000-b547-3e13b1a32c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001262105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1001262105
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2850853089
Short name T85
Test name
Test status
Simulation time 166003801117 ps
CPU time 1468 seconds
Started Aug 03 04:42:26 PM PDT 24
Finished Aug 03 05:06:54 PM PDT 24
Peak memory 699024 kb
Host smart-d097733c-fde3-4e59-aaf6-07bffa8b6be6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850853089 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2850853089
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2954385334
Short name T346
Test name
Test status
Simulation time 1940187710 ps
CPU time 19.9 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:42:36 PM PDT 24
Peak memory 199716 kb
Host smart-30216263-b38b-468b-90dd-1b5e3876269e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954385334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2954385334
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2215891085
Short name T31
Test name
Test status
Simulation time 49032633 ps
CPU time 0.59 seconds
Started Aug 03 04:42:10 PM PDT 24
Finished Aug 03 04:42:10 PM PDT 24
Peak memory 195912 kb
Host smart-7c974975-5f80-4ccd-b756-29c5a58c9016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215891085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2215891085
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1998770661
Short name T446
Test name
Test status
Simulation time 1531792958 ps
CPU time 84.11 seconds
Started Aug 03 04:42:29 PM PDT 24
Finished Aug 03 04:43:53 PM PDT 24
Peak memory 199828 kb
Host smart-7c2d9c39-76fa-4920-a731-e8c160291541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998770661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1998770661
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2887866749
Short name T170
Test name
Test status
Simulation time 636550983 ps
CPU time 8.42 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:42:32 PM PDT 24
Peak memory 199792 kb
Host smart-ac8ba882-1aaf-4709-a33d-1e38ed9c912b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887866749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2887866749
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4197457692
Short name T27
Test name
Test status
Simulation time 917242869 ps
CPU time 157.47 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:44:47 PM PDT 24
Peak memory 604184 kb
Host smart-c6c00ce2-d3d7-4b88-996b-a9d26be907e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197457692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4197457692
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3676950919
Short name T63
Test name
Test status
Simulation time 2992851608 ps
CPU time 163.16 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:45:04 PM PDT 24
Peak memory 200192 kb
Host smart-8ace5cc8-ba41-438a-8662-0428dc45fac0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676950919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3676950919
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.179191660
Short name T466
Test name
Test status
Simulation time 172836973 ps
CPU time 9.04 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:42:30 PM PDT 24
Peak memory 199832 kb
Host smart-ae063865-24fa-4703-b463-4fb4c04e3039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179191660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.179191660
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3745345355
Short name T362
Test name
Test status
Simulation time 644534303 ps
CPU time 7.81 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:42:29 PM PDT 24
Peak memory 199776 kb
Host smart-97baf3d8-2be5-4950-8d70-dace423c1581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745345355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3745345355
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3402757464
Short name T492
Test name
Test status
Simulation time 35851771760 ps
CPU time 951.03 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:57:57 PM PDT 24
Peak memory 498452 kb
Host smart-c4057b4d-c4ea-4f45-a293-a929c5cb13be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402757464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3402757464
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1023361203
Short name T393
Test name
Test status
Simulation time 3414909161 ps
CPU time 51.79 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:43:12 PM PDT 24
Peak memory 199940 kb
Host smart-e41d5275-2eef-40d3-bd3f-95548062c23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023361203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1023361203
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2496975008
Short name T76
Test name
Test status
Simulation time 34882807 ps
CPU time 0.57 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:42:03 PM PDT 24
Peak memory 196592 kb
Host smart-bf634804-c414-42ed-854c-dfd77fd4c94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496975008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2496975008
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.851267366
Short name T515
Test name
Test status
Simulation time 3267569190 ps
CPU time 92.97 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:43:39 PM PDT 24
Peak memory 199976 kb
Host smart-d4bd6671-bf24-4e52-9d46-4accb535fb28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=851267366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.851267366
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3127036797
Short name T5
Test name
Test status
Simulation time 819962523 ps
CPU time 22.89 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 04:42:28 PM PDT 24
Peak memory 199820 kb
Host smart-4b79bebe-cf62-483b-a8dd-63405db80d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127036797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3127036797
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2832230074
Short name T257
Test name
Test status
Simulation time 8480613498 ps
CPU time 292.66 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:47:04 PM PDT 24
Peak memory 440768 kb
Host smart-fadac2b5-aef9-44cf-ab27-87c2af3b4f7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2832230074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2832230074
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2924674354
Short name T198
Test name
Test status
Simulation time 4275904079 ps
CPU time 110.98 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:43:58 PM PDT 24
Peak memory 199960 kb
Host smart-835e109e-4b65-414b-9f99-131270285310
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924674354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2924674354
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2070663944
Short name T199
Test name
Test status
Simulation time 17384211655 ps
CPU time 161.6 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:44:50 PM PDT 24
Peak memory 200184 kb
Host smart-e0165b46-3542-49a4-9c6d-1e599fc20cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070663944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2070663944
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.376799060
Short name T55
Test name
Test status
Simulation time 154171365 ps
CPU time 0.84 seconds
Started Aug 03 04:41:52 PM PDT 24
Finished Aug 03 04:41:53 PM PDT 24
Peak memory 218456 kb
Host smart-66ae7a70-d264-4e7e-b07d-6bc9ff2472e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376799060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.376799060
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.541612327
Short name T34
Test name
Test status
Simulation time 119661422 ps
CPU time 5.04 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:42:08 PM PDT 24
Peak memory 199872 kb
Host smart-11dd2e5c-0c74-418a-a8df-184ff89782dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541612327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.541612327
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2701753942
Short name T396
Test name
Test status
Simulation time 56616268779 ps
CPU time 237.87 seconds
Started Aug 03 04:41:49 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 208180 kb
Host smart-db4703ce-286a-42bc-b554-9842ef255862
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701753942 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2701753942
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2756691569
Short name T501
Test name
Test status
Simulation time 15817213269 ps
CPU time 81.54 seconds
Started Aug 03 04:42:02 PM PDT 24
Finished Aug 03 04:43:23 PM PDT 24
Peak memory 200160 kb
Host smart-77c83d18-4703-478c-a3a6-ea279b44b73c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2756691569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2756691569
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.2752592604
Short name T270
Test name
Test status
Simulation time 9273378185 ps
CPU time 59.76 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:43:03 PM PDT 24
Peak memory 199936 kb
Host smart-3842a358-2a77-4fab-8c77-52bb1e051580
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2752592604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2752592604
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3431295933
Short name T451
Test name
Test status
Simulation time 7668668232 ps
CPU time 117.07 seconds
Started Aug 03 04:41:54 PM PDT 24
Finished Aug 03 04:43:51 PM PDT 24
Peak memory 199980 kb
Host smart-b0497a71-c5ea-4885-8f89-bbc715fed461
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3431295933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3431295933
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3978363616
Short name T516
Test name
Test status
Simulation time 48476009959 ps
CPU time 656.52 seconds
Started Aug 03 04:41:54 PM PDT 24
Finished Aug 03 04:52:51 PM PDT 24
Peak memory 199932 kb
Host smart-2f575de4-f358-4b12-ba3e-565803fdf371
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3978363616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3978363616
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.4038153545
Short name T403
Test name
Test status
Simulation time 652050905008 ps
CPU time 2433.93 seconds
Started Aug 03 04:41:55 PM PDT 24
Finished Aug 03 05:22:30 PM PDT 24
Peak memory 216292 kb
Host smart-6eadf5f9-8194-4dda-8ea4-e5a341baf579
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4038153545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.4038153545
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3274169837
Short name T153
Test name
Test status
Simulation time 576924246051 ps
CPU time 2484.39 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 05:23:28 PM PDT 24
Peak memory 215504 kb
Host smart-5854dbc8-50f6-437f-a3a4-50521a35f882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3274169837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3274169837
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2131805094
Short name T79
Test name
Test status
Simulation time 11474411802 ps
CPU time 144.68 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:44:33 PM PDT 24
Peak memory 199956 kb
Host smart-c16c12ea-efc1-41e9-827d-b5973cbbc71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131805094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2131805094
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2011123355
Short name T342
Test name
Test status
Simulation time 13388977 ps
CPU time 0.57 seconds
Started Aug 03 04:42:22 PM PDT 24
Finished Aug 03 04:42:28 PM PDT 24
Peak memory 194904 kb
Host smart-e3080f57-8650-4799-bbb6-c1f2d967bebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011123355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2011123355
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1429592406
Short name T107
Test name
Test status
Simulation time 1673930793 ps
CPU time 49.96 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:42:57 PM PDT 24
Peak memory 199840 kb
Host smart-1a96e1be-a1f9-46b0-bb2b-2cf160a97fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429592406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1429592406
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2276832511
Short name T517
Test name
Test status
Simulation time 2984236553 ps
CPU time 35.17 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:42:56 PM PDT 24
Peak memory 199980 kb
Host smart-6787e804-11b9-40ae-af4e-a0133359eca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276832511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2276832511
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2655093730
Short name T193
Test name
Test status
Simulation time 3963899943 ps
CPU time 771.07 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:55:00 PM PDT 24
Peak memory 692244 kb
Host smart-58a5c5af-1841-46f4-aac5-88fb528dd59e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2655093730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2655093730
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.4165956766
Short name T162
Test name
Test status
Simulation time 41611899627 ps
CPU time 130.41 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:44:20 PM PDT 24
Peak memory 199984 kb
Host smart-f7e92395-2778-4959-a7ce-e387d3842ef8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165956766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.4165956766
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.138499869
Short name T72
Test name
Test status
Simulation time 3746961411 ps
CPU time 50.93 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:43:08 PM PDT 24
Peak memory 199956 kb
Host smart-966fbb99-93c7-4a28-bcb2-d73974653c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138499869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.138499869
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.53809632
Short name T415
Test name
Test status
Simulation time 3718399954 ps
CPU time 11.98 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:42:28 PM PDT 24
Peak memory 199952 kb
Host smart-4249c39a-bf5a-4263-9f00-65b6a4d9c6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53809632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.53809632
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1370049461
Short name T304
Test name
Test status
Simulation time 120402021131 ps
CPU time 905.08 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:57:14 PM PDT 24
Peak memory 674396 kb
Host smart-48f87e00-d89d-490e-8b76-7df498c9f537
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370049461 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1370049461
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2336153648
Short name T185
Test name
Test status
Simulation time 177449122880 ps
CPU time 116.78 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:44:13 PM PDT 24
Peak memory 199940 kb
Host smart-ce4e033a-bfd6-43d2-a3ff-0e0d28475505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336153648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2336153648
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2440681562
Short name T249
Test name
Test status
Simulation time 20377937 ps
CPU time 0.59 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:42:09 PM PDT 24
Peak memory 195548 kb
Host smart-c8eba83a-3b32-4190-8178-71e2575c33d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440681562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2440681562
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.871790421
Short name T78
Test name
Test status
Simulation time 2987121088 ps
CPU time 43.11 seconds
Started Aug 03 04:42:19 PM PDT 24
Finished Aug 03 04:43:03 PM PDT 24
Peak memory 199972 kb
Host smart-483f83a7-41e4-4415-b8c4-6c82e08ae119
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871790421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.871790421
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3779952127
Short name T276
Test name
Test status
Simulation time 6365492846 ps
CPU time 30.36 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:42:54 PM PDT 24
Peak memory 216164 kb
Host smart-1217b362-23ed-413a-b3a6-02992d0ca2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779952127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3779952127
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1042696171
Short name T232
Test name
Test status
Simulation time 4838135812 ps
CPU time 748.68 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:54:45 PM PDT 24
Peak memory 658888 kb
Host smart-1671414e-1dae-4294-a70c-a74df4848f53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042696171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1042696171
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.238160349
Short name T392
Test name
Test status
Simulation time 352692316 ps
CPU time 18.18 seconds
Started Aug 03 04:42:18 PM PDT 24
Finished Aug 03 04:42:36 PM PDT 24
Peak memory 199828 kb
Host smart-243dfc05-f13b-4c7d-8196-9d8f76a51eda
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238160349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.238160349
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1412574322
Short name T89
Test name
Test status
Simulation time 14764195100 ps
CPU time 50.1 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:43:10 PM PDT 24
Peak memory 199972 kb
Host smart-04ea0550-4ad8-47a1-83ab-bb6e26116045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412574322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1412574322
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.690173785
Short name T301
Test name
Test status
Simulation time 341486606 ps
CPU time 6.2 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:42:14 PM PDT 24
Peak memory 199840 kb
Host smart-5f9aaf38-86a8-4df1-8c18-1b9662ff8f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690173785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.690173785
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.137461737
Short name T83
Test name
Test status
Simulation time 37874543185 ps
CPU time 482.74 seconds
Started Aug 03 04:42:26 PM PDT 24
Finished Aug 03 04:50:29 PM PDT 24
Peak memory 208180 kb
Host smart-ff990f75-b8f5-452b-a926-fb37c0c034ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137461737 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.137461737
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2777611812
Short name T473
Test name
Test status
Simulation time 4090772286 ps
CPU time 52.44 seconds
Started Aug 03 04:42:13 PM PDT 24
Finished Aug 03 04:43:06 PM PDT 24
Peak memory 199952 kb
Host smart-d39a6d40-f909-4777-a8cc-b39c560194bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777611812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2777611812
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3960118007
Short name T273
Test name
Test status
Simulation time 42049353 ps
CPU time 0.57 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:42:21 PM PDT 24
Peak memory 195948 kb
Host smart-f824877c-f2f7-480d-8159-43d470eb4068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960118007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3960118007
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1004879181
Short name T413
Test name
Test status
Simulation time 8529988161 ps
CPU time 61.22 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:43:17 PM PDT 24
Peak memory 199964 kb
Host smart-bdcce72b-1e2d-43d3-bd90-08f198482dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004879181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1004879181
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2851173252
Short name T271
Test name
Test status
Simulation time 1950384022 ps
CPU time 31.59 seconds
Started Aug 03 04:42:35 PM PDT 24
Finished Aug 03 04:43:06 PM PDT 24
Peak memory 199120 kb
Host smart-79843330-a5df-422c-bd6d-abf47a882b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851173252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2851173252
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3661525689
Short name T441
Test name
Test status
Simulation time 1421310432 ps
CPU time 165.99 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:45:03 PM PDT 24
Peak memory 368704 kb
Host smart-53e19cec-b1ac-4b7f-91b2-507f902e4e94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3661525689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3661525689
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1681123138
Short name T459
Test name
Test status
Simulation time 58774426807 ps
CPU time 184.01 seconds
Started Aug 03 04:42:18 PM PDT 24
Finished Aug 03 04:45:22 PM PDT 24
Peak memory 199948 kb
Host smart-3c1ec326-ba97-44ad-8d55-03e9bf1b5bf4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681123138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1681123138
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2557651497
Short name T195
Test name
Test status
Simulation time 3832457429 ps
CPU time 52.37 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:43:14 PM PDT 24
Peak memory 199944 kb
Host smart-4a2c98c1-68dc-4b28-8d00-f17214bdbbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557651497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2557651497
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1959158837
Short name T391
Test name
Test status
Simulation time 374671081 ps
CPU time 3.6 seconds
Started Aug 03 04:42:36 PM PDT 24
Finished Aug 03 04:42:40 PM PDT 24
Peak memory 199832 kb
Host smart-181cd1ff-5290-4a98-9549-1a8793d2045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959158837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1959158837
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2580184583
Short name T293
Test name
Test status
Simulation time 1770773225 ps
CPU time 21.23 seconds
Started Aug 03 04:42:18 PM PDT 24
Finished Aug 03 04:42:39 PM PDT 24
Peak memory 199864 kb
Host smart-dfaa65eb-8287-4846-b510-a025f60d05f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580184583 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2580184583
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3471212238
Short name T102
Test name
Test status
Simulation time 8270615803 ps
CPU time 102.65 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:43:59 PM PDT 24
Peak memory 199996 kb
Host smart-f9198d25-3e62-4be5-8638-5848e1a353d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471212238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3471212238
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.190919355
Short name T294
Test name
Test status
Simulation time 37581110 ps
CPU time 0.58 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:42:21 PM PDT 24
Peak memory 195872 kb
Host smart-59e4299a-c814-4521-9370-e0665b5de41a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190919355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.190919355
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1551597809
Short name T91
Test name
Test status
Simulation time 1578759533 ps
CPU time 22.1 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:42:37 PM PDT 24
Peak memory 199812 kb
Host smart-aeaf9b15-9a8d-483e-8aad-11f424d37395
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1551597809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1551597809
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.451800343
Short name T443
Test name
Test status
Simulation time 20296284832 ps
CPU time 54.78 seconds
Started Aug 03 04:42:18 PM PDT 24
Finished Aug 03 04:43:13 PM PDT 24
Peak memory 200248 kb
Host smart-f055815f-483e-4cda-b491-bb148d8b2922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451800343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.451800343
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.723620020
Short name T179
Test name
Test status
Simulation time 15066049053 ps
CPU time 1400.63 seconds
Started Aug 03 04:42:17 PM PDT 24
Finished Aug 03 05:05:38 PM PDT 24
Peak memory 758232 kb
Host smart-4ddf1af9-273d-4e93-b11d-85fd32ab8fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723620020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.723620020
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.654431773
Short name T142
Test name
Test status
Simulation time 1671179461 ps
CPU time 88.71 seconds
Started Aug 03 04:42:27 PM PDT 24
Finished Aug 03 04:43:56 PM PDT 24
Peak memory 199860 kb
Host smart-05cbc1a3-d2a7-424d-95ee-8715d040d56a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654431773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.654431773
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.927630349
Short name T145
Test name
Test status
Simulation time 6937770893 ps
CPU time 124.54 seconds
Started Aug 03 04:42:28 PM PDT 24
Finished Aug 03 04:44:33 PM PDT 24
Peak memory 208192 kb
Host smart-8d11e999-464a-4233-9b5e-a4f4e4964acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927630349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.927630349
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2602797868
Short name T262
Test name
Test status
Simulation time 582158396 ps
CPU time 9.25 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:42:29 PM PDT 24
Peak memory 199872 kb
Host smart-86e92b88-e174-455b-a836-6d157e812dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602797868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2602797868
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2178801410
Short name T86
Test name
Test status
Simulation time 53310561891 ps
CPU time 1527.04 seconds
Started Aug 03 04:42:24 PM PDT 24
Finished Aug 03 05:07:52 PM PDT 24
Peak memory 797420 kb
Host smart-8ed15393-a80d-47dc-abd7-5d07f56e107a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178801410 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2178801410
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2002800124
Short name T464
Test name
Test status
Simulation time 22994303305 ps
CPU time 76.77 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:43:40 PM PDT 24
Peak memory 199988 kb
Host smart-67a7ceee-cafb-45d2-80aa-f4c513e7cce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002800124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2002800124
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2335029237
Short name T358
Test name
Test status
Simulation time 32212716 ps
CPU time 0.59 seconds
Started Aug 03 04:42:18 PM PDT 24
Finished Aug 03 04:42:18 PM PDT 24
Peak memory 195884 kb
Host smart-a6b64896-9d71-436a-87e7-7f5df6c5caf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335029237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2335029237
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3809493967
Short name T108
Test name
Test status
Simulation time 91256360 ps
CPU time 5.21 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:42:28 PM PDT 24
Peak memory 199832 kb
Host smart-7cf4b617-0a1c-4739-b619-3b362a3656c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3809493967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3809493967
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1075215348
Short name T384
Test name
Test status
Simulation time 13878972982 ps
CPU time 63.53 seconds
Started Aug 03 04:42:26 PM PDT 24
Finished Aug 03 04:43:29 PM PDT 24
Peak memory 200036 kb
Host smart-10e2f358-2cb4-438f-bd30-dbf3b8e1fd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075215348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1075215348
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.520670474
Short name T463
Test name
Test status
Simulation time 3790879957 ps
CPU time 594.67 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 04:52:20 PM PDT 24
Peak memory 712212 kb
Host smart-c7c4ec09-dace-4767-80c8-d85ecdc51b88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520670474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.520670474
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.257203490
Short name T183
Test name
Test status
Simulation time 6139537382 ps
CPU time 23.99 seconds
Started Aug 03 04:42:30 PM PDT 24
Finished Aug 03 04:42:54 PM PDT 24
Peak memory 199956 kb
Host smart-c241c6cd-6095-4a51-83fd-b97a12db3fbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257203490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.257203490
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1034722211
Short name T261
Test name
Test status
Simulation time 36782029653 ps
CPU time 165.29 seconds
Started Aug 03 04:42:30 PM PDT 24
Finished Aug 03 04:45:15 PM PDT 24
Peak memory 200012 kb
Host smart-b5e460a7-e857-4b50-89e0-f1613ac3239c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034722211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1034722211
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3474335664
Short name T93
Test name
Test status
Simulation time 7835172898 ps
CPU time 8.87 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 04:42:34 PM PDT 24
Peak memory 200000 kb
Host smart-13e7b276-2ea4-4127-97d3-e35de7ffeed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474335664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3474335664
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3687700379
Short name T469
Test name
Test status
Simulation time 5410505117 ps
CPU time 39.07 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:43:00 PM PDT 24
Peak memory 199976 kb
Host smart-87e66b00-9b94-48bb-b203-ce5f09b57a03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687700379 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3687700379
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1211404588
Short name T349
Test name
Test status
Simulation time 15307456953 ps
CPU time 99.2 seconds
Started Aug 03 04:42:17 PM PDT 24
Finished Aug 03 04:43:56 PM PDT 24
Peak memory 199904 kb
Host smart-12518f7e-3d7f-4ca0-9725-f3eeab97ac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211404588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1211404588
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1411284248
Short name T332
Test name
Test status
Simulation time 13229603 ps
CPU time 0.58 seconds
Started Aug 03 04:42:34 PM PDT 24
Finished Aug 03 04:42:35 PM PDT 24
Peak memory 195848 kb
Host smart-a35d673e-6c68-4952-8eeb-3613e482745e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411284248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1411284248
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1611934720
Short name T246
Test name
Test status
Simulation time 728905771 ps
CPU time 10.61 seconds
Started Aug 03 04:42:17 PM PDT 24
Finished Aug 03 04:42:27 PM PDT 24
Peak memory 199740 kb
Host smart-a5f9a9a2-edc2-4bbd-858a-8b4efcf20daa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611934720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1611934720
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2711837239
Short name T258
Test name
Test status
Simulation time 1521193028 ps
CPU time 29.08 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 04:42:55 PM PDT 24
Peak memory 199856 kb
Host smart-a988ce79-78ee-4b95-b233-85e75366193c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711837239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2711837239
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3418017046
Short name T485
Test name
Test status
Simulation time 2139749646 ps
CPU time 370.59 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:48:27 PM PDT 24
Peak memory 669652 kb
Host smart-e1c1f77a-f408-49a3-943b-9abc05e6aa28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418017046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3418017046
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.554997671
Short name T295
Test name
Test status
Simulation time 9869887107 ps
CPU time 61.84 seconds
Started Aug 03 04:42:30 PM PDT 24
Finished Aug 03 04:43:32 PM PDT 24
Peak memory 199824 kb
Host smart-1184c4f0-3479-40c5-8d53-a0af9f04fe3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554997671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.554997671
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3995272273
Short name T372
Test name
Test status
Simulation time 9745450839 ps
CPU time 25.18 seconds
Started Aug 03 04:42:22 PM PDT 24
Finished Aug 03 04:42:47 PM PDT 24
Peak memory 200028 kb
Host smart-71fecc4a-f5d5-4c4c-a156-7112a3c2713d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995272273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3995272273
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3353186960
Short name T354
Test name
Test status
Simulation time 231912848 ps
CPU time 10.75 seconds
Started Aug 03 04:42:22 PM PDT 24
Finished Aug 03 04:42:32 PM PDT 24
Peak memory 199768 kb
Host smart-4083bd22-ff05-4bfa-8e4f-9e2a7a45fa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353186960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3353186960
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1156178968
Short name T42
Test name
Test status
Simulation time 53761988035 ps
CPU time 346.95 seconds
Started Aug 03 04:42:22 PM PDT 24
Finished Aug 03 04:48:09 PM PDT 24
Peak memory 671976 kb
Host smart-9e07e176-e8a2-41ad-87ee-db6270f36269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156178968 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1156178968
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2736998732
Short name T423
Test name
Test status
Simulation time 5746835436 ps
CPU time 51.12 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 04:43:16 PM PDT 24
Peak memory 199996 kb
Host smart-5e4c79e9-aa95-4bb3-9200-f0f0463e4905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736998732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2736998732
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3301751192
Short name T223
Test name
Test status
Simulation time 31449917 ps
CPU time 0.58 seconds
Started Aug 03 04:42:24 PM PDT 24
Finished Aug 03 04:42:24 PM PDT 24
Peak memory 194904 kb
Host smart-ae982ae9-aa2e-48d9-a6f6-22dad37d060f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301751192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3301751192
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2528246518
Short name T309
Test name
Test status
Simulation time 34127165 ps
CPU time 1.9 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:42:25 PM PDT 24
Peak memory 199872 kb
Host smart-7529c88c-1987-40bf-8e68-64575cee0d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528246518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2528246518
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.255700691
Short name T201
Test name
Test status
Simulation time 5212961429 ps
CPU time 444.84 seconds
Started Aug 03 04:42:22 PM PDT 24
Finished Aug 03 04:49:47 PM PDT 24
Peak memory 669116 kb
Host smart-92bd7e62-31b2-451b-a0a5-0c558b3d34c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255700691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.255700691
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.226198577
Short name T313
Test name
Test status
Simulation time 23556243488 ps
CPU time 203.41 seconds
Started Aug 03 04:42:35 PM PDT 24
Finished Aug 03 04:45:58 PM PDT 24
Peak memory 199988 kb
Host smart-119315f6-a964-4f49-a9c5-cbac702c9b1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226198577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.226198577
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1155772909
Short name T253
Test name
Test status
Simulation time 251591935 ps
CPU time 13.59 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:42:36 PM PDT 24
Peak memory 199780 kb
Host smart-d5eda445-7af8-4f6e-bb3f-a64be991f904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155772909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1155772909
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3179568346
Short name T317
Test name
Test status
Simulation time 2138860712 ps
CPU time 4.43 seconds
Started Aug 03 04:42:37 PM PDT 24
Finished Aug 03 04:42:42 PM PDT 24
Peak memory 199920 kb
Host smart-05e1da6d-3a1e-4293-82c1-493ed9e724af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179568346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3179568346
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1199052502
Short name T477
Test name
Test status
Simulation time 7251142575 ps
CPU time 334.67 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:47:50 PM PDT 24
Peak memory 643680 kb
Host smart-ca275769-d898-41c7-8539-66db458a338d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199052502 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1199052502
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2211584731
Short name T494
Test name
Test status
Simulation time 17857126593 ps
CPU time 77.73 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:43:39 PM PDT 24
Peak memory 199916 kb
Host smart-23a3416d-99b2-4823-9eaa-2f6f713afefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211584731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2211584731
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2892111615
Short name T502
Test name
Test status
Simulation time 192919148 ps
CPU time 0.57 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:42:17 PM PDT 24
Peak memory 195912 kb
Host smart-2e657f81-e2b4-4fe2-912c-cf4a34bc1534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892111615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2892111615
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1692275538
Short name T186
Test name
Test status
Simulation time 184875891 ps
CPU time 9.36 seconds
Started Aug 03 04:42:27 PM PDT 24
Finished Aug 03 04:42:36 PM PDT 24
Peak memory 199844 kb
Host smart-af3c3cb3-79b1-498c-a054-1d725d5c0094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692275538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1692275538
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2190151234
Short name T20
Test name
Test status
Simulation time 1772999732 ps
CPU time 46.26 seconds
Started Aug 03 04:42:24 PM PDT 24
Finished Aug 03 04:43:11 PM PDT 24
Peak memory 199860 kb
Host smart-12f12bd6-732b-4e73-b814-fa3ece328a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190151234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2190151234
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3077314630
Short name T73
Test name
Test status
Simulation time 11699974605 ps
CPU time 1223.04 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 05:02:46 PM PDT 24
Peak memory 758744 kb
Host smart-be15dc2a-7646-4bc6-a51a-b6e35b7ddbab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077314630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3077314630
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3375220452
Short name T364
Test name
Test status
Simulation time 49889716648 ps
CPU time 168.09 seconds
Started Aug 03 04:42:26 PM PDT 24
Finished Aug 03 04:45:15 PM PDT 24
Peak memory 199972 kb
Host smart-98376002-eb22-4939-a3b8-0f405fb87ee3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375220452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3375220452
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1233627402
Short name T300
Test name
Test status
Simulation time 61572297212 ps
CPU time 167.24 seconds
Started Aug 03 04:42:35 PM PDT 24
Finished Aug 03 04:45:22 PM PDT 24
Peak memory 199612 kb
Host smart-67eab52a-12e2-403f-aee4-8839e023732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233627402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1233627402
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3499716450
Short name T387
Test name
Test status
Simulation time 178350623 ps
CPU time 1.72 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:42:25 PM PDT 24
Peak memory 199796 kb
Host smart-181f7230-140e-49ad-a7f4-2dc59bc19227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499716450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3499716450
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2581185566
Short name T426
Test name
Test status
Simulation time 53026447291 ps
CPU time 1345.34 seconds
Started Aug 03 04:42:31 PM PDT 24
Finished Aug 03 05:04:57 PM PDT 24
Peak memory 697908 kb
Host smart-c06da9fe-5299-41be-9340-b2f31e7af81a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581185566 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2581185566
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.4276703636
Short name T524
Test name
Test status
Simulation time 5238112757 ps
CPU time 68.39 seconds
Started Aug 03 04:42:36 PM PDT 24
Finished Aug 03 04:43:45 PM PDT 24
Peak memory 199948 kb
Host smart-fee303c1-1013-491b-a512-13d1b9034cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276703636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.4276703636
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1821954953
Short name T16
Test name
Test status
Simulation time 14583097 ps
CPU time 0.58 seconds
Started Aug 03 04:42:17 PM PDT 24
Finished Aug 03 04:42:18 PM PDT 24
Peak memory 194908 kb
Host smart-d3178e09-9bec-4a9f-b1d8-2348ae71c21e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821954953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1821954953
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.4244839306
Short name T12
Test name
Test status
Simulation time 2180535069 ps
CPU time 62.06 seconds
Started Aug 03 04:42:24 PM PDT 24
Finished Aug 03 04:43:26 PM PDT 24
Peak memory 199912 kb
Host smart-09931da6-42a7-4cbe-9412-2e678b76e289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244839306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4244839306
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.214390929
Short name T487
Test name
Test status
Simulation time 8191619811 ps
CPU time 36.24 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 04:43:01 PM PDT 24
Peak memory 199912 kb
Host smart-b8492abf-b017-4af9-8407-e17a364d60f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214390929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.214390929
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3025276234
Short name T217
Test name
Test status
Simulation time 12188558466 ps
CPU time 515.21 seconds
Started Aug 03 04:42:16 PM PDT 24
Finished Aug 03 04:50:51 PM PDT 24
Peak memory 713156 kb
Host smart-27fecf10-6bec-4e29-ba0e-3e2bc8cd5d38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025276234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3025276234
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.4023229913
Short name T377
Test name
Test status
Simulation time 1974556447 ps
CPU time 107.68 seconds
Started Aug 03 04:42:30 PM PDT 24
Finished Aug 03 04:44:18 PM PDT 24
Peak memory 199924 kb
Host smart-04fd401b-7de2-404e-9ee7-49218c98d50f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023229913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4023229913
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.245905204
Short name T461
Test name
Test status
Simulation time 3289786010 ps
CPU time 49.48 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:43:13 PM PDT 24
Peak memory 199952 kb
Host smart-82a65273-b7b7-4ae5-8b79-902c9b3fc552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245905204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.245905204
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3747137739
Short name T416
Test name
Test status
Simulation time 1613531100 ps
CPU time 5.61 seconds
Started Aug 03 04:42:26 PM PDT 24
Finished Aug 03 04:42:32 PM PDT 24
Peak memory 199824 kb
Host smart-26f914f3-dce5-4993-bb52-f0738997779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747137739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3747137739
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3204182977
Short name T240
Test name
Test status
Simulation time 190080208779 ps
CPU time 325.95 seconds
Started Aug 03 04:42:27 PM PDT 24
Finished Aug 03 04:47:53 PM PDT 24
Peak memory 200608 kb
Host smart-29ffa313-de0f-425e-af80-26764b38cfa9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204182977 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3204182977
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1844714786
Short name T291
Test name
Test status
Simulation time 9366739357 ps
CPU time 106.08 seconds
Started Aug 03 04:42:24 PM PDT 24
Finished Aug 03 04:44:11 PM PDT 24
Peak memory 199904 kb
Host smart-552dbd6f-111d-44bb-b7c8-12673c8d026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844714786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1844714786
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3445747544
Short name T467
Test name
Test status
Simulation time 29398614 ps
CPU time 0.57 seconds
Started Aug 03 04:42:19 PM PDT 24
Finished Aug 03 04:42:20 PM PDT 24
Peak memory 195560 kb
Host smart-627880cc-586c-4f46-a830-701e8d9bd0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445747544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3445747544
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2652982436
Short name T225
Test name
Test status
Simulation time 2004914994 ps
CPU time 27.51 seconds
Started Aug 03 04:42:22 PM PDT 24
Finished Aug 03 04:42:50 PM PDT 24
Peak memory 199872 kb
Host smart-49e346e1-808e-451b-980e-058fc2841403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652982436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2652982436
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.4157630529
Short name T19
Test name
Test status
Simulation time 185690682 ps
CPU time 4.72 seconds
Started Aug 03 04:42:26 PM PDT 24
Finished Aug 03 04:42:31 PM PDT 24
Peak memory 199820 kb
Host smart-fced4188-32f4-48fc-a73b-0fd58bf6afc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157630529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.4157630529
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1574968871
Short name T7
Test name
Test status
Simulation time 5161972030 ps
CPU time 469.67 seconds
Started Aug 03 04:42:24 PM PDT 24
Finished Aug 03 04:50:14 PM PDT 24
Peak memory 663680 kb
Host smart-d7a494b7-0936-4754-afad-2a126fb69fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574968871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1574968871
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.344171305
Short name T247
Test name
Test status
Simulation time 2981168465 ps
CPU time 153.2 seconds
Started Aug 03 04:42:27 PM PDT 24
Finished Aug 03 04:45:01 PM PDT 24
Peak memory 199928 kb
Host smart-dabf3f6c-6562-4b3a-bb8b-050b8ed89a6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344171305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.344171305
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.33523222
Short name T507
Test name
Test status
Simulation time 953724798 ps
CPU time 3.79 seconds
Started Aug 03 04:42:30 PM PDT 24
Finished Aug 03 04:42:34 PM PDT 24
Peak memory 199800 kb
Host smart-1b263c4c-6797-4c01-a5ea-73677d9cebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33523222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.33523222
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3289269263
Short name T227
Test name
Test status
Simulation time 983184099 ps
CPU time 4.81 seconds
Started Aug 03 04:42:17 PM PDT 24
Finished Aug 03 04:42:22 PM PDT 24
Peak memory 199860 kb
Host smart-1bea7be9-3ed4-4675-bafc-35f202ae2f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289269263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3289269263
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1344502986
Short name T428
Test name
Test status
Simulation time 95436614081 ps
CPU time 1803.33 seconds
Started Aug 03 04:42:27 PM PDT 24
Finished Aug 03 05:12:31 PM PDT 24
Peak memory 776136 kb
Host smart-15538898-a3eb-4569-a821-dc30fd5c3352
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344502986 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1344502986
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2380857077
Short name T35
Test name
Test status
Simulation time 7539275577 ps
CPU time 91.79 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 04:43:57 PM PDT 24
Peak memory 199980 kb
Host smart-b110bb70-07d6-4876-8abb-eb860fab2f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380857077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2380857077
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3712969008
Short name T166
Test name
Test status
Simulation time 43827409 ps
CPU time 0.6 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:42:08 PM PDT 24
Peak memory 195868 kb
Host smart-654b1541-c32f-4a44-986d-9eb89047a1b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712969008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3712969008
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.4264345862
Short name T475
Test name
Test status
Simulation time 802428637 ps
CPU time 29.54 seconds
Started Aug 03 04:41:56 PM PDT 24
Finished Aug 03 04:42:25 PM PDT 24
Peak memory 199848 kb
Host smart-08e0a026-0aaf-41e6-b23e-06930cf020f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264345862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.4264345862
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.4250565664
Short name T371
Test name
Test status
Simulation time 4370661417 ps
CPU time 40.09 seconds
Started Aug 03 04:41:55 PM PDT 24
Finished Aug 03 04:42:35 PM PDT 24
Peak memory 199852 kb
Host smart-c5a57bb8-2967-4183-a52e-68b9de2f764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250565664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.4250565664
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2678738240
Short name T366
Test name
Test status
Simulation time 1136691362 ps
CPU time 155.75 seconds
Started Aug 03 04:41:58 PM PDT 24
Finished Aug 03 04:44:34 PM PDT 24
Peak memory 588544 kb
Host smart-2fa4323f-1753-42ea-b239-dc21726ad358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2678738240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2678738240
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2904457009
Short name T296
Test name
Test status
Simulation time 6927128550 ps
CPU time 120.7 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:44:06 PM PDT 24
Peak memory 199920 kb
Host smart-63e04d76-6d4d-40e1-9ec7-2ed5548dd429
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904457009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2904457009
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3909993179
Short name T506
Test name
Test status
Simulation time 2563290361 ps
CPU time 151.05 seconds
Started Aug 03 04:41:53 PM PDT 24
Finished Aug 03 04:44:25 PM PDT 24
Peak memory 199940 kb
Host smart-13a35bfe-e6ac-4373-abcc-e5f7daf801e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909993179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3909993179
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3263935017
Short name T58
Test name
Test status
Simulation time 91927844 ps
CPU time 1.01 seconds
Started Aug 03 04:42:02 PM PDT 24
Finished Aug 03 04:42:04 PM PDT 24
Peak memory 219620 kb
Host smart-c4df8c36-23e4-4bd9-b210-1b79da5d1052
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263935017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3263935017
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1390633484
Short name T144
Test name
Test status
Simulation time 701600981 ps
CPU time 8.98 seconds
Started Aug 03 04:42:04 PM PDT 24
Finished Aug 03 04:42:13 PM PDT 24
Peak memory 199784 kb
Host smart-81ffadca-5c16-4488-8595-ede484b23f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390633484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1390633484
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.925208653
Short name T24
Test name
Test status
Simulation time 1504109065 ps
CPU time 82.98 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:43:27 PM PDT 24
Peak memory 199856 kb
Host smart-948833cd-59b8-4952-9441-61f94ff7bd25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925208653 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.925208653
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1161560797
Short name T10
Test name
Test status
Simulation time 24481920710 ps
CPU time 777.62 seconds
Started Aug 03 04:41:59 PM PDT 24
Finished Aug 03 04:54:57 PM PDT 24
Peak memory 690880 kb
Host smart-5c0beb10-dd7d-42fb-8fff-01fb4b3f3c0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1161560797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1161560797
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2677392082
Short name T442
Test name
Test status
Simulation time 3890573116 ps
CPU time 50.7 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 04:42:56 PM PDT 24
Peak memory 199980 kb
Host smart-bfb00d80-a069-4ab4-bfa1-4e063eaabb33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2677392082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2677392082
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.4187898818
Short name T406
Test name
Test status
Simulation time 6187018657 ps
CPU time 97.34 seconds
Started Aug 03 04:41:54 PM PDT 24
Finished Aug 03 04:43:31 PM PDT 24
Peak memory 200160 kb
Host smart-1b81e6b4-4523-4eb2-b701-973eb2457c3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4187898818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.4187898818
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.4179399221
Short name T236
Test name
Test status
Simulation time 9037423479 ps
CPU time 76.79 seconds
Started Aug 03 04:42:00 PM PDT 24
Finished Aug 03 04:43:17 PM PDT 24
Peak memory 199972 kb
Host smart-6cf7160b-8c6f-4a81-9a55-511cb3ed280a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4179399221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.4179399221
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.629769437
Short name T379
Test name
Test status
Simulation time 8649437195 ps
CPU time 498.09 seconds
Started Aug 03 04:41:54 PM PDT 24
Finished Aug 03 04:50:13 PM PDT 24
Peak memory 199884 kb
Host smart-0ae7e852-658b-4c4c-afcf-d3e1b5435447
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=629769437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.629769437
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1251675799
Short name T210
Test name
Test status
Simulation time 811562462702 ps
CPU time 2539.82 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 05:24:28 PM PDT 24
Peak memory 216036 kb
Host smart-957aae3e-42e3-457e-ac9b-b92f01d01f72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1251675799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1251675799
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1101124289
Short name T292
Test name
Test status
Simulation time 42675609654 ps
CPU time 2339.96 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 05:21:03 PM PDT 24
Peak memory 215536 kb
Host smart-d9989087-0616-4793-a494-23e03eab35de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1101124289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1101124289
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3559835968
Short name T202
Test name
Test status
Simulation time 5063606034 ps
CPU time 58.84 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:43:02 PM PDT 24
Peak memory 199992 kb
Host smart-dacfa145-9188-4c7a-a170-c3eff9bdb228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559835968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3559835968
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2320576993
Short name T402
Test name
Test status
Simulation time 49989702 ps
CPU time 0.6 seconds
Started Aug 03 04:42:35 PM PDT 24
Finished Aug 03 04:42:36 PM PDT 24
Peak memory 196596 kb
Host smart-7784f727-e744-4fe0-99c2-9b987fcc0d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320576993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2320576993
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1821668405
Short name T60
Test name
Test status
Simulation time 405644753 ps
CPU time 5.38 seconds
Started Aug 03 04:42:27 PM PDT 24
Finished Aug 03 04:42:32 PM PDT 24
Peak memory 199812 kb
Host smart-6485008b-724d-4e84-b991-bb1f2f644f40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821668405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1821668405
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.97161832
Short name T344
Test name
Test status
Simulation time 12768074127 ps
CPU time 46.59 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:43:10 PM PDT 24
Peak memory 208368 kb
Host smart-141017ae-5200-473c-b4db-55bf978eb071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97161832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.97161832
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2880160653
Short name T363
Test name
Test status
Simulation time 1745152968 ps
CPU time 295.71 seconds
Started Aug 03 04:42:30 PM PDT 24
Finished Aug 03 04:47:26 PM PDT 24
Peak memory 459644 kb
Host smart-af410d00-e36e-4e46-9556-6516de0c8256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880160653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2880160653
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.4291068478
Short name T50
Test name
Test status
Simulation time 17339837497 ps
CPU time 100.04 seconds
Started Aug 03 04:42:28 PM PDT 24
Finished Aug 03 04:44:08 PM PDT 24
Peak memory 199920 kb
Host smart-6eafcc5c-29a2-4fb9-ae78-f2bfd5ae7dbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291068478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.4291068478
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.545772313
Short name T341
Test name
Test status
Simulation time 115541829958 ps
CPU time 210.89 seconds
Started Aug 03 04:42:38 PM PDT 24
Finished Aug 03 04:46:09 PM PDT 24
Peak memory 200000 kb
Host smart-e229cd94-7767-4257-90e0-05a0511d4368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545772313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.545772313
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1094055812
Short name T6
Test name
Test status
Simulation time 35031627 ps
CPU time 1.8 seconds
Started Aug 03 04:42:28 PM PDT 24
Finished Aug 03 04:42:30 PM PDT 24
Peak memory 199780 kb
Host smart-a17a2e26-488b-4b61-b422-e06138ff3f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094055812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1094055812
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.443002024
Short name T290
Test name
Test status
Simulation time 186720718650 ps
CPU time 1048.53 seconds
Started Aug 03 04:42:33 PM PDT 24
Finished Aug 03 05:00:02 PM PDT 24
Peak memory 449140 kb
Host smart-4a277d4e-2ee6-4145-ae44-a25615c3811a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443002024 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.443002024
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2302827406
Short name T220
Test name
Test status
Simulation time 8332214833 ps
CPU time 89.85 seconds
Started Aug 03 04:42:37 PM PDT 24
Finished Aug 03 04:44:07 PM PDT 24
Peak memory 199920 kb
Host smart-7e76ce16-8113-4f65-b59c-4395f9895e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302827406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2302827406
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3278048849
Short name T513
Test name
Test status
Simulation time 33477548 ps
CPU time 0.56 seconds
Started Aug 03 04:42:40 PM PDT 24
Finished Aug 03 04:42:41 PM PDT 24
Peak memory 194880 kb
Host smart-54432dd8-f3a9-482b-a79b-2c241c8c396f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278048849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3278048849
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.4121242
Short name T350
Test name
Test status
Simulation time 3588063376 ps
CPU time 22.05 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:42:45 PM PDT 24
Peak memory 199980 kb
Host smart-7ebcfbeb-55a9-45a5-b7d1-25a3707cb79d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.4121242
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.357356528
Short name T95
Test name
Test status
Simulation time 989941760 ps
CPU time 17.39 seconds
Started Aug 03 04:42:29 PM PDT 24
Finished Aug 03 04:42:47 PM PDT 24
Peak memory 199832 kb
Host smart-2e274e31-5280-4b37-9198-b42edb588091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357356528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.357356528
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1786068939
Short name T508
Test name
Test status
Simulation time 49023587 ps
CPU time 0.66 seconds
Started Aug 03 04:42:30 PM PDT 24
Finished Aug 03 04:42:31 PM PDT 24
Peak memory 198108 kb
Host smart-b5a30aea-e1f6-4096-9c75-14525c89e955
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1786068939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1786068939
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3335365236
Short name T39
Test name
Test status
Simulation time 129620785188 ps
CPU time 184.33 seconds
Started Aug 03 04:42:42 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 199988 kb
Host smart-a1043ab8-bc5c-48ae-b325-fe4a1d8abd87
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335365236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3335365236
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.120740983
Short name T444
Test name
Test status
Simulation time 8383021485 ps
CPU time 121.44 seconds
Started Aug 03 04:42:36 PM PDT 24
Finished Aug 03 04:44:38 PM PDT 24
Peak memory 200016 kb
Host smart-966cc460-5481-486d-8b50-ac1e295b5bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120740983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.120740983
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3071527957
Short name T143
Test name
Test status
Simulation time 143213562 ps
CPU time 6.64 seconds
Started Aug 03 04:42:37 PM PDT 24
Finished Aug 03 04:42:44 PM PDT 24
Peak memory 199872 kb
Host smart-b684c1e8-9eb2-4ce3-aaee-3a436b951982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071527957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3071527957
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1803017586
Short name T398
Test name
Test status
Simulation time 29476614579 ps
CPU time 32.02 seconds
Started Aug 03 04:42:37 PM PDT 24
Finished Aug 03 04:43:09 PM PDT 24
Peak memory 200036 kb
Host smart-2dec8b5c-b5bd-4910-93d2-364014104a23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803017586 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1803017586
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1716412628
Short name T288
Test name
Test status
Simulation time 2170432539 ps
CPU time 7.39 seconds
Started Aug 03 04:42:43 PM PDT 24
Finished Aug 03 04:42:50 PM PDT 24
Peak memory 199828 kb
Host smart-11a28b27-215b-4da8-995c-a03a06bc314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716412628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1716412628
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3806978851
Short name T164
Test name
Test status
Simulation time 24479017 ps
CPU time 0.61 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:42:24 PM PDT 24
Peak memory 194876 kb
Host smart-a28cc2d0-1f4d-4a24-9d0e-94dcf5be4c4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806978851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3806978851
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2161779962
Short name T259
Test name
Test status
Simulation time 6064444534 ps
CPU time 75.05 seconds
Started Aug 03 04:42:37 PM PDT 24
Finished Aug 03 04:43:52 PM PDT 24
Peak memory 208140 kb
Host smart-f01dd66c-0e5a-4f33-a076-911c61ad21fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161779962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2161779962
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.532051590
Short name T234
Test name
Test status
Simulation time 9130909229 ps
CPU time 61.14 seconds
Started Aug 03 04:42:48 PM PDT 24
Finished Aug 03 04:43:49 PM PDT 24
Peak memory 216544 kb
Host smart-d52458de-b138-4287-95e8-b739fc04a8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532051590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.532051590
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1999706800
Short name T154
Test name
Test status
Simulation time 704254217 ps
CPU time 118.87 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:44:22 PM PDT 24
Peak memory 568620 kb
Host smart-3007544d-1a60-4857-be83-5d9ba1ccd027
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1999706800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1999706800
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2186998651
Short name T449
Test name
Test status
Simulation time 4652890793 ps
CPU time 58.46 seconds
Started Aug 03 04:42:44 PM PDT 24
Finished Aug 03 04:43:43 PM PDT 24
Peak memory 200016 kb
Host smart-16cc9343-0435-4f25-97b7-d90a03073fa6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186998651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2186998651
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.4136245032
Short name T325
Test name
Test status
Simulation time 5800687147 ps
CPU time 82.67 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 04:43:48 PM PDT 24
Peak memory 200036 kb
Host smart-2e9fbd58-bc1f-4f5e-a3a9-a7fae92780a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136245032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.4136245032
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3962369666
Short name T497
Test name
Test status
Simulation time 915259795 ps
CPU time 15.84 seconds
Started Aug 03 04:42:28 PM PDT 24
Finished Aug 03 04:42:44 PM PDT 24
Peak memory 199864 kb
Host smart-a4b0f88d-3426-4a30-8de8-d83346293ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962369666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3962369666
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.585803135
Short name T491
Test name
Test status
Simulation time 20044515072 ps
CPU time 316.2 seconds
Started Aug 03 04:42:23 PM PDT 24
Finished Aug 03 04:47:40 PM PDT 24
Peak memory 321688 kb
Host smart-1ae9cbc9-945a-496c-b09a-e0978f633b45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585803135 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.585803135
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1948886462
Short name T327
Test name
Test status
Simulation time 12333811595 ps
CPU time 70.19 seconds
Started Aug 03 04:42:33 PM PDT 24
Finished Aug 03 04:43:43 PM PDT 24
Peak memory 199980 kb
Host smart-4d8c1b8f-16a5-452b-a881-ec6b02a16497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948886462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1948886462
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1726710522
Short name T436
Test name
Test status
Simulation time 29816181 ps
CPU time 0.59 seconds
Started Aug 03 04:42:38 PM PDT 24
Finished Aug 03 04:42:38 PM PDT 24
Peak memory 195884 kb
Host smart-9b89ad85-57e9-447b-994d-e4c4c736cbff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726710522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1726710522
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2244929833
Short name T500
Test name
Test status
Simulation time 1293750309 ps
CPU time 17.95 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 04:42:44 PM PDT 24
Peak memory 199828 kb
Host smart-80c31da4-351a-45d9-8b7e-817d6196aa3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244929833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2244929833
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1786314457
Short name T302
Test name
Test status
Simulation time 458341995 ps
CPU time 6.33 seconds
Started Aug 03 04:42:49 PM PDT 24
Finished Aug 03 04:42:55 PM PDT 24
Peak memory 199832 kb
Host smart-c4b010cd-5794-4ffb-9c3c-a96b2966df1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786314457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1786314457
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3223068125
Short name T357
Test name
Test status
Simulation time 28407553836 ps
CPU time 1242.52 seconds
Started Aug 03 04:42:25 PM PDT 24
Finished Aug 03 05:03:07 PM PDT 24
Peak memory 751500 kb
Host smart-2d1f588e-e4f3-4dc9-8265-e17b464c0b74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223068125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3223068125
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2491131123
Short name T465
Test name
Test status
Simulation time 3937435446 ps
CPU time 46.39 seconds
Started Aug 03 04:42:37 PM PDT 24
Finished Aug 03 04:43:24 PM PDT 24
Peak memory 200008 kb
Host smart-0775527b-8479-4b77-84bb-495453026e27
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491131123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2491131123
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1354736882
Short name T283
Test name
Test status
Simulation time 18110836697 ps
CPU time 140.41 seconds
Started Aug 03 04:42:39 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 199976 kb
Host smart-ed94a466-7dcc-4f56-9999-af24a75be1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354736882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1354736882
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2402490269
Short name T18
Test name
Test status
Simulation time 795098329 ps
CPU time 9.47 seconds
Started Aug 03 04:42:24 PM PDT 24
Finished Aug 03 04:42:33 PM PDT 24
Peak memory 199772 kb
Host smart-061d574b-9f39-413f-bb49-832039c4481c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402490269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2402490269
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3067181010
Short name T496
Test name
Test status
Simulation time 21542897078 ps
CPU time 2971.21 seconds
Started Aug 03 04:42:42 PM PDT 24
Finished Aug 03 05:32:14 PM PDT 24
Peak memory 814680 kb
Host smart-37490949-ed66-448d-a59f-0750da021534
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067181010 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3067181010
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2803036957
Short name T503
Test name
Test status
Simulation time 5954724491 ps
CPU time 52.77 seconds
Started Aug 03 04:42:38 PM PDT 24
Finished Aug 03 04:43:31 PM PDT 24
Peak memory 199972 kb
Host smart-388b3645-1e49-4181-82bb-205bf2d5f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803036957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2803036957
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3348153266
Short name T52
Test name
Test status
Simulation time 60934044 ps
CPU time 0.65 seconds
Started Aug 03 04:42:43 PM PDT 24
Finished Aug 03 04:42:44 PM PDT 24
Peak memory 195840 kb
Host smart-52f9d9d0-743e-4a46-86a9-c09cdff47bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348153266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3348153266
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.519424850
Short name T254
Test name
Test status
Simulation time 3690199476 ps
CPU time 50.33 seconds
Started Aug 03 04:42:41 PM PDT 24
Finished Aug 03 04:43:32 PM PDT 24
Peak memory 199960 kb
Host smart-ecbd6bc4-beec-4cd6-a823-e1f98e665738
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=519424850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.519424850
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2458599722
Short name T409
Test name
Test status
Simulation time 9312623805 ps
CPU time 57.17 seconds
Started Aug 03 04:42:31 PM PDT 24
Finished Aug 03 04:43:28 PM PDT 24
Peak memory 199976 kb
Host smart-61723e92-991b-40c0-aa84-c9c340c01720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458599722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2458599722
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.39920985
Short name T263
Test name
Test status
Simulation time 4785369684 ps
CPU time 859.46 seconds
Started Aug 03 04:42:46 PM PDT 24
Finished Aug 03 04:57:06 PM PDT 24
Peak memory 691444 kb
Host smart-35690479-bd9d-4802-b72b-97956e641493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39920985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.39920985
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3408585342
Short name T275
Test name
Test status
Simulation time 3199158560 ps
CPU time 176.35 seconds
Started Aug 03 04:42:46 PM PDT 24
Finished Aug 03 04:45:43 PM PDT 24
Peak memory 199952 kb
Host smart-be02c5ca-0f04-41ea-9109-806f235a3e2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408585342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3408585342
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3886382834
Short name T397
Test name
Test status
Simulation time 18810851552 ps
CPU time 109.78 seconds
Started Aug 03 04:42:42 PM PDT 24
Finished Aug 03 04:44:32 PM PDT 24
Peak memory 199920 kb
Host smart-552c33e1-dea6-4b95-9df0-50532a5f79b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886382834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3886382834
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2615091140
Short name T316
Test name
Test status
Simulation time 122119435 ps
CPU time 5.85 seconds
Started Aug 03 04:42:37 PM PDT 24
Finished Aug 03 04:42:43 PM PDT 24
Peak memory 199812 kb
Host smart-a93a2d13-ef63-4f42-aa5f-10e6aa17bad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615091140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2615091140
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.358498093
Short name T284
Test name
Test status
Simulation time 76690061325 ps
CPU time 336.64 seconds
Started Aug 03 04:42:34 PM PDT 24
Finished Aug 03 04:48:11 PM PDT 24
Peak memory 216376 kb
Host smart-2f8331f0-0153-4809-926b-7a2d83822708
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358498093 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.358498093
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3978243997
Short name T419
Test name
Test status
Simulation time 3958317957 ps
CPU time 37.53 seconds
Started Aug 03 04:42:41 PM PDT 24
Finished Aug 03 04:43:18 PM PDT 24
Peak memory 199868 kb
Host smart-ac0c3db2-4683-4099-bb35-fc18693800f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978243997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3978243997
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1382432083
Short name T243
Test name
Test status
Simulation time 27940322 ps
CPU time 0.58 seconds
Started Aug 03 04:42:38 PM PDT 24
Finished Aug 03 04:42:38 PM PDT 24
Peak memory 196608 kb
Host smart-a32fa289-ba28-4dd6-859d-67dccda70a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382432083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1382432083
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2724569889
Short name T504
Test name
Test status
Simulation time 871370528 ps
CPU time 46.58 seconds
Started Aug 03 04:42:31 PM PDT 24
Finished Aug 03 04:43:18 PM PDT 24
Peak memory 199828 kb
Host smart-9626474c-e55e-42ec-a467-a15ed4084b7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724569889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2724569889
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.356867735
Short name T352
Test name
Test status
Simulation time 7287509268 ps
CPU time 18.44 seconds
Started Aug 03 04:42:41 PM PDT 24
Finished Aug 03 04:42:59 PM PDT 24
Peak memory 199944 kb
Host smart-c57cfe4d-c2e4-451b-8b7b-3acbd85963ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356867735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.356867735
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.4281494643
Short name T38
Test name
Test status
Simulation time 1343697273 ps
CPU time 112.19 seconds
Started Aug 03 04:42:31 PM PDT 24
Finished Aug 03 04:44:23 PM PDT 24
Peak memory 558168 kb
Host smart-0b13dfd9-c7e1-45bf-aa4c-093adb9c6d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4281494643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.4281494643
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1300975868
Short name T103
Test name
Test status
Simulation time 274786282 ps
CPU time 15.1 seconds
Started Aug 03 04:42:42 PM PDT 24
Finished Aug 03 04:42:57 PM PDT 24
Peak memory 199760 kb
Host smart-b65ba20d-5546-4406-98ac-a7766a015be8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300975868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1300975868
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.510951280
Short name T94
Test name
Test status
Simulation time 11495941301 ps
CPU time 163.71 seconds
Started Aug 03 04:42:41 PM PDT 24
Finished Aug 03 04:45:25 PM PDT 24
Peak memory 199980 kb
Host smart-9a200723-0b68-4e1f-9881-5f855b29c8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510951280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.510951280
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3163422552
Short name T401
Test name
Test status
Simulation time 82023162 ps
CPU time 1.73 seconds
Started Aug 03 04:42:35 PM PDT 24
Finished Aug 03 04:42:37 PM PDT 24
Peak memory 199844 kb
Host smart-85876a3b-cf40-4286-a7a1-60cb7609df16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163422552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3163422552
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1681210396
Short name T330
Test name
Test status
Simulation time 194270782172 ps
CPU time 574.27 seconds
Started Aug 03 04:42:28 PM PDT 24
Finished Aug 03 04:52:03 PM PDT 24
Peak memory 199920 kb
Host smart-f750e17a-14b2-4af0-9a76-bb39d132379a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681210396 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1681210396
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2652675144
Short name T493
Test name
Test status
Simulation time 14368848047 ps
CPU time 46.97 seconds
Started Aug 03 04:42:40 PM PDT 24
Finished Aug 03 04:43:27 PM PDT 24
Peak memory 199916 kb
Host smart-96425d8c-62a7-4a65-b7c7-f1350e5fb850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652675144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2652675144
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.952008923
Short name T474
Test name
Test status
Simulation time 61887848 ps
CPU time 0.55 seconds
Started Aug 03 04:42:33 PM PDT 24
Finished Aug 03 04:42:33 PM PDT 24
Peak memory 194848 kb
Host smart-d4a8d312-6ad0-46ba-bb6a-680624286316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952008923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.952008923
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3844429143
Short name T231
Test name
Test status
Simulation time 1194305788 ps
CPU time 75.37 seconds
Started Aug 03 04:42:37 PM PDT 24
Finished Aug 03 04:43:52 PM PDT 24
Peak memory 199816 kb
Host smart-26da3b81-93c8-4eec-9983-e003b51e99bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3844429143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3844429143
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1161692399
Short name T17
Test name
Test status
Simulation time 1117786048 ps
CPU time 14.98 seconds
Started Aug 03 04:42:44 PM PDT 24
Finished Aug 03 04:42:59 PM PDT 24
Peak memory 199824 kb
Host smart-98a4788e-ad06-4567-92b4-09a9ea56fcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161692399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1161692399
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.4242231743
Short name T167
Test name
Test status
Simulation time 28099357574 ps
CPU time 1288.46 seconds
Started Aug 03 04:42:38 PM PDT 24
Finished Aug 03 05:04:06 PM PDT 24
Peak memory 744808 kb
Host smart-f8b8b307-9b79-4ba5-bfb8-d586444f456e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4242231743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.4242231743
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2221923791
Short name T163
Test name
Test status
Simulation time 23166398518 ps
CPU time 207.71 seconds
Started Aug 03 04:42:40 PM PDT 24
Finished Aug 03 04:46:08 PM PDT 24
Peak memory 199944 kb
Host smart-9c3c01f2-adb3-4390-9308-2695028515b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221923791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2221923791
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1467124258
Short name T529
Test name
Test status
Simulation time 7918851214 ps
CPU time 104.89 seconds
Started Aug 03 04:42:44 PM PDT 24
Finished Aug 03 04:44:29 PM PDT 24
Peak memory 199948 kb
Host smart-6a7ab569-c55e-4247-87db-6713af5358d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467124258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1467124258
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.918818495
Short name T88
Test name
Test status
Simulation time 1224215362 ps
CPU time 8.25 seconds
Started Aug 03 04:42:41 PM PDT 24
Finished Aug 03 04:42:50 PM PDT 24
Peak memory 199724 kb
Host smart-2ef1ea23-600c-4ea6-b241-8db583a971ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918818495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.918818495
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1493958830
Short name T390
Test name
Test status
Simulation time 99922160974 ps
CPU time 302.05 seconds
Started Aug 03 04:42:30 PM PDT 24
Finished Aug 03 04:47:32 PM PDT 24
Peak memory 199972 kb
Host smart-1e58cecd-828b-47b1-b5db-0aee5eda275f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493958830 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1493958830
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3411980137
Short name T165
Test name
Test status
Simulation time 437618494 ps
CPU time 13.08 seconds
Started Aug 03 04:42:36 PM PDT 24
Finished Aug 03 04:42:49 PM PDT 24
Peak memory 199808 kb
Host smart-703dc8a7-6102-4030-86f7-1594d2f1399e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411980137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3411980137
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3974683260
Short name T174
Test name
Test status
Simulation time 14020778 ps
CPU time 0.58 seconds
Started Aug 03 04:42:46 PM PDT 24
Finished Aug 03 04:42:46 PM PDT 24
Peak memory 196536 kb
Host smart-5008aaa3-76eb-4de4-8ca9-5e2618771249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974683260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3974683260
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2125781241
Short name T462
Test name
Test status
Simulation time 4565728410 ps
CPU time 49.62 seconds
Started Aug 03 04:42:33 PM PDT 24
Finished Aug 03 04:43:22 PM PDT 24
Peak memory 216084 kb
Host smart-8a60aba9-9044-4862-b590-7b176bab8d22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2125781241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2125781241
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1372064117
Short name T175
Test name
Test status
Simulation time 7637240552 ps
CPU time 11.96 seconds
Started Aug 03 04:42:51 PM PDT 24
Finished Aug 03 04:43:03 PM PDT 24
Peak memory 199952 kb
Host smart-55856561-9949-4d90-90cc-89b1e461eb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372064117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1372064117
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3862471095
Short name T172
Test name
Test status
Simulation time 327186021 ps
CPU time 2.96 seconds
Started Aug 03 04:42:46 PM PDT 24
Finished Aug 03 04:42:49 PM PDT 24
Peak memory 216212 kb
Host smart-942e7a58-8917-4e87-abf6-b0b3e9009621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3862471095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3862471095
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.845477548
Short name T425
Test name
Test status
Simulation time 4274456433 ps
CPU time 27.85 seconds
Started Aug 03 04:42:46 PM PDT 24
Finished Aug 03 04:43:14 PM PDT 24
Peak memory 200016 kb
Host smart-9f1c2ed4-5229-471e-84c2-fe25ff2ceb23
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845477548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.845477548
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3335803596
Short name T527
Test name
Test status
Simulation time 4774360075 ps
CPU time 148.59 seconds
Started Aug 03 04:42:37 PM PDT 24
Finished Aug 03 04:45:06 PM PDT 24
Peak memory 199880 kb
Host smart-ecc1c02e-9624-4761-8caa-6ea6814f9923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335803596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3335803596
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.517911624
Short name T62
Test name
Test status
Simulation time 74838387 ps
CPU time 3.24 seconds
Started Aug 03 04:42:43 PM PDT 24
Finished Aug 03 04:42:46 PM PDT 24
Peak memory 199792 kb
Host smart-b200153a-e137-4e4c-8ad1-e44508cc2cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517911624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.517911624
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2225162998
Short name T181
Test name
Test status
Simulation time 139933633465 ps
CPU time 3452.95 seconds
Started Aug 03 04:42:47 PM PDT 24
Finished Aug 03 05:40:21 PM PDT 24
Peak memory 805564 kb
Host smart-352711c8-bdb3-4f9f-9698-0a9b4caf22f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225162998 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2225162998
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2529626963
Short name T307
Test name
Test status
Simulation time 4841598075 ps
CPU time 31.9 seconds
Started Aug 03 04:42:41 PM PDT 24
Finished Aug 03 04:43:13 PM PDT 24
Peak memory 199964 kb
Host smart-5149ab7e-086e-4873-987e-133e894d87dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529626963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2529626963
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1760860152
Short name T211
Test name
Test status
Simulation time 13576249 ps
CPU time 0.57 seconds
Started Aug 03 04:42:42 PM PDT 24
Finished Aug 03 04:42:42 PM PDT 24
Peak memory 194864 kb
Host smart-6fc3c11a-0da4-4add-88ef-de642932b9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760860152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1760860152
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.216338007
Short name T104
Test name
Test status
Simulation time 1489624994 ps
CPU time 80.34 seconds
Started Aug 03 04:42:51 PM PDT 24
Finished Aug 03 04:44:11 PM PDT 24
Peak memory 199796 kb
Host smart-507586fc-c293-4ce5-adac-a67fe701ee9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216338007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.216338007
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.548744818
Short name T399
Test name
Test status
Simulation time 836344208 ps
CPU time 23.31 seconds
Started Aug 03 04:42:44 PM PDT 24
Finished Aug 03 04:43:07 PM PDT 24
Peak memory 199784 kb
Host smart-0dcfca54-575d-4e1e-82e8-0f6c1a51fa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548744818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.548744818
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4223618385
Short name T433
Test name
Test status
Simulation time 2211355972 ps
CPU time 284.32 seconds
Started Aug 03 04:42:50 PM PDT 24
Finished Aug 03 04:47:35 PM PDT 24
Peak memory 597508 kb
Host smart-d86772de-840a-4dd4-bc48-dba51a0b8f15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4223618385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4223618385
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1932507658
Short name T345
Test name
Test status
Simulation time 12863667156 ps
CPU time 176.58 seconds
Started Aug 03 04:42:50 PM PDT 24
Finished Aug 03 04:45:47 PM PDT 24
Peak memory 199940 kb
Host smart-70f297ab-da70-4e9e-8a22-d9ed13b18255
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932507658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1932507658
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1991178967
Short name T265
Test name
Test status
Simulation time 45452621245 ps
CPU time 155.43 seconds
Started Aug 03 04:42:43 PM PDT 24
Finished Aug 03 04:45:18 PM PDT 24
Peak memory 199908 kb
Host smart-04c38a25-6372-431d-99fa-d889466df38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991178967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1991178967
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3707796699
Short name T59
Test name
Test status
Simulation time 496041374 ps
CPU time 11.27 seconds
Started Aug 03 04:42:48 PM PDT 24
Finished Aug 03 04:43:00 PM PDT 24
Peak memory 199916 kb
Host smart-f1e845ea-a4cd-4ace-86ba-688b2ade3ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707796699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3707796699
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1700960305
Short name T279
Test name
Test status
Simulation time 1444760826 ps
CPU time 19.22 seconds
Started Aug 03 04:42:50 PM PDT 24
Finished Aug 03 04:43:09 PM PDT 24
Peak memory 199756 kb
Host smart-5c3646e3-f305-454a-887e-9a9d63473dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700960305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1700960305
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2979538346
Short name T389
Test name
Test status
Simulation time 11466174 ps
CPU time 0.58 seconds
Started Aug 03 04:42:49 PM PDT 24
Finished Aug 03 04:42:50 PM PDT 24
Peak memory 195924 kb
Host smart-c95651ee-e276-42c5-88ff-d992c67e432e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979538346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2979538346
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2107649662
Short name T13
Test name
Test status
Simulation time 4880996151 ps
CPU time 66.06 seconds
Started Aug 03 04:42:46 PM PDT 24
Finished Aug 03 04:43:52 PM PDT 24
Peak memory 200000 kb
Host smart-15100ec6-9b2b-4a3c-9526-27e18c9221c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2107649662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2107649662
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.317328917
Short name T480
Test name
Test status
Simulation time 4043020306 ps
CPU time 36.26 seconds
Started Aug 03 04:42:47 PM PDT 24
Finished Aug 03 04:43:24 PM PDT 24
Peak memory 199880 kb
Host smart-42bd7eab-0c3c-4372-b3c0-7c948e536a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317328917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.317328917
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.4292379003
Short name T200
Test name
Test status
Simulation time 20444432775 ps
CPU time 857.85 seconds
Started Aug 03 04:42:52 PM PDT 24
Finished Aug 03 04:57:10 PM PDT 24
Peak memory 732020 kb
Host smart-791438f9-d1b8-400b-bffb-15d4db2d9399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292379003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.4292379003
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1658294109
Short name T335
Test name
Test status
Simulation time 38934089732 ps
CPU time 118.37 seconds
Started Aug 03 04:42:39 PM PDT 24
Finished Aug 03 04:44:38 PM PDT 24
Peak memory 199988 kb
Host smart-f82c0167-e2c1-4c1d-a094-ceb976ad3bb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658294109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1658294109
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.17213318
Short name T414
Test name
Test status
Simulation time 4299099373 ps
CPU time 59.52 seconds
Started Aug 03 04:42:49 PM PDT 24
Finished Aug 03 04:43:49 PM PDT 24
Peak memory 199972 kb
Host smart-4291e180-fe0a-4031-88df-bf46e4fe7847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17213318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.17213318
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2093379633
Short name T380
Test name
Test status
Simulation time 2011468013 ps
CPU time 6.67 seconds
Started Aug 03 04:42:49 PM PDT 24
Finished Aug 03 04:42:56 PM PDT 24
Peak memory 199808 kb
Host smart-b8ca2054-cdd2-4b3a-9867-ac87a86b52b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093379633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2093379633
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.178569602
Short name T331
Test name
Test status
Simulation time 7026881276 ps
CPU time 91.46 seconds
Started Aug 03 04:42:48 PM PDT 24
Finished Aug 03 04:44:19 PM PDT 24
Peak memory 199940 kb
Host smart-d4c374cb-2383-4350-bceb-8e492885661d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178569602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.178569602
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3616829813
Short name T512
Test name
Test status
Simulation time 22164664 ps
CPU time 0.61 seconds
Started Aug 03 04:42:11 PM PDT 24
Finished Aug 03 04:42:12 PM PDT 24
Peak memory 196616 kb
Host smart-ca732525-9727-4132-b0b1-220f815dd810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616829813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3616829813
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2219189781
Short name T218
Test name
Test status
Simulation time 1133148499 ps
CPU time 66.54 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:43:13 PM PDT 24
Peak memory 199756 kb
Host smart-dfa71666-a328-4d1e-a273-ac518991a93c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219189781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2219189781
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3103548083
Short name T212
Test name
Test status
Simulation time 2075468054 ps
CPU time 38.47 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:42:42 PM PDT 24
Peak memory 199836 kb
Host smart-944578b7-6d39-4236-9654-c1291ad24369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103548083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3103548083
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1317334235
Short name T310
Test name
Test status
Simulation time 1826739919 ps
CPU time 343.73 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:47:52 PM PDT 24
Peak memory 647476 kb
Host smart-e0f3f774-3813-4eb7-9975-1c9c0fca5ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317334235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1317334235
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2343490600
Short name T430
Test name
Test status
Simulation time 3019310635 ps
CPU time 50.92 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:42:54 PM PDT 24
Peak memory 199928 kb
Host smart-9e6d6e6f-e1cc-46ca-9dca-4e08053fbeaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343490600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2343490600
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2339091818
Short name T173
Test name
Test status
Simulation time 1785487343 ps
CPU time 99.89 seconds
Started Aug 03 04:42:04 PM PDT 24
Finished Aug 03 04:43:44 PM PDT 24
Peak memory 199820 kb
Host smart-e490910c-f746-4fc8-9f44-efe4e915a9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339091818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2339091818
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4191496388
Short name T57
Test name
Test status
Simulation time 77410961 ps
CPU time 0.81 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:42:07 PM PDT 24
Peak memory 218220 kb
Host smart-c667a671-1c72-4695-839a-1d821e9a05cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191496388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4191496388
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.532555191
Short name T303
Test name
Test status
Simulation time 101369948 ps
CPU time 4.73 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:42:14 PM PDT 24
Peak memory 199824 kb
Host smart-fb96df85-854b-47f8-b583-882727a0c76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532555191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.532555191
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1233531071
Short name T152
Test name
Test status
Simulation time 80977615671 ps
CPU time 1615.8 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 05:09:04 PM PDT 24
Peak memory 776384 kb
Host smart-3a094701-f4ba-4eb4-89d0-a36202f9a1ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233531071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1233531071
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3952654209
Short name T69
Test name
Test status
Simulation time 280530630675 ps
CPU time 1243.57 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 05:02:49 PM PDT 24
Peak memory 767536 kb
Host smart-fdc064a5-2b7a-432d-a4b2-331a671e5fb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3952654209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3952654209
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1822890959
Short name T458
Test name
Test status
Simulation time 4896280915 ps
CPU time 70.24 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:43:14 PM PDT 24
Peak memory 200000 kb
Host smart-83cca389-4175-422f-94fe-f41cd3e2caa3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1822890959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1822890959
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.670502899
Short name T184
Test name
Test status
Simulation time 2264386861 ps
CPU time 89.38 seconds
Started Aug 03 04:41:58 PM PDT 24
Finished Aug 03 04:43:27 PM PDT 24
Peak memory 199896 kb
Host smart-8efc3f89-4b50-4f97-9826-f949a1b71225
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=670502899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.670502899
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1152531707
Short name T450
Test name
Test status
Simulation time 16692168142 ps
CPU time 129.88 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:44:16 PM PDT 24
Peak memory 199868 kb
Host smart-73203adb-7a72-4c2e-b967-cd2b39165033
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1152531707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1152531707
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1418498063
Short name T251
Test name
Test status
Simulation time 75215796594 ps
CPU time 647.44 seconds
Started Aug 03 04:42:04 PM PDT 24
Finished Aug 03 04:52:51 PM PDT 24
Peak memory 199964 kb
Host smart-f57af183-84dc-46d2-be00-370e0d3b2982
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1418498063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1418498063
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1068829238
Short name T337
Test name
Test status
Simulation time 165237423569 ps
CPU time 2213.32 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 05:19:02 PM PDT 24
Peak memory 216348 kb
Host smart-c723d022-9852-483b-869f-e7fa147b6bcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1068829238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1068829238
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1146710374
Short name T323
Test name
Test status
Simulation time 176805879183 ps
CPU time 2375.36 seconds
Started Aug 03 04:42:11 PM PDT 24
Finished Aug 03 05:21:47 PM PDT 24
Peak memory 216028 kb
Host smart-137a01cc-b29f-4f6e-a513-fbd169e8b9d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1146710374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1146710374
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.607092122
Short name T523
Test name
Test status
Simulation time 937889962 ps
CPU time 43.16 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:42:50 PM PDT 24
Peak memory 199832 kb
Host smart-f19e155a-fe24-47d5-aa03-1431626997c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607092122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.607092122
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3581799826
Short name T226
Test name
Test status
Simulation time 15586281 ps
CPU time 0.61 seconds
Started Aug 03 04:42:43 PM PDT 24
Finished Aug 03 04:42:43 PM PDT 24
Peak memory 195884 kb
Host smart-ba04d12d-8c5c-4648-843a-efad6d2ab378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581799826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3581799826
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.289467370
Short name T209
Test name
Test status
Simulation time 6649569143 ps
CPU time 87.56 seconds
Started Aug 03 04:42:44 PM PDT 24
Finished Aug 03 04:44:12 PM PDT 24
Peak memory 208164 kb
Host smart-e24509dc-9c33-4e60-bcf3-7d335a131a04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289467370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.289467370
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1727066383
Short name T47
Test name
Test status
Simulation time 2067849125 ps
CPU time 51.32 seconds
Started Aug 03 04:42:45 PM PDT 24
Finished Aug 03 04:43:36 PM PDT 24
Peak memory 199820 kb
Host smart-5a9c656e-aa0a-4db0-9d39-41055dbe395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727066383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1727066383
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1539389601
Short name T277
Test name
Test status
Simulation time 13640702386 ps
CPU time 1366.62 seconds
Started Aug 03 04:42:36 PM PDT 24
Finished Aug 03 05:05:23 PM PDT 24
Peak memory 766956 kb
Host smart-75babd64-227e-4a53-996a-909fb24568e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539389601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1539389601
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.894529100
Short name T490
Test name
Test status
Simulation time 1383043852 ps
CPU time 76.63 seconds
Started Aug 03 04:42:44 PM PDT 24
Finished Aug 03 04:44:00 PM PDT 24
Peak memory 199820 kb
Host smart-16948468-4e89-4610-88f8-2a70a63bf44b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894529100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.894529100
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1590514160
Short name T171
Test name
Test status
Simulation time 895563441 ps
CPU time 52.89 seconds
Started Aug 03 04:42:48 PM PDT 24
Finished Aug 03 04:43:41 PM PDT 24
Peak memory 199856 kb
Host smart-52342d97-3525-4dcf-9aa4-96715f7e2629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590514160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1590514160
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2573539221
Short name T208
Test name
Test status
Simulation time 1909545630 ps
CPU time 8.21 seconds
Started Aug 03 04:42:56 PM PDT 24
Finished Aug 03 04:43:04 PM PDT 24
Peak memory 199820 kb
Host smart-6f705c7f-7785-4ad6-add9-dd735a93c991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573539221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2573539221
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3514023855
Short name T99
Test name
Test status
Simulation time 132483544586 ps
CPU time 427.12 seconds
Started Aug 03 04:42:46 PM PDT 24
Finished Aug 03 04:49:53 PM PDT 24
Peak memory 216368 kb
Host smart-2ec360dd-c384-480a-9cb1-75c0a9e6dfa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514023855 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3514023855
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2259129
Short name T216
Test name
Test status
Simulation time 1067801355 ps
CPU time 19.62 seconds
Started Aug 03 04:42:51 PM PDT 24
Finished Aug 03 04:43:10 PM PDT 24
Peak memory 199812 kb
Host smart-0e3606a4-1da2-42d0-88af-1925b340f92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2259129
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.311943200
Short name T336
Test name
Test status
Simulation time 38046559 ps
CPU time 0.59 seconds
Started Aug 03 04:42:42 PM PDT 24
Finished Aug 03 04:42:43 PM PDT 24
Peak memory 195904 kb
Host smart-dbf89ef8-72b2-4928-880c-0c3c2f2aaace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311943200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.311943200
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3800243837
Short name T448
Test name
Test status
Simulation time 1747611327 ps
CPU time 49.25 seconds
Started Aug 03 04:42:38 PM PDT 24
Finished Aug 03 04:43:28 PM PDT 24
Peak memory 199852 kb
Host smart-a1e89afd-fa67-4e00-8c81-63cff29fc381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800243837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3800243837
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2770457257
Short name T498
Test name
Test status
Simulation time 2742568939 ps
CPU time 71.83 seconds
Started Aug 03 04:42:47 PM PDT 24
Finished Aug 03 04:43:59 PM PDT 24
Peak memory 199904 kb
Host smart-0b00e274-1a1c-4d9d-863a-67ed957318d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770457257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2770457257
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2533616130
Short name T41
Test name
Test status
Simulation time 2387884897 ps
CPU time 63.49 seconds
Started Aug 03 04:42:46 PM PDT 24
Finished Aug 03 04:43:49 PM PDT 24
Peak memory 315372 kb
Host smart-f13bac19-687b-4d86-a635-6be07e4ce841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533616130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2533616130
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1796202091
Short name T252
Test name
Test status
Simulation time 5472574469 ps
CPU time 95.56 seconds
Started Aug 03 04:42:43 PM PDT 24
Finished Aug 03 04:44:18 PM PDT 24
Peak memory 199968 kb
Host smart-d8199217-fdeb-48dc-8f0f-337fab3cfd95
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796202091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1796202091
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1282989750
Short name T160
Test name
Test status
Simulation time 5183781148 ps
CPU time 80.1 seconds
Started Aug 03 04:42:44 PM PDT 24
Finished Aug 03 04:44:04 PM PDT 24
Peak memory 199920 kb
Host smart-093d5e15-cc48-4f83-956a-c1cfbf40b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282989750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1282989750
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.59525029
Short name T180
Test name
Test status
Simulation time 366749039 ps
CPU time 15.62 seconds
Started Aug 03 04:42:37 PM PDT 24
Finished Aug 03 04:42:52 PM PDT 24
Peak memory 199828 kb
Host smart-ce2b562e-5079-4e61-b175-6a03df2ae05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59525029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.59525029
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.4120517980
Short name T82
Test name
Test status
Simulation time 68549349153 ps
CPU time 1213.13 seconds
Started Aug 03 04:42:51 PM PDT 24
Finished Aug 03 05:03:04 PM PDT 24
Peak memory 640520 kb
Host smart-4c2572a9-099f-4037-8617-71f3990414a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120517980 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.4120517980
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2572919170
Short name T205
Test name
Test status
Simulation time 7126364456 ps
CPU time 96.23 seconds
Started Aug 03 04:42:43 PM PDT 24
Finished Aug 03 04:44:20 PM PDT 24
Peak memory 200024 kb
Host smart-7808a8f8-298f-41df-869f-c449e10e7961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572919170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2572919170
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3018387815
Short name T360
Test name
Test status
Simulation time 32031444 ps
CPU time 0.56 seconds
Started Aug 03 04:42:56 PM PDT 24
Finished Aug 03 04:42:56 PM PDT 24
Peak memory 194844 kb
Host smart-0da197a3-a11d-4202-8f58-75cb5b85be06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018387815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3018387815
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3722891995
Short name T274
Test name
Test status
Simulation time 1560037298 ps
CPU time 23.13 seconds
Started Aug 03 04:42:48 PM PDT 24
Finished Aug 03 04:43:11 PM PDT 24
Peak memory 199840 kb
Host smart-ad56bd03-f1d4-45c2-8cc4-17bf57a7ca46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722891995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3722891995
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1400777418
Short name T306
Test name
Test status
Simulation time 15319837234 ps
CPU time 51.01 seconds
Started Aug 03 04:42:47 PM PDT 24
Finished Aug 03 04:43:38 PM PDT 24
Peak memory 199996 kb
Host smart-3f840b50-ae1c-4107-8ba8-8e2d41363fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400777418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1400777418
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1179674805
Short name T368
Test name
Test status
Simulation time 11719399509 ps
CPU time 595.16 seconds
Started Aug 03 04:42:54 PM PDT 24
Finished Aug 03 04:52:50 PM PDT 24
Peak memory 692608 kb
Host smart-a3c2ac33-2f9d-4697-9134-c792a50a363c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179674805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1179674805
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3324878083
Short name T190
Test name
Test status
Simulation time 1627643438 ps
CPU time 42.66 seconds
Started Aug 03 04:42:56 PM PDT 24
Finished Aug 03 04:43:39 PM PDT 24
Peak memory 199820 kb
Host smart-916f4d82-235b-4200-a5a6-21a77c1fdbed
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324878083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3324878083
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2608675581
Short name T206
Test name
Test status
Simulation time 22937160307 ps
CPU time 148.63 seconds
Started Aug 03 04:42:51 PM PDT 24
Finished Aug 03 04:45:20 PM PDT 24
Peak memory 199980 kb
Host smart-1d887d91-17ad-4fd7-a6bf-e6bed28d0419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608675581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2608675581
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.4025440532
Short name T378
Test name
Test status
Simulation time 2268129570 ps
CPU time 7.11 seconds
Started Aug 03 04:42:48 PM PDT 24
Finished Aug 03 04:42:55 PM PDT 24
Peak memory 199924 kb
Host smart-eab9320e-c658-4f7a-827f-15f8465c7ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025440532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4025440532
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1732497084
Short name T495
Test name
Test status
Simulation time 117000111302 ps
CPU time 730.31 seconds
Started Aug 03 04:42:56 PM PDT 24
Finished Aug 03 04:55:06 PM PDT 24
Peak memory 216320 kb
Host smart-da40c680-4326-4ec3-bfdd-7917ed7496f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732497084 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1732497084
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.586414543
Short name T98
Test name
Test status
Simulation time 12525156696 ps
CPU time 53.5 seconds
Started Aug 03 04:42:53 PM PDT 24
Finished Aug 03 04:43:46 PM PDT 24
Peak memory 199944 kb
Host smart-66c5892e-ae3b-4dc7-b656-9109172fdeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586414543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.586414543
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3157173143
Short name T421
Test name
Test status
Simulation time 25473864 ps
CPU time 0.63 seconds
Started Aug 03 04:42:56 PM PDT 24
Finished Aug 03 04:42:57 PM PDT 24
Peak memory 195924 kb
Host smart-e5436aed-c164-4c0a-97d9-e84326028dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157173143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3157173143
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1638769694
Short name T23
Test name
Test status
Simulation time 7198252864 ps
CPU time 78.75 seconds
Started Aug 03 04:42:47 PM PDT 24
Finished Aug 03 04:44:06 PM PDT 24
Peak memory 216304 kb
Host smart-8464ba3f-3575-45ea-9eb0-4771cdb536ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638769694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1638769694
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.4121552460
Short name T376
Test name
Test status
Simulation time 14765578773 ps
CPU time 51.37 seconds
Started Aug 03 04:42:51 PM PDT 24
Finished Aug 03 04:43:43 PM PDT 24
Peak memory 199996 kb
Host smart-329a9791-2b60-46ef-9a2b-43fae479b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121552460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4121552460
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1765590374
Short name T386
Test name
Test status
Simulation time 3418682190 ps
CPU time 536.32 seconds
Started Aug 03 04:42:55 PM PDT 24
Finished Aug 03 04:51:51 PM PDT 24
Peak memory 624292 kb
Host smart-52722247-51ea-403a-8ece-74f0823d6a33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1765590374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1765590374
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3155614492
Short name T478
Test name
Test status
Simulation time 3418604238 ps
CPU time 55.48 seconds
Started Aug 03 04:42:56 PM PDT 24
Finished Aug 03 04:43:52 PM PDT 24
Peak memory 199960 kb
Host smart-64002ca7-b669-4177-b743-a01ee1318a11
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155614492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3155614492
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.658875495
Short name T229
Test name
Test status
Simulation time 7466565002 ps
CPU time 123.15 seconds
Started Aug 03 04:42:55 PM PDT 24
Finished Aug 03 04:44:58 PM PDT 24
Peak memory 200004 kb
Host smart-525c6bba-72e2-49e0-b36f-bc1a8e8d8c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658875495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.658875495
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.406215891
Short name T370
Test name
Test status
Simulation time 300941613 ps
CPU time 4.34 seconds
Started Aug 03 04:42:53 PM PDT 24
Finished Aug 03 04:42:57 PM PDT 24
Peak memory 199852 kb
Host smart-b6056710-a1ca-4a40-a6c0-54b8e0659fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406215891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.406215891
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.289461445
Short name T75
Test name
Test status
Simulation time 6599575454 ps
CPU time 90.63 seconds
Started Aug 03 04:42:52 PM PDT 24
Finished Aug 03 04:44:23 PM PDT 24
Peak memory 199908 kb
Host smart-9653c87e-e1ec-4ec5-9382-c3f8091fbeba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289461445 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.289461445
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3701341983
Short name T375
Test name
Test status
Simulation time 5000968918 ps
CPU time 63.28 seconds
Started Aug 03 04:42:47 PM PDT 24
Finished Aug 03 04:43:50 PM PDT 24
Peak memory 199904 kb
Host smart-f697b666-724d-49f9-88df-edd5f3f33725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701341983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3701341983
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2067366274
Short name T456
Test name
Test status
Simulation time 24493653 ps
CPU time 0.57 seconds
Started Aug 03 04:43:02 PM PDT 24
Finished Aug 03 04:43:02 PM PDT 24
Peak memory 195560 kb
Host smart-dc4f0977-230a-4fa6-ad3f-b5fb4b2c2ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067366274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2067366274
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3019845624
Short name T522
Test name
Test status
Simulation time 6725831733 ps
CPU time 87.9 seconds
Started Aug 03 04:42:54 PM PDT 24
Finished Aug 03 04:44:23 PM PDT 24
Peak memory 208108 kb
Host smart-f8199fef-8e2a-4fc5-b58e-5b2c4f06ddd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019845624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3019845624
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1378740624
Short name T266
Test name
Test status
Simulation time 738686913 ps
CPU time 9.07 seconds
Started Aug 03 04:42:47 PM PDT 24
Finished Aug 03 04:42:56 PM PDT 24
Peak memory 199828 kb
Host smart-969c9285-dced-4285-aebe-61fe6c72335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378740624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1378740624
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.58898613
Short name T356
Test name
Test status
Simulation time 7721481337 ps
CPU time 725.55 seconds
Started Aug 03 04:42:52 PM PDT 24
Finished Aug 03 04:54:57 PM PDT 24
Peak memory 718984 kb
Host smart-bb0261b7-54d1-49a2-b9cf-5623535b41a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58898613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.58898613
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.226914599
Short name T412
Test name
Test status
Simulation time 1208955315 ps
CPU time 18.6 seconds
Started Aug 03 04:42:53 PM PDT 24
Finished Aug 03 04:43:11 PM PDT 24
Peak memory 199720 kb
Host smart-cfbcb6fb-f511-4e21-a0b0-59314f6ea8ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226914599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.226914599
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1028327047
Short name T297
Test name
Test status
Simulation time 7808717984 ps
CPU time 109.74 seconds
Started Aug 03 04:42:54 PM PDT 24
Finished Aug 03 04:44:44 PM PDT 24
Peak memory 216344 kb
Host smart-7d66d5a0-ff86-49db-b549-92d0c22a623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028327047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1028327047
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.253611687
Short name T71
Test name
Test status
Simulation time 1682925424 ps
CPU time 5.58 seconds
Started Aug 03 04:42:54 PM PDT 24
Finished Aug 03 04:43:00 PM PDT 24
Peak memory 199828 kb
Host smart-a3de9a33-8fe0-4a51-9bb4-542cb840e023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253611687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.253611687
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3754936670
Short name T178
Test name
Test status
Simulation time 160710959840 ps
CPU time 2083.16 seconds
Started Aug 03 04:42:49 PM PDT 24
Finished Aug 03 05:17:33 PM PDT 24
Peak memory 758464 kb
Host smart-eaf67646-ad99-4af4-9e2c-2391fe124463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754936670 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3754936670
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.337468173
Short name T33
Test name
Test status
Simulation time 565863598 ps
CPU time 23.29 seconds
Started Aug 03 04:43:07 PM PDT 24
Finished Aug 03 04:43:30 PM PDT 24
Peak memory 199804 kb
Host smart-0655115e-0c70-4661-9ac5-6f0be21754f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337468173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.337468173
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3885326625
Short name T329
Test name
Test status
Simulation time 100899628 ps
CPU time 0.6 seconds
Started Aug 03 04:42:59 PM PDT 24
Finished Aug 03 04:43:00 PM PDT 24
Peak memory 195444 kb
Host smart-984a6617-b660-44f8-b4f5-2e292fac9284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885326625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3885326625
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3501056751
Short name T305
Test name
Test status
Simulation time 1212462163 ps
CPU time 60.16 seconds
Started Aug 03 04:42:50 PM PDT 24
Finished Aug 03 04:43:51 PM PDT 24
Peak memory 199812 kb
Host smart-d0a85a1a-45f6-48af-96be-4dc240ad9136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3501056751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3501056751
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.979103340
Short name T420
Test name
Test status
Simulation time 28215521787 ps
CPU time 61.19 seconds
Started Aug 03 04:42:48 PM PDT 24
Finished Aug 03 04:43:50 PM PDT 24
Peak memory 199976 kb
Host smart-255a0a9b-7f4a-428e-aba0-1a59273c3ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979103340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.979103340
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.4131332626
Short name T37
Test name
Test status
Simulation time 4213248804 ps
CPU time 732.46 seconds
Started Aug 03 04:42:55 PM PDT 24
Finished Aug 03 04:55:07 PM PDT 24
Peak memory 672124 kb
Host smart-05fff2aa-4962-460b-8302-08bfba6bde32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131332626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.4131332626
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.553620384
Short name T479
Test name
Test status
Simulation time 1457132058 ps
CPU time 79.89 seconds
Started Aug 03 04:42:53 PM PDT 24
Finished Aug 03 04:44:13 PM PDT 24
Peak memory 199796 kb
Host smart-daacf019-3dd8-452e-a277-2822a50f9238
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553620384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.553620384
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4208787692
Short name T373
Test name
Test status
Simulation time 36954939680 ps
CPU time 232.98 seconds
Started Aug 03 04:42:54 PM PDT 24
Finished Aug 03 04:46:48 PM PDT 24
Peak memory 199944 kb
Host smart-665d691b-9749-42c7-a56d-72e00a7c79b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208787692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4208787692
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.873000235
Short name T74
Test name
Test status
Simulation time 309041867 ps
CPU time 8.62 seconds
Started Aug 03 04:42:54 PM PDT 24
Finished Aug 03 04:43:03 PM PDT 24
Peak memory 199916 kb
Host smart-db4c532d-0c51-4a38-87f7-89da4b8284f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873000235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.873000235
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3982087337
Short name T411
Test name
Test status
Simulation time 84199430433 ps
CPU time 963.99 seconds
Started Aug 03 04:42:52 PM PDT 24
Finished Aug 03 04:58:56 PM PDT 24
Peak memory 474996 kb
Host smart-4eb121fb-ebbd-46a0-bc0b-e47c75acf450
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982087337 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3982087337
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4032652990
Short name T255
Test name
Test status
Simulation time 1063600849 ps
CPU time 37.17 seconds
Started Aug 03 04:42:56 PM PDT 24
Finished Aug 03 04:43:33 PM PDT 24
Peak memory 199844 kb
Host smart-5cb5be86-4623-45ed-9474-f53666817682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032652990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4032652990
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.21541270
Short name T385
Test name
Test status
Simulation time 23909883 ps
CPU time 0.62 seconds
Started Aug 03 04:43:04 PM PDT 24
Finished Aug 03 04:43:05 PM PDT 24
Peak memory 195868 kb
Host smart-9376a2c1-a366-478b-a3b7-4943818cf8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21541270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.21541270
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3646159644
Short name T11
Test name
Test status
Simulation time 1218654401 ps
CPU time 70.36 seconds
Started Aug 03 04:42:59 PM PDT 24
Finished Aug 03 04:44:09 PM PDT 24
Peak memory 199856 kb
Host smart-5ace16f8-ec75-45c4-80a5-3e74c5189beb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646159644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3646159644
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1623555137
Short name T405
Test name
Test status
Simulation time 5670448482 ps
CPU time 78.11 seconds
Started Aug 03 04:42:55 PM PDT 24
Finished Aug 03 04:44:13 PM PDT 24
Peak memory 216316 kb
Host smart-772b7ecf-e7e2-402f-b617-311a36348bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623555137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1623555137
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.115254054
Short name T518
Test name
Test status
Simulation time 3022018019 ps
CPU time 540.65 seconds
Started Aug 03 04:42:57 PM PDT 24
Finished Aug 03 04:51:58 PM PDT 24
Peak memory 711488 kb
Host smart-6381ddd5-5b13-4585-9e96-cdfbbb29ab99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115254054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.115254054
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2349651377
Short name T404
Test name
Test status
Simulation time 8063514187 ps
CPU time 147.98 seconds
Started Aug 03 04:42:55 PM PDT 24
Finished Aug 03 04:45:23 PM PDT 24
Peak memory 199928 kb
Host smart-4043f0df-df98-4851-add5-fb0a72e2be6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349651377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2349651377
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4279106336
Short name T197
Test name
Test status
Simulation time 8377029773 ps
CPU time 73.91 seconds
Started Aug 03 04:42:50 PM PDT 24
Finished Aug 03 04:44:04 PM PDT 24
Peak memory 200012 kb
Host smart-00debaff-3040-4208-aa36-ed216f803768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279106336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4279106336
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3733778399
Short name T187
Test name
Test status
Simulation time 273095902 ps
CPU time 1.74 seconds
Started Aug 03 04:42:53 PM PDT 24
Finished Aug 03 04:42:55 PM PDT 24
Peak memory 199792 kb
Host smart-12584299-b895-4148-b86a-b5d7839e2bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733778399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3733778399
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3292237591
Short name T248
Test name
Test status
Simulation time 9775430610 ps
CPU time 1777.65 seconds
Started Aug 03 04:42:57 PM PDT 24
Finished Aug 03 05:12:35 PM PDT 24
Peak memory 765092 kb
Host smart-e75535f0-b208-400e-91d1-33513b0e7560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292237591 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3292237591
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2726537136
Short name T525
Test name
Test status
Simulation time 54567959 ps
CPU time 0.68 seconds
Started Aug 03 04:42:58 PM PDT 24
Finished Aug 03 04:42:59 PM PDT 24
Peak memory 196604 kb
Host smart-27b1e794-0054-4b7c-854f-0c17ae66be80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726537136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2726537136
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2295471123
Short name T359
Test name
Test status
Simulation time 29976557 ps
CPU time 0.54 seconds
Started Aug 03 04:43:00 PM PDT 24
Finished Aug 03 04:43:00 PM PDT 24
Peak memory 195536 kb
Host smart-f18a4da2-69ee-4bc6-ac14-fe034d8aa594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295471123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2295471123
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1900865032
Short name T260
Test name
Test status
Simulation time 3951922202 ps
CPU time 120.69 seconds
Started Aug 03 04:42:59 PM PDT 24
Finished Aug 03 04:45:00 PM PDT 24
Peak memory 200032 kb
Host smart-db51a189-818f-40f3-9c6a-f1f0b062f90f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900865032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1900865032
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2829086007
Short name T151
Test name
Test status
Simulation time 1467742829 ps
CPU time 14.13 seconds
Started Aug 03 04:42:52 PM PDT 24
Finished Aug 03 04:43:06 PM PDT 24
Peak memory 199824 kb
Host smart-9ce4d441-f25b-4f6e-8dc6-6a9f27eadca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829086007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2829086007
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3302031738
Short name T230
Test name
Test status
Simulation time 2215707517 ps
CPU time 438.29 seconds
Started Aug 03 04:42:54 PM PDT 24
Finished Aug 03 04:50:13 PM PDT 24
Peak memory 692564 kb
Host smart-e56eb5fb-24a6-474b-b4ea-bde06ba63020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302031738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3302031738
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1310744349
Short name T499
Test name
Test status
Simulation time 7493998902 ps
CPU time 63.27 seconds
Started Aug 03 04:42:50 PM PDT 24
Finished Aug 03 04:43:54 PM PDT 24
Peak memory 199972 kb
Host smart-e07e5f26-ce03-4c5e-955d-59f456a0f7cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310744349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1310744349
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3962305734
Short name T355
Test name
Test status
Simulation time 33752279 ps
CPU time 1.03 seconds
Started Aug 03 04:42:52 PM PDT 24
Finished Aug 03 04:42:53 PM PDT 24
Peak memory 199660 kb
Host smart-5d18dd4a-aa9c-4db0-abb9-10211fd15636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962305734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3962305734
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2210503183
Short name T222
Test name
Test status
Simulation time 375810931 ps
CPU time 4.58 seconds
Started Aug 03 04:42:52 PM PDT 24
Finished Aug 03 04:42:56 PM PDT 24
Peak memory 199820 kb
Host smart-998765a5-3bed-4e8d-add7-5e9b2076e560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210503183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2210503183
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.4207704960
Short name T438
Test name
Test status
Simulation time 87290354290 ps
CPU time 129.62 seconds
Started Aug 03 04:43:04 PM PDT 24
Finished Aug 03 04:45:14 PM PDT 24
Peak memory 199924 kb
Host smart-250f5984-c8e5-4597-b445-c016546d2344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207704960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.4207704960
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1770350858
Short name T388
Test name
Test status
Simulation time 11471405 ps
CPU time 0.58 seconds
Started Aug 03 04:42:55 PM PDT 24
Finished Aug 03 04:42:56 PM PDT 24
Peak memory 194876 kb
Host smart-ebe7e0ee-8bed-4367-b04e-8b063743080e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770350858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1770350858
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3265151488
Short name T188
Test name
Test status
Simulation time 868031967 ps
CPU time 24.74 seconds
Started Aug 03 04:42:57 PM PDT 24
Finished Aug 03 04:43:22 PM PDT 24
Peak memory 199872 kb
Host smart-dd12f169-a88d-4bc6-9cf3-8fac1d1ebada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265151488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3265151488
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.4023461846
Short name T424
Test name
Test status
Simulation time 5004353353 ps
CPU time 63.68 seconds
Started Aug 03 04:43:04 PM PDT 24
Finished Aug 03 04:44:08 PM PDT 24
Peak memory 199988 kb
Host smart-9624a831-6abf-4950-8f7a-8ece179ea05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023461846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4023461846
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2585732186
Short name T505
Test name
Test status
Simulation time 5547516953 ps
CPU time 317.79 seconds
Started Aug 03 04:42:55 PM PDT 24
Finished Aug 03 04:48:13 PM PDT 24
Peak memory 569076 kb
Host smart-3b2448d0-3062-468d-ba85-375835db4171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585732186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2585732186
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1192456059
Short name T347
Test name
Test status
Simulation time 16964451113 ps
CPU time 215.73 seconds
Started Aug 03 04:42:56 PM PDT 24
Finished Aug 03 04:46:32 PM PDT 24
Peak memory 200016 kb
Host smart-36e30ade-6d67-44a4-a406-d8558034ffe9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192456059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1192456059
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2256221684
Short name T509
Test name
Test status
Simulation time 29331269466 ps
CPU time 95.96 seconds
Started Aug 03 04:42:58 PM PDT 24
Finished Aug 03 04:44:34 PM PDT 24
Peak memory 199984 kb
Host smart-69134a93-d0cc-405c-8212-3732ca05dd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256221684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2256221684
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.4100531387
Short name T365
Test name
Test status
Simulation time 580239547 ps
CPU time 8.58 seconds
Started Aug 03 04:42:58 PM PDT 24
Finished Aug 03 04:43:06 PM PDT 24
Peak memory 199844 kb
Host smart-9f4ffb43-c169-4764-9107-94924e579a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100531387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4100531387
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1150899602
Short name T432
Test name
Test status
Simulation time 41987464069 ps
CPU time 624.37 seconds
Started Aug 03 04:42:57 PM PDT 24
Finished Aug 03 04:53:21 PM PDT 24
Peak memory 269752 kb
Host smart-b78fa172-40da-4322-b185-7f551ef34add
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150899602 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1150899602
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1855842189
Short name T189
Test name
Test status
Simulation time 7031113384 ps
CPU time 65.33 seconds
Started Aug 03 04:42:59 PM PDT 24
Finished Aug 03 04:44:05 PM PDT 24
Peak memory 199924 kb
Host smart-5983ffd9-fe9a-4031-af16-627399585918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855842189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1855842189
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1467947311
Short name T176
Test name
Test status
Simulation time 44886180 ps
CPU time 0.64 seconds
Started Aug 03 04:43:03 PM PDT 24
Finished Aug 03 04:43:04 PM PDT 24
Peak memory 196548 kb
Host smart-cdab1a4d-42dd-4ad6-8fd9-5e17e00e5bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467947311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1467947311
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2148099613
Short name T460
Test name
Test status
Simulation time 557861268 ps
CPU time 33.47 seconds
Started Aug 03 04:42:58 PM PDT 24
Finished Aug 03 04:43:31 PM PDT 24
Peak memory 199864 kb
Host smart-e37128e1-53a8-4a66-9cd1-dd8e381a900d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148099613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2148099613
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1396670059
Short name T407
Test name
Test status
Simulation time 5330482016 ps
CPU time 7.09 seconds
Started Aug 03 04:43:02 PM PDT 24
Finished Aug 03 04:43:09 PM PDT 24
Peak memory 199908 kb
Host smart-2c950cae-fca0-47bb-8b35-d0aa33096ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396670059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1396670059
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2586417515
Short name T520
Test name
Test status
Simulation time 48117839 ps
CPU time 2.97 seconds
Started Aug 03 04:42:57 PM PDT 24
Finished Aug 03 04:43:00 PM PDT 24
Peak memory 199772 kb
Host smart-1957508f-0ad3-4283-8dfb-8b6847049597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586417515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2586417515
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2287366971
Short name T333
Test name
Test status
Simulation time 41475907497 ps
CPU time 184.89 seconds
Started Aug 03 04:42:55 PM PDT 24
Finished Aug 03 04:46:00 PM PDT 24
Peak memory 199972 kb
Host smart-f279cd60-1ef8-4ca7-a3b7-515381fbf4f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287366971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2287366971
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2764365468
Short name T382
Test name
Test status
Simulation time 1033888852 ps
CPU time 14.62 seconds
Started Aug 03 04:42:57 PM PDT 24
Finished Aug 03 04:43:12 PM PDT 24
Peak memory 199812 kb
Host smart-81789f9a-6365-43dd-bcad-322c61b648ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764365468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2764365468
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3196279174
Short name T328
Test name
Test status
Simulation time 616725937 ps
CPU time 9.41 seconds
Started Aug 03 04:42:56 PM PDT 24
Finished Aug 03 04:43:06 PM PDT 24
Peak memory 199824 kb
Host smart-e9e51fd2-6205-410e-ba94-839ab94d93c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196279174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3196279174
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2971867047
Short name T81
Test name
Test status
Simulation time 500506417848 ps
CPU time 3579.17 seconds
Started Aug 03 04:43:04 PM PDT 24
Finished Aug 03 05:42:44 PM PDT 24
Peak memory 792188 kb
Host smart-5c66f940-fcb7-4985-bff2-eda22e01daac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971867047 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2971867047
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1132286213
Short name T455
Test name
Test status
Simulation time 11342920990 ps
CPU time 102.02 seconds
Started Aug 03 04:43:03 PM PDT 24
Finished Aug 03 04:44:45 PM PDT 24
Peak memory 199976 kb
Host smart-ea891a15-52c8-45ac-8f40-29bc36b4a38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132286213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1132286213
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2046637500
Short name T383
Test name
Test status
Simulation time 11691157 ps
CPU time 0.58 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:42:07 PM PDT 24
Peak memory 194876 kb
Host smart-aaa76f5c-ead9-414d-9b3b-3adc780ad6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046637500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2046637500
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2357696863
Short name T320
Test name
Test status
Simulation time 342784995 ps
CPU time 19.58 seconds
Started Aug 03 04:42:04 PM PDT 24
Finished Aug 03 04:42:24 PM PDT 24
Peak memory 199836 kb
Host smart-bc7c7384-0d92-4228-915f-6f88ba66de00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357696863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2357696863
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1085293220
Short name T239
Test name
Test status
Simulation time 1048836189 ps
CPU time 9 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:42:12 PM PDT 24
Peak memory 199828 kb
Host smart-0fafc2ff-08ed-4458-9660-3aee5a05c891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085293220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1085293220
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.4119239182
Short name T514
Test name
Test status
Simulation time 9023694592 ps
CPU time 306.65 seconds
Started Aug 03 04:42:10 PM PDT 24
Finished Aug 03 04:47:16 PM PDT 24
Peak memory 667192 kb
Host smart-26563825-6dfc-4334-8c43-7d0c4611b224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4119239182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.4119239182
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1249583691
Short name T312
Test name
Test status
Simulation time 494423669 ps
CPU time 8.96 seconds
Started Aug 03 04:42:00 PM PDT 24
Finished Aug 03 04:42:09 PM PDT 24
Peak memory 199660 kb
Host smart-93617b5c-24ea-46ab-bfe8-6679ffa78f49
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249583691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1249583691
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2050724263
Short name T452
Test name
Test status
Simulation time 1836288999 ps
CPU time 24.97 seconds
Started Aug 03 04:41:56 PM PDT 24
Finished Aug 03 04:42:21 PM PDT 24
Peak memory 199876 kb
Host smart-6861b115-f674-40e3-b781-2f5bf977cb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050724263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2050724263
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.76037960
Short name T468
Test name
Test status
Simulation time 1822634733 ps
CPU time 14.99 seconds
Started Aug 03 04:42:12 PM PDT 24
Finished Aug 03 04:42:27 PM PDT 24
Peak memory 199828 kb
Host smart-548a6637-c7a7-41c0-93e3-8928ab51cc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76037960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.76037960
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.16267303
Short name T80
Test name
Test status
Simulation time 316832831599 ps
CPU time 1638.11 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 05:09:27 PM PDT 24
Peak memory 751756 kb
Host smart-f020441e-d0c4-47cc-b8b0-d8961a2f2ec5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16267303 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.16267303
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1586778616
Short name T9
Test name
Test status
Simulation time 43837641910 ps
CPU time 4151.18 seconds
Started Aug 03 04:42:12 PM PDT 24
Finished Aug 03 05:51:24 PM PDT 24
Peak memory 862904 kb
Host smart-19faab2b-a179-46be-9de7-7cc001b2626c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586778616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1586778616
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.374135749
Short name T471
Test name
Test status
Simulation time 717928722 ps
CPU time 41.69 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:42:57 PM PDT 24
Peak memory 199916 kb
Host smart-ccc194bb-3031-467c-be68-27552f6fe09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374135749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.374135749
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4165898922
Short name T422
Test name
Test status
Simulation time 34276729 ps
CPU time 0.61 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:42:08 PM PDT 24
Peak memory 194804 kb
Host smart-755c48a2-c9f8-4dd5-9d1c-cdf6328c6dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165898922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4165898922
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.8705347
Short name T361
Test name
Test status
Simulation time 2384998379 ps
CPU time 67.22 seconds
Started Aug 03 04:42:04 PM PDT 24
Finished Aug 03 04:43:11 PM PDT 24
Peak memory 199916 kb
Host smart-43d4972b-4886-446f-a5e5-57edb8fb41a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8705347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.8705347
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1560701337
Short name T168
Test name
Test status
Simulation time 3684630111 ps
CPU time 51.22 seconds
Started Aug 03 04:42:13 PM PDT 24
Finished Aug 03 04:43:05 PM PDT 24
Peak memory 199972 kb
Host smart-0538d6f3-1fd9-4b2b-bc0f-ee01498e0095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560701337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1560701337
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1249171796
Short name T36
Test name
Test status
Simulation time 6497867896 ps
CPU time 493.58 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:50:19 PM PDT 24
Peak memory 656016 kb
Host smart-bd79dec0-bccd-4650-9c99-dedade5b685b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249171796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1249171796
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2491542315
Short name T224
Test name
Test status
Simulation time 2357974605 ps
CPU time 129.86 seconds
Started Aug 03 04:42:04 PM PDT 24
Finished Aug 03 04:44:14 PM PDT 24
Peak memory 199924 kb
Host smart-26a98404-a475-442a-94d4-5ddad2fa52b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491542315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2491542315
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.4285029561
Short name T44
Test name
Test status
Simulation time 3879336358 ps
CPU time 226.83 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:45:53 PM PDT 24
Peak memory 208092 kb
Host smart-58202404-e024-4916-a585-5a33f0ea4815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285029561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4285029561
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2191783746
Short name T319
Test name
Test status
Simulation time 2347307155 ps
CPU time 8.59 seconds
Started Aug 03 04:42:01 PM PDT 24
Finished Aug 03 04:42:10 PM PDT 24
Peak memory 199964 kb
Host smart-e0d0463b-fedb-4bf0-90d7-bbf71d0c5299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191783746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2191783746
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.39575426
Short name T268
Test name
Test status
Simulation time 525875476820 ps
CPU time 1639.23 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 05:09:29 PM PDT 24
Peak memory 769768 kb
Host smart-02abd6d6-a041-442e-a7be-becb0539d6f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39575426 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.39575426
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1856300022
Short name T314
Test name
Test status
Simulation time 3639501134 ps
CPU time 63.78 seconds
Started Aug 03 04:42:04 PM PDT 24
Finished Aug 03 04:43:08 PM PDT 24
Peak memory 200016 kb
Host smart-fb82c766-df78-47ee-91e9-8e5714de20cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856300022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1856300022
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.611131841
Short name T482
Test name
Test status
Simulation time 70581787 ps
CPU time 0.6 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:42:06 PM PDT 24
Peak memory 196600 kb
Host smart-995c24e4-b11e-423e-9cbe-76597782088d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611131841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.611131841
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3629775253
Short name T272
Test name
Test status
Simulation time 1340668828 ps
CPU time 76.84 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 04:43:22 PM PDT 24
Peak memory 199764 kb
Host smart-1743749e-8006-499d-ab8f-e3d04d5621ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629775253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3629775253
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2561882861
Short name T149
Test name
Test status
Simulation time 9261191067 ps
CPU time 86.44 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:43:34 PM PDT 24
Peak memory 216348 kb
Host smart-e5ae57e9-547b-4efd-8572-4c391b7ef853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561882861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2561882861
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2751803317
Short name T221
Test name
Test status
Simulation time 5896521411 ps
CPU time 1096.5 seconds
Started Aug 03 04:42:13 PM PDT 24
Finished Aug 03 05:00:30 PM PDT 24
Peak memory 728568 kb
Host smart-f8721500-b2a2-42fe-ba1d-1fc349e663a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751803317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2751803317
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2104724051
Short name T453
Test name
Test status
Simulation time 21749968562 ps
CPU time 61.37 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 04:43:06 PM PDT 24
Peak memory 199932 kb
Host smart-bbe5e378-914c-4513-a102-48e03af3851a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104724051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2104724051
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3910304635
Short name T410
Test name
Test status
Simulation time 13023537531 ps
CPU time 73.69 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:43:20 PM PDT 24
Peak memory 199916 kb
Host smart-181fd846-5e8b-42b1-8152-5eec61c9728c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910304635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3910304635
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.957869120
Short name T264
Test name
Test status
Simulation time 1017944730 ps
CPU time 13.48 seconds
Started Aug 03 04:41:57 PM PDT 24
Finished Aug 03 04:42:10 PM PDT 24
Peak memory 199828 kb
Host smart-30ae2f14-e795-43c1-bc2c-369a656de8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957869120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.957869120
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3052339776
Short name T100
Test name
Test status
Simulation time 98960512250 ps
CPU time 1946.78 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 05:14:33 PM PDT 24
Peak memory 716736 kb
Host smart-6909889f-f250-4b81-943f-69b667997fb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052339776 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3052339776
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3457044609
Short name T470
Test name
Test status
Simulation time 8319036444 ps
CPU time 104 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:43:53 PM PDT 24
Peak memory 199964 kb
Host smart-eb8edb0e-8cee-408d-b086-ce6e6d1912cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457044609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3457044609
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2725880838
Short name T440
Test name
Test status
Simulation time 11327132 ps
CPU time 0.58 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:42:16 PM PDT 24
Peak memory 195912 kb
Host smart-a734c19e-0c06-45cd-9789-396f7d998c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725880838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2725880838
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.306693863
Short name T486
Test name
Test status
Simulation time 1917307868 ps
CPU time 32.26 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 04:42:37 PM PDT 24
Peak memory 199792 kb
Host smart-8a01a193-c771-4f76-ba6d-30de39c297ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306693863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.306693863
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1800214639
Short name T343
Test name
Test status
Simulation time 1582047841 ps
CPU time 29.3 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 04:42:37 PM PDT 24
Peak memory 199856 kb
Host smart-1595dd75-291f-494b-9946-2164bcf20b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800214639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1800214639
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2323324266
Short name T367
Test name
Test status
Simulation time 3085917817 ps
CPU time 458.41 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 04:49:44 PM PDT 24
Peak memory 721588 kb
Host smart-a00b3a88-d8d6-4d2a-b81e-f09481bc41c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323324266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2323324266
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1370777205
Short name T281
Test name
Test status
Simulation time 4777141284 ps
CPU time 41.69 seconds
Started Aug 03 04:42:26 PM PDT 24
Finished Aug 03 04:43:08 PM PDT 24
Peak memory 199952 kb
Host smart-bd7fa1d2-9283-4b25-a04d-9298becee131
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370777205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1370777205
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.600511337
Short name T245
Test name
Test status
Simulation time 2106521783 ps
CPU time 112.25 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 04:43:58 PM PDT 24
Peak memory 199840 kb
Host smart-73425071-48b4-4da3-a80e-58fae3b37628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600511337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.600511337
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3132669140
Short name T481
Test name
Test status
Simulation time 258403248 ps
CPU time 11.63 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:42:21 PM PDT 24
Peak memory 199824 kb
Host smart-74fe3f94-dddc-4b74-afd8-b98b994fcdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132669140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3132669140
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1093621061
Short name T77
Test name
Test status
Simulation time 85039585534 ps
CPU time 1296.22 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 05:03:42 PM PDT 24
Peak memory 476564 kb
Host smart-e85858a0-b0a1-41d1-8bbc-8633679efcb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093621061 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1093621061
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2783953811
Short name T374
Test name
Test status
Simulation time 29847870297 ps
CPU time 133.48 seconds
Started Aug 03 04:42:15 PM PDT 24
Finished Aug 03 04:44:28 PM PDT 24
Peak memory 200012 kb
Host smart-0bac48d7-2f77-4ae4-8666-c32a7cf128f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783953811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2783953811
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4146738646
Short name T32
Test name
Test status
Simulation time 36816292 ps
CPU time 0.58 seconds
Started Aug 03 04:42:21 PM PDT 24
Finished Aug 03 04:42:22 PM PDT 24
Peak memory 194908 kb
Host smart-b1e59d09-b519-4e52-b9ca-e5a78e319c8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146738646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4146738646
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.431847819
Short name T381
Test name
Test status
Simulation time 2033031995 ps
CPU time 27.94 seconds
Started Aug 03 04:42:05 PM PDT 24
Finished Aug 03 04:42:33 PM PDT 24
Peak memory 199740 kb
Host smart-76a1ca42-026f-4b24-aa6d-41f9b22353c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431847819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.431847819
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2870467083
Short name T2
Test name
Test status
Simulation time 263733759 ps
CPU time 3.95 seconds
Started Aug 03 04:42:04 PM PDT 24
Finished Aug 03 04:42:08 PM PDT 24
Peak memory 199836 kb
Host smart-32fa08ca-48dd-4c7f-b81d-80f172841017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870467083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2870467083
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.583627659
Short name T215
Test name
Test status
Simulation time 1770623155 ps
CPU time 313.64 seconds
Started Aug 03 04:42:09 PM PDT 24
Finished Aug 03 04:47:22 PM PDT 24
Peak memory 628056 kb
Host smart-e64ba20c-2371-44d1-91bf-b77f5fd5858b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=583627659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.583627659
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.955511705
Short name T353
Test name
Test status
Simulation time 16635599939 ps
CPU time 212.62 seconds
Started Aug 03 04:42:18 PM PDT 24
Finished Aug 03 04:45:50 PM PDT 24
Peak memory 199984 kb
Host smart-d7cb0e9e-1755-4349-8513-56d7eaa3f561
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955511705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.955511705
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.906598896
Short name T219
Test name
Test status
Simulation time 34251905676 ps
CPU time 151.74 seconds
Started Aug 03 04:42:20 PM PDT 24
Finished Aug 03 04:44:57 PM PDT 24
Peak memory 200152 kb
Host smart-40815791-39b2-4626-852e-0a05bdbaa28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906598896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.906598896
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3835340888
Short name T106
Test name
Test status
Simulation time 123123113 ps
CPU time 5.15 seconds
Started Aug 03 04:42:06 PM PDT 24
Finished Aug 03 04:42:11 PM PDT 24
Peak memory 199908 kb
Host smart-8e1de22c-4a2e-4dce-89a0-13da6a18d339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835340888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3835340888
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.4254265526
Short name T46
Test name
Test status
Simulation time 1629541283 ps
CPU time 88.48 seconds
Started Aug 03 04:42:07 PM PDT 24
Finished Aug 03 04:43:35 PM PDT 24
Peak memory 200148 kb
Host smart-8e8ac12c-2cf3-4cc2-8e50-69addd2252d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254265526 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.4254265526
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.4135250512
Short name T68
Test name
Test status
Simulation time 19449993985 ps
CPU time 2028.11 seconds
Started Aug 03 04:42:08 PM PDT 24
Finished Aug 03 05:15:56 PM PDT 24
Peak memory 779616 kb
Host smart-d509b73b-e140-45e3-ac53-6132701a7d5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135250512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.4135250512
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3643332946
Short name T429
Test name
Test status
Simulation time 9167560199 ps
CPU time 114.47 seconds
Started Aug 03 04:42:03 PM PDT 24
Finished Aug 03 04:43:58 PM PDT 24
Peak memory 199964 kb
Host smart-fdf4bff8-d88e-4dd9-aff2-f97f041d7820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643332946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3643332946
Directory /workspace/9.hmac_wipe_secret/latest
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