Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19765585	1			T1	23398		T2	380147		T3	31731
all_values[1]	19765585	1			T1	23398		T2	380147		T3	31731
all_values[2]	19765585	1			T1	23398		T2	380147		T3	31731

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234310

1

T1

2463

T2

1140

T19

91

auto[1]

59062445

1

T1

67731

T2

113930

T3

95193

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50469881

1

T1

60362

T2

955748

T3

80710

auto[1]

8826874

1

T1

9832

T2

184693

T3

14483

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	82035	1			T2	469		T22	865		T11	15
all_values[0]	auto[0]	auto[1]	362	1			T2	2		T22	2		T11	10
all_values[0]	auto[1]	auto[0]	19661844	1			T1	23389		T2	379436		T3	31707
all_values[0]	auto[1]	auto[1]	21344	1			T1	9		T2	240		T3	24
all_values[1]	auto[0]	auto[0]	75784	1			T2	1		T21	938		T9	390
all_values[1]	auto[0]	auto[1]	246	1			T2	1		T22	1		T11	9
all_values[1]	auto[1]	auto[0]	19689113	1			T1	23398		T2	380142		T3	31731
all_values[1]	auto[1]	auto[1]	442	1			T2	3		T11	10		T12	19
all_values[2]	auto[0]	auto[0]	42100	1			T1	2463		T2	182		T19	22
all_values[2]	auto[0]	auto[1]	33783	1			T2	485		T19	69		T20	268
all_values[2]	auto[1]	auto[0]	10919005	1			T1	11112		T2	195518		T3	17272
all_values[2]	auto[1]	auto[1]	8770697	1			T1	9823		T2	183962		T3	14459