Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156291

1

T2

1116

T3

32

T6

26

auto[1]

145864

1

T1

42

T2

1186

T3

28

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	114424	1			T1	17		T2	922		T3	25
len_1026_2046	8007	1			T2	86		T3	3		T6	5
len_514_1022	5134	1			T2	7		T20	2		T63	1
len_2_510	4273	1			T2	11		T5	2		T61	10
len_2056	191	1			T2	2		T61	2		T11	4
len_2048	409	1			T2	1		T5	1		T21	1
len_2040	265	1			T2	2		T22	6		T11	7
len_1032	176	1			T2	3		T61	1		T22	2
len_1024	2302	1			T2	5		T4	1		T5	1
len_1016	216	1			T2	3		T61	1		T11	5
len_520	242	1			T2	12		T62	3		T22	2
len_512	560	1			T2	3		T5	1		T140	1
len_504	253	1			T2	2		T11	1		T80	1
len_8	1378	1			T1	4		T2	58		T22	19
len_0	13249	1			T2	34		T3	2		T6	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

133

1

T5

3

T21

2

T9

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	61788	1			T2	503		T3	13		T6	10
auto[0]	len_1026_2046	3619	1			T2	19		T3	3		T6	3
auto[0]	len_514_1022	3237	1			T2	5		T20	1		T63	1
auto[0]	len_2_510	2427	1			T2	4		T61	7		T11	11
auto[0]	len_2056	102	1			T2	2		T11	4		T80	2
auto[0]	len_2048	235	1			T5	1		T21	1		T61	1
auto[0]	len_2040	132	1			T2	1		T22	2		T11	6
auto[0]	len_1032	99	1			T61	1		T22	2		T141	2
auto[0]	len_1024	476	1			T2	1		T4	1		T5	1
auto[0]	len_1016	112	1			T2	2		T61	1		T11	3
auto[0]	len_520	120	1			T2	3		T62	1		T141	1
auto[0]	len_512	303	1			T2	1		T140	1		T61	4
auto[0]	len_504	161	1			T2	2		T11	1		T141	6
auto[0]	len_8	25	1			T142	1		T143	1		T32	1
auto[0]	len_0	5311	1			T2	15		T19	1		T20	1
auto[1]	len_2050_plus	52636	1			T1	17		T2	419		T3	12
auto[1]	len_1026_2046	4388	1			T2	67		T6	2		T61	34
auto[1]	len_514_1022	1897	1			T2	2		T20	1		T61	85
auto[1]	len_2_510	1846	1			T2	7		T5	2		T61	3
auto[1]	len_2056	89	1			T61	2		T124	1		T12	2
auto[1]	len_2048	174	1			T2	1		T11	4		T141	5
auto[1]	len_2040	133	1			T2	1		T22	4		T11	1
auto[1]	len_1032	77	1			T2	3		T141	3		T124	1
auto[1]	len_1024	1826	1			T2	4		T9	1		T25	86
auto[1]	len_1016	104	1			T2	1		T11	2		T124	1
auto[1]	len_520	122	1			T2	9		T62	2		T22	2
auto[1]	len_512	257	1			T2	2		T5	1		T61	2
auto[1]	len_504	92	1			T80	1		T82	2		T141	2
auto[1]	len_8	1353	1			T1	4		T2	58		T22	19
auto[1]	len_0	7938	1			T2	19		T3	2		T6	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

80

1

T5

1

T21

2

T43

2

auto[1]

len_upper

53

1

T5

2

T9

1

T79

1