Group : hmac_env_pkg::hmac_env_cov::save_and_restore_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : hmac_env_pkg::hmac_env_cov::save_and_restore_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv



Summary for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 9 0 9 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_size_cp 3 0 3 100.00 100 1 1 0
save_and_restore_cp 3 0 3 100.00 100 1 1 0


Crosses for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sar_type_x_digest_size 9 0 9 100.00 100 1 1 0


Summary for Variable digest_size_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for digest_size_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sha2_512 215 1 T4 4 T5 3 T9 3
sha2_384 203 1 T2 1 T4 1 T21 1
sha2_256 197 1 T1 1 T3 1 T5 2



Summary for Variable save_and_restore_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for save_and_restore_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stop_and_continue 203 1 T3 1 T4 3 T5 1
different_context 208 1 T1 1 T4 1 T5 3
same_context 204 1 T2 1 T4 1 T5 1



Summary for Cross sar_type_x_digest_size

Samples crossed: save_and_restore_cp digest_size_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 9 0 9 100.00


Automatically Generated Cross Bins for sar_type_x_digest_size

Bins
save_and_restore_cpdigest_size_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stop_and_continue sha2_512 78 1 T4 3 T5 1 T9 1
stop_and_continue sha2_384 66 1 T22 1 T141 1 T144 2
stop_and_continue sha2_256 59 1 T3 1 T145 1 T146 1
different_context sha2_512 76 1 T4 1 T5 1 T9 1
different_context sha2_384 64 1 T21 1 T61 1 T22 1
different_context sha2_256 68 1 T1 1 T5 2 T140 1
same_context sha2_512 61 1 T5 1 T9 1 T147 2
same_context sha2_384 73 1 T2 1 T4 1 T61 1
same_context sha2_256 70 1 T61 2 T147 1 T7 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%