Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5004188

1

T1

5575

T2

86741

T3

7817

auto[1]

3273807

1

T1

5886

T2

76702

T3

7938

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3361910

1

T1

7963

T2

89135

T3

5735

auto[1]

4916085

1

T1

3498

T2

74308

T3

10020

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3582835

1

T2

29183

T3

7177

T6

2085

auto[1]

4695160

1

T1

11461

T2

134260

T3

8578

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4921033

1

T1

3525

T2

76284

T3

7916

auto[1]

3356962

1

T1

7936

T2

87159

T3

7839

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7399999	1			T1	10068		T2	161350		T3	15589
fifo_depth[1]	141043	1			T1	230		T2	1349		T3	137
fifo_depth[2]	113014	1			T1	225		T2	506		T3	21
fifo_depth[3]	90748	1			T1	244		T2	135		T3	8
fifo_depth[4]	81919	1			T1	213		T2	66		T5	3
fifo_depth[5]	65320	1			T1	178		T2	11		T4	5
fifo_depth[6]	51574	1			T1	139		T2	17		T5	1
fifo_depth[7]	34286	1			T1	76		T2	2		T5	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

877996

1

T1

1393

T2

2093

T3

166

auto[1]

7399999

1

T1

10068

T2

161350

T3

15589

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8261411

1

T1

11461

T2

163443

T3

15755

auto[1]

16584

1

T22

83

T11

229

T23

1910

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

38194

1

T2

117

T3

8

T4

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

45824

1

T2

98

T21

390

T28

232

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

41269

1

T2

36

T3

30

T6

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

49271

1

T2

46

T3

22

T4

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

195041

1

T2

126

T6

4

T4

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

40963

1

T2

26

T3

14

T4

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35580

1

T2

17

T3

17

T4

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

41044

1

T2

73

T3

11

T6

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44168

1

T3

24

T4

1

T61

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

52817

1

T1

703

T2

256

T3

15

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42334

1

T2

326

T3

7

T4

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

49353

1

T1

395

T2

71

T4

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

55776

1

T2

335

T5

3

T20

110

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

49390

1

T1

13

T2

317

T3

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

50747

1

T1

282

T2

103

T3

13

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

46225

1

T2

146

T6

8

T4

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

206535

1

T2

5771

T3

1161

T4

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

181914

1

T2

5304

T6

1

T4

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

210367

1

T2

3552

T3

1090

T6

1343

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

216500

1

T2

2483

T3

1216

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1693654

1

T2

6191

T3

703

T6

240

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

199676

1

T2

1468

T3

1887

T6

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

198986

1

T2

1043

T3

574

T6

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

188017

1

T2

2832

T3

444

T6

480

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

500460

1

T1

5

T2

11122

T3

729

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

570688

1

T1

4026

T2

24504

T3

721

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

539240

1

T1

1511

T2

20621

T3

712

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

572976

1

T1

1323

T2

14828

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

576388

1

T1

798

T2

12498

T3

1813

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

552700

1

T1

30

T2

18608

T3

737

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

492294

1

T1

929

T2

14426

T3

1035

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

499604

1

T1

1446

T2

16099

T3

2767

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

243788

1

T2

5888

T3

1169

T4

6

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

225935

1

T2

5402

T6

1

T4

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

250393

1

T2

3588

T3

1120

T6

1348

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

264181

1

T2

2529

T3

1238

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1887754

1

T2

6317

T3

703

T6

244

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

239474

1

T2

1494

T3

1901

T6

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

233736

1

T2

1060

T3

591

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

227082

1

T2

2905

T3

455

T6

488

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

543916

1

T1

5

T2

11122

T3

753

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

621721

1

T1

4729

T2

24760

T3

736

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

581047

1

T1

1511

T2

20947

T3

719

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

621647

1

T1

1718

T2

14899

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

631695

1

T1

798

T2

12833

T3

1813

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

601607

1

T1

43

T2

18925

T3

742

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

542159

1

T1

1211

T2

14529

T3

1048

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

545276

1

T1

1446

T2

16245

T3

2767

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

941

1

T22

82

T11

153

T12

124

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1803

1

T23

2

T12

438

T13

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1243

1

T12

180

T13

65

T60

13

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1590

1

T12

287

T13

10

T60

572

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

941

1

T12

72

T148

71

T16

41

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1165

1

T22

1

T23

142

T12

14

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

830

1

T12

13

T13

7

T15

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1979

1

T23

268

T12

4

T13

14

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

712

1

T12

16

T149

16

T10

18

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1784

1

T23

1498

T13

3

T60

12

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

527

1

T13

34

T15

1

T16

47

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

682

1

T12

12

T13

12

T60

9

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

469

1

T11

6

T13

1

T59

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

483

1

T11

70

T12

1

T15

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

882

1

T13

70

T60

2

T15

164

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

553

1

T12

11

T13

2

T60

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

206535

1

T2

5771

T3

1161

T4

4

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

181914

1

T2

5304

T6

1

T4

1

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

210367

1

T2

3552

T3

1090

T6

1343

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

216500

1

T2

2483

T3

1216

T6

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1693654

1

T2

6191

T3

703

T6

240

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

199676

1

T2

1468

T3

1887

T6

2

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

198986

1

T2

1043

T3

574

T6

1

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

188017

1

T2

2832

T3

444

T6

480

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

500460

1

T1

5

T2

11122

T3

729

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

570688

1

T1

4026

T2

24504

T3

721

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

539240

1

T1

1511

T2

20621

T3

712

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

572976

1

T1

1323

T2

14828

T6

1

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

576388

1

T1

798

T2

12498

T3

1813

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

552700

1

T1

30

T2

18608

T3

737

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

492294

1

T1

929

T2

14426

T3

1035

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

499604

1

T1

1446

T2

16099

T3

2767

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

4744

1

T2

63

T3

7

T4

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

4081

1

T2

70

T21

59

T28

34

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

4556

1

T2

28

T3

28

T6

5

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

4711

1

T2

22

T3

18

T28

22

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

50886

1

T2

82

T6

4

T5

1

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

4473

1

T2

22

T3

12

T20

7

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3842

1

T2

5

T3

12

T140

1

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3490

1

T2

45

T3

9

T6

8

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6976

1

T3

18

T61

3

T147

13

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

7913

1

T1

135

T2

162

T3

14

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6920

1

T2

216

T3

5

T4

1

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

7327

1

T1

53

T2

45

T28

42

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

9591

1

T2

181

T5

1

T20

15

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

7664

1

T1

2

T2

227

T3

5

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

7059

1

T1

40

T2

82

T3

9

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1

T2

99

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8

T20

27

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1

T2

30

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1

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17

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1

T2

19

T21

74

T28

32

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1

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7

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2

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8

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1

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10

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2

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21

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35

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12

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24

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1

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4

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2

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1

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1

T2

4

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3

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3

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1

T2

17

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2

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10

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1

T3

5

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3

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2

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1

T1

126

T2

64

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1

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5614

1

T2

80

T3

1

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1

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1

T1

58

T2

19

T28

35

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1

T2

98

T20

14

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9

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1

T1

3

T2

71

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9

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1

T1

38

T2

13

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2

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1

T2

35

T20

27

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9

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1

T2

13

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13

T28

35

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1

T2

3

T21

66

T28

32

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1

T2

1

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12

T28

23

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1

T2

5

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2

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1

fifo_depth[3]

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1

T2

5

T28

12

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2

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1

T20

6

T21

93

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1

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2414

1

T2

3

T3

2

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1

fifo_depth[3]

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1

T2

5

T20

4

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17

fifo_depth[3]

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1

T3

1

T61

3

T22

78

fifo_depth[3]

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1

T1

138

T2

17

T20

21

fifo_depth[3]

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auto[0]

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1

T2

21

T3

1

T28

18

fifo_depth[3]

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auto[1]

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1

T1

69

T2

7

T28

39

fifo_depth[3]

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1

T2

23

T5

1

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20

fifo_depth[3]

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1

T2

16

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2

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1

fifo_depth[3]

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auto[0]

5089

1

T1

37

T2

7

T3

2

fifo_depth[3]

auto[1]

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auto[1]

5206

1

T2

9

T20

25

T21

16

fifo_depth[4]

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auto[0]

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2994

1

T2

8

T20

16

T28

35

fifo_depth[4]

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1

T2

4

T21

55

T28

29

fifo_depth[4]

auto[0]

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auto[0]

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1

T21

3

T28

30

T63

15

fifo_depth[4]

auto[0]

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3283

1

T2

4

T28

20

T22

34

fifo_depth[4]

auto[0]

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auto[0]

auto[0]

20969

1

T2

3

T28

10

T61

8

fifo_depth[4]

auto[0]

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auto[0]

auto[1]

3288

1

T20

6

T21

77

T61

5

fifo_depth[4]

auto[0]

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auto[0]

2383

1

T2

1

T28

2

T22

1

fifo_depth[4]

auto[0]

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2377

1

T2

3

T20

6

T21

20

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[0]

4921

1

T61

2

T22

75

T11

68

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[1]

5428

1

T1

123

T2

7

T20

19

fifo_depth[4]

auto[1]

auto[0]

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auto[0]

4320

1

T2

7

T5

1

T28

19

fifo_depth[4]

auto[1]

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5105

1

T1

51

T28

37

T22

61

fifo_depth[4]

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1

T2

23

T20

17

T9

1

fifo_depth[4]

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5418

1

T1

1

T2

3

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2

fifo_depth[4]

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auto[0]

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1

T1

38

T2

1

T28

16

fifo_depth[4]

auto[1]

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5110

1

T2

2

T20

25

T21

7

fifo_depth[5]

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2381

1

T20

11

T28

30

T22

8

fifo_depth[5]

auto[0]

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auto[1]

2211

1

T21

58

T28

30

T61

1

fifo_depth[5]

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1

T21

5

T28

28

T63

13

fifo_depth[5]

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1

T28

21

T22

56

T11

45

fifo_depth[5]

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1

T4

1

T28

7

T22

18

fifo_depth[5]

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1

T4

2

T20

4

T21

77

fifo_depth[5]

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1

T2

1

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1

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3

fifo_depth[5]

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1

T2

2

T20

5

T21

13

fifo_depth[5]

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1

T61

1

T22

77

T11

62

fifo_depth[5]

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4749

1

T1

92

T2

2

T20

15

fifo_depth[5]

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auto[0]

3593

1

T2

2

T28

12

T22

74

fifo_depth[5]

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auto[1]

4363

1

T1

48

T4

1

T28

35

fifo_depth[5]

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1

T2

3

T20

13

T22

104

fifo_depth[5]

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4761

1

T1

1

T22

18

T11

5

fifo_depth[5]

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auto[1]

auto[0]

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1

T1

37

T28

10

T22

115

fifo_depth[5]

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4347

1

T2

1

T4

1

T20

13

fifo_depth[6]

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1

T2

3

T20

9

T28

20

fifo_depth[6]

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1

T2

1

T21

38

T28

30

fifo_depth[6]

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1

T21

9

T28

14

T63

7

fifo_depth[6]

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2232

1

T2

4

T28

10

T22

22

fifo_depth[6]

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1

T28

6

T22

12

T11

34

fifo_depth[6]

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2090

1

T20

4

T21

51

T61

2

fifo_depth[6]

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1663

1

T2

1

T28

5

T11

38

fifo_depth[6]

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1560

1

T20

4

T21

14

T28

15

fifo_depth[6]

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3192

1

T22

55

T11

42

T141

2

fifo_depth[6]

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3667

1

T1

57

T2

2

T20

14

fifo_depth[6]

auto[1]

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auto[1]

auto[0]

3031

1

T28

14

T61

1

T22

137

fifo_depth[6]

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auto[0]

auto[1]

auto[1]

3446

1

T1

44

T28

22

T22

43

fifo_depth[6]

auto[1]

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3508

1

T2

6

T5

1

T20

13

fifo_depth[6]

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3878

1

T1

2

T22

9

T11

6

fifo_depth[6]

auto[1]

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auto[1]

auto[0]

3461

1

T1

36

T28

11

T61

1

fifo_depth[6]

auto[1]

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3258

1

T20

14

T21

10

T28

2

fifo_depth[7]

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auto[0]

1131

1

T20

7

T28

11

T22

5

fifo_depth[7]

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1

T21

19

T28

21

T61

1

fifo_depth[7]

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1

T21

4

T28

7

T63

3

fifo_depth[7]

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1565

1

T2

1

T5

1

T9

1

fifo_depth[7]

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6549

1

T28

3

T22

7

T11

29

fifo_depth[7]

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1361

1

T20

3

T21

21

T22

6

fifo_depth[7]

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auto[0]

1120

1

T2

1

T28

2

T22

1

fifo_depth[7]

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1193

1

T20

3

T21

8

T28

8

fifo_depth[7]

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auto[0]

2163

1

T22

41

T11

20

T144

11

fifo_depth[7]

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auto[0]

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2510

1

T1

21

T20

10

T21

8

fifo_depth[7]

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auto[0]

2075

1

T28

7

T22

62

T11

7

fifo_depth[7]

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auto[1]

auto[1]

2341

1

T1

31

T28

21

T22

40

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

2482

1

T20

9

T22

64

T11

24

fifo_depth[7]

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auto[1]

auto[0]

auto[1]

2538

1

T1

1

T140

1

T22

11

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

2335

1

T1

23

T28

10

T22

61

fifo_depth[7]

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auto[1]

auto[1]

auto[1]

2238

1

T20

6

T21

9

T28

5