Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19765585	1			T1	23398		T2	380147		T3	31731
all_pins[1]	19765585	1			T1	23398		T2	380147		T3	31731
all_pins[2]	19765585	1			T1	23398		T2	380147		T3	31731

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	50503251	1			T1	60361		T2	956230		T3	80709
values[0x1]	8793504	1			T1	9833		T2	184211		T3	14484
transitions[0x0=>0x1]	8793287	1			T1	9833		T2	184209		T3	14484
transitions[0x1=>0x0]	8793306	1			T1	9833		T2	184209		T3	14484

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19743255	1			T1	23388		T2	379901		T3	31706
all_pins[0]	values[0x1]	22330	1			T1	10		T2	246		T3	25
all_pins[0]	transitions[0x0=>0x1]	22237	1			T1	10		T2	246		T3	25
all_pins[0]	transitions[0x1=>0x0]	8770623	1			T1	9823		T2	183962		T3	14459
all_pins[1]	values[0x0]	19765108	1			T1	23398		T2	380144		T3	31731
all_pins[1]	values[0x1]	477	1			T2	3		T11	10		T23	1
all_pins[1]	transitions[0x0=>0x1]	412	1			T2	1		T11	10		T23	1
all_pins[1]	transitions[0x1=>0x0]	22265	1			T1	10		T2	244		T3	25
all_pins[2]	values[0x0]	10994888	1			T1	13575		T2	196185		T3	17272
all_pins[2]	values[0x1]	8770697	1			T1	9823		T2	183962		T3	14459
all_pins[2]	transitions[0x0=>0x1]	8770638	1			T1	9823		T2	183962		T3	14459
all_pins[2]	transitions[0x1=>0x0]	418	1			T2	3		T11	9		T23	1