Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1136 1 T2 7 T22 4 T11 34
all_values[1] 1136 1 T2 7 T22 4 T11 34
all_values[2] 1136 1 T2 7 T22 4 T11 34


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1716 1 T2 4 T22 2 T11 53
auto[1] 1692 1 T2 17 T22 10 T11 49


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1212 1 T2 7 T22 5 T11 37
auto[1] 2196 1 T2 14 T22 7 T11 65


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1924 1 T2 11 T22 9 T11 58
auto[1] 1484 1 T2 10 T22 3 T11 44


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 230 1 T2 1 T11 9 T12 6
all_values[0] auto[0] auto[0] auto[1] 102 1 T11 4 T12 3 T13 4
all_values[0] auto[0] auto[1] auto[0] 211 1 T22 1 T11 7 T12 7
all_values[0] auto[0] auto[1] auto[1] 110 1 T2 2 T22 2 T11 2
all_values[0] auto[1] auto[0] auto[1] 262 1 T11 9 T12 5 T127 1
all_values[0] auto[1] auto[1] auto[1] 221 1 T2 4 T22 1 T11 3
all_values[1] auto[0] auto[0] auto[0] 174 1 T2 1 T22 1 T11 5
all_values[1] auto[0] auto[0] auto[1] 149 1 T11 6 T12 2 T127 1
all_values[1] auto[0] auto[1] auto[0] 157 1 T22 1 T11 3 T12 5
all_values[1] auto[0] auto[1] auto[1] 141 1 T2 2 T22 1 T11 3
all_values[1] auto[1] auto[0] auto[1] 246 1 T2 2 T22 1 T11 6
all_values[1] auto[1] auto[1] auto[1] 269 1 T2 2 T11 11 T12 7
all_values[2] auto[0] auto[0] auto[0] 219 1 T11 4 T12 6 T127 1
all_values[2] auto[0] auto[0] auto[1] 99 1 T11 1 T12 3 T127 2
all_values[2] auto[0] auto[1] auto[0] 221 1 T2 5 T22 2 T11 9
all_values[2] auto[0] auto[1] auto[1] 111 1 T22 1 T11 5 T12 2
all_values[2] auto[1] auto[0] auto[1] 235 1 T11 9 T12 2 T127 2
all_values[2] auto[1] auto[1] auto[1] 251 1 T2 2 T22 1 T11 6


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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