Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4750	1			T1	6		T2	107		T3	8
sha2_none	4840	1			T1	6		T2	81		T3	10
sha2_512	8156	1			T1	2		T2	89		T3	6
sha2_384	7892	1			T1	7		T2	91		T3	11
sha2_256	6909	1			T1	4		T2	92		T3	9

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20139

1

T1

14

T2

238

T3

19

auto[1]

12849

1

T1

11

T2

230

T3

26

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12819

1

T1

16

T2

222

T3

18

auto[1]

20169

1

T1

9

T2

246

T3

27

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17192

1

T1

25

T2

303

T3

25

disabled

15796

1

T2

165

T3

20

T6

10

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5185	1			T1	1		T2	100		T3	5
key_none	8114	1			T1	5		T2	67		T3	7
key_1024	4771	1			T1	4		T2	65		T3	11
key_512	4133	1			T2	67		T3	5		T6	5
key_384	3764	1			T1	3		T2	62		T3	7
key_256	3604	1			T1	8		T2	48		T3	6
key_128	3331	1			T1	3		T2	58		T3	4

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20376

1

T1

12

T2

241

T3

22

auto[1]

12612

1

T1

13

T2

227

T3

23

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

32783

1

T1

25

T2

467

T3

45

disabled

205

1

T2

1

T6

4

T62

3

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1802

1

T1

3

T2

31

T3

2

enabled

auto[0]

auto[0]

auto[1]

1783

1

T1

5

T2

37

T3

3

enabled

auto[0]

auto[1]

auto[0]

1790

1

T1

4

T2

41

T3

3

enabled

auto[0]

auto[1]

auto[1]

1835

1

T1

4

T2

28

T4

2

enabled

auto[1]

auto[0]

auto[0]

4526

1

T1

3

T2

43

T3

2

enabled

auto[1]

auto[0]

auto[1]

1788

1

T1

3

T2

41

T3

3

enabled

auto[1]

auto[1]

auto[0]

1908

1

T1

2

T2

41

T3

4

enabled

auto[1]

auto[1]

auto[1]

1760

1

T1

1

T2

41

T3

8

disabled

auto[0]

auto[0]

auto[0]

1414

1

T2

24

T3

3

T4

7

disabled

auto[0]

auto[0]

auto[1]

1349

1

T2

18

T6

2

T4

1

disabled

auto[0]

auto[1]

auto[0]

1433

1

T2

21

T3

3

T6

3

disabled

auto[0]

auto[1]

auto[1]

1413

1

T2

22

T3

4

T6

1

disabled

auto[1]

auto[0]

auto[0]

6165

1

T2

21

T3

3

T6

2

disabled

auto[1]

auto[0]

auto[1]

1312

1

T2

23

T3

3

T19

1

disabled

auto[1]

auto[1]

auto[0]

1338

1

T2

19

T3

2

T6

1

disabled

auto[1]

auto[1]

auto[1]

1372

1

T2

17

T3

2

T6

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17101

1

T1

25

T2

302

T3

25

enabled

disabled

91

1

T2

1

T6

2

T139

1

disabled

disabled

114

1

T6

2

T62

3

T139

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15682

1

T2

165

T3

20

T6

8

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1244	1			T1	1		T2	25		T3	1
key_invalid	sha2_none	952	1			T2	20		T3	2		T4	2
key_invalid	sha2_512	986	1			T2	21		T6	2		T4	6
key_invalid	sha2_384	945	1			T2	18		T3	2		T5	5
key_invalid	sha2_256	942	1			T2	15		T6	2		T4	2
key_none	sha2_invalid	571	1			T1	1		T2	10		T3	1
key_none	sha2_none	653	1			T1	1		T2	11		T3	1
key_none	sha2_512	2615	1			T1	1		T2	16		T3	3
key_none	sha2_384	2574	1			T1	2		T2	15		T4	2
key_none	sha2_256	1657	1			T2	14		T3	1		T4	2
key_1024	sha2_invalid	589	1			T2	22		T3	1		T6	1
key_1024	sha2_none	649	1			T1	1		T2	5		T3	1
key_1024	sha2_512	1783	1			T2	12		T3	3		T6	1
key_1024	sha2_384	999	1			T1	2		T2	10		T3	3
key_512	sha2_invalid	550	1			T2	15		T4	1		T20	1
key_512	sha2_none	644	1			T2	10		T3	3		T4	1
key_512	sha2_512	653	1			T2	14		T6	2		T4	1
key_512	sha2_384	1272	1			T2	16		T3	1		T6	1
key_512	sha2_256	947	1			T2	10		T3	1		T6	2
key_384	sha2_invalid	566	1			T2	14		T3	2		T4	1
key_384	sha2_none	609	1			T2	13		T3	1		T4	2
key_384	sha2_512	692	1			T2	7		T6	1		T4	1
key_384	sha2_384	678	1			T1	2		T2	13		T3	3
key_384	sha2_256	1168	1			T1	1		T2	14		T3	1
key_256	sha2_invalid	576	1			T1	3		T2	9		T3	2
key_256	sha2_none	673	1			T1	2		T2	11		T3	2
key_256	sha2_512	703	1			T1	1		T2	7		T4	3
key_256	sha2_384	745	1			T2	9		T3	1		T6	2
key_256	sha2_256	853	1			T1	2		T2	11		T3	1
key_128	sha2_invalid	637	1			T2	12		T3	1		T4	1
key_128	sha2_none	652	1			T1	2		T2	11		T5	1
key_128	sha2_512	707	1			T2	12		T6	2		T4	1
key_128	sha2_384	659	1			T1	1		T2	10		T3	1
key_128	sha2_256	618	1			T2	12		T3	2		T4	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

701

1

T1

1

T2

15

T3

3

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1244	1			T1	1		T2	25		T3	1
key_invalid	sha2_none	952	1			T2	20		T3	2		T4	2
key_invalid	sha2_512	986	1			T2	21		T6	2		T4	6
key_invalid	sha2_384	945	1			T2	18		T3	2		T5	5
key_invalid	sha2_256	942	1			T2	15		T6	2		T4	2
key_none	sha2_invalid	571	1			T1	1		T2	10		T3	1
key_none	sha2_none	653	1			T1	1		T2	11		T3	1
key_none	sha2_512	2615	1			T1	1		T2	16		T3	3
key_none	sha2_384	2574	1			T1	2		T2	15		T4	2
key_none	sha2_256	1657	1			T2	14		T3	1		T4	2
key_1024	sha2_invalid	589	1			T2	22		T3	1		T6	1
key_1024	sha2_none	649	1			T1	1		T2	5		T3	1
key_1024	sha2_512	1783	1			T2	12		T3	3		T6	1
key_1024	sha2_384	999	1			T1	2		T2	10		T3	3
key_1024	sha2_256	701	1			T1	1		T2	15		T3	3
key_512	sha2_invalid	550	1			T2	15		T4	1		T20	1
key_512	sha2_none	644	1			T2	10		T3	3		T4	1
key_512	sha2_512	653	1			T2	14		T6	2		T4	1
key_512	sha2_384	1272	1			T2	16		T3	1		T6	1
key_512	sha2_256	947	1			T2	10		T3	1		T6	2
key_384	sha2_invalid	566	1			T2	14		T3	2		T4	1
key_384	sha2_none	609	1			T2	13		T3	1		T4	2
key_384	sha2_512	692	1			T2	7		T6	1		T4	1
key_384	sha2_384	678	1			T1	2		T2	13		T3	3
key_384	sha2_256	1168	1			T1	1		T2	14		T3	1
key_256	sha2_invalid	576	1			T1	3		T2	9		T3	2
key_256	sha2_none	673	1			T1	2		T2	11		T3	2
key_256	sha2_512	703	1			T1	1		T2	7		T4	3
key_256	sha2_384	745	1			T2	9		T3	1		T6	2
key_256	sha2_256	853	1			T1	2		T2	11		T3	1
key_128	sha2_invalid	637	1			T2	12		T3	1		T4	1
key_128	sha2_none	652	1			T1	2		T2	11		T5	1
key_128	sha2_512	707	1			T2	12		T6	2		T4	1
key_128	sha2_384	659	1			T1	1		T2	10		T3	1
key_128	sha2_256	618	1			T2	12		T3	2		T4	1