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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 95.40 97.22 100.00 94.12 98.27 98.48 99.85


Total test records in report: 657
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T75 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2845735298 Aug 04 04:36:10 PM PDT 24 Aug 04 04:36:12 PM PDT 24 191111726 ps
T537 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1581271611 Aug 04 04:36:27 PM PDT 24 Aug 04 04:36:27 PM PDT 24 54234803 ps
T98 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2823215579 Aug 04 04:36:22 PM PDT 24 Aug 04 04:36:23 PM PDT 24 139415578 ps
T538 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2926860515 Aug 04 04:36:23 PM PDT 24 Aug 04 04:36:24 PM PDT 24 15006542 ps
T539 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1238021437 Aug 04 04:36:26 PM PDT 24 Aug 04 04:36:30 PM PDT 24 171461590 ps
T76 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.95831340 Aug 04 04:36:16 PM PDT 24 Aug 04 04:36:18 PM PDT 24 105099317 ps
T116 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.793590261 Aug 04 04:35:58 PM PDT 24 Aug 04 04:35:59 PM PDT 24 18673330 ps
T99 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2684836425 Aug 04 04:36:15 PM PDT 24 Aug 04 04:36:16 PM PDT 24 14617600 ps
T540 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3614849147 Aug 04 04:36:17 PM PDT 24 Aug 04 04:39:31 PM PDT 24 56329036829 ps
T133 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4293921723 Aug 04 04:35:56 PM PDT 24 Aug 04 04:35:59 PM PDT 24 86444715 ps
T128 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1023571468 Aug 04 04:37:25 PM PDT 24 Aug 04 04:37:28 PM PDT 24 316179438 ps
T541 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3298227664 Aug 04 04:36:07 PM PDT 24 Aug 04 04:36:09 PM PDT 24 64523171 ps
T542 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.905569688 Aug 04 04:36:22 PM PDT 24 Aug 04 04:36:25 PM PDT 24 40199538 ps
T543 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1045090274 Aug 04 04:36:34 PM PDT 24 Aug 04 04:36:35 PM PDT 24 51194850 ps
T544 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2072653487 Aug 04 04:36:44 PM PDT 24 Aug 04 04:36:44 PM PDT 24 31340635 ps
T117 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1426651828 Aug 04 04:35:59 PM PDT 24 Aug 04 04:36:01 PM PDT 24 48039668 ps
T545 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2447268028 Aug 04 04:36:10 PM PDT 24 Aug 04 04:36:10 PM PDT 24 21803799 ps
T546 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3205142362 Aug 04 04:36:27 PM PDT 24 Aug 04 04:36:28 PM PDT 24 28940296 ps
T547 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2295492280 Aug 04 04:36:00 PM PDT 24 Aug 04 04:36:03 PM PDT 24 129587540 ps
T118 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.699454265 Aug 04 04:37:14 PM PDT 24 Aug 04 04:37:15 PM PDT 24 194635453 ps
T548 /workspace/coverage/cover_reg_top/26.hmac_intr_test.591368541 Aug 04 04:36:37 PM PDT 24 Aug 04 04:36:38 PM PDT 24 43012640 ps
T549 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3659175523 Aug 04 04:36:14 PM PDT 24 Aug 04 04:36:17 PM PDT 24 86213453 ps
T550 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1370063783 Aug 04 04:37:12 PM PDT 24 Aug 04 04:37:13 PM PDT 24 42034242 ps
T551 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3801811928 Aug 04 04:35:54 PM PDT 24 Aug 04 04:37:18 PM PDT 24 16966283828 ps
T129 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1939153272 Aug 04 04:36:30 PM PDT 24 Aug 04 04:36:35 PM PDT 24 456212659 ps
T552 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3731957210 Aug 04 04:36:40 PM PDT 24 Aug 04 04:36:44 PM PDT 24 187879153 ps
T553 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2078363884 Aug 04 04:35:51 PM PDT 24 Aug 04 04:35:53 PM PDT 24 26491799 ps
T554 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1029334279 Aug 04 04:36:27 PM PDT 24 Aug 04 04:36:29 PM PDT 24 84172424 ps
T555 /workspace/coverage/cover_reg_top/2.hmac_intr_test.325967449 Aug 04 04:36:29 PM PDT 24 Aug 04 04:36:29 PM PDT 24 11600423 ps
T556 /workspace/coverage/cover_reg_top/9.hmac_intr_test.59352570 Aug 04 04:36:10 PM PDT 24 Aug 04 04:36:10 PM PDT 24 37513444 ps
T557 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1247962256 Aug 04 04:36:04 PM PDT 24 Aug 04 04:36:06 PM PDT 24 309676359 ps
T119 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.392767321 Aug 04 04:35:51 PM PDT 24 Aug 04 04:35:53 PM PDT 24 527078197 ps
T120 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1810364855 Aug 04 04:36:10 PM PDT 24 Aug 04 04:36:12 PM PDT 24 180459630 ps
T121 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3825129042 Aug 04 04:36:11 PM PDT 24 Aug 04 04:36:14 PM PDT 24 292895336 ps
T558 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3832270370 Aug 04 04:36:08 PM PDT 24 Aug 04 04:36:10 PM PDT 24 267962566 ps
T122 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.18510973 Aug 04 04:36:11 PM PDT 24 Aug 04 04:36:13 PM PDT 24 149354204 ps
T559 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.512599266 Aug 04 04:36:23 PM PDT 24 Aug 04 04:36:27 PM PDT 24 409245641 ps
T560 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3286637341 Aug 04 04:36:00 PM PDT 24 Aug 04 04:36:01 PM PDT 24 15534152 ps
T561 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.575138033 Aug 04 04:36:27 PM PDT 24 Aug 04 04:36:29 PM PDT 24 48985954 ps
T562 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1690996761 Aug 04 04:36:21 PM PDT 24 Aug 04 04:36:22 PM PDT 24 50432177 ps
T136 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.254095149 Aug 04 04:36:12 PM PDT 24 Aug 04 04:36:16 PM PDT 24 460669470 ps
T100 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1429661496 Aug 04 04:36:21 PM PDT 24 Aug 04 04:36:27 PM PDT 24 340362539 ps
T563 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.432678126 Aug 04 04:36:26 PM PDT 24 Aug 04 04:36:29 PM PDT 24 478004820 ps
T564 /workspace/coverage/cover_reg_top/10.hmac_intr_test.937647437 Aug 04 04:37:26 PM PDT 24 Aug 04 04:37:27 PM PDT 24 15367939 ps
T565 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1120207024 Aug 04 04:35:54 PM PDT 24 Aug 04 04:35:55 PM PDT 24 23384632 ps
T566 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3570534475 Aug 04 04:36:23 PM PDT 24 Aug 04 04:36:23 PM PDT 24 16820878 ps
T567 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3675835505 Aug 04 04:36:16 PM PDT 24 Aug 04 04:36:22 PM PDT 24 18903843 ps
T130 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3044785292 Aug 04 04:36:20 PM PDT 24 Aug 04 04:36:24 PM PDT 24 127497730 ps
T568 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1516547146 Aug 04 04:36:06 PM PDT 24 Aug 04 04:36:10 PM PDT 24 220658995 ps
T138 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.818145669 Aug 04 04:36:11 PM PDT 24 Aug 04 04:36:14 PM PDT 24 315049580 ps
T569 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2474052851 Aug 04 04:36:05 PM PDT 24 Aug 04 04:36:08 PM PDT 24 362639816 ps
T101 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1497515163 Aug 04 04:36:25 PM PDT 24 Aug 04 04:36:26 PM PDT 24 26170832 ps
T570 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1732918667 Aug 04 04:36:07 PM PDT 24 Aug 04 04:36:08 PM PDT 24 39633241 ps
T571 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3049657339 Aug 04 04:36:15 PM PDT 24 Aug 04 04:36:17 PM PDT 24 67610311 ps
T572 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3002931684 Aug 04 04:35:54 PM PDT 24 Aug 04 04:35:55 PM PDT 24 46074039 ps
T573 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1257823682 Aug 04 04:36:17 PM PDT 24 Aug 04 04:36:18 PM PDT 24 15148842 ps
T574 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3499324687 Aug 04 04:37:08 PM PDT 24 Aug 04 04:37:10 PM PDT 24 94345954 ps
T575 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2330512985 Aug 04 04:36:02 PM PDT 24 Aug 04 04:36:03 PM PDT 24 42071460 ps
T576 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.270559909 Aug 04 04:36:29 PM PDT 24 Aug 04 04:36:32 PM PDT 24 156382428 ps
T577 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3799004602 Aug 04 04:36:10 PM PDT 24 Aug 04 04:36:13 PM PDT 24 83140628 ps
T578 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1608126190 Aug 04 04:36:27 PM PDT 24 Aug 04 04:36:29 PM PDT 24 250906420 ps
T579 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2046819832 Aug 04 04:35:59 PM PDT 24 Aug 04 04:36:07 PM PDT 24 271592154 ps
T580 /workspace/coverage/cover_reg_top/48.hmac_intr_test.218556891 Aug 04 04:36:18 PM PDT 24 Aug 04 04:36:23 PM PDT 24 62023067 ps
T581 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2775896634 Aug 04 04:36:00 PM PDT 24 Aug 04 04:36:01 PM PDT 24 69737463 ps
T131 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1537731282 Aug 04 04:35:58 PM PDT 24 Aug 04 04:36:02 PM PDT 24 426292981 ps
T132 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.809056980 Aug 04 04:36:13 PM PDT 24 Aug 04 04:36:17 PM PDT 24 638354997 ps
T582 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1454039209 Aug 04 04:36:27 PM PDT 24 Aug 04 04:36:30 PM PDT 24 319301106 ps
T102 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1070963322 Aug 04 04:36:13 PM PDT 24 Aug 04 04:36:21 PM PDT 24 310761486 ps
T583 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2338682949 Aug 04 04:36:34 PM PDT 24 Aug 04 04:36:35 PM PDT 24 18384781 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.983357911 Aug 04 04:36:22 PM PDT 24 Aug 04 04:36:23 PM PDT 24 14719517 ps
T584 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3543240306 Aug 04 04:36:17 PM PDT 24 Aug 04 04:36:18 PM PDT 24 23789883 ps
T585 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4187928465 Aug 04 04:36:16 PM PDT 24 Aug 04 04:36:19 PM PDT 24 85453119 ps
T586 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.46739646 Aug 04 04:36:16 PM PDT 24 Aug 04 04:36:16 PM PDT 24 25688296 ps
T587 /workspace/coverage/cover_reg_top/6.hmac_intr_test.907508615 Aug 04 04:36:34 PM PDT 24 Aug 04 04:36:35 PM PDT 24 61703839 ps
T588 /workspace/coverage/cover_reg_top/15.hmac_intr_test.4238809174 Aug 04 04:36:22 PM PDT 24 Aug 04 04:36:22 PM PDT 24 27635338 ps
T589 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.430783298 Aug 04 04:36:18 PM PDT 24 Aug 04 04:49:10 PM PDT 24 1277066426193 ps
T590 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1091043364 Aug 04 04:36:37 PM PDT 24 Aug 04 04:36:38 PM PDT 24 32914040 ps
T591 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2266671031 Aug 04 04:36:13 PM PDT 24 Aug 04 04:36:19 PM PDT 24 1421006827 ps
T592 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3588271342 Aug 04 04:36:17 PM PDT 24 Aug 04 04:36:17 PM PDT 24 24949137 ps
T593 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3999979004 Aug 04 04:36:11 PM PDT 24 Aug 04 04:36:15 PM PDT 24 649754887 ps
T594 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3244817156 Aug 04 04:36:25 PM PDT 24 Aug 04 04:36:26 PM PDT 24 31413923 ps
T595 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.348119168 Aug 04 04:36:00 PM PDT 24 Aug 04 04:36:16 PM PDT 24 2924761325 ps
T596 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1380540944 Aug 04 04:36:02 PM PDT 24 Aug 04 04:36:03 PM PDT 24 113619657 ps
T597 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.793757151 Aug 04 04:36:00 PM PDT 24 Aug 04 04:36:08 PM PDT 24 241079204 ps
T598 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.304446390 Aug 04 04:36:27 PM PDT 24 Aug 04 04:36:29 PM PDT 24 51898014 ps
T599 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.415864080 Aug 04 04:36:01 PM PDT 24 Aug 04 04:36:03 PM PDT 24 64395443 ps
T600 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1030860453 Aug 04 04:36:25 PM PDT 24 Aug 04 04:36:26 PM PDT 24 33573914 ps
T601 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2072486708 Aug 04 04:36:15 PM PDT 24 Aug 04 04:36:21 PM PDT 24 378888223 ps
T602 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1094692367 Aug 04 04:36:13 PM PDT 24 Aug 04 04:36:14 PM PDT 24 119151632 ps
T603 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1929211855 Aug 04 04:36:13 PM PDT 24 Aug 04 04:36:15 PM PDT 24 679537866 ps
T604 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1363065058 Aug 04 04:36:32 PM PDT 24 Aug 04 04:36:33 PM PDT 24 15657066 ps
T605 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1781595705 Aug 04 04:35:55 PM PDT 24 Aug 04 04:36:01 PM PDT 24 2961481360 ps
T606 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1587942901 Aug 04 04:36:25 PM PDT 24 Aug 04 04:36:27 PM PDT 24 34873901 ps
T607 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1388787658 Aug 04 04:36:25 PM PDT 24 Aug 04 04:36:26 PM PDT 24 59080779 ps
T104 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.133520265 Aug 04 04:36:17 PM PDT 24 Aug 04 04:36:18 PM PDT 24 230814745 ps
T608 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4150065356 Aug 04 04:36:08 PM PDT 24 Aug 04 04:36:09 PM PDT 24 51585376 ps
T609 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1440024328 Aug 04 04:36:23 PM PDT 24 Aug 04 04:36:24 PM PDT 24 59325095 ps
T105 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4038694189 Aug 04 04:36:16 PM PDT 24 Aug 04 04:36:19 PM PDT 24 2558964435 ps
T610 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1338673920 Aug 04 04:36:25 PM PDT 24 Aug 04 04:36:26 PM PDT 24 12518295 ps
T611 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3385914630 Aug 04 04:36:12 PM PDT 24 Aug 04 04:36:18 PM PDT 24 175600492 ps
T612 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2870224635 Aug 04 04:36:14 PM PDT 24 Aug 04 04:36:15 PM PDT 24 21060134 ps
T134 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3389539236 Aug 04 04:36:12 PM PDT 24 Aug 04 04:36:15 PM PDT 24 385321718 ps
T613 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2983132087 Aug 04 04:36:10 PM PDT 24 Aug 04 04:36:11 PM PDT 24 17572915 ps
T614 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4059817661 Aug 04 04:35:57 PM PDT 24 Aug 04 04:41:45 PM PDT 24 24415145389 ps
T615 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1728595238 Aug 04 04:36:11 PM PDT 24 Aug 04 04:36:12 PM PDT 24 23827003 ps
T106 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.605874054 Aug 04 04:36:02 PM PDT 24 Aug 04 04:36:03 PM PDT 24 28353381 ps
T616 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.372768812 Aug 04 04:35:52 PM PDT 24 Aug 04 04:35:54 PM PDT 24 282319959 ps
T617 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1198612043 Aug 04 04:35:58 PM PDT 24 Aug 04 04:36:03 PM PDT 24 48703030 ps
T618 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1814246880 Aug 04 04:36:07 PM PDT 24 Aug 04 04:36:09 PM PDT 24 248605198 ps
T619 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1700924622 Aug 04 04:36:18 PM PDT 24 Aug 04 04:36:18 PM PDT 24 14070531 ps
T620 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3258576060 Aug 04 04:36:01 PM PDT 24 Aug 04 04:36:02 PM PDT 24 39251949 ps
T621 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1130726342 Aug 04 04:36:12 PM PDT 24 Aug 04 04:36:12 PM PDT 24 17173809 ps
T622 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3500133845 Aug 04 04:36:22 PM PDT 24 Aug 04 04:36:23 PM PDT 24 11289108 ps
T107 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.905558498 Aug 04 04:36:20 PM PDT 24 Aug 04 04:36:21 PM PDT 24 60572785 ps
T623 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3144203352 Aug 04 04:35:58 PM PDT 24 Aug 04 04:36:06 PM PDT 24 172430609 ps
T624 /workspace/coverage/cover_reg_top/3.hmac_intr_test.578784191 Aug 04 04:36:25 PM PDT 24 Aug 04 04:36:25 PM PDT 24 16168981 ps
T625 /workspace/coverage/cover_reg_top/43.hmac_intr_test.437086887 Aug 04 04:36:31 PM PDT 24 Aug 04 04:36:32 PM PDT 24 60430428 ps
T108 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2961906632 Aug 04 04:35:56 PM PDT 24 Aug 04 04:35:59 PM PDT 24 57880022 ps
T109 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4234228466 Aug 04 04:36:25 PM PDT 24 Aug 04 04:36:25 PM PDT 24 33741058 ps
T626 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.402712996 Aug 04 04:35:59 PM PDT 24 Aug 04 04:36:00 PM PDT 24 21870307 ps
T627 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3934760049 Aug 04 04:36:04 PM PDT 24 Aug 04 04:36:05 PM PDT 24 18871488 ps
T628 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2674641730 Aug 04 04:36:31 PM PDT 24 Aug 04 04:36:32 PM PDT 24 28181233 ps
T110 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3522473982 Aug 04 04:36:08 PM PDT 24 Aug 04 04:36:09 PM PDT 24 113586885 ps
T629 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.978536965 Aug 04 04:35:58 PM PDT 24 Aug 04 04:35:59 PM PDT 24 23948578 ps
T630 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3697990213 Aug 04 04:36:35 PM PDT 24 Aug 04 04:36:39 PM PDT 24 1169480255 ps
T631 /workspace/coverage/cover_reg_top/34.hmac_intr_test.308192540 Aug 04 04:36:26 PM PDT 24 Aug 04 04:36:27 PM PDT 24 31702723 ps
T111 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1711069662 Aug 04 04:35:57 PM PDT 24 Aug 04 04:35:58 PM PDT 24 60527645 ps
T632 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2799138772 Aug 04 04:36:47 PM PDT 24 Aug 04 04:37:00 PM PDT 24 316154039 ps
T112 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2115202300 Aug 04 04:36:08 PM PDT 24 Aug 04 04:36:09 PM PDT 24 70814285 ps
T633 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2145610682 Aug 04 04:36:22 PM PDT 24 Aug 04 04:36:24 PM PDT 24 112904378 ps
T634 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1328256710 Aug 04 04:36:04 PM PDT 24 Aug 04 04:36:09 PM PDT 24 851247045 ps
T635 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2077293657 Aug 04 04:36:31 PM PDT 24 Aug 04 04:36:33 PM PDT 24 84957597 ps
T636 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.999480100 Aug 04 04:36:33 PM PDT 24 Aug 04 04:36:35 PM PDT 24 92252392 ps
T637 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2717068915 Aug 04 04:36:20 PM PDT 24 Aug 04 04:36:24 PM PDT 24 80360035 ps
T638 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1891899068 Aug 04 04:36:34 PM PDT 24 Aug 04 04:36:35 PM PDT 24 21047266 ps
T639 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3049557418 Aug 04 04:36:19 PM PDT 24 Aug 04 04:36:20 PM PDT 24 13895569 ps
T640 /workspace/coverage/cover_reg_top/20.hmac_intr_test.64673217 Aug 04 04:36:30 PM PDT 24 Aug 04 04:36:36 PM PDT 24 55114997 ps
T641 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3362805947 Aug 04 04:36:06 PM PDT 24 Aug 04 04:36:08 PM PDT 24 86668297 ps
T642 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.296786567 Aug 04 04:36:09 PM PDT 24 Aug 04 04:36:11 PM PDT 24 404535056 ps
T643 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2350404756 Aug 04 04:36:19 PM PDT 24 Aug 04 04:36:20 PM PDT 24 34434607 ps
T113 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1313355382 Aug 04 04:36:19 PM PDT 24 Aug 04 04:36:20 PM PDT 24 23697423 ps
T644 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1511943668 Aug 04 04:36:31 PM PDT 24 Aug 04 04:36:32 PM PDT 24 78730241 ps
T645 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1713737853 Aug 04 04:36:10 PM PDT 24 Aug 04 04:36:11 PM PDT 24 132220933 ps
T646 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3214500924 Aug 04 04:36:05 PM PDT 24 Aug 04 04:36:07 PM PDT 24 198899008 ps
T137 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4049881973 Aug 04 04:36:16 PM PDT 24 Aug 04 04:36:19 PM PDT 24 154254623 ps
T135 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1873159449 Aug 04 04:36:23 PM PDT 24 Aug 04 04:36:27 PM PDT 24 144434648 ps
T647 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3770944401 Aug 04 04:36:22 PM PDT 24 Aug 04 04:36:23 PM PDT 24 17298058 ps
T648 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.41312866 Aug 04 04:36:04 PM PDT 24 Aug 04 04:36:06 PM PDT 24 44775184 ps
T649 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1547237436 Aug 04 04:35:50 PM PDT 24 Aug 04 04:35:53 PM PDT 24 142110671 ps
T650 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.700872457 Aug 04 04:36:23 PM PDT 24 Aug 04 04:36:24 PM PDT 24 28346768 ps
T651 /workspace/coverage/cover_reg_top/49.hmac_intr_test.409159377 Aug 04 04:36:28 PM PDT 24 Aug 04 04:36:29 PM PDT 24 66422877 ps
T652 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1549545438 Aug 04 04:36:11 PM PDT 24 Aug 04 04:36:15 PM PDT 24 387383043 ps
T653 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1572668697 Aug 04 04:36:25 PM PDT 24 Aug 04 04:36:27 PM PDT 24 269695052 ps
T654 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3250024239 Aug 04 04:36:14 PM PDT 24 Aug 04 04:36:16 PM PDT 24 56925263 ps
T655 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3284853045 Aug 04 04:36:28 PM PDT 24 Aug 04 04:36:29 PM PDT 24 59888435 ps
T656 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2908775980 Aug 04 04:36:12 PM PDT 24 Aug 04 04:36:13 PM PDT 24 131247853 ps
T657 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3203272180 Aug 04 04:36:17 PM PDT 24 Aug 04 04:43:12 PM PDT 24 38298860458 ps

Test location /workspace/coverage/default/11.hmac_stress_all.3068516624
Short name T2
Test name
Test status
Simulation time 151885004710 ps
CPU time 4906.28 seconds
Started Aug 04 04:49:12 PM PDT 24
Finished Aug 04 06:10:58 PM PDT 24
Peak memory 837960 kb
Host smart-dc4881a9-d2e0-4a83-94c4-5efc82bb0269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068516624 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3068516624
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2861926584
Short name T11
Test name
Test status
Simulation time 11004975566 ps
CPU time 630.82 seconds
Started Aug 04 04:47:35 PM PDT 24
Finished Aug 04 04:58:06 PM PDT 24
Peak memory 252384 kb
Host smart-6927686f-43b9-4f99-8dbd-33aa9ed1eee5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861926584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2861926584
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2092097150
Short name T10
Test name
Test status
Simulation time 419880246350 ps
CPU time 6108.8 seconds
Started Aug 04 04:47:45 PM PDT 24
Finished Aug 04 06:29:34 PM PDT 24
Peak memory 862900 kb
Host smart-ae0504ee-c9e4-4c1b-aaf7-ba61ac53926b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092097150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2092097150
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1023571468
Short name T128
Test name
Test status
Simulation time 316179438 ps
CPU time 2.78 seconds
Started Aug 04 04:37:25 PM PDT 24
Finished Aug 04 04:37:28 PM PDT 24
Peak memory 199972 kb
Host smart-002c0034-600d-4a55-805a-37e6a29a8e90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023571468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1023571468
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1845968426
Short name T5
Test name
Test status
Simulation time 1990122567 ps
CPU time 110.63 seconds
Started Aug 04 04:50:42 PM PDT 24
Finished Aug 04 04:52:32 PM PDT 24
Peak memory 199840 kb
Host smart-0afba2ca-04e2-44d9-8b47-39ee013902ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845968426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1845968426
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2630331399
Short name T16
Test name
Test status
Simulation time 16007295744 ps
CPU time 1497.89 seconds
Started Aug 04 04:52:08 PM PDT 24
Finished Aug 04 05:17:07 PM PDT 24
Peak memory 732684 kb
Host smart-8546c0da-f153-41c6-a407-a547529c107b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630331399 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2630331399
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4227887957
Short name T171
Test name
Test status
Simulation time 33561106 ps
CPU time 0.58 seconds
Started Aug 04 04:47:37 PM PDT 24
Finished Aug 04 04:47:38 PM PDT 24
Peak memory 195508 kb
Host smart-f84c315a-9d92-495e-b0f9-0bd2e02fccac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227887957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4227887957
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.905558498
Short name T107
Test name
Test status
Simulation time 60572785 ps
CPU time 0.9 seconds
Started Aug 04 04:36:20 PM PDT 24
Finished Aug 04 04:36:21 PM PDT 24
Peak memory 199768 kb
Host smart-5e955abe-46d7-428d-b1d7-8c0d9e1397b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905558498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.905558498
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1077596701
Short name T13
Test name
Test status
Simulation time 200149953184 ps
CPU time 5817.54 seconds
Started Aug 04 04:48:37 PM PDT 24
Finished Aug 04 06:25:36 PM PDT 24
Peak memory 816132 kb
Host smart-f5789055-67c2-4f7c-a1b8-6b1eb9ce550e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077596701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1077596701
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.786644306
Short name T71
Test name
Test status
Simulation time 72624405 ps
CPU time 0.81 seconds
Started Aug 04 04:47:34 PM PDT 24
Finished Aug 04 04:47:35 PM PDT 24
Peak memory 218364 kb
Host smart-93960da6-33a6-49a7-ad43-67a2fcaa4587
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786644306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.786644306
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1602300009
Short name T22
Test name
Test status
Simulation time 73463570577 ps
CPU time 1738.95 seconds
Started Aug 04 04:51:10 PM PDT 24
Finished Aug 04 05:20:10 PM PDT 24
Peak memory 749976 kb
Host smart-6d124d8c-8401-4120-99be-8f08f6220045
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602300009 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1602300009
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1537731282
Short name T131
Test name
Test status
Simulation time 426292981 ps
CPU time 3.99 seconds
Started Aug 04 04:35:58 PM PDT 24
Finished Aug 04 04:36:02 PM PDT 24
Peak memory 200160 kb
Host smart-161d835a-f56e-4a65-831c-2c0aed1fe7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537731282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1537731282
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.809056980
Short name T132
Test name
Test status
Simulation time 638354997 ps
CPU time 4.88 seconds
Started Aug 04 04:36:13 PM PDT 24
Finished Aug 04 04:36:17 PM PDT 24
Peak memory 200076 kb
Host smart-98222156-2b05-46d6-a5a9-00c73ebec331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809056980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.809056980
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1086097002
Short name T145
Test name
Test status
Simulation time 5568396896 ps
CPU time 150.36 seconds
Started Aug 04 04:50:13 PM PDT 24
Finished Aug 04 04:52:43 PM PDT 24
Peak memory 199952 kb
Host smart-1cb665fe-b0f4-418a-9dec-9f3e22770a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086097002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1086097002
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.392767321
Short name T119
Test name
Test status
Simulation time 527078197 ps
CPU time 2.21 seconds
Started Aug 04 04:35:51 PM PDT 24
Finished Aug 04 04:35:53 PM PDT 24
Peak memory 200088 kb
Host smart-a7bd1762-6c6f-4b59-a364-780aa2a5d177
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392767321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.392767321
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.95831340
Short name T76
Test name
Test status
Simulation time 105099317 ps
CPU time 1.83 seconds
Started Aug 04 04:36:16 PM PDT 24
Finished Aug 04 04:36:18 PM PDT 24
Peak memory 200104 kb
Host smart-a81fad78-b83f-4546-b5e4-9b88d836ee64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95831340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.95831340
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1431803717
Short name T294
Test name
Test status
Simulation time 276293555327 ps
CPU time 2342.3 seconds
Started Aug 04 04:47:34 PM PDT 24
Finished Aug 04 05:26:37 PM PDT 24
Peak memory 216284 kb
Host smart-f7604d6a-199e-4473-8f95-2919ab0f29a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1431803717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1431803717
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.4063300160
Short name T74
Test name
Test status
Simulation time 101768963 ps
CPU time 1.87 seconds
Started Aug 04 04:36:07 PM PDT 24
Finished Aug 04 04:36:09 PM PDT 24
Peak memory 199992 kb
Host smart-8010b88a-2f47-4df1-b0dd-e02a7632291d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063300160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.4063300160
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2707563590
Short name T17
Test name
Test status
Simulation time 284348715720 ps
CPU time 746.01 seconds
Started Aug 04 04:47:57 PM PDT 24
Finished Aug 04 05:00:23 PM PDT 24
Peak memory 651104 kb
Host smart-c669a272-07b2-4e88-9867-eb1b0456c579
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2707563590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2707563590
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1070963322
Short name T102
Test name
Test status
Simulation time 310761486 ps
CPU time 7.88 seconds
Started Aug 04 04:36:13 PM PDT 24
Finished Aug 04 04:36:21 PM PDT 24
Peak memory 200032 kb
Host smart-41e29702-abca-40fd-87e7-ee781d91874e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070963322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1070963322
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1781595705
Short name T605
Test name
Test status
Simulation time 2961481360 ps
CPU time 5.77 seconds
Started Aug 04 04:35:55 PM PDT 24
Finished Aug 04 04:36:01 PM PDT 24
Peak memory 198940 kb
Host smart-79682cb9-7c8b-4732-bf08-8192d60bbeee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781595705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1781595705
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1728595238
Short name T615
Test name
Test status
Simulation time 23827003 ps
CPU time 0.73 seconds
Started Aug 04 04:36:11 PM PDT 24
Finished Aug 04 04:36:12 PM PDT 24
Peak memory 197976 kb
Host smart-acf11767-dc95-4202-8733-f1c3ecca7933
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728595238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1728595238
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2670848593
Short name T535
Test name
Test status
Simulation time 272891508008 ps
CPU time 655.25 seconds
Started Aug 04 04:36:11 PM PDT 24
Finished Aug 04 04:47:07 PM PDT 24
Peak memory 225900 kb
Host smart-0f9b654d-10d7-403d-92c3-15a0a1e03a90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670848593 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2670848593
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.700872457
Short name T650
Test name
Test status
Simulation time 28346768 ps
CPU time 0.87 seconds
Started Aug 04 04:36:23 PM PDT 24
Finished Aug 04 04:36:24 PM PDT 24
Peak memory 199744 kb
Host smart-e20c91d1-b8e1-402f-b41e-07f1cd8ec440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700872457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.700872457
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1370063783
Short name T550
Test name
Test status
Simulation time 42034242 ps
CPU time 0.53 seconds
Started Aug 04 04:37:12 PM PDT 24
Finished Aug 04 04:37:13 PM PDT 24
Peak memory 194824 kb
Host smart-9b8fc064-69e4-4674-85a3-113b623f2f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370063783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1370063783
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2145610682
Short name T633
Test name
Test status
Simulation time 112904378 ps
CPU time 1.61 seconds
Started Aug 04 04:36:22 PM PDT 24
Finished Aug 04 04:36:24 PM PDT 24
Peak memory 200032 kb
Host smart-b8458d82-7029-4409-91af-83339fe49afb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145610682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2145610682
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2046819832
Short name T579
Test name
Test status
Simulation time 271592154 ps
CPU time 3.47 seconds
Started Aug 04 04:35:59 PM PDT 24
Finished Aug 04 04:36:07 PM PDT 24
Peak memory 200052 kb
Host smart-156f8cee-8b81-4c17-a599-c681489bdf34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046819832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2046819832
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.793757151
Short name T597
Test name
Test status
Simulation time 241079204 ps
CPU time 2.77 seconds
Started Aug 04 04:36:00 PM PDT 24
Finished Aug 04 04:36:08 PM PDT 24
Peak memory 198940 kb
Host smart-590dd908-db11-481c-9647-bfa96ab86022
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793757151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.793757151
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2799138772
Short name T632
Test name
Test status
Simulation time 316154039 ps
CPU time 13.04 seconds
Started Aug 04 04:36:47 PM PDT 24
Finished Aug 04 04:37:00 PM PDT 24
Peak memory 198136 kb
Host smart-0c0170b2-118f-4890-b49e-fd1cc6cdbc7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799138772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2799138772
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2870224635
Short name T612
Test name
Test status
Simulation time 21060134 ps
CPU time 0.78 seconds
Started Aug 04 04:36:14 PM PDT 24
Finished Aug 04 04:36:15 PM PDT 24
Peak memory 198056 kb
Host smart-d0ee3a11-d142-4b4d-ada4-d076be28ea1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870224635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2870224635
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2330512985
Short name T575
Test name
Test status
Simulation time 42071460 ps
CPU time 1.19 seconds
Started Aug 04 04:36:02 PM PDT 24
Finished Aug 04 04:36:03 PM PDT 24
Peak memory 199844 kb
Host smart-0d4dbc5c-e4f0-4a76-99cc-f0534db6f9b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330512985 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2330512985
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4234228466
Short name T109
Test name
Test status
Simulation time 33741058 ps
CPU time 0.68 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:25 PM PDT 24
Peak memory 198176 kb
Host smart-7f138304-190f-4c55-88ab-d1b38d942b2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234228466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4234228466
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1581271611
Short name T537
Test name
Test status
Simulation time 54234803 ps
CPU time 0.58 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 195056 kb
Host smart-647438c6-0ec2-48f1-8f9b-370063615664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581271611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1581271611
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.415864080
Short name T599
Test name
Test status
Simulation time 64395443 ps
CPU time 1.58 seconds
Started Aug 04 04:36:01 PM PDT 24
Finished Aug 04 04:36:03 PM PDT 24
Peak memory 200136 kb
Host smart-4d73f650-6900-4b84-89e0-ad27276cec21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415864080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.415864080
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2775896634
Short name T581
Test name
Test status
Simulation time 69737463 ps
CPU time 1.14 seconds
Started Aug 04 04:36:00 PM PDT 24
Finished Aug 04 04:36:01 PM PDT 24
Peak memory 199856 kb
Host smart-bfdbfd87-6f6f-4fc6-8b29-980cdcbae00b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775896634 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2775896634
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.793590261
Short name T116
Test name
Test status
Simulation time 18673330 ps
CPU time 0.89 seconds
Started Aug 04 04:35:58 PM PDT 24
Finished Aug 04 04:35:59 PM PDT 24
Peak memory 199432 kb
Host smart-b0cfe392-7481-4f04-842c-c2132e1cf473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793590261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.793590261
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.937647437
Short name T564
Test name
Test status
Simulation time 15367939 ps
CPU time 0.58 seconds
Started Aug 04 04:37:26 PM PDT 24
Finished Aug 04 04:37:27 PM PDT 24
Peak memory 194860 kb
Host smart-c7d34349-7b99-4022-8cc2-f145307e7d11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937647437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.937647437
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1814246880
Short name T618
Test name
Test status
Simulation time 248605198 ps
CPU time 1.15 seconds
Started Aug 04 04:36:07 PM PDT 24
Finished Aug 04 04:36:09 PM PDT 24
Peak memory 198580 kb
Host smart-1384e155-62ae-4a7f-9f5d-b464c5be6ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814246880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1814246880
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.512599266
Short name T559
Test name
Test status
Simulation time 409245641 ps
CPU time 4.11 seconds
Started Aug 04 04:36:23 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 199968 kb
Host smart-716cb7e9-8e46-4b8d-ad0c-45297ba57140
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512599266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.512599266
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3389539236
Short name T134
Test name
Test status
Simulation time 385321718 ps
CPU time 2.81 seconds
Started Aug 04 04:36:12 PM PDT 24
Finished Aug 04 04:36:15 PM PDT 24
Peak memory 200048 kb
Host smart-cb6e61d2-6901-417b-a2da-89bd0e166cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389539236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3389539236
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3203272180
Short name T657
Test name
Test status
Simulation time 38298860458 ps
CPU time 415.65 seconds
Started Aug 04 04:36:17 PM PDT 24
Finished Aug 04 04:43:12 PM PDT 24
Peak memory 216632 kb
Host smart-71a58120-9208-4972-a118-c1a73cd46d92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203272180 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3203272180
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.402712996
Short name T626
Test name
Test status
Simulation time 21870307 ps
CPU time 0.73 seconds
Started Aug 04 04:35:59 PM PDT 24
Finished Aug 04 04:36:00 PM PDT 24
Peak memory 198220 kb
Host smart-5a7a2bf0-648a-442d-8337-8ab134a532d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402712996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.402712996
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1732918667
Short name T570
Test name
Test status
Simulation time 39633241 ps
CPU time 0.59 seconds
Started Aug 04 04:36:07 PM PDT 24
Finished Aug 04 04:36:08 PM PDT 24
Peak memory 194868 kb
Host smart-fb3e46ee-0f06-4032-8285-0ca4666d8fa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732918667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1732918667
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3825129042
Short name T121
Test name
Test status
Simulation time 292895336 ps
CPU time 2.01 seconds
Started Aug 04 04:36:11 PM PDT 24
Finished Aug 04 04:36:14 PM PDT 24
Peak memory 199976 kb
Host smart-e9315d4d-cd65-4d93-b08d-427f09149c6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825129042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3825129042
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3832270370
Short name T558
Test name
Test status
Simulation time 267962566 ps
CPU time 2.42 seconds
Started Aug 04 04:36:08 PM PDT 24
Finished Aug 04 04:36:10 PM PDT 24
Peak memory 200136 kb
Host smart-a7294da2-115a-400e-b3d9-b24dd3230434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832270370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3832270370
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1939153272
Short name T129
Test name
Test status
Simulation time 456212659 ps
CPU time 4.42 seconds
Started Aug 04 04:36:30 PM PDT 24
Finished Aug 04 04:36:35 PM PDT 24
Peak memory 200132 kb
Host smart-0b8b0b68-2a94-4e60-aed5-4233e82a2fec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939153272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1939153272
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1094692367
Short name T602
Test name
Test status
Simulation time 119151632 ps
CPU time 1.54 seconds
Started Aug 04 04:36:13 PM PDT 24
Finished Aug 04 04:36:14 PM PDT 24
Peak memory 200056 kb
Host smart-9f8c7ca4-0717-4200-b114-536f9e48e2ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094692367 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1094692367
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3500133845
Short name T622
Test name
Test status
Simulation time 11289108 ps
CPU time 0.63 seconds
Started Aug 04 04:36:22 PM PDT 24
Finished Aug 04 04:36:23 PM PDT 24
Peak memory 194872 kb
Host smart-26ab059c-966b-4b8a-8f4c-6f840e6dd6c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500133845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3500133845
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.999480100
Short name T636
Test name
Test status
Simulation time 92252392 ps
CPU time 2.16 seconds
Started Aug 04 04:36:33 PM PDT 24
Finished Aug 04 04:36:35 PM PDT 24
Peak memory 200056 kb
Host smart-8aacee1e-1ed9-467a-b45b-9ddc45e4c18e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999480100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.999480100
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2078363884
Short name T553
Test name
Test status
Simulation time 26491799 ps
CPU time 1.28 seconds
Started Aug 04 04:35:51 PM PDT 24
Finished Aug 04 04:35:53 PM PDT 24
Peak memory 200088 kb
Host smart-c7fd849a-e30d-48dd-89dd-c457a526213e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078363884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2078363884
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.372768812
Short name T616
Test name
Test status
Simulation time 282319959 ps
CPU time 1.85 seconds
Started Aug 04 04:35:52 PM PDT 24
Finished Aug 04 04:35:54 PM PDT 24
Peak memory 200044 kb
Host smart-225d230f-b65e-400c-98b3-b99a70602342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372768812 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.372768812
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1713737853
Short name T645
Test name
Test status
Simulation time 132220933 ps
CPU time 0.79 seconds
Started Aug 04 04:36:10 PM PDT 24
Finished Aug 04 04:36:11 PM PDT 24
Peak memory 199852 kb
Host smart-197b86b1-803c-4132-b61f-938fb447cf59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713737853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1713737853
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1120207024
Short name T565
Test name
Test status
Simulation time 23384632 ps
CPU time 0.58 seconds
Started Aug 04 04:35:54 PM PDT 24
Finished Aug 04 04:35:55 PM PDT 24
Peak memory 194868 kb
Host smart-52c33242-0dda-4819-a947-b561056dcf57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120207024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1120207024
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3214500924
Short name T646
Test name
Test status
Simulation time 198899008 ps
CPU time 1.78 seconds
Started Aug 04 04:36:05 PM PDT 24
Finished Aug 04 04:36:07 PM PDT 24
Peak memory 199980 kb
Host smart-6cc926ad-d8c1-42b6-b19a-48a42c7de409
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214500924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3214500924
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3731957210
Short name T552
Test name
Test status
Simulation time 187879153 ps
CPU time 3.9 seconds
Started Aug 04 04:36:40 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 200188 kb
Host smart-68129e77-4482-4536-bc58-014aaeb79c25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731957210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3731957210
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1873159449
Short name T135
Test name
Test status
Simulation time 144434648 ps
CPU time 3.89 seconds
Started Aug 04 04:36:23 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 199976 kb
Host smart-c857a584-591a-492c-90ca-640ad07a73d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873159449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1873159449
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1608126190
Short name T578
Test name
Test status
Simulation time 250906420 ps
CPU time 1.84 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 04:36:29 PM PDT 24
Peak memory 200084 kb
Host smart-1a03d181-e239-45c8-b3ac-941a24337d18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608126190 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1608126190
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1030860453
Short name T600
Test name
Test status
Simulation time 33573914 ps
CPU time 0.7 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:26 PM PDT 24
Peak memory 197988 kb
Host smart-d80bfa87-13fc-4b9f-9a1b-8bed7e1a9b9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030860453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1030860453
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3675835505
Short name T567
Test name
Test status
Simulation time 18903843 ps
CPU time 0.58 seconds
Started Aug 04 04:36:16 PM PDT 24
Finished Aug 04 04:36:22 PM PDT 24
Peak memory 195032 kb
Host smart-efc9509b-6960-4eb0-95fb-d916dc11ef21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675835505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3675835505
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1929211855
Short name T603
Test name
Test status
Simulation time 679537866 ps
CPU time 1.86 seconds
Started Aug 04 04:36:13 PM PDT 24
Finished Aug 04 04:36:15 PM PDT 24
Peak memory 200076 kb
Host smart-6d7e5434-4df6-46c8-9d0c-c6317f6e005f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929211855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1929211855
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3144203352
Short name T623
Test name
Test status
Simulation time 172430609 ps
CPU time 2.31 seconds
Started Aug 04 04:35:58 PM PDT 24
Finished Aug 04 04:36:06 PM PDT 24
Peak memory 199984 kb
Host smart-9b97c136-1958-405a-ae32-b967c74091cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144203352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3144203352
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2845735298
Short name T75
Test name
Test status
Simulation time 191111726 ps
CPU time 1.71 seconds
Started Aug 04 04:36:10 PM PDT 24
Finished Aug 04 04:36:12 PM PDT 24
Peak memory 200040 kb
Host smart-51a269f6-9dbd-4a33-8349-42eb8fd51439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845735298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2845735298
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.430783298
Short name T589
Test name
Test status
Simulation time 1277066426193 ps
CPU time 772.06 seconds
Started Aug 04 04:36:18 PM PDT 24
Finished Aug 04 04:49:10 PM PDT 24
Peak memory 224752 kb
Host smart-053f9194-4d20-4484-bcd5-624b6b11e786
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430783298 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.430783298
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3522473982
Short name T110
Test name
Test status
Simulation time 113586885 ps
CPU time 0.92 seconds
Started Aug 04 04:36:08 PM PDT 24
Finished Aug 04 04:36:09 PM PDT 24
Peak memory 199496 kb
Host smart-54b57c7b-4358-41cd-aa71-c5569a114991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522473982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3522473982
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.4238809174
Short name T588
Test name
Test status
Simulation time 27635338 ps
CPU time 0.62 seconds
Started Aug 04 04:36:22 PM PDT 24
Finished Aug 04 04:36:22 PM PDT 24
Peak memory 194928 kb
Host smart-ba8c1f01-0f45-41a7-b94d-915afe51fde2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238809174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.4238809174
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.432678126
Short name T563
Test name
Test status
Simulation time 478004820 ps
CPU time 2.43 seconds
Started Aug 04 04:36:26 PM PDT 24
Finished Aug 04 04:36:29 PM PDT 24
Peak memory 200096 kb
Host smart-8bf9bb09-a282-4c7a-b594-d332cae04b4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432678126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.432678126
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2077293657
Short name T635
Test name
Test status
Simulation time 84957597 ps
CPU time 1.66 seconds
Started Aug 04 04:36:31 PM PDT 24
Finished Aug 04 04:36:33 PM PDT 24
Peak memory 199984 kb
Host smart-a64747be-812d-45c6-a261-c57b8d450fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077293657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2077293657
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4293921723
Short name T133
Test name
Test status
Simulation time 86444715 ps
CPU time 2.79 seconds
Started Aug 04 04:35:56 PM PDT 24
Finished Aug 04 04:35:59 PM PDT 24
Peak memory 200040 kb
Host smart-9c9cd605-332f-4700-b330-bfdc0c310a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293921723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4293921723
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3614849147
Short name T540
Test name
Test status
Simulation time 56329036829 ps
CPU time 194.22 seconds
Started Aug 04 04:36:17 PM PDT 24
Finished Aug 04 04:39:31 PM PDT 24
Peak memory 216496 kb
Host smart-d2f39139-e4de-48be-ab62-61aa87576735
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614849147 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3614849147
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2823215579
Short name T98
Test name
Test status
Simulation time 139415578 ps
CPU time 0.91 seconds
Started Aug 04 04:36:22 PM PDT 24
Finished Aug 04 04:36:23 PM PDT 24
Peak memory 199640 kb
Host smart-b24d77d8-c41f-4edd-b2a8-bce417adb920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823215579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2823215579
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1198612043
Short name T617
Test name
Test status
Simulation time 48703030 ps
CPU time 0.63 seconds
Started Aug 04 04:35:58 PM PDT 24
Finished Aug 04 04:36:03 PM PDT 24
Peak memory 194956 kb
Host smart-879e67d6-bc98-4cb2-bf3a-5a2c1b408db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198612043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1198612043
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3624402796
Short name T114
Test name
Test status
Simulation time 322312357 ps
CPU time 2.63 seconds
Started Aug 04 04:36:11 PM PDT 24
Finished Aug 04 04:36:14 PM PDT 24
Peak memory 199912 kb
Host smart-b85282d2-3da0-4e9a-8a1b-693ee0cacad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624402796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3624402796
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2295492280
Short name T547
Test name
Test status
Simulation time 129587540 ps
CPU time 2.83 seconds
Started Aug 04 04:36:00 PM PDT 24
Finished Aug 04 04:36:03 PM PDT 24
Peak memory 200076 kb
Host smart-04f6edff-1b79-436c-8a9d-080030665c77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295492280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2295492280
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1454039209
Short name T582
Test name
Test status
Simulation time 319301106 ps
CPU time 3.42 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 04:36:30 PM PDT 24
Peak memory 200052 kb
Host smart-b6be7f5f-4835-4624-a171-2ea9720d733f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454039209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1454039209
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.905569688
Short name T542
Test name
Test status
Simulation time 40199538 ps
CPU time 2.51 seconds
Started Aug 04 04:36:22 PM PDT 24
Finished Aug 04 04:36:25 PM PDT 24
Peak memory 200068 kb
Host smart-112d6984-80f5-467f-96a1-e9e90463afaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905569688 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.905569688
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.46739646
Short name T586
Test name
Test status
Simulation time 25688296 ps
CPU time 0.67 seconds
Started Aug 04 04:36:16 PM PDT 24
Finished Aug 04 04:36:16 PM PDT 24
Peak memory 198120 kb
Host smart-aecb497d-6d07-4df1-89c1-9fb1f46409ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46739646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.46739646
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1045090274
Short name T543
Test name
Test status
Simulation time 51194850 ps
CPU time 0.59 seconds
Started Aug 04 04:36:34 PM PDT 24
Finished Aug 04 04:36:35 PM PDT 24
Peak memory 195044 kb
Host smart-9757f1cd-5f1c-40dd-b54c-dd8869bebcb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045090274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1045090274
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1440024328
Short name T609
Test name
Test status
Simulation time 59325095 ps
CPU time 1.17 seconds
Started Aug 04 04:36:23 PM PDT 24
Finished Aug 04 04:36:24 PM PDT 24
Peak memory 198780 kb
Host smart-b6bd3ac2-39c8-44ae-99d5-61027c47fabd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440024328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1440024328
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3298227664
Short name T541
Test name
Test status
Simulation time 64523171 ps
CPU time 1.67 seconds
Started Aug 04 04:36:07 PM PDT 24
Finished Aug 04 04:36:09 PM PDT 24
Peak memory 200152 kb
Host smart-1b08b2f7-6e38-4e5a-bcd4-d6177bcacd42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298227664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3298227664
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3044785292
Short name T130
Test name
Test status
Simulation time 127497730 ps
CPU time 3.93 seconds
Started Aug 04 04:36:20 PM PDT 24
Finished Aug 04 04:36:24 PM PDT 24
Peak memory 199984 kb
Host smart-82c7038f-1469-43bc-9390-68d5873171c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044785292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3044785292
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2474052851
Short name T569
Test name
Test status
Simulation time 362639816 ps
CPU time 2.43 seconds
Started Aug 04 04:36:05 PM PDT 24
Finished Aug 04 04:36:08 PM PDT 24
Peak memory 200140 kb
Host smart-8981919d-ba3f-43d3-8400-2602d68ea732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474052851 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2474052851
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.133520265
Short name T104
Test name
Test status
Simulation time 230814745 ps
CPU time 0.97 seconds
Started Aug 04 04:36:17 PM PDT 24
Finished Aug 04 04:36:18 PM PDT 24
Peak memory 199896 kb
Host smart-5fef36a7-a217-468b-ba29-234b6764b2fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133520265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.133520265
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3934760049
Short name T627
Test name
Test status
Simulation time 18871488 ps
CPU time 0.59 seconds
Started Aug 04 04:36:04 PM PDT 24
Finished Aug 04 04:36:05 PM PDT 24
Peak memory 194956 kb
Host smart-8d34109b-d0d7-4d7c-9b7e-d106202a845c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934760049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3934760049
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.304446390
Short name T598
Test name
Test status
Simulation time 51898014 ps
CPU time 2.14 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 04:36:29 PM PDT 24
Peak memory 200124 kb
Host smart-d330f3b1-7f1e-46cd-9584-118ab2c13d78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304446390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.304446390
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1549545438
Short name T652
Test name
Test status
Simulation time 387383043 ps
CPU time 3.77 seconds
Started Aug 04 04:36:11 PM PDT 24
Finished Aug 04 04:36:15 PM PDT 24
Peak memory 200044 kb
Host smart-176ee619-2c0b-40aa-a706-874f597d1c95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549545438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1549545438
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3697990213
Short name T630
Test name
Test status
Simulation time 1169480255 ps
CPU time 4.6 seconds
Started Aug 04 04:36:35 PM PDT 24
Finished Aug 04 04:36:39 PM PDT 24
Peak memory 200008 kb
Host smart-d1692d89-5154-406c-81d9-3662e42fbede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697990213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3697990213
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1029334279
Short name T554
Test name
Test status
Simulation time 84172424 ps
CPU time 1.63 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 04:36:29 PM PDT 24
Peak memory 200084 kb
Host smart-cabe297d-f143-40a0-8e71-c55063d1d10a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029334279 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1029334279
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2684836425
Short name T99
Test name
Test status
Simulation time 14617600 ps
CPU time 0.78 seconds
Started Aug 04 04:36:15 PM PDT 24
Finished Aug 04 04:36:16 PM PDT 24
Peak memory 199448 kb
Host smart-aa77ebaa-1d62-498a-9c4e-30769ecf7644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684836425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2684836425
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2447268028
Short name T545
Test name
Test status
Simulation time 21803799 ps
CPU time 0.58 seconds
Started Aug 04 04:36:10 PM PDT 24
Finished Aug 04 04:36:10 PM PDT 24
Peak memory 194888 kb
Host smart-7526232e-f92e-4f62-beb8-af35fe1f7cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447268028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2447268028
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1572668697
Short name T653
Test name
Test status
Simulation time 269695052 ps
CPU time 2.23 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 199980 kb
Host smart-f508d5ff-a026-4027-9645-7eb580cd2f67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572668697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1572668697
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2717068915
Short name T637
Test name
Test status
Simulation time 80360035 ps
CPU time 3.89 seconds
Started Aug 04 04:36:20 PM PDT 24
Finished Aug 04 04:36:24 PM PDT 24
Peak memory 200004 kb
Host smart-aae6ee2b-572f-4337-a7ea-5ab762ac65a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717068915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2717068915
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4049881973
Short name T137
Test name
Test status
Simulation time 154254623 ps
CPU time 2.81 seconds
Started Aug 04 04:36:16 PM PDT 24
Finished Aug 04 04:36:19 PM PDT 24
Peak memory 200016 kb
Host smart-349f0f6e-17e2-4e9c-82b1-8d25340b8041
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049881973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4049881973
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1429661496
Short name T100
Test name
Test status
Simulation time 340362539 ps
CPU time 5.9 seconds
Started Aug 04 04:36:21 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 199976 kb
Host smart-8ceb3c3c-2068-4585-828e-ff04c3bd8255
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429661496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1429661496
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2266671031
Short name T591
Test name
Test status
Simulation time 1421006827 ps
CPU time 5.78 seconds
Started Aug 04 04:36:13 PM PDT 24
Finished Aug 04 04:36:19 PM PDT 24
Peak memory 200048 kb
Host smart-76282e7f-d583-4fba-a3b5-9b2aae635a68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266671031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2266671031
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2908775980
Short name T656
Test name
Test status
Simulation time 131247853 ps
CPU time 0.91 seconds
Started Aug 04 04:36:12 PM PDT 24
Finished Aug 04 04:36:13 PM PDT 24
Peak memory 199524 kb
Host smart-0ecd9ba0-325d-49b5-8760-e0a4a888e680
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908775980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2908775980
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.575138033
Short name T561
Test name
Test status
Simulation time 48985954 ps
CPU time 1.55 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 04:36:29 PM PDT 24
Peak memory 200108 kb
Host smart-ff251ce3-f1c7-4084-b1ff-e3637ec7f747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575138033 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.575138033
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3286637341
Short name T560
Test name
Test status
Simulation time 15534152 ps
CPU time 0.8 seconds
Started Aug 04 04:36:00 PM PDT 24
Finished Aug 04 04:36:01 PM PDT 24
Peak memory 199600 kb
Host smart-63a218d1-f106-4e8d-ae8a-648e821f934c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286637341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3286637341
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.325967449
Short name T555
Test name
Test status
Simulation time 11600423 ps
CPU time 0.61 seconds
Started Aug 04 04:36:29 PM PDT 24
Finished Aug 04 04:36:29 PM PDT 24
Peak memory 195008 kb
Host smart-5c3f26a5-91d6-4d9a-92ca-7265aa58f567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325967449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.325967449
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.781294590
Short name T115
Test name
Test status
Simulation time 432670701 ps
CPU time 2.16 seconds
Started Aug 04 04:36:09 PM PDT 24
Finished Aug 04 04:36:12 PM PDT 24
Peak memory 199984 kb
Host smart-26922081-ad5a-4c74-a8bf-73f86c40b333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781294590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.781294590
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.41312866
Short name T648
Test name
Test status
Simulation time 44775184 ps
CPU time 2.15 seconds
Started Aug 04 04:36:04 PM PDT 24
Finished Aug 04 04:36:06 PM PDT 24
Peak memory 199972 kb
Host smart-20f72d8b-b3da-438c-9e4a-5066675fb2e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41312866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.41312866
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3499324687
Short name T574
Test name
Test status
Simulation time 94345954 ps
CPU time 1.7 seconds
Started Aug 04 04:37:08 PM PDT 24
Finished Aug 04 04:37:10 PM PDT 24
Peak memory 199960 kb
Host smart-d347666b-54d7-4a6a-aa98-4c888ebdd935
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499324687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3499324687
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.64673217
Short name T640
Test name
Test status
Simulation time 55114997 ps
CPU time 0.59 seconds
Started Aug 04 04:36:30 PM PDT 24
Finished Aug 04 04:36:36 PM PDT 24
Peak memory 194996 kb
Host smart-3e6806a3-0265-4846-8904-b94f3f5929c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64673217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.64673217
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3543240306
Short name T584
Test name
Test status
Simulation time 23789883 ps
CPU time 0.61 seconds
Started Aug 04 04:36:17 PM PDT 24
Finished Aug 04 04:36:18 PM PDT 24
Peak memory 194996 kb
Host smart-4b3bd6ae-2590-4aa6-9e91-7a2d0ab7157a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543240306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3543240306
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3770944401
Short name T647
Test name
Test status
Simulation time 17298058 ps
CPU time 0.62 seconds
Started Aug 04 04:36:22 PM PDT 24
Finished Aug 04 04:36:23 PM PDT 24
Peak memory 195364 kb
Host smart-ed9b80cd-2b30-43ac-a3c7-e7764e89d445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770944401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3770944401
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3385914630
Short name T611
Test name
Test status
Simulation time 175600492 ps
CPU time 0.59 seconds
Started Aug 04 04:36:12 PM PDT 24
Finished Aug 04 04:36:18 PM PDT 24
Peak memory 195220 kb
Host smart-04aa3d0c-4f07-4e80-82bc-e8400eb4ee7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385914630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3385914630
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1130726342
Short name T621
Test name
Test status
Simulation time 17173809 ps
CPU time 0.63 seconds
Started Aug 04 04:36:12 PM PDT 24
Finished Aug 04 04:36:12 PM PDT 24
Peak memory 194940 kb
Host smart-c5ccb225-7fd3-422e-b4c8-a5adf9e1ece9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130726342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1130726342
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2983132087
Short name T613
Test name
Test status
Simulation time 17572915 ps
CPU time 0.61 seconds
Started Aug 04 04:36:10 PM PDT 24
Finished Aug 04 04:36:11 PM PDT 24
Peak memory 195040 kb
Host smart-abe4d4c3-a6c8-4cd3-8458-85229bc875d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983132087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2983132087
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.591368541
Short name T548
Test name
Test status
Simulation time 43012640 ps
CPU time 0.55 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 195020 kb
Host smart-3880f489-6a0e-476d-83c0-683480fb4a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591368541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.591368541
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1338673920
Short name T610
Test name
Test status
Simulation time 12518295 ps
CPU time 0.61 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:26 PM PDT 24
Peak memory 195040 kb
Host smart-02eb2b85-fd7d-4cf1-bf72-557f9aecb31d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338673920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1338673920
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1511943668
Short name T644
Test name
Test status
Simulation time 78730241 ps
CPU time 0.58 seconds
Started Aug 04 04:36:31 PM PDT 24
Finished Aug 04 04:36:32 PM PDT 24
Peak memory 195012 kb
Host smart-52dcd938-6cf5-4a25-a74e-4d2e97dd8274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511943668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1511943668
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1700924622
Short name T619
Test name
Test status
Simulation time 14070531 ps
CPU time 0.58 seconds
Started Aug 04 04:36:18 PM PDT 24
Finished Aug 04 04:36:18 PM PDT 24
Peak memory 195008 kb
Host smart-92dea4f9-18b4-4e0e-9348-06f548823de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700924622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1700924622
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4038694189
Short name T105
Test name
Test status
Simulation time 2558964435 ps
CPU time 3.35 seconds
Started Aug 04 04:36:16 PM PDT 24
Finished Aug 04 04:36:19 PM PDT 24
Peak memory 200028 kb
Host smart-0f73d195-2916-4200-8eca-376f312f7d70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038694189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4038694189
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.348119168
Short name T595
Test name
Test status
Simulation time 2924761325 ps
CPU time 15.38 seconds
Started Aug 04 04:36:00 PM PDT 24
Finished Aug 04 04:36:16 PM PDT 24
Peak memory 200068 kb
Host smart-b1afb21d-9ef4-4c0e-9868-9d913a91d7fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348119168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.348119168
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3258576060
Short name T620
Test name
Test status
Simulation time 39251949 ps
CPU time 0.67 seconds
Started Aug 04 04:36:01 PM PDT 24
Finished Aug 04 04:36:02 PM PDT 24
Peak memory 197876 kb
Host smart-5b9e2bdb-ac61-47ed-ae82-915ca0fb9757
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258576060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3258576060
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4059817661
Short name T614
Test name
Test status
Simulation time 24415145389 ps
CPU time 347.45 seconds
Started Aug 04 04:35:57 PM PDT 24
Finished Aug 04 04:41:45 PM PDT 24
Peak memory 215760 kb
Host smart-3808c531-67a5-43da-8762-d2575bdec3d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059817661 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.4059817661
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.605874054
Short name T106
Test name
Test status
Simulation time 28353381 ps
CPU time 0.72 seconds
Started Aug 04 04:36:02 PM PDT 24
Finished Aug 04 04:36:03 PM PDT 24
Peak memory 197860 kb
Host smart-219cf06e-ffc3-43c2-a88d-d8ed1ead03b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605874054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.605874054
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.578784191
Short name T624
Test name
Test status
Simulation time 16168981 ps
CPU time 0.59 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:25 PM PDT 24
Peak memory 195084 kb
Host smart-52662f10-0cdd-47af-a1eb-fd935bb12cde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578784191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.578784191
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3362805947
Short name T641
Test name
Test status
Simulation time 86668297 ps
CPU time 2.04 seconds
Started Aug 04 04:36:06 PM PDT 24
Finished Aug 04 04:36:08 PM PDT 24
Peak memory 199992 kb
Host smart-2fef442b-bf48-440f-9cc9-e81909501af3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362805947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3362805947
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1547237436
Short name T649
Test name
Test status
Simulation time 142110671 ps
CPU time 2.67 seconds
Started Aug 04 04:35:50 PM PDT 24
Finished Aug 04 04:35:53 PM PDT 24
Peak memory 200068 kb
Host smart-df05f84d-1bfb-411e-aed0-82555804a58e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547237436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1547237436
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3250024239
Short name T654
Test name
Test status
Simulation time 56925263 ps
CPU time 1.66 seconds
Started Aug 04 04:36:14 PM PDT 24
Finished Aug 04 04:36:16 PM PDT 24
Peak memory 200072 kb
Host smart-c3d3876c-296c-4cd4-9d79-2d0d51e19e5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250024239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3250024239
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3284853045
Short name T655
Test name
Test status
Simulation time 59888435 ps
CPU time 0.6 seconds
Started Aug 04 04:36:28 PM PDT 24
Finished Aug 04 04:36:29 PM PDT 24
Peak memory 194940 kb
Host smart-611c4045-d2d3-47bb-b68b-7d27e1f31097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284853045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3284853045
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3049557418
Short name T639
Test name
Test status
Simulation time 13895569 ps
CPU time 0.58 seconds
Started Aug 04 04:36:19 PM PDT 24
Finished Aug 04 04:36:20 PM PDT 24
Peak memory 194880 kb
Host smart-218e5b3a-f5e9-4231-957f-ab585cd74498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049557418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3049557418
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3244817156
Short name T594
Test name
Test status
Simulation time 31413923 ps
CPU time 0.63 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:26 PM PDT 24
Peak memory 195052 kb
Host smart-dd701e6c-abaa-4012-b1c2-55b950f5e052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244817156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3244817156
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2674641730
Short name T628
Test name
Test status
Simulation time 28181233 ps
CPU time 0.59 seconds
Started Aug 04 04:36:31 PM PDT 24
Finished Aug 04 04:36:32 PM PDT 24
Peak memory 194960 kb
Host smart-9c926fa2-4a86-4942-a3e4-0f4ec7d5dc8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674641730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2674641730
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.308192540
Short name T631
Test name
Test status
Simulation time 31702723 ps
CPU time 0.59 seconds
Started Aug 04 04:36:26 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 194932 kb
Host smart-cdb9a552-f835-4dbc-bc3f-85eb7236a140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308192540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.308192540
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1891899068
Short name T638
Test name
Test status
Simulation time 21047266 ps
CPU time 0.62 seconds
Started Aug 04 04:36:34 PM PDT 24
Finished Aug 04 04:36:35 PM PDT 24
Peak memory 195172 kb
Host smart-d7671457-8912-4358-be8b-ce02da6ec965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891899068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1891899068
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2926860515
Short name T538
Test name
Test status
Simulation time 15006542 ps
CPU time 0.61 seconds
Started Aug 04 04:36:23 PM PDT 24
Finished Aug 04 04:36:24 PM PDT 24
Peak memory 194928 kb
Host smart-fef7ebd9-afcf-476c-9328-399e59716e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926860515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2926860515
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1363065058
Short name T604
Test name
Test status
Simulation time 15657066 ps
CPU time 0.59 seconds
Started Aug 04 04:36:32 PM PDT 24
Finished Aug 04 04:36:33 PM PDT 24
Peak memory 195096 kb
Host smart-7abf7ee4-3c42-4137-b501-c2a802364207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363065058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1363065058
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2338682949
Short name T583
Test name
Test status
Simulation time 18384781 ps
CPU time 0.59 seconds
Started Aug 04 04:36:34 PM PDT 24
Finished Aug 04 04:36:35 PM PDT 24
Peak memory 194936 kb
Host smart-f9c41661-2f26-4ab1-a05c-7fb814f088cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338682949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2338682949
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3570534475
Short name T566
Test name
Test status
Simulation time 16820878 ps
CPU time 0.59 seconds
Started Aug 04 04:36:23 PM PDT 24
Finished Aug 04 04:36:23 PM PDT 24
Peak memory 194956 kb
Host smart-b1bbdfb6-6dcb-40c5-9fe3-b07c141463ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570534475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3570534475
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2961906632
Short name T108
Test name
Test status
Simulation time 57880022 ps
CPU time 2.95 seconds
Started Aug 04 04:35:56 PM PDT 24
Finished Aug 04 04:35:59 PM PDT 24
Peak memory 200040 kb
Host smart-1d709479-2573-4412-b5a8-6d11e75dae9a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961906632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2961906632
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2072486708
Short name T601
Test name
Test status
Simulation time 378888223 ps
CPU time 5.68 seconds
Started Aug 04 04:36:15 PM PDT 24
Finished Aug 04 04:36:21 PM PDT 24
Peak memory 199952 kb
Host smart-b1c6f6ab-7ead-4dfe-8cf7-9da1a52e1022
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072486708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2072486708
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2115202300
Short name T112
Test name
Test status
Simulation time 70814285 ps
CPU time 0.73 seconds
Started Aug 04 04:36:08 PM PDT 24
Finished Aug 04 04:36:09 PM PDT 24
Peak memory 198296 kb
Host smart-fe67e79f-6e8e-4caf-86e4-32b8c55f833b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115202300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2115202300
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3801811928
Short name T551
Test name
Test status
Simulation time 16966283828 ps
CPU time 83.84 seconds
Started Aug 04 04:35:54 PM PDT 24
Finished Aug 04 04:37:18 PM PDT 24
Peak memory 216220 kb
Host smart-cc1ebdb5-9672-4895-af9b-320b384c96a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801811928 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3801811928
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.983357911
Short name T103
Test name
Test status
Simulation time 14719517 ps
CPU time 0.66 seconds
Started Aug 04 04:36:22 PM PDT 24
Finished Aug 04 04:36:23 PM PDT 24
Peak memory 197836 kb
Host smart-9f3dbae8-7696-412e-9920-95e4a451e1e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983357911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.983357911
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1690996761
Short name T562
Test name
Test status
Simulation time 50432177 ps
CPU time 0.6 seconds
Started Aug 04 04:36:21 PM PDT 24
Finished Aug 04 04:36:22 PM PDT 24
Peak memory 194952 kb
Host smart-1f534638-1673-4c99-99b1-22792f9c8783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690996761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1690996761
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.18510973
Short name T122
Test name
Test status
Simulation time 149354204 ps
CPU time 1.97 seconds
Started Aug 04 04:36:11 PM PDT 24
Finished Aug 04 04:36:13 PM PDT 24
Peak memory 199932 kb
Host smart-092b9264-3597-4615-80b5-1b01f0562eb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18510973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_o
utstanding.18510973
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1238021437
Short name T539
Test name
Test status
Simulation time 171461590 ps
CPU time 3.09 seconds
Started Aug 04 04:36:26 PM PDT 24
Finished Aug 04 04:36:30 PM PDT 24
Peak memory 200088 kb
Host smart-a1c6f568-be56-4259-8273-30d024ea0a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238021437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1238021437
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.254095149
Short name T136
Test name
Test status
Simulation time 460669470 ps
CPU time 3.84 seconds
Started Aug 04 04:36:12 PM PDT 24
Finished Aug 04 04:36:16 PM PDT 24
Peak memory 200120 kb
Host smart-44fe1c3b-e9ba-479c-8bad-7859b8ad8c48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254095149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.254095149
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2142403618
Short name T534
Test name
Test status
Simulation time 33779116 ps
CPU time 0.58 seconds
Started Aug 04 04:36:30 PM PDT 24
Finished Aug 04 04:36:31 PM PDT 24
Peak memory 195080 kb
Host smart-085fd287-0fb2-4a38-a9a5-6b9a384de8d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142403618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2142403618
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1257823682
Short name T573
Test name
Test status
Simulation time 15148842 ps
CPU time 0.61 seconds
Started Aug 04 04:36:17 PM PDT 24
Finished Aug 04 04:36:18 PM PDT 24
Peak memory 195008 kb
Host smart-cd16d601-cb17-45e3-ab91-d03fbfcf5809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257823682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1257823682
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1388787658
Short name T607
Test name
Test status
Simulation time 59080779 ps
CPU time 0.64 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:26 PM PDT 24
Peak memory 195280 kb
Host smart-ade988a7-0876-4431-85bd-b8717f76b804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388787658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1388787658
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.437086887
Short name T625
Test name
Test status
Simulation time 60430428 ps
CPU time 0.59 seconds
Started Aug 04 04:36:31 PM PDT 24
Finished Aug 04 04:36:32 PM PDT 24
Peak memory 195056 kb
Host smart-7748a962-4e4c-429f-8ab8-d04b7bc7c667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437086887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.437086887
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3588271342
Short name T592
Test name
Test status
Simulation time 24949137 ps
CPU time 0.64 seconds
Started Aug 04 04:36:17 PM PDT 24
Finished Aug 04 04:36:17 PM PDT 24
Peak memory 195032 kb
Host smart-796cc380-3929-46f0-bb2b-9fe4ad5c7339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588271342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3588271342
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2072653487
Short name T544
Test name
Test status
Simulation time 31340635 ps
CPU time 0.59 seconds
Started Aug 04 04:36:44 PM PDT 24
Finished Aug 04 04:36:44 PM PDT 24
Peak memory 195116 kb
Host smart-74e2a9a8-0d5c-445d-b5f7-1d6abb75f3df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072653487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2072653487
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1091043364
Short name T590
Test name
Test status
Simulation time 32914040 ps
CPU time 0.58 seconds
Started Aug 04 04:36:37 PM PDT 24
Finished Aug 04 04:36:38 PM PDT 24
Peak memory 194932 kb
Host smart-0784495b-14cd-42b0-855c-ed385e513177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091043364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1091043364
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3205142362
Short name T546
Test name
Test status
Simulation time 28940296 ps
CPU time 0.59 seconds
Started Aug 04 04:36:27 PM PDT 24
Finished Aug 04 04:36:28 PM PDT 24
Peak memory 194904 kb
Host smart-ef7bbacb-c45f-48a6-b0fc-9f323369f48e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205142362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3205142362
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.218556891
Short name T580
Test name
Test status
Simulation time 62023067 ps
CPU time 0.61 seconds
Started Aug 04 04:36:18 PM PDT 24
Finished Aug 04 04:36:23 PM PDT 24
Peak memory 195020 kb
Host smart-9ee9ab67-a9d7-4c79-bacf-e21a045430e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218556891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.218556891
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.409159377
Short name T651
Test name
Test status
Simulation time 66422877 ps
CPU time 0.62 seconds
Started Aug 04 04:36:28 PM PDT 24
Finished Aug 04 04:36:29 PM PDT 24
Peak memory 194944 kb
Host smart-5efa3ccf-fd4f-4ec5-8eb8-2429ee4cfff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409159377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.409159377
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4187928465
Short name T585
Test name
Test status
Simulation time 85453119 ps
CPU time 2.81 seconds
Started Aug 04 04:36:16 PM PDT 24
Finished Aug 04 04:36:19 PM PDT 24
Peak memory 200036 kb
Host smart-13728c94-626a-44af-8036-3982aa573a52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187928465 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4187928465
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3364696524
Short name T533
Test name
Test status
Simulation time 77197473 ps
CPU time 0.78 seconds
Started Aug 04 04:36:22 PM PDT 24
Finished Aug 04 04:36:23 PM PDT 24
Peak memory 199436 kb
Host smart-6678d72d-792e-44cc-bced-e340448273f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364696524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3364696524
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.342198998
Short name T536
Test name
Test status
Simulation time 18600264 ps
CPU time 0.55 seconds
Started Aug 04 04:36:04 PM PDT 24
Finished Aug 04 04:36:05 PM PDT 24
Peak memory 195044 kb
Host smart-918788de-1910-4cf4-a2b2-b0a312be83b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342198998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.342198998
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4150065356
Short name T608
Test name
Test status
Simulation time 51585376 ps
CPU time 1.08 seconds
Started Aug 04 04:36:08 PM PDT 24
Finished Aug 04 04:36:09 PM PDT 24
Peak memory 198772 kb
Host smart-47a6094c-7d39-4dc4-b1ab-dde7ef7ecdb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150065356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4150065356
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1587942901
Short name T606
Test name
Test status
Simulation time 34873901 ps
CPU time 1.66 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:27 PM PDT 24
Peak memory 200056 kb
Host smart-e839db9c-948b-46f4-8e32-6426baedc234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587942901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1587942901
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.270559909
Short name T576
Test name
Test status
Simulation time 156382428 ps
CPU time 2.91 seconds
Started Aug 04 04:36:29 PM PDT 24
Finished Aug 04 04:36:32 PM PDT 24
Peak memory 200072 kb
Host smart-d7c63ae4-9754-4d54-afd4-8f278b109a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270559909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.270559909
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3049657339
Short name T571
Test name
Test status
Simulation time 67610311 ps
CPU time 1.51 seconds
Started Aug 04 04:36:15 PM PDT 24
Finished Aug 04 04:36:17 PM PDT 24
Peak memory 200032 kb
Host smart-44655060-8522-4557-a2c9-95cdc76589af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049657339 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3049657339
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1711069662
Short name T111
Test name
Test status
Simulation time 60527645 ps
CPU time 0.86 seconds
Started Aug 04 04:35:57 PM PDT 24
Finished Aug 04 04:35:58 PM PDT 24
Peak memory 199812 kb
Host smart-4f84aa42-848b-4d6b-8c1e-9c36d6337073
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711069662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1711069662
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.907508615
Short name T587
Test name
Test status
Simulation time 61703839 ps
CPU time 0.6 seconds
Started Aug 04 04:36:34 PM PDT 24
Finished Aug 04 04:36:35 PM PDT 24
Peak memory 195076 kb
Host smart-7c5a67db-a487-47da-9c7b-517abc9c230c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907508615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.907508615
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1426651828
Short name T117
Test name
Test status
Simulation time 48039668 ps
CPU time 2.27 seconds
Started Aug 04 04:35:59 PM PDT 24
Finished Aug 04 04:36:01 PM PDT 24
Peak memory 200120 kb
Host smart-f1190ddc-1a06-41b9-a429-03d71f468720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426651828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1426651828
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.296786567
Short name T642
Test name
Test status
Simulation time 404535056 ps
CPU time 2.21 seconds
Started Aug 04 04:36:09 PM PDT 24
Finished Aug 04 04:36:11 PM PDT 24
Peak memory 200060 kb
Host smart-285532fa-f967-4c84-883c-0bd8f632ff21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296786567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.296786567
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3002931684
Short name T572
Test name
Test status
Simulation time 46074039 ps
CPU time 1.25 seconds
Started Aug 04 04:35:54 PM PDT 24
Finished Aug 04 04:35:55 PM PDT 24
Peak memory 199952 kb
Host smart-fbb9bcc6-9e15-430e-bee9-4d1e4f159def
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002931684 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3002931684
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1497515163
Short name T101
Test name
Test status
Simulation time 26170832 ps
CPU time 0.69 seconds
Started Aug 04 04:36:25 PM PDT 24
Finished Aug 04 04:36:26 PM PDT 24
Peak memory 198116 kb
Host smart-d95184e7-aa56-4db5-a96f-0f419c2b51da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497515163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1497515163
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2350404756
Short name T643
Test name
Test status
Simulation time 34434607 ps
CPU time 0.56 seconds
Started Aug 04 04:36:19 PM PDT 24
Finished Aug 04 04:36:20 PM PDT 24
Peak memory 194916 kb
Host smart-cc2cd166-b46e-4aff-a4af-7442efa0cf79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350404756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2350404756
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.699454265
Short name T118
Test name
Test status
Simulation time 194635453 ps
CPU time 1 seconds
Started Aug 04 04:37:14 PM PDT 24
Finished Aug 04 04:37:15 PM PDT 24
Peak memory 198568 kb
Host smart-2f791613-92e1-45df-a0ac-ba2cc8eb2aab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699454265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.699454265
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1328256710
Short name T634
Test name
Test status
Simulation time 851247045 ps
CPU time 4.75 seconds
Started Aug 04 04:36:04 PM PDT 24
Finished Aug 04 04:36:09 PM PDT 24
Peak memory 200192 kb
Host smart-e2dcc776-4f39-4512-87f3-d2c13e87a278
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328256710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1328256710
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.818145669
Short name T138
Test name
Test status
Simulation time 315049580 ps
CPU time 2.93 seconds
Started Aug 04 04:36:11 PM PDT 24
Finished Aug 04 04:36:14 PM PDT 24
Peak memory 200016 kb
Host smart-b452dd1a-d5d2-4563-8963-5810419e493c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818145669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.818145669
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1516547146
Short name T568
Test name
Test status
Simulation time 220658995 ps
CPU time 3.57 seconds
Started Aug 04 04:36:06 PM PDT 24
Finished Aug 04 04:36:10 PM PDT 24
Peak memory 207356 kb
Host smart-677672a7-0d66-4074-9a60-39d1cc963a9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516547146 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1516547146
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1313355382
Short name T113
Test name
Test status
Simulation time 23697423 ps
CPU time 0.85 seconds
Started Aug 04 04:36:19 PM PDT 24
Finished Aug 04 04:36:20 PM PDT 24
Peak memory 199892 kb
Host smart-caf24a4b-4a94-4c9a-902e-df31d6b77205
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313355382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1313355382
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2616238310
Short name T532
Test name
Test status
Simulation time 33474504 ps
CPU time 0.58 seconds
Started Aug 04 04:36:12 PM PDT 24
Finished Aug 04 04:36:13 PM PDT 24
Peak memory 195020 kb
Host smart-7e441348-cfde-46bf-a64e-f56d481cd786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616238310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2616238310
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1810364855
Short name T120
Test name
Test status
Simulation time 180459630 ps
CPU time 2.02 seconds
Started Aug 04 04:36:10 PM PDT 24
Finished Aug 04 04:36:12 PM PDT 24
Peak memory 200000 kb
Host smart-89b47d99-aff0-46d5-b22c-315a5c34d509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810364855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1810364855
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3659175523
Short name T549
Test name
Test status
Simulation time 86213453 ps
CPU time 2.1 seconds
Started Aug 04 04:36:14 PM PDT 24
Finished Aug 04 04:36:17 PM PDT 24
Peak memory 200120 kb
Host smart-cd6a1fbc-bb1b-4b1f-803c-d8118e50d741
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659175523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3659175523
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3999979004
Short name T593
Test name
Test status
Simulation time 649754887 ps
CPU time 4.04 seconds
Started Aug 04 04:36:11 PM PDT 24
Finished Aug 04 04:36:15 PM PDT 24
Peak memory 200092 kb
Host smart-9a793f16-3dd4-4734-aef5-9d153893ffa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999979004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3999979004
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3799004602
Short name T577
Test name
Test status
Simulation time 83140628 ps
CPU time 2.67 seconds
Started Aug 04 04:36:10 PM PDT 24
Finished Aug 04 04:36:13 PM PDT 24
Peak memory 200108 kb
Host smart-a7fe5846-2274-42c9-85ae-b21a508499a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799004602 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3799004602
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1380540944
Short name T596
Test name
Test status
Simulation time 113619657 ps
CPU time 0.72 seconds
Started Aug 04 04:36:02 PM PDT 24
Finished Aug 04 04:36:03 PM PDT 24
Peak memory 197984 kb
Host smart-615d8940-54ec-421f-97ef-da0f307c7748
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380540944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1380540944
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.59352570
Short name T556
Test name
Test status
Simulation time 37513444 ps
CPU time 0.58 seconds
Started Aug 04 04:36:10 PM PDT 24
Finished Aug 04 04:36:10 PM PDT 24
Peak memory 194916 kb
Host smart-8437b004-fa1d-47e6-9130-359670f44ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59352570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.59352570
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.978536965
Short name T629
Test name
Test status
Simulation time 23948578 ps
CPU time 1.13 seconds
Started Aug 04 04:35:58 PM PDT 24
Finished Aug 04 04:35:59 PM PDT 24
Peak memory 198440 kb
Host smart-aae48ba7-a2e6-4b0f-a377-14ddbc87697e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978536965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.978536965
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1247962256
Short name T557
Test name
Test status
Simulation time 309676359 ps
CPU time 2.02 seconds
Started Aug 04 04:36:04 PM PDT 24
Finished Aug 04 04:36:06 PM PDT 24
Peak memory 200112 kb
Host smart-f8da8d52-7a77-4749-be48-4a0def84bf12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247962256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1247962256
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.642793534
Short name T273
Test name
Test status
Simulation time 1150501150 ps
CPU time 71.23 seconds
Started Aug 04 04:47:36 PM PDT 24
Finished Aug 04 04:48:47 PM PDT 24
Peak memory 200068 kb
Host smart-fc468de3-62f2-40ab-af94-865a7dea3480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642793534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.642793534
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2995159779
Short name T495
Test name
Test status
Simulation time 5048694623 ps
CPU time 76.63 seconds
Started Aug 04 04:47:33 PM PDT 24
Finished Aug 04 04:48:50 PM PDT 24
Peak memory 208164 kb
Host smart-2cbff6bb-de3f-4630-a7af-85961aa595ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995159779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2995159779
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.912449214
Short name T150
Test name
Test status
Simulation time 27656497314 ps
CPU time 1093.42 seconds
Started Aug 04 04:47:38 PM PDT 24
Finished Aug 04 05:05:52 PM PDT 24
Peak memory 755648 kb
Host smart-c0c7bfc7-d105-44b8-88ce-20df3535fb0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912449214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.912449214
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.285099357
Short name T206
Test name
Test status
Simulation time 40245817144 ps
CPU time 128.4 seconds
Started Aug 04 04:47:31 PM PDT 24
Finished Aug 04 04:49:40 PM PDT 24
Peak memory 199932 kb
Host smart-38f1a6ac-6f76-4fa3-a90e-043d0ae9c647
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285099357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.285099357
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3124654135
Short name T81
Test name
Test status
Simulation time 31188313202 ps
CPU time 139.39 seconds
Started Aug 04 04:47:32 PM PDT 24
Finished Aug 04 04:49:51 PM PDT 24
Peak memory 199944 kb
Host smart-745327bc-d5ea-498a-9ad1-c2538d2a0069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124654135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3124654135
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.3231943594
Short name T193
Test name
Test status
Simulation time 1840768938 ps
CPU time 16.75 seconds
Started Aug 04 04:47:32 PM PDT 24
Finished Aug 04 04:47:49 PM PDT 24
Peak memory 199756 kb
Host smart-76389b35-a3a1-4deb-a1d2-7adb1e9df9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231943594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3231943594
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1638720122
Short name T517
Test name
Test status
Simulation time 8016608779 ps
CPU time 27.72 seconds
Started Aug 04 04:47:38 PM PDT 24
Finished Aug 04 04:48:06 PM PDT 24
Peak memory 199972 kb
Host smart-bfa2495d-9924-4d91-8019-11864b20ad18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638720122 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1638720122
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3912450575
Short name T36
Test name
Test status
Simulation time 1744889605 ps
CPU time 72.19 seconds
Started Aug 04 04:47:40 PM PDT 24
Finished Aug 04 04:48:52 PM PDT 24
Peak memory 199820 kb
Host smart-5a7fab5b-01a3-439e-abfc-fb105a037785
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3912450575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3912450575
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.212413849
Short name T25
Test name
Test status
Simulation time 39764445127 ps
CPU time 114.25 seconds
Started Aug 04 04:47:35 PM PDT 24
Finished Aug 04 04:49:30 PM PDT 24
Peak memory 199944 kb
Host smart-38662213-0ce2-40aa-b3e8-001f6b7f53cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=212413849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.212413849
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.903454142
Short name T467
Test name
Test status
Simulation time 5577317651 ps
CPU time 73.13 seconds
Started Aug 04 04:47:36 PM PDT 24
Finished Aug 04 04:48:49 PM PDT 24
Peak memory 199880 kb
Host smart-c2a75013-13d8-428b-bc38-2cbf33165015
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=903454142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.903454142
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.1333995815
Short name T507
Test name
Test status
Simulation time 40091454089 ps
CPU time 565.86 seconds
Started Aug 04 04:47:31 PM PDT 24
Finished Aug 04 04:56:57 PM PDT 24
Peak memory 199880 kb
Host smart-00e17935-816a-45d1-8a1a-48d18d8a38ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1333995815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1333995815
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3752260675
Short name T494
Test name
Test status
Simulation time 166686275253 ps
CPU time 2309.94 seconds
Started Aug 04 04:47:34 PM PDT 24
Finished Aug 04 05:26:05 PM PDT 24
Peak memory 215524 kb
Host smart-71a7e5ab-e825-403a-8318-0df4dc69604b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3752260675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3752260675
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.876234216
Short name T334
Test name
Test status
Simulation time 3429400022 ps
CPU time 77.5 seconds
Started Aug 04 04:47:34 PM PDT 24
Finished Aug 04 04:48:52 PM PDT 24
Peak memory 199904 kb
Host smart-8c970627-029f-45b5-a553-410ccb1448ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876234216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.876234216
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1633581040
Short name T407
Test name
Test status
Simulation time 40448263 ps
CPU time 0.57 seconds
Started Aug 04 04:47:45 PM PDT 24
Finished Aug 04 04:47:45 PM PDT 24
Peak memory 195856 kb
Host smart-7f2be5f3-1614-4871-ad69-77b82c1f9a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633581040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1633581040
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.865347373
Short name T414
Test name
Test status
Simulation time 6572605666 ps
CPU time 68.79 seconds
Started Aug 04 04:47:38 PM PDT 24
Finished Aug 04 04:48:47 PM PDT 24
Peak memory 200228 kb
Host smart-16070b9d-8791-4115-ba76-715514832a92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=865347373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.865347373
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.786604393
Short name T487
Test name
Test status
Simulation time 11921507543 ps
CPU time 48.37 seconds
Started Aug 04 04:47:38 PM PDT 24
Finished Aug 04 04:48:26 PM PDT 24
Peak memory 200000 kb
Host smart-d155c3fd-6cae-4572-a488-d6250b893823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786604393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.786604393
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1136293384
Short name T159
Test name
Test status
Simulation time 5496321989 ps
CPU time 1019.7 seconds
Started Aug 04 04:47:38 PM PDT 24
Finished Aug 04 05:04:38 PM PDT 24
Peak memory 755288 kb
Host smart-050b55d1-4f42-4bab-8b64-623e5aa2600a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136293384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1136293384
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.4148732904
Short name T250
Test name
Test status
Simulation time 1437342959 ps
CPU time 88.48 seconds
Started Aug 04 04:47:42 PM PDT 24
Finished Aug 04 04:49:10 PM PDT 24
Peak memory 199780 kb
Host smart-2554b55c-42c1-4c25-bcde-15bffc26288e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148732904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.4148732904
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2076081202
Short name T463
Test name
Test status
Simulation time 127398897912 ps
CPU time 192.46 seconds
Started Aug 04 04:47:35 PM PDT 24
Finished Aug 04 04:50:48 PM PDT 24
Peak memory 200068 kb
Host smart-53a9b11c-5465-49dc-b1e6-ad9e17245536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076081202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2076081202
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2376838467
Short name T69
Test name
Test status
Simulation time 447587955 ps
CPU time 0.8 seconds
Started Aug 04 04:47:45 PM PDT 24
Finished Aug 04 04:47:46 PM PDT 24
Peak memory 218520 kb
Host smart-40eac9f1-f0fb-433d-9b31-9b4db0e07aaf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376838467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2376838467
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1005736181
Short name T403
Test name
Test status
Simulation time 506717655 ps
CPU time 6.31 seconds
Started Aug 04 04:47:39 PM PDT 24
Finished Aug 04 04:47:45 PM PDT 24
Peak memory 199832 kb
Host smart-70ee0ff6-3f90-4f56-8a23-93a0c3722753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005736181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1005736181
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3589114836
Short name T148
Test name
Test status
Simulation time 23048432997 ps
CPU time 1067.14 seconds
Started Aug 04 04:47:46 PM PDT 24
Finished Aug 04 05:05:34 PM PDT 24
Peak memory 729312 kb
Host smart-1cb92279-6632-40fd-87b1-fce3b8cd5949
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589114836 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3589114836
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.685277838
Short name T449
Test name
Test status
Simulation time 1098622727 ps
CPU time 40.73 seconds
Started Aug 04 04:47:45 PM PDT 24
Finished Aug 04 04:48:25 PM PDT 24
Peak memory 199748 kb
Host smart-3f3983c2-cadb-40ca-8f68-3cd0e0af1f51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=685277838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.685277838
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2617550861
Short name T151
Test name
Test status
Simulation time 8981277838 ps
CPU time 103.66 seconds
Started Aug 04 04:47:45 PM PDT 24
Finished Aug 04 04:49:28 PM PDT 24
Peak memory 199900 kb
Host smart-6d715313-9fc7-4fd1-90f1-432c37b1a1ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2617550861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2617550861
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.3637569820
Short name T286
Test name
Test status
Simulation time 3175965949 ps
CPU time 119.59 seconds
Started Aug 04 04:47:46 PM PDT 24
Finished Aug 04 04:49:46 PM PDT 24
Peak memory 199944 kb
Host smart-dc70706e-985a-40c5-ab01-5f2a834939af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3637569820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.3637569820
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1771926097
Short name T304
Test name
Test status
Simulation time 20106499498 ps
CPU time 512.24 seconds
Started Aug 04 04:47:42 PM PDT 24
Finished Aug 04 04:56:14 PM PDT 24
Peak memory 200012 kb
Host smart-bff386c3-50b8-4a10-bda8-832ed45f7c3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1771926097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1771926097
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.693121887
Short name T253
Test name
Test status
Simulation time 148710128549 ps
CPU time 2497.79 seconds
Started Aug 04 04:47:41 PM PDT 24
Finished Aug 04 05:29:19 PM PDT 24
Peak memory 215480 kb
Host smart-d2108cd1-a21c-4f6b-be92-4896511c4c49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=693121887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.693121887
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3636671086
Short name T477
Test name
Test status
Simulation time 541753493705 ps
CPU time 2357.34 seconds
Started Aug 04 04:47:40 PM PDT 24
Finished Aug 04 05:26:58 PM PDT 24
Peak memory 216352 kb
Host smart-317dcf18-f047-4753-aab8-830b5f831913
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3636671086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3636671086
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.420573767
Short name T486
Test name
Test status
Simulation time 12054726797 ps
CPU time 118.2 seconds
Started Aug 04 04:47:41 PM PDT 24
Finished Aug 04 04:49:39 PM PDT 24
Peak memory 199916 kb
Host smart-1fdc57a8-b2ac-4247-8503-36e6846635fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420573767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.420573767
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1609473646
Short name T41
Test name
Test status
Simulation time 73744991 ps
CPU time 0.63 seconds
Started Aug 04 04:49:01 PM PDT 24
Finished Aug 04 04:49:02 PM PDT 24
Peak memory 195860 kb
Host smart-ab310f76-e00f-4de3-848d-24ad82163aee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609473646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1609473646
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4186519426
Short name T490
Test name
Test status
Simulation time 2875725214 ps
CPU time 42.42 seconds
Started Aug 04 04:48:59 PM PDT 24
Finished Aug 04 04:49:41 PM PDT 24
Peak memory 199976 kb
Host smart-e9a4bd0d-aff9-41aa-9899-209791b6096c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186519426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4186519426
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2653220353
Short name T8
Test name
Test status
Simulation time 4342316076 ps
CPU time 78.99 seconds
Started Aug 04 04:48:58 PM PDT 24
Finished Aug 04 04:50:17 PM PDT 24
Peak memory 208172 kb
Host smart-0ea89dc1-86ae-4a40-a7aa-e095b5a7fc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653220353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2653220353
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.71691107
Short name T367
Test name
Test status
Simulation time 3271010903 ps
CPU time 138.12 seconds
Started Aug 04 04:49:01 PM PDT 24
Finished Aug 04 04:51:19 PM PDT 24
Peak memory 560072 kb
Host smart-bc7e2792-7d72-499b-8745-bda0179af619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71691107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.71691107
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1792840468
Short name T185
Test name
Test status
Simulation time 19713591651 ps
CPU time 166.2 seconds
Started Aug 04 04:49:01 PM PDT 24
Finished Aug 04 04:51:48 PM PDT 24
Peak memory 199832 kb
Host smart-ecc7a21f-4df0-41b9-893e-e52395cc03c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792840468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1792840468
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.541502783
Short name T327
Test name
Test status
Simulation time 10219719144 ps
CPU time 133.81 seconds
Started Aug 04 04:49:00 PM PDT 24
Finished Aug 04 04:51:14 PM PDT 24
Peak memory 216276 kb
Host smart-6c9149a0-be49-4600-841d-25e75d4c2874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541502783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.541502783
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.689731676
Short name T398
Test name
Test status
Simulation time 3544742381 ps
CPU time 9.89 seconds
Started Aug 04 04:48:58 PM PDT 24
Finished Aug 04 04:49:08 PM PDT 24
Peak memory 199960 kb
Host smart-5fd3bd37-385c-4f95-8abf-72a6e4c68f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689731676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.689731676
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.113192217
Short name T361
Test name
Test status
Simulation time 20809616259 ps
CPU time 1141.22 seconds
Started Aug 04 04:48:57 PM PDT 24
Finished Aug 04 05:07:59 PM PDT 24
Peak memory 715976 kb
Host smart-8aecb5dc-6d32-4c2c-a16c-ef6f2961ea1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113192217 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.113192217
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2626956836
Short name T96
Test name
Test status
Simulation time 19870706553 ps
CPU time 137.57 seconds
Started Aug 04 04:48:59 PM PDT 24
Finished Aug 04 04:51:16 PM PDT 24
Peak memory 199920 kb
Host smart-ef2d12ae-0176-4441-bcbc-d196b9536765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626956836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2626956836
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1140087635
Short name T66
Test name
Test status
Simulation time 16705242 ps
CPU time 0.57 seconds
Started Aug 04 04:49:11 PM PDT 24
Finished Aug 04 04:49:12 PM PDT 24
Peak memory 195460 kb
Host smart-42371bef-72d4-4a62-a19c-f3247331291c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140087635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1140087635
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.238675720
Short name T257
Test name
Test status
Simulation time 1516560474 ps
CPU time 87.45 seconds
Started Aug 04 04:49:07 PM PDT 24
Finished Aug 04 04:50:34 PM PDT 24
Peak memory 199680 kb
Host smart-60b8b7c0-7c14-469d-a0dd-d666ab47b086
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=238675720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.238675720
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2104943496
Short name T356
Test name
Test status
Simulation time 331743248 ps
CPU time 17.81 seconds
Started Aug 04 04:49:08 PM PDT 24
Finished Aug 04 04:49:26 PM PDT 24
Peak memory 199772 kb
Host smart-90dd4d54-2f6f-4a8c-bff9-0daf55e7242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104943496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2104943496
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4070788413
Short name T180
Test name
Test status
Simulation time 3139145961 ps
CPU time 640.31 seconds
Started Aug 04 04:49:09 PM PDT 24
Finished Aug 04 04:59:50 PM PDT 24
Peak memory 726320 kb
Host smart-d2c357f7-7215-4478-94b6-e6fe962c15ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070788413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4070788413
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2894976239
Short name T373
Test name
Test status
Simulation time 4145105509 ps
CPU time 117.2 seconds
Started Aug 04 04:49:07 PM PDT 24
Finished Aug 04 04:51:05 PM PDT 24
Peak memory 199892 kb
Host smart-92b0d9b5-e1b1-4fb5-a15b-55495d6fb56a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894976239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2894976239
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.4210178212
Short name T438
Test name
Test status
Simulation time 13371299583 ps
CPU time 178.92 seconds
Started Aug 04 04:49:04 PM PDT 24
Finished Aug 04 04:52:04 PM PDT 24
Peak memory 199932 kb
Host smart-452392a4-682d-410e-b8c5-33bdf9cde3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210178212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.4210178212
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.549478053
Short name T160
Test name
Test status
Simulation time 8915630453 ps
CPU time 9.15 seconds
Started Aug 04 04:49:02 PM PDT 24
Finished Aug 04 04:49:11 PM PDT 24
Peak memory 199908 kb
Host smart-4f992438-29fe-4e09-b713-633628204e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549478053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.549478053
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2814134536
Short name T207
Test name
Test status
Simulation time 1803121644 ps
CPU time 80.73 seconds
Started Aug 04 04:49:08 PM PDT 24
Finished Aug 04 04:50:29 PM PDT 24
Peak memory 199880 kb
Host smart-b2fdee23-df16-47a6-895b-fb66dbda26bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814134536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2814134536
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1167139131
Short name T277
Test name
Test status
Simulation time 23854529 ps
CPU time 0.57 seconds
Started Aug 04 04:49:20 PM PDT 24
Finished Aug 04 04:49:21 PM PDT 24
Peak memory 195484 kb
Host smart-81b368a4-17e7-4103-b1e5-560ece3eb2e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167139131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1167139131
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1057301499
Short name T14
Test name
Test status
Simulation time 1162979912 ps
CPU time 75.94 seconds
Started Aug 04 04:49:16 PM PDT 24
Finished Aug 04 04:50:32 PM PDT 24
Peak memory 199824 kb
Host smart-11889f4a-afa2-429b-acae-8ff048e2fcac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057301499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1057301499
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.612794601
Short name T232
Test name
Test status
Simulation time 33625788035 ps
CPU time 63.67 seconds
Started Aug 04 04:49:15 PM PDT 24
Finished Aug 04 04:50:19 PM PDT 24
Peak memory 199932 kb
Host smart-05bd1c4f-fcc4-48fd-9106-975ab317cdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612794601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.612794601
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2994150152
Short name T224
Test name
Test status
Simulation time 22823000520 ps
CPU time 892.96 seconds
Started Aug 04 04:49:14 PM PDT 24
Finished Aug 04 05:04:07 PM PDT 24
Peak memory 732952 kb
Host smart-ab759a39-83ff-4691-804b-ab0a437bd356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994150152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2994150152
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2728700761
Short name T189
Test name
Test status
Simulation time 3321552056 ps
CPU time 106.01 seconds
Started Aug 04 04:49:16 PM PDT 24
Finished Aug 04 04:51:02 PM PDT 24
Peak memory 199952 kb
Host smart-59fd26c6-4a06-44da-88e2-d8ed110ad3e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728700761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2728700761
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.303434647
Short name T271
Test name
Test status
Simulation time 8598011274 ps
CPU time 141.1 seconds
Started Aug 04 04:49:15 PM PDT 24
Finished Aug 04 04:51:36 PM PDT 24
Peak memory 216140 kb
Host smart-63e79dee-0a52-466e-b8da-b84ef7715356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303434647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.303434647
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2046355521
Short name T276
Test name
Test status
Simulation time 70622751 ps
CPU time 3.12 seconds
Started Aug 04 04:49:16 PM PDT 24
Finished Aug 04 04:49:19 PM PDT 24
Peak memory 199876 kb
Host smart-ed5ad270-0e77-4308-b40b-b256ae9936ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046355521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2046355521
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2534859220
Short name T461
Test name
Test status
Simulation time 37142363784 ps
CPU time 1198.92 seconds
Started Aug 04 04:49:22 PM PDT 24
Finished Aug 04 05:09:22 PM PDT 24
Peak memory 639768 kb
Host smart-ec7c18e2-e531-4617-9342-3aa1fe4e0bab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534859220 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2534859220
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1362253240
Short name T313
Test name
Test status
Simulation time 33944508435 ps
CPU time 74.16 seconds
Started Aug 04 04:49:14 PM PDT 24
Finished Aug 04 04:50:29 PM PDT 24
Peak memory 200040 kb
Host smart-740a4878-ef58-4063-bb27-43599aad0052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362253240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1362253240
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2436275572
Short name T235
Test name
Test status
Simulation time 49953718 ps
CPU time 0.58 seconds
Started Aug 04 04:49:25 PM PDT 24
Finished Aug 04 04:49:26 PM PDT 24
Peak memory 195844 kb
Host smart-9c5f96a3-6d6a-4565-9dc6-af3e4c5d5e3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436275572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2436275572
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3125692437
Short name T162
Test name
Test status
Simulation time 11289477541 ps
CPU time 103 seconds
Started Aug 04 04:49:22 PM PDT 24
Finished Aug 04 04:51:05 PM PDT 24
Peak memory 215460 kb
Host smart-f379fcf8-83f0-4aba-aedb-752a5456d6f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125692437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3125692437
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.169798812
Short name T422
Test name
Test status
Simulation time 2169790175 ps
CPU time 26.96 seconds
Started Aug 04 04:49:23 PM PDT 24
Finished Aug 04 04:49:50 PM PDT 24
Peak memory 199832 kb
Host smart-abda8845-5b23-4868-90c6-7ecdad6a3e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169798812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.169798812
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.312382188
Short name T431
Test name
Test status
Simulation time 8491369539 ps
CPU time 367.76 seconds
Started Aug 04 04:49:22 PM PDT 24
Finished Aug 04 04:55:30 PM PDT 24
Peak memory 639792 kb
Host smart-5c41f2fd-ce45-4a5c-8c90-e2e448313b4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312382188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.312382188
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3140621727
Short name T62
Test name
Test status
Simulation time 7820649744 ps
CPU time 149.01 seconds
Started Aug 04 04:49:22 PM PDT 24
Finished Aug 04 04:51:51 PM PDT 24
Peak memory 199956 kb
Host smart-f7702b95-cba0-4d70-90a6-0d2d88a66ee8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140621727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3140621727
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.4129167885
Short name T205
Test name
Test status
Simulation time 7602879092 ps
CPU time 89.76 seconds
Started Aug 04 04:49:21 PM PDT 24
Finished Aug 04 04:50:51 PM PDT 24
Peak memory 200068 kb
Host smart-12210190-fffe-4a17-a4a1-09091d0cc2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129167885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4129167885
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1470959058
Short name T314
Test name
Test status
Simulation time 1468964449 ps
CPU time 10.15 seconds
Started Aug 04 04:49:17 PM PDT 24
Finished Aug 04 04:49:27 PM PDT 24
Peak memory 199848 kb
Host smart-37884f90-b359-4932-a739-4d8c73742fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470959058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1470959058
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3105966285
Short name T360
Test name
Test status
Simulation time 58353796963 ps
CPU time 1245.75 seconds
Started Aug 04 04:49:23 PM PDT 24
Finished Aug 04 05:10:09 PM PDT 24
Peak memory 722800 kb
Host smart-27bffe67-1ef4-4e47-b463-de10dd69f515
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105966285 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3105966285
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2007622303
Short name T82
Test name
Test status
Simulation time 45167799163 ps
CPU time 120.05 seconds
Started Aug 04 04:49:21 PM PDT 24
Finished Aug 04 04:51:22 PM PDT 24
Peak memory 199936 kb
Host smart-4b671c8b-7d50-44a6-9800-63170e2da99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007622303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2007622303
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3546931911
Short name T230
Test name
Test status
Simulation time 54191156 ps
CPU time 0.55 seconds
Started Aug 04 04:49:25 PM PDT 24
Finished Aug 04 04:49:26 PM PDT 24
Peak memory 195572 kb
Host smart-b5c93fc9-ad63-45db-91d3-0edac97e258a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546931911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3546931911
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3807503678
Short name T506
Test name
Test status
Simulation time 6011868259 ps
CPU time 57.31 seconds
Started Aug 04 04:49:24 PM PDT 24
Finished Aug 04 04:50:22 PM PDT 24
Peak memory 215344 kb
Host smart-7ee4c14f-9653-4694-b783-31a287df9562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807503678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3807503678
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3580158333
Short name T174
Test name
Test status
Simulation time 647648070 ps
CPU time 51.68 seconds
Started Aug 04 04:49:28 PM PDT 24
Finished Aug 04 04:50:20 PM PDT 24
Peak memory 325324 kb
Host smart-d989014a-2811-41a3-a718-1ebfd367d9fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580158333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3580158333
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1920467564
Short name T78
Test name
Test status
Simulation time 20051754082 ps
CPU time 225.37 seconds
Started Aug 04 04:49:28 PM PDT 24
Finished Aug 04 04:53:13 PM PDT 24
Peak memory 199936 kb
Host smart-f338f98b-045c-4891-b0d9-53d6bfaee3f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920467564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1920467564
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.4160292300
Short name T354
Test name
Test status
Simulation time 960460055 ps
CPU time 25.37 seconds
Started Aug 04 04:49:24 PM PDT 24
Finished Aug 04 04:49:50 PM PDT 24
Peak memory 199812 kb
Host smart-433721f5-b87c-4358-be9a-85bc82919d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160292300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.4160292300
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3463015054
Short name T258
Test name
Test status
Simulation time 572830061 ps
CPU time 4.95 seconds
Started Aug 04 04:49:25 PM PDT 24
Finished Aug 04 04:49:30 PM PDT 24
Peak memory 199736 kb
Host smart-13356497-0170-43ca-b7b3-40def43b529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463015054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3463015054
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2639256787
Short name T141
Test name
Test status
Simulation time 4947396803 ps
CPU time 133.81 seconds
Started Aug 04 04:49:25 PM PDT 24
Finished Aug 04 04:51:39 PM PDT 24
Peak memory 216368 kb
Host smart-d55e7429-3b62-4a43-922c-7d572f2de4c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639256787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2639256787
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3960233246
Short name T470
Test name
Test status
Simulation time 35172000574 ps
CPU time 125.74 seconds
Started Aug 04 04:49:29 PM PDT 24
Finished Aug 04 04:51:34 PM PDT 24
Peak memory 199932 kb
Host smart-a6d51fa3-a2c0-471e-a521-d529655a4ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960233246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3960233246
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.777963395
Short name T192
Test name
Test status
Simulation time 61650370 ps
CPU time 0.59 seconds
Started Aug 04 04:49:33 PM PDT 24
Finished Aug 04 04:49:34 PM PDT 24
Peak memory 195904 kb
Host smart-869e45e3-9862-4371-a8e9-150789a3b86c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777963395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.777963395
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.771223519
Short name T9
Test name
Test status
Simulation time 2056248027 ps
CPU time 58.62 seconds
Started Aug 04 04:49:27 PM PDT 24
Finished Aug 04 04:50:26 PM PDT 24
Peak memory 200076 kb
Host smart-508609c4-269c-4616-a9ea-1befc1dc759c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=771223519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.771223519
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2941248384
Short name T59
Test name
Test status
Simulation time 5401625328 ps
CPU time 38.96 seconds
Started Aug 04 04:49:30 PM PDT 24
Finished Aug 04 04:50:09 PM PDT 24
Peak memory 208028 kb
Host smart-c80bd33f-3833-4b64-ac0b-10d32519af37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941248384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2941248384
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3725539581
Short name T262
Test name
Test status
Simulation time 16595989465 ps
CPU time 910.56 seconds
Started Aug 04 04:49:28 PM PDT 24
Finished Aug 04 05:04:39 PM PDT 24
Peak memory 772896 kb
Host smart-56b654ba-1990-4aa7-9ffd-f9b1f803abe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725539581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3725539581
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.838896423
Short name T321
Test name
Test status
Simulation time 150761204 ps
CPU time 8.83 seconds
Started Aug 04 04:49:29 PM PDT 24
Finished Aug 04 04:49:38 PM PDT 24
Peak memory 199704 kb
Host smart-cbea3e95-4f49-4026-8ebb-31984f2f5ba7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838896423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.838896423
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2850159709
Short name T175
Test name
Test status
Simulation time 15310896600 ps
CPU time 140.92 seconds
Started Aug 04 04:49:27 PM PDT 24
Finished Aug 04 04:51:48 PM PDT 24
Peak memory 200216 kb
Host smart-db38c05a-2e00-47f6-aa3e-fbbf1b055f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850159709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2850159709
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.463511699
Short name T245
Test name
Test status
Simulation time 774172902 ps
CPU time 13.52 seconds
Started Aug 04 04:49:25 PM PDT 24
Finished Aug 04 04:49:39 PM PDT 24
Peak memory 199848 kb
Host smart-664c3460-4ef4-48a2-89ee-e77df694683d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463511699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.463511699
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2287840999
Short name T30
Test name
Test status
Simulation time 15059966408 ps
CPU time 1359.53 seconds
Started Aug 04 04:49:32 PM PDT 24
Finished Aug 04 05:12:12 PM PDT 24
Peak memory 717644 kb
Host smart-0188b5e5-f529-4b3d-9a67-58b4d5069e4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287840999 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2287840999
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1310321460
Short name T126
Test name
Test status
Simulation time 289406098 ps
CPU time 5.71 seconds
Started Aug 04 04:49:28 PM PDT 24
Finished Aug 04 04:49:33 PM PDT 24
Peak memory 199792 kb
Host smart-d7bde131-9788-4d2e-892c-cb9b7e806c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310321460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1310321460
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3882092218
Short name T320
Test name
Test status
Simulation time 14940697 ps
CPU time 0.58 seconds
Started Aug 04 04:49:36 PM PDT 24
Finished Aug 04 04:49:37 PM PDT 24
Peak memory 195420 kb
Host smart-4bb810d2-ef5b-49e0-a8f1-47752cbf498d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882092218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3882092218
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.4253046774
Short name T7
Test name
Test status
Simulation time 1895319012 ps
CPU time 54.45 seconds
Started Aug 04 04:49:32 PM PDT 24
Finished Aug 04 04:50:27 PM PDT 24
Peak memory 199824 kb
Host smart-ea8d0dba-60ea-4424-99b5-78f6231532cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253046774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4253046774
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1932004490
Short name T239
Test name
Test status
Simulation time 2253282813 ps
CPU time 66.28 seconds
Started Aug 04 04:49:35 PM PDT 24
Finished Aug 04 04:50:41 PM PDT 24
Peak memory 199936 kb
Host smart-16366716-0eb0-48b9-9ba7-8ce8623a7631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932004490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1932004490
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2509123591
Short name T191
Test name
Test status
Simulation time 5102459342 ps
CPU time 668.41 seconds
Started Aug 04 04:49:32 PM PDT 24
Finished Aug 04 05:00:41 PM PDT 24
Peak memory 694064 kb
Host smart-72fd6e48-ce7d-450f-baea-6f0a0704b077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509123591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2509123591
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.738877315
Short name T322
Test name
Test status
Simulation time 21586917072 ps
CPU time 95.94 seconds
Started Aug 04 04:49:35 PM PDT 24
Finished Aug 04 04:51:11 PM PDT 24
Peak memory 200024 kb
Host smart-6e33b9bb-f771-43f9-81f3-dfbe5f159182
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738877315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.738877315
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1180568708
Short name T295
Test name
Test status
Simulation time 2691762926 ps
CPU time 36.99 seconds
Started Aug 04 04:49:32 PM PDT 24
Finished Aug 04 04:50:09 PM PDT 24
Peak memory 199960 kb
Host smart-3720141d-2c51-4a65-878f-683ea2140024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180568708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1180568708
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1490005553
Short name T379
Test name
Test status
Simulation time 2265537153 ps
CPU time 9.3 seconds
Started Aug 04 04:49:32 PM PDT 24
Finished Aug 04 04:49:41 PM PDT 24
Peak memory 199856 kb
Host smart-ad6923f7-4ac2-4325-9df3-161e134a796c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490005553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1490005553
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3973028798
Short name T88
Test name
Test status
Simulation time 61407991720 ps
CPU time 849.67 seconds
Started Aug 04 04:49:35 PM PDT 24
Finished Aug 04 05:03:45 PM PDT 24
Peak memory 216352 kb
Host smart-064ea0dd-dbef-4047-b850-d51d7b6e489c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973028798 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3973028798
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1688350224
Short name T530
Test name
Test status
Simulation time 30493040959 ps
CPU time 30.97 seconds
Started Aug 04 04:49:36 PM PDT 24
Finished Aug 04 04:50:07 PM PDT 24
Peak memory 199988 kb
Host smart-a6d87c3d-cf20-4f28-8967-d6ba7cd8e40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688350224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1688350224
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2549379933
Short name T223
Test name
Test status
Simulation time 12976002 ps
CPU time 0.59 seconds
Started Aug 04 04:49:43 PM PDT 24
Finished Aug 04 04:49:44 PM PDT 24
Peak memory 195480 kb
Host smart-7922b31c-513a-4970-8d5e-d7aa0f37f907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549379933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2549379933
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2153944342
Short name T51
Test name
Test status
Simulation time 195132093 ps
CPU time 10.58 seconds
Started Aug 04 04:49:42 PM PDT 24
Finished Aug 04 04:49:52 PM PDT 24
Peak memory 199768 kb
Host smart-8e453273-1f2a-426c-b877-65971da55ea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2153944342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2153944342
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2275654860
Short name T479
Test name
Test status
Simulation time 1571454965 ps
CPU time 43.39 seconds
Started Aug 04 04:49:40 PM PDT 24
Finished Aug 04 04:50:23 PM PDT 24
Peak memory 199780 kb
Host smart-37135f44-e75f-4dfb-b10b-67443d9f098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275654860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2275654860
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1350453416
Short name T79
Test name
Test status
Simulation time 8504550659 ps
CPU time 835.16 seconds
Started Aug 04 04:49:43 PM PDT 24
Finished Aug 04 05:03:39 PM PDT 24
Peak memory 700396 kb
Host smart-36a75146-e4e2-4aa7-a0f9-0904797e281d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350453416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1350453416
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.966623973
Short name T514
Test name
Test status
Simulation time 14919610021 ps
CPU time 134.91 seconds
Started Aug 04 04:49:44 PM PDT 24
Finished Aug 04 04:51:59 PM PDT 24
Peak memory 199856 kb
Host smart-dc4d88e1-1fe1-4e04-92bd-3d012a835003
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966623973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.966623973
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.9805395
Short name T280
Test name
Test status
Simulation time 18840240930 ps
CPU time 148.7 seconds
Started Aug 04 04:49:43 PM PDT 24
Finished Aug 04 04:52:12 PM PDT 24
Peak memory 208168 kb
Host smart-d1825819-2923-4ef2-a040-96684b6d3b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9805395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.9805395
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1456053691
Short name T238
Test name
Test status
Simulation time 1654211516 ps
CPU time 8.61 seconds
Started Aug 04 04:49:44 PM PDT 24
Finished Aug 04 04:49:53 PM PDT 24
Peak memory 199864 kb
Host smart-8bcf56da-4857-44ae-abce-824bfda1e159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456053691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1456053691
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3635246543
Short name T187
Test name
Test status
Simulation time 65127109559 ps
CPU time 678.41 seconds
Started Aug 04 04:49:43 PM PDT 24
Finished Aug 04 05:01:02 PM PDT 24
Peak memory 513572 kb
Host smart-59e522ed-ac71-4277-a47c-1149aab60416
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635246543 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3635246543
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2102656432
Short name T284
Test name
Test status
Simulation time 3649348613 ps
CPU time 39.86 seconds
Started Aug 04 04:49:44 PM PDT 24
Finished Aug 04 04:50:24 PM PDT 24
Peak memory 199888 kb
Host smart-dab1c56a-5dc6-412b-bf9f-9a2811948de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102656432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2102656432
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1646318012
Short name T482
Test name
Test status
Simulation time 52951841 ps
CPU time 0.62 seconds
Started Aug 04 04:49:46 PM PDT 24
Finished Aug 04 04:49:47 PM PDT 24
Peak memory 196544 kb
Host smart-041b4eb4-0f8e-491e-bb06-aeedc5add186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646318012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1646318012
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.937014598
Short name T366
Test name
Test status
Simulation time 444766421 ps
CPU time 24.53 seconds
Started Aug 04 04:49:42 PM PDT 24
Finished Aug 04 04:50:07 PM PDT 24
Peak memory 199812 kb
Host smart-f30f4c9b-2274-42ea-bc17-256a4f7797dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937014598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.937014598
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2141592135
Short name T392
Test name
Test status
Simulation time 9031081828 ps
CPU time 34.74 seconds
Started Aug 04 04:49:42 PM PDT 24
Finished Aug 04 04:50:17 PM PDT 24
Peak memory 200012 kb
Host smart-12f72d81-0db3-4ea2-955f-1759de47e74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141592135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2141592135
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2206149339
Short name T387
Test name
Test status
Simulation time 6162135089 ps
CPU time 1286.15 seconds
Started Aug 04 04:49:45 PM PDT 24
Finished Aug 04 05:11:11 PM PDT 24
Peak memory 759408 kb
Host smart-37155273-c4b7-4274-97d6-aa40b027b606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206149339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2206149339
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3016816859
Short name T50
Test name
Test status
Simulation time 66514008034 ps
CPU time 275.46 seconds
Started Aug 04 04:49:44 PM PDT 24
Finished Aug 04 04:54:20 PM PDT 24
Peak memory 199880 kb
Host smart-76e199a2-6f43-4b07-bd3f-5bdb02cbd3be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016816859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3016816859
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1553412889
Short name T254
Test name
Test status
Simulation time 7110386428 ps
CPU time 193.38 seconds
Started Aug 04 04:49:44 PM PDT 24
Finished Aug 04 04:52:57 PM PDT 24
Peak memory 199972 kb
Host smart-6215004f-9d91-4c1e-bb37-f2559a4d482b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553412889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1553412889
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.4110076903
Short name T200
Test name
Test status
Simulation time 586915216 ps
CPU time 10.19 seconds
Started Aug 04 04:49:44 PM PDT 24
Finished Aug 04 04:49:54 PM PDT 24
Peak memory 199824 kb
Host smart-1ab896a5-ba13-4aab-b2f8-0cbfd5fb46a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110076903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.4110076903
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2602705746
Short name T124
Test name
Test status
Simulation time 10540892361 ps
CPU time 760.83 seconds
Started Aug 04 04:49:46 PM PDT 24
Finished Aug 04 05:02:27 PM PDT 24
Peak memory 665188 kb
Host smart-70596c30-4bff-4fd9-ae26-39fb647e1f7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602705746 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2602705746
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.835994515
Short name T523
Test name
Test status
Simulation time 15216193406 ps
CPU time 77.26 seconds
Started Aug 04 04:49:46 PM PDT 24
Finished Aug 04 04:51:04 PM PDT 24
Peak memory 199904 kb
Host smart-60bcd79d-fc39-4fa1-b844-049bca6c62d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835994515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.835994515
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2279826781
Short name T52
Test name
Test status
Simulation time 20109143 ps
CPU time 0.59 seconds
Started Aug 04 04:49:56 PM PDT 24
Finished Aug 04 04:49:56 PM PDT 24
Peak memory 195616 kb
Host smart-25247354-9998-4502-9d40-5c2882791c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279826781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2279826781
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3438076886
Short name T499
Test name
Test status
Simulation time 3746930126 ps
CPU time 50.16 seconds
Started Aug 04 04:49:51 PM PDT 24
Finished Aug 04 04:50:42 PM PDT 24
Peak memory 208100 kb
Host smart-0ddb4664-88ad-4d9f-b953-1bba6c32bec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438076886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3438076886
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1680949432
Short name T288
Test name
Test status
Simulation time 3602169083 ps
CPU time 57.39 seconds
Started Aug 04 04:49:55 PM PDT 24
Finished Aug 04 04:50:52 PM PDT 24
Peak memory 199904 kb
Host smart-5d23b53b-e5e5-46d8-81dc-55a4b868be82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680949432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1680949432
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1724298459
Short name T310
Test name
Test status
Simulation time 6244598825 ps
CPU time 229.84 seconds
Started Aug 04 04:49:54 PM PDT 24
Finished Aug 04 04:53:44 PM PDT 24
Peak memory 606260 kb
Host smart-faff755f-3753-4cb6-bad4-d301281acde6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724298459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1724298459
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2604081509
Short name T279
Test name
Test status
Simulation time 4123205408 ps
CPU time 72.14 seconds
Started Aug 04 04:49:55 PM PDT 24
Finished Aug 04 04:51:07 PM PDT 24
Peak memory 199884 kb
Host smart-8f95252c-8e54-49f6-9878-407f5f15f1a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604081509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2604081509
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2681263127
Short name T283
Test name
Test status
Simulation time 1701735617 ps
CPU time 103.79 seconds
Started Aug 04 04:49:50 PM PDT 24
Finished Aug 04 04:51:34 PM PDT 24
Peak memory 199752 kb
Host smart-a3776aa5-1d4f-4348-bd48-cdf995b067cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681263127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2681263127
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3282001473
Short name T489
Test name
Test status
Simulation time 1022987182 ps
CPU time 5.24 seconds
Started Aug 04 04:49:47 PM PDT 24
Finished Aug 04 04:49:52 PM PDT 24
Peak memory 199784 kb
Host smart-1449c117-69c6-4745-8fcd-d5e289af6714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282001473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3282001473
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.598804065
Short name T300
Test name
Test status
Simulation time 270387437071 ps
CPU time 2368.11 seconds
Started Aug 04 04:49:55 PM PDT 24
Finished Aug 04 05:29:23 PM PDT 24
Peak memory 801832 kb
Host smart-32b26b58-6753-4ec3-bbb9-51ef208b5369
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598804065 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.598804065
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1353939243
Short name T28
Test name
Test status
Simulation time 3802927708 ps
CPU time 103.11 seconds
Started Aug 04 04:49:55 PM PDT 24
Finished Aug 04 04:51:38 PM PDT 24
Peak memory 199908 kb
Host smart-71566cd4-9920-429f-a03c-c2ba1527e048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353939243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1353939243
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3235809392
Short name T226
Test name
Test status
Simulation time 21337708 ps
CPU time 0.64 seconds
Started Aug 04 04:47:59 PM PDT 24
Finished Aug 04 04:48:00 PM PDT 24
Peak memory 195852 kb
Host smart-852f7bcc-c8fb-4cf0-89e3-16f385b36e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235809392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3235809392
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1446217586
Short name T154
Test name
Test status
Simulation time 633160025 ps
CPU time 35.82 seconds
Started Aug 04 04:47:48 PM PDT 24
Finished Aug 04 04:48:24 PM PDT 24
Peak memory 199748 kb
Host smart-f41fc018-8ca5-4e91-a2ba-ba27ff87ff67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446217586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1446217586
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.819307936
Short name T53
Test name
Test status
Simulation time 382819050 ps
CPU time 5.99 seconds
Started Aug 04 04:47:48 PM PDT 24
Finished Aug 04 04:47:54 PM PDT 24
Peak memory 199844 kb
Host smart-d9f2388c-91f3-4d22-b50b-a983f315d2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819307936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.819307936
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3607535429
Short name T173
Test name
Test status
Simulation time 14361067623 ps
CPU time 757.72 seconds
Started Aug 04 04:47:48 PM PDT 24
Finished Aug 04 05:00:25 PM PDT 24
Peak memory 728968 kb
Host smart-2e7a196f-cf76-4a88-aa06-d48ded8ef5ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607535429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3607535429
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.358930633
Short name T34
Test name
Test status
Simulation time 23584849481 ps
CPU time 162.75 seconds
Started Aug 04 04:47:48 PM PDT 24
Finished Aug 04 04:50:31 PM PDT 24
Peak memory 199848 kb
Host smart-f5e70af3-f56a-4d64-8305-bb402bc69282
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358930633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.358930633
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3816178772
Short name T213
Test name
Test status
Simulation time 25705544023 ps
CPU time 85.79 seconds
Started Aug 04 04:47:48 PM PDT 24
Finished Aug 04 04:49:14 PM PDT 24
Peak memory 199904 kb
Host smart-cd38820a-e668-43c4-8bb3-f4e5e616e5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816178772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3816178772
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.902945090
Short name T70
Test name
Test status
Simulation time 58948490 ps
CPU time 0.8 seconds
Started Aug 04 04:47:55 PM PDT 24
Finished Aug 04 04:47:56 PM PDT 24
Peak memory 218432 kb
Host smart-836f3eb5-64e8-4a35-8210-a0decfbe717f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902945090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.902945090
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1241451737
Short name T19
Test name
Test status
Simulation time 74452354 ps
CPU time 1.22 seconds
Started Aug 04 04:47:45 PM PDT 24
Finished Aug 04 04:47:46 PM PDT 24
Peak memory 199760 kb
Host smart-ebf73ba6-a0d9-4ebf-b0bc-2779e582b8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241451737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1241451737
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2780715035
Short name T91
Test name
Test status
Simulation time 131611146406 ps
CPU time 1264.01 seconds
Started Aug 04 04:47:55 PM PDT 24
Finished Aug 04 05:09:00 PM PDT 24
Peak memory 653152 kb
Host smart-a2adc110-8cc1-4fc6-b9a5-777f5d4a74e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780715035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2780715035
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1224412507
Short name T58
Test name
Test status
Simulation time 1187649807 ps
CPU time 45.71 seconds
Started Aug 04 04:47:52 PM PDT 24
Finished Aug 04 04:48:38 PM PDT 24
Peak memory 199800 kb
Host smart-1e8a2019-ea11-4751-b38d-5ad8061c6ca4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1224412507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1224412507
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3124287559
Short name T504
Test name
Test status
Simulation time 15496821110 ps
CPU time 58.68 seconds
Started Aug 04 04:47:52 PM PDT 24
Finished Aug 04 04:48:50 PM PDT 24
Peak memory 199968 kb
Host smart-3a72923b-5c93-4761-88f7-27f098ae8473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3124287559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3124287559
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1791572248
Short name T176
Test name
Test status
Simulation time 11292016073 ps
CPU time 88.28 seconds
Started Aug 04 04:47:56 PM PDT 24
Finished Aug 04 04:49:25 PM PDT 24
Peak memory 199876 kb
Host smart-d78f7cce-5cb3-4af2-998c-76b25ea58b5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1791572248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1791572248
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3394888540
Short name T353
Test name
Test status
Simulation time 160880106802 ps
CPU time 511.89 seconds
Started Aug 04 04:47:52 PM PDT 24
Finished Aug 04 04:56:24 PM PDT 24
Peak memory 199356 kb
Host smart-a301e538-72ca-4148-917a-c27b4a4942cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3394888540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3394888540
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.840025208
Short name T496
Test name
Test status
Simulation time 135278731220 ps
CPU time 2205.38 seconds
Started Aug 04 04:47:52 PM PDT 24
Finished Aug 04 05:24:37 PM PDT 24
Peak memory 215444 kb
Host smart-e07121d7-0446-4013-bd93-fff29d40aeb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=840025208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.840025208
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3800377454
Short name T143
Test name
Test status
Simulation time 186097729387 ps
CPU time 2106.5 seconds
Started Aug 04 04:47:52 PM PDT 24
Finished Aug 04 05:22:59 PM PDT 24
Peak memory 215584 kb
Host smart-12d47fd3-c345-4be1-8b98-dd5677d0e08e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3800377454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3800377454
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2338971405
Short name T337
Test name
Test status
Simulation time 2570355635 ps
CPU time 48.73 seconds
Started Aug 04 04:47:51 PM PDT 24
Finished Aug 04 04:48:40 PM PDT 24
Peak memory 199904 kb
Host smart-e30761f5-ba2d-48f6-8063-82df4ee64dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338971405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2338971405
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2407234391
Short name T186
Test name
Test status
Simulation time 15205662 ps
CPU time 0.59 seconds
Started Aug 04 04:50:00 PM PDT 24
Finished Aug 04 04:50:01 PM PDT 24
Peak memory 195896 kb
Host smart-76021f7d-a7b3-4363-beff-59d64e01679f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407234391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2407234391
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.16456672
Short name T24
Test name
Test status
Simulation time 1560265282 ps
CPU time 94.16 seconds
Started Aug 04 04:49:57 PM PDT 24
Finished Aug 04 04:51:31 PM PDT 24
Peak memory 199812 kb
Host smart-b32db541-6f96-4544-a379-d60594113ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16456672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.16456672
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.4082697388
Short name T265
Test name
Test status
Simulation time 34454016774 ps
CPU time 49.31 seconds
Started Aug 04 04:49:58 PM PDT 24
Finished Aug 04 04:50:48 PM PDT 24
Peak memory 199884 kb
Host smart-dd6f366d-e0c0-4fce-9b38-bcd683226600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082697388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.4082697388
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3984511265
Short name T172
Test name
Test status
Simulation time 37206012775 ps
CPU time 940.6 seconds
Started Aug 04 04:49:57 PM PDT 24
Finished Aug 04 05:05:38 PM PDT 24
Peak memory 700332 kb
Host smart-c2560a6e-7d0a-4762-9fc3-4ee3fbd8b003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984511265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3984511265
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.4228152134
Short name T139
Test name
Test status
Simulation time 8605237201 ps
CPU time 146.74 seconds
Started Aug 04 04:49:57 PM PDT 24
Finished Aug 04 04:52:24 PM PDT 24
Peak memory 199832 kb
Host smart-9a44c535-6684-4eb9-b07b-04273cfeb861
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228152134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.4228152134
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2741340083
Short name T3
Test name
Test status
Simulation time 13761591016 ps
CPU time 177.76 seconds
Started Aug 04 04:49:58 PM PDT 24
Finished Aug 04 04:52:56 PM PDT 24
Peak memory 200008 kb
Host smart-d6bba92b-b32b-4be8-bed0-98dace0a5df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741340083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2741340083
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.734908035
Short name T364
Test name
Test status
Simulation time 840610842 ps
CPU time 14.28 seconds
Started Aug 04 04:49:53 PM PDT 24
Finished Aug 04 04:50:08 PM PDT 24
Peak memory 199844 kb
Host smart-535c2cfa-51c8-4fbd-9669-4b466078231a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734908035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.734908035
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2138015410
Short name T508
Test name
Test status
Simulation time 14378829728 ps
CPU time 164.08 seconds
Started Aug 04 04:49:57 PM PDT 24
Finished Aug 04 04:52:42 PM PDT 24
Peak memory 216220 kb
Host smart-81fb0a0b-7732-41c7-9140-69cb5d7ff439
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138015410 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2138015410
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.692255308
Short name T263
Test name
Test status
Simulation time 15205699773 ps
CPU time 152.8 seconds
Started Aug 04 04:49:57 PM PDT 24
Finished Aug 04 04:52:30 PM PDT 24
Peak memory 199944 kb
Host smart-51839c9f-5da3-439d-a7d1-35d267ea830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692255308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.692255308
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1102988060
Short name T351
Test name
Test status
Simulation time 34256079 ps
CPU time 0.61 seconds
Started Aug 04 04:50:05 PM PDT 24
Finished Aug 04 04:50:06 PM PDT 24
Peak memory 196584 kb
Host smart-b081c03e-42c6-4caf-825f-731782de9781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102988060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1102988060
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.916817162
Short name T217
Test name
Test status
Simulation time 48959603 ps
CPU time 2.3 seconds
Started Aug 04 04:50:02 PM PDT 24
Finished Aug 04 04:50:05 PM PDT 24
Peak memory 199748 kb
Host smart-27a19089-f418-46ca-80d4-b6bdb5e65d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=916817162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.916817162
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2835857610
Short name T23
Test name
Test status
Simulation time 1742404918 ps
CPU time 49.71 seconds
Started Aug 04 04:50:05 PM PDT 24
Finished Aug 04 04:50:54 PM PDT 24
Peak memory 199728 kb
Host smart-10dbee3e-2043-4439-9163-e294f2237a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835857610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2835857610
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.231078608
Short name T177
Test name
Test status
Simulation time 64636425300 ps
CPU time 773.47 seconds
Started Aug 04 04:50:05 PM PDT 24
Finished Aug 04 05:02:58 PM PDT 24
Peak memory 655028 kb
Host smart-6fadb2e0-b541-41a3-aaef-f63f3f4c0034
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231078608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.231078608
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2771140871
Short name T416
Test name
Test status
Simulation time 3797575066 ps
CPU time 8.31 seconds
Started Aug 04 04:50:00 PM PDT 24
Finished Aug 04 04:50:09 PM PDT 24
Peak memory 199956 kb
Host smart-fc0e1cbb-a69e-41bb-816c-8ec1cb6b90fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771140871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2771140871
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3692320028
Short name T307
Test name
Test status
Simulation time 38742845627 ps
CPU time 120.64 seconds
Started Aug 04 04:50:04 PM PDT 24
Finished Aug 04 04:52:05 PM PDT 24
Peak memory 199832 kb
Host smart-05cb2acc-88cf-4417-b97b-1dfab9c6d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692320028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3692320028
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.198807838
Short name T194
Test name
Test status
Simulation time 361790505 ps
CPU time 9.62 seconds
Started Aug 04 04:50:03 PM PDT 24
Finished Aug 04 04:50:13 PM PDT 24
Peak memory 199748 kb
Host smart-fe76942b-97e1-41cb-a17c-4aee082c7ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198807838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.198807838
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2047892024
Short name T281
Test name
Test status
Simulation time 110909660471 ps
CPU time 359.84 seconds
Started Aug 04 04:50:05 PM PDT 24
Finished Aug 04 04:56:05 PM PDT 24
Peak memory 199924 kb
Host smart-6c8ffb00-05eb-40cc-97c7-a8f5b267e97f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047892024 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2047892024
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1951407306
Short name T249
Test name
Test status
Simulation time 3922399598 ps
CPU time 101.11 seconds
Started Aug 04 04:50:04 PM PDT 24
Finished Aug 04 04:51:45 PM PDT 24
Peak memory 199920 kb
Host smart-ae7952d2-5523-4be5-9b60-9ab9e1e65851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951407306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1951407306
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3814278910
Short name T57
Test name
Test status
Simulation time 28718850 ps
CPU time 0.59 seconds
Started Aug 04 04:50:10 PM PDT 24
Finished Aug 04 04:50:10 PM PDT 24
Peak memory 195488 kb
Host smart-65ca0594-9e4e-47bd-867b-70e97124fc63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814278910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3814278910
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1815297618
Short name T140
Test name
Test status
Simulation time 2672856017 ps
CPU time 40.09 seconds
Started Aug 04 04:50:12 PM PDT 24
Finished Aug 04 04:50:52 PM PDT 24
Peak memory 199960 kb
Host smart-08b56530-2103-4b70-b065-3b67ca75288e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815297618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1815297618
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1550755627
Short name T72
Test name
Test status
Simulation time 2842912438 ps
CPU time 55.39 seconds
Started Aug 04 04:50:09 PM PDT 24
Finished Aug 04 04:51:04 PM PDT 24
Peak memory 199980 kb
Host smart-e4430c97-f27f-4d9e-a7b2-ecad69c6836d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550755627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1550755627
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.4160479805
Short name T519
Test name
Test status
Simulation time 4918607292 ps
CPU time 1073.15 seconds
Started Aug 04 04:50:07 PM PDT 24
Finished Aug 04 05:08:00 PM PDT 24
Peak memory 750604 kb
Host smart-f2f1796e-a436-4994-a793-88f4d1b1bdf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160479805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.4160479805
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2302039010
Short name T33
Test name
Test status
Simulation time 3199415753 ps
CPU time 120.65 seconds
Started Aug 04 04:50:07 PM PDT 24
Finished Aug 04 04:52:07 PM PDT 24
Peak memory 199900 kb
Host smart-882dd664-c699-44f3-a949-203e1e08624b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302039010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2302039010
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1918604370
Short name T290
Test name
Test status
Simulation time 1927892406 ps
CPU time 27.67 seconds
Started Aug 04 04:50:12 PM PDT 24
Finished Aug 04 04:50:40 PM PDT 24
Peak memory 199828 kb
Host smart-302f0d02-8474-4dea-a2b1-c2d46bf63f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918604370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1918604370
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.671125365
Short name T218
Test name
Test status
Simulation time 4272013050 ps
CPU time 10.9 seconds
Started Aug 04 04:50:06 PM PDT 24
Finished Aug 04 04:50:17 PM PDT 24
Peak memory 199904 kb
Host smart-25fe331a-c21c-40e2-8d8f-37840bd486ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671125365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.671125365
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2754448784
Short name T95
Test name
Test status
Simulation time 183382282606 ps
CPU time 3482.54 seconds
Started Aug 04 04:50:12 PM PDT 24
Finished Aug 04 05:48:15 PM PDT 24
Peak memory 805040 kb
Host smart-ed9e0a87-40f1-421b-bb7b-d6e139cde7bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754448784 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2754448784
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.448436192
Short name T305
Test name
Test status
Simulation time 5285048375 ps
CPU time 66.69 seconds
Started Aug 04 04:50:09 PM PDT 24
Finished Aug 04 04:51:16 PM PDT 24
Peak memory 199984 kb
Host smart-513fe911-2c32-4579-8f2f-f1d7feafbd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448436192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.448436192
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3338530346
Short name T395
Test name
Test status
Simulation time 17723210 ps
CPU time 0.58 seconds
Started Aug 04 04:50:13 PM PDT 24
Finished Aug 04 04:50:14 PM PDT 24
Peak memory 195824 kb
Host smart-a02d0529-a2db-4dd1-a324-8b2086c3d731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338530346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3338530346
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.795624944
Short name T31
Test name
Test status
Simulation time 6301487511 ps
CPU time 44.36 seconds
Started Aug 04 04:50:13 PM PDT 24
Finished Aug 04 04:50:58 PM PDT 24
Peak memory 199920 kb
Host smart-235aa8a8-09a8-4b37-8973-427fadb9e588
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795624944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.795624944
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3767537186
Short name T221
Test name
Test status
Simulation time 2110328262 ps
CPU time 31.1 seconds
Started Aug 04 04:50:14 PM PDT 24
Finished Aug 04 04:50:45 PM PDT 24
Peak memory 199812 kb
Host smart-c6d3f464-ed22-4828-9715-3fb057a2bd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767537186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3767537186
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1647739472
Short name T203
Test name
Test status
Simulation time 10899540252 ps
CPU time 1026.05 seconds
Started Aug 04 04:50:14 PM PDT 24
Finished Aug 04 05:07:20 PM PDT 24
Peak memory 731800 kb
Host smart-36132faa-08f0-4e6c-b3ec-16781ff17507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647739472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1647739472
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.414766327
Short name T237
Test name
Test status
Simulation time 16227150832 ps
CPU time 129.42 seconds
Started Aug 04 04:50:15 PM PDT 24
Finished Aug 04 04:52:25 PM PDT 24
Peak memory 199920 kb
Host smart-8e31e0c0-771b-4d88-ad49-88c1e549d607
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414766327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.414766327
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_smoke.1908654414
Short name T512
Test name
Test status
Simulation time 2353867551 ps
CPU time 14.19 seconds
Started Aug 04 04:50:11 PM PDT 24
Finished Aug 04 04:50:25 PM PDT 24
Peak memory 199956 kb
Host smart-4b556cb3-b044-406f-9db5-455cc09c8b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908654414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1908654414
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2544295556
Short name T345
Test name
Test status
Simulation time 3682144142 ps
CPU time 30.76 seconds
Started Aug 04 04:50:14 PM PDT 24
Finished Aug 04 04:50:45 PM PDT 24
Peak memory 199904 kb
Host smart-3212cb14-a6f9-4481-a875-7ce1400faacc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544295556 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2544295556
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3341119827
Short name T481
Test name
Test status
Simulation time 11103863915 ps
CPU time 136.61 seconds
Started Aug 04 04:50:13 PM PDT 24
Finished Aug 04 04:52:30 PM PDT 24
Peak memory 199952 kb
Host smart-e1005512-6240-4960-a647-741381a7c71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341119827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3341119827
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2697094535
Short name T386
Test name
Test status
Simulation time 26572572 ps
CPU time 0.61 seconds
Started Aug 04 04:50:21 PM PDT 24
Finished Aug 04 04:50:22 PM PDT 24
Peak memory 195944 kb
Host smart-c7af1941-eb39-413e-90ae-28dcda361b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697094535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2697094535
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2254508610
Short name T425
Test name
Test status
Simulation time 1176416896 ps
CPU time 37.62 seconds
Started Aug 04 04:50:18 PM PDT 24
Finished Aug 04 04:50:55 PM PDT 24
Peak memory 199704 kb
Host smart-16251e93-2a35-49a0-8500-1fa2686391b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254508610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2254508610
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3211251598
Short name T326
Test name
Test status
Simulation time 4599367720 ps
CPU time 39.38 seconds
Started Aug 04 04:50:15 PM PDT 24
Finished Aug 04 04:50:55 PM PDT 24
Peak memory 199928 kb
Host smart-23d7ce55-2e78-4158-9515-2e15d97e5011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211251598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3211251598
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2071975840
Short name T484
Test name
Test status
Simulation time 5128200107 ps
CPU time 769.37 seconds
Started Aug 04 04:50:15 PM PDT 24
Finished Aug 04 05:03:05 PM PDT 24
Peak memory 512148 kb
Host smart-e9856c4e-b91a-41b2-b6ef-745a81b9e06f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071975840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2071975840
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2565963753
Short name T419
Test name
Test status
Simulation time 7062285203 ps
CPU time 31.86 seconds
Started Aug 04 04:50:17 PM PDT 24
Finished Aug 04 04:50:49 PM PDT 24
Peak memory 199984 kb
Host smart-6347e857-2642-4f1a-976a-a063a9edb48b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565963753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2565963753
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1098264526
Short name T308
Test name
Test status
Simulation time 9728790401 ps
CPU time 153.14 seconds
Started Aug 04 04:50:13 PM PDT 24
Finished Aug 04 04:52:47 PM PDT 24
Peak memory 208244 kb
Host smart-2d60b996-fed6-401d-94b7-574ea7daf931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098264526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1098264526
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2280994541
Short name T146
Test name
Test status
Simulation time 3517151270 ps
CPU time 11.65 seconds
Started Aug 04 04:50:14 PM PDT 24
Finished Aug 04 04:50:26 PM PDT 24
Peak memory 200240 kb
Host smart-0a6d4146-5325-48d0-95b8-4619a8d58d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280994541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2280994541
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2370218404
Short name T97
Test name
Test status
Simulation time 116988775400 ps
CPU time 3184.71 seconds
Started Aug 04 04:50:19 PM PDT 24
Finished Aug 04 05:43:25 PM PDT 24
Peak memory 832636 kb
Host smart-26181800-380e-4cde-98f3-b8947eb09707
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370218404 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2370218404
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.704038817
Short name T252
Test name
Test status
Simulation time 1733336127 ps
CPU time 12.75 seconds
Started Aug 04 04:50:18 PM PDT 24
Finished Aug 04 04:50:31 PM PDT 24
Peak memory 199800 kb
Host smart-71850ccd-6648-48fb-bdca-404e255c0aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704038817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.704038817
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1619008080
Short name T390
Test name
Test status
Simulation time 13541704 ps
CPU time 0.58 seconds
Started Aug 04 04:50:24 PM PDT 24
Finished Aug 04 04:50:25 PM PDT 24
Peak memory 195096 kb
Host smart-cfde00e9-e593-466b-a91c-1a9a96e024d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619008080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1619008080
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3990237832
Short name T402
Test name
Test status
Simulation time 509875905 ps
CPU time 30.25 seconds
Started Aug 04 04:50:30 PM PDT 24
Finished Aug 04 04:51:01 PM PDT 24
Peak memory 199032 kb
Host smart-e884caca-e443-4438-a516-960cb91c5fb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990237832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3990237832
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.247285929
Short name T363
Test name
Test status
Simulation time 982019305 ps
CPU time 7.4 seconds
Started Aug 04 04:50:31 PM PDT 24
Finished Aug 04 04:50:38 PM PDT 24
Peak memory 199764 kb
Host smart-746aaf5a-16ff-4732-aa9b-743c36f913b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247285929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.247285929
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1157315282
Short name T518
Test name
Test status
Simulation time 7400051679 ps
CPU time 287.72 seconds
Started Aug 04 04:50:30 PM PDT 24
Finished Aug 04 04:55:18 PM PDT 24
Peak memory 475616 kb
Host smart-96b1ab7a-43b3-435c-b529-5843baf30850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157315282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1157315282
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3530326458
Short name T525
Test name
Test status
Simulation time 65310853752 ps
CPU time 121.47 seconds
Started Aug 04 04:50:22 PM PDT 24
Finished Aug 04 04:52:23 PM PDT 24
Peak memory 200040 kb
Host smart-d7da6ffd-ba41-45cc-925d-2f0c1b4feec1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530326458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3530326458
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2396529609
Short name T492
Test name
Test status
Simulation time 5453267252 ps
CPU time 146.22 seconds
Started Aug 04 04:50:26 PM PDT 24
Finished Aug 04 04:52:52 PM PDT 24
Peak memory 199924 kb
Host smart-c2b5f4fe-cc28-485a-8fc2-863e2b984f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396529609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2396529609
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.669336073
Short name T269
Test name
Test status
Simulation time 300482813 ps
CPU time 3.98 seconds
Started Aug 04 04:50:26 PM PDT 24
Finished Aug 04 04:50:30 PM PDT 24
Peak memory 199820 kb
Host smart-c7317097-f0e7-452b-8a0b-a21f9d4f9e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669336073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.669336073
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.396185356
Short name T29
Test name
Test status
Simulation time 40377183098 ps
CPU time 1161.87 seconds
Started Aug 04 04:50:31 PM PDT 24
Finished Aug 04 05:09:53 PM PDT 24
Peak memory 606096 kb
Host smart-166efb05-41b3-45da-b520-3f6bad0817a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396185356 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.396185356
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1233641054
Short name T415
Test name
Test status
Simulation time 546970727 ps
CPU time 8.07 seconds
Started Aug 04 04:50:38 PM PDT 24
Finished Aug 04 04:50:46 PM PDT 24
Peak memory 199856 kb
Host smart-31c2c54c-9ff9-47e4-a5dc-90a812870066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233641054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1233641054
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3176475494
Short name T64
Test name
Test status
Simulation time 38944592 ps
CPU time 0.59 seconds
Started Aug 04 04:50:32 PM PDT 24
Finished Aug 04 04:50:33 PM PDT 24
Peak memory 195616 kb
Host smart-339d4ba6-8a0c-4c2d-bdb2-2e66ff93296e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176475494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3176475494
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.4078466275
Short name T400
Test name
Test status
Simulation time 6688612679 ps
CPU time 45.13 seconds
Started Aug 04 04:50:38 PM PDT 24
Finished Aug 04 04:51:23 PM PDT 24
Peak memory 199868 kb
Host smart-9d81ffe3-d3a9-4fb4-b98d-03f1e11f3d13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078466275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.4078466275
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.836945230
Short name T528
Test name
Test status
Simulation time 6530594531 ps
CPU time 47.6 seconds
Started Aug 04 04:50:28 PM PDT 24
Finished Aug 04 04:51:16 PM PDT 24
Peak memory 215664 kb
Host smart-73431e69-d3f3-4496-92c9-4184d1fc434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836945230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.836945230
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1973822191
Short name T184
Test name
Test status
Simulation time 450164355 ps
CPU time 80.31 seconds
Started Aug 04 04:50:38 PM PDT 24
Finished Aug 04 04:51:58 PM PDT 24
Peak memory 431020 kb
Host smart-3a193210-a80f-4087-ad7e-c17dcb761105
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973822191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1973822191
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3772246468
Short name T198
Test name
Test status
Simulation time 8004334127 ps
CPU time 70.4 seconds
Started Aug 04 04:50:29 PM PDT 24
Finished Aug 04 04:51:39 PM PDT 24
Peak memory 199892 kb
Host smart-c52066cb-d6d8-4d2f-811f-fe9d1ac9cf9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772246468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3772246468
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2748802647
Short name T451
Test name
Test status
Simulation time 51498278594 ps
CPU time 160.28 seconds
Started Aug 04 04:50:38 PM PDT 24
Finished Aug 04 04:53:19 PM PDT 24
Peak memory 199888 kb
Host smart-009036c4-d39c-4492-b126-72034f70375c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748802647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2748802647
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1554646796
Short name T220
Test name
Test status
Simulation time 858548244 ps
CPU time 10.19 seconds
Started Aug 04 04:50:29 PM PDT 24
Finished Aug 04 04:50:39 PM PDT 24
Peak memory 199820 kb
Host smart-a7ca3792-618b-49c9-8a81-8a0540e248e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554646796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1554646796
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.628794385
Short name T86
Test name
Test status
Simulation time 256128621957 ps
CPU time 1637.83 seconds
Started Aug 04 04:50:29 PM PDT 24
Finished Aug 04 05:17:47 PM PDT 24
Peak memory 776632 kb
Host smart-a3643e7d-ce45-471e-8b94-b262a5f0f05e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628794385 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.628794385
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3009316974
Short name T123
Test name
Test status
Simulation time 3752659549 ps
CPU time 48.98 seconds
Started Aug 04 04:50:38 PM PDT 24
Finished Aug 04 04:51:27 PM PDT 24
Peak memory 199996 kb
Host smart-e7962434-58ab-4f9e-9ff5-ad627a4ae800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009316974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3009316974
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2971582411
Short name T65
Test name
Test status
Simulation time 12576800 ps
CPU time 0.6 seconds
Started Aug 04 04:50:36 PM PDT 24
Finished Aug 04 04:50:36 PM PDT 24
Peak memory 196448 kb
Host smart-a62d1621-a65a-4c45-8195-5285820e4084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971582411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2971582411
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.4181073981
Short name T204
Test name
Test status
Simulation time 1370559638 ps
CPU time 72.57 seconds
Started Aug 04 04:50:32 PM PDT 24
Finished Aug 04 04:51:45 PM PDT 24
Peak memory 199828 kb
Host smart-e3b8badb-4d00-490d-9581-c123e80aae04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181073981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.4181073981
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1958040064
Short name T434
Test name
Test status
Simulation time 12874018276 ps
CPU time 63.12 seconds
Started Aug 04 04:50:32 PM PDT 24
Finished Aug 04 04:51:35 PM PDT 24
Peak memory 208120 kb
Host smart-4b1de9f5-b914-4a44-9530-08b94f4e5c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958040064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1958040064
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2462337693
Short name T169
Test name
Test status
Simulation time 2366859509 ps
CPU time 371.05 seconds
Started Aug 04 04:50:31 PM PDT 24
Finished Aug 04 04:56:43 PM PDT 24
Peak memory 651384 kb
Host smart-0a0c29ea-745c-4a0c-9b89-cdfbbffee672
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2462337693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2462337693
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2134049199
Short name T231
Test name
Test status
Simulation time 15585293524 ps
CPU time 182.23 seconds
Started Aug 04 04:50:38 PM PDT 24
Finished Aug 04 04:53:40 PM PDT 24
Peak memory 199944 kb
Host smart-efabe601-d1da-4a7f-9188-367fa3e889bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134049199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2134049199
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.63544544
Short name T488
Test name
Test status
Simulation time 2993627735 ps
CPU time 83.86 seconds
Started Aug 04 04:50:33 PM PDT 24
Finished Aug 04 04:51:57 PM PDT 24
Peak memory 199964 kb
Host smart-a1b255bd-e197-4d31-b231-e85135287e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63544544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.63544544
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1688488535
Short name T48
Test name
Test status
Simulation time 401013308 ps
CPU time 6.77 seconds
Started Aug 04 04:50:38 PM PDT 24
Finished Aug 04 04:50:45 PM PDT 24
Peak memory 199824 kb
Host smart-a6e733be-557f-4391-be32-ab72c269edd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688488535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1688488535
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.381928464
Short name T335
Test name
Test status
Simulation time 39779879708 ps
CPU time 381.06 seconds
Started Aug 04 04:50:35 PM PDT 24
Finished Aug 04 04:56:56 PM PDT 24
Peak memory 199880 kb
Host smart-34fec47e-c92c-4dff-9edd-4a2faf9f52ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381928464 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.381928464
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2859162342
Short name T435
Test name
Test status
Simulation time 7715681717 ps
CPU time 27.03 seconds
Started Aug 04 04:50:41 PM PDT 24
Finished Aug 04 04:51:08 PM PDT 24
Peak memory 199984 kb
Host smart-83f21b1d-1099-4e05-be63-0398c08483a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859162342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2859162342
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3186750820
Short name T443
Test name
Test status
Simulation time 39460776 ps
CPU time 0.6 seconds
Started Aug 04 04:50:42 PM PDT 24
Finished Aug 04 04:50:43 PM PDT 24
Peak memory 195860 kb
Host smart-fa249285-dfcc-4d13-86d5-2b17a7463b19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186750820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3186750820
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3703675002
Short name T202
Test name
Test status
Simulation time 3211244144 ps
CPU time 77.25 seconds
Started Aug 04 04:50:37 PM PDT 24
Finished Aug 04 04:51:55 PM PDT 24
Peak memory 199956 kb
Host smart-cb4376cb-505e-4f5d-a05d-d110df96c89d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703675002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3703675002
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1454163500
Short name T55
Test name
Test status
Simulation time 9783907155 ps
CPU time 65.45 seconds
Started Aug 04 04:50:39 PM PDT 24
Finished Aug 04 04:51:44 PM PDT 24
Peak memory 199888 kb
Host smart-54b41c19-3129-4bff-a596-74ca1a28d067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454163500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1454163500
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.840492642
Short name T502
Test name
Test status
Simulation time 260632862 ps
CPU time 20.71 seconds
Started Aug 04 04:50:37 PM PDT 24
Finished Aug 04 04:50:58 PM PDT 24
Peak memory 228048 kb
Host smart-a5ca662a-c49e-4432-afd5-cac34d831831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=840492642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.840492642
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2155721343
Short name T409
Test name
Test status
Simulation time 2196750249 ps
CPU time 12.96 seconds
Started Aug 04 04:50:39 PM PDT 24
Finished Aug 04 04:50:52 PM PDT 24
Peak memory 199864 kb
Host smart-89ccc7e4-080a-4d78-b4f6-37dca202a873
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155721343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2155721343
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1515212064
Short name T371
Test name
Test status
Simulation time 3498715839 ps
CPU time 58.11 seconds
Started Aug 04 04:50:38 PM PDT 24
Finished Aug 04 04:51:36 PM PDT 24
Peak memory 199932 kb
Host smart-26672fc6-210d-4dc2-ba9f-99805cf18eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515212064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1515212064
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.911708380
Short name T229
Test name
Test status
Simulation time 3479353172 ps
CPU time 12.55 seconds
Started Aug 04 04:50:37 PM PDT 24
Finished Aug 04 04:50:49 PM PDT 24
Peak memory 199948 kb
Host smart-4d2406ea-28a1-494b-87a2-39ca2a05a795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911708380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.911708380
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2144062266
Short name T454
Test name
Test status
Simulation time 138464206230 ps
CPU time 2283.17 seconds
Started Aug 04 04:50:41 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 774020 kb
Host smart-56924f7e-d1b5-4ba1-a53a-0946f32403b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144062266 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2144062266
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.57911467
Short name T92
Test name
Test status
Simulation time 8489066873 ps
CPU time 79.95 seconds
Started Aug 04 04:50:39 PM PDT 24
Finished Aug 04 04:51:59 PM PDT 24
Peak memory 199880 kb
Host smart-32f0141d-8ced-4903-a150-aa4d008ce388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57911467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.57911467
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1355251419
Short name T285
Test name
Test status
Simulation time 13885060 ps
CPU time 0.55 seconds
Started Aug 04 04:50:47 PM PDT 24
Finished Aug 04 04:50:47 PM PDT 24
Peak memory 194792 kb
Host smart-950c2a33-19db-46e1-9d83-815c7cca2247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355251419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1355251419
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.961584298
Short name T473
Test name
Test status
Simulation time 4997519896 ps
CPU time 44.3 seconds
Started Aug 04 04:50:41 PM PDT 24
Finished Aug 04 04:51:26 PM PDT 24
Peak memory 199988 kb
Host smart-d08824bb-07ed-4f1d-a972-87e17664eff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961584298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.961584298
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3242372427
Short name T83
Test name
Test status
Simulation time 5859170817 ps
CPU time 1167.67 seconds
Started Aug 04 04:50:42 PM PDT 24
Finished Aug 04 05:10:10 PM PDT 24
Peak memory 689324 kb
Host smart-9a3e2f0f-ff1e-4fb2-ba71-ce01a87809a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3242372427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3242372427
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1874566491
Short name T405
Test name
Test status
Simulation time 7123403611 ps
CPU time 113.84 seconds
Started Aug 04 04:50:46 PM PDT 24
Finished Aug 04 04:52:39 PM PDT 24
Peak memory 199884 kb
Host smart-cf0d352f-07f5-4562-a44f-7bd7d4fe50de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874566491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1874566491
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1450122951
Short name T325
Test name
Test status
Simulation time 330909164 ps
CPU time 6.88 seconds
Started Aug 04 04:50:41 PM PDT 24
Finished Aug 04 04:50:48 PM PDT 24
Peak memory 199728 kb
Host smart-930ed333-faf2-4164-85f7-1cb3c87b7c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450122951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1450122951
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2867488172
Short name T368
Test name
Test status
Simulation time 2442280897 ps
CPU time 13.02 seconds
Started Aug 04 04:50:43 PM PDT 24
Finished Aug 04 04:50:56 PM PDT 24
Peak memory 199948 kb
Host smart-045183a9-47dd-4e45-8a34-a933a048eb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867488172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2867488172
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3388059217
Short name T60
Test name
Test status
Simulation time 137469283459 ps
CPU time 1956.4 seconds
Started Aug 04 04:50:46 PM PDT 24
Finished Aug 04 05:23:23 PM PDT 24
Peak memory 706448 kb
Host smart-0676547b-8fdd-488e-9c62-37adeaf607a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388059217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3388059217
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.4037605630
Short name T247
Test name
Test status
Simulation time 12037413225 ps
CPU time 41.96 seconds
Started Aug 04 04:50:46 PM PDT 24
Finished Aug 04 04:51:28 PM PDT 24
Peak memory 199960 kb
Host smart-89b66e6d-50db-47d8-9be2-03ccf96ef301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037605630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.4037605630
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2563701595
Short name T291
Test name
Test status
Simulation time 22323669 ps
CPU time 0.59 seconds
Started Aug 04 04:48:09 PM PDT 24
Finished Aug 04 04:48:09 PM PDT 24
Peak memory 194800 kb
Host smart-1535c6dd-ea00-4432-bbab-a750291676f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563701595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2563701595
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.949982365
Short name T397
Test name
Test status
Simulation time 440483706 ps
CPU time 8.67 seconds
Started Aug 04 04:47:59 PM PDT 24
Finished Aug 04 04:48:08 PM PDT 24
Peak memory 199840 kb
Host smart-0175bbf2-9647-4105-a96f-206c9b5bb07c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949982365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.949982365
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2262688292
Short name T236
Test name
Test status
Simulation time 1128512699 ps
CPU time 59.77 seconds
Started Aug 04 04:48:02 PM PDT 24
Finished Aug 04 04:49:02 PM PDT 24
Peak memory 199852 kb
Host smart-f21ffbcb-8368-4f34-8948-6bbf359f57d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262688292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2262688292
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1833463469
Short name T458
Test name
Test status
Simulation time 3618605837 ps
CPU time 592 seconds
Started Aug 04 04:48:00 PM PDT 24
Finished Aug 04 04:57:52 PM PDT 24
Peak memory 653388 kb
Host smart-7167d63f-bb4d-4769-b71b-a52465d50109
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833463469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1833463469
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1707678053
Short name T161
Test name
Test status
Simulation time 6196112114 ps
CPU time 186.01 seconds
Started Aug 04 04:48:02 PM PDT 24
Finished Aug 04 04:51:08 PM PDT 24
Peak memory 199968 kb
Host smart-d1f63961-4d4d-49d6-9f5b-2434588f74b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707678053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1707678053
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2090430706
Short name T355
Test name
Test status
Simulation time 7087351218 ps
CPU time 84.55 seconds
Started Aug 04 04:47:58 PM PDT 24
Finished Aug 04 04:49:22 PM PDT 24
Peak memory 199984 kb
Host smart-b70fbeb1-6997-4094-b3d7-cfc0146fda8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090430706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2090430706
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.847818037
Short name T35
Test name
Test status
Simulation time 81748807 ps
CPU time 0.97 seconds
Started Aug 04 04:48:09 PM PDT 24
Finished Aug 04 04:48:10 PM PDT 24
Peak memory 218376 kb
Host smart-a757c669-b131-46fb-bfd1-5fa74d07f3d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847818037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.847818037
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.851196430
Short name T420
Test name
Test status
Simulation time 3527366975 ps
CPU time 13.99 seconds
Started Aug 04 04:47:59 PM PDT 24
Finished Aug 04 04:48:13 PM PDT 24
Peak memory 199952 kb
Host smart-3f300cc7-12b3-490b-8f0b-2436feb39fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851196430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.851196430
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3681667623
Short name T178
Test name
Test status
Simulation time 296326782617 ps
CPU time 796.69 seconds
Started Aug 04 04:48:05 PM PDT 24
Finished Aug 04 05:01:21 PM PDT 24
Peak memory 390708 kb
Host smart-0e1aa98a-f17f-4a44-ad7b-3244bb44fbe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681667623 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3681667623
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.448168798
Short name T27
Test name
Test status
Simulation time 401628032614 ps
CPU time 3394.95 seconds
Started Aug 04 04:48:06 PM PDT 24
Finished Aug 04 05:44:41 PM PDT 24
Peak memory 779508 kb
Host smart-8354cb83-4e1a-41e4-93f9-9fb0835f84e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448168798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.448168798
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2570482740
Short name T330
Test name
Test status
Simulation time 10813407086 ps
CPU time 48.03 seconds
Started Aug 04 04:48:05 PM PDT 24
Finished Aug 04 04:48:54 PM PDT 24
Peak memory 199868 kb
Host smart-cb5c5de0-dab9-447b-9999-b2c47bcf4c50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2570482740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2570482740
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.657580672
Short name T469
Test name
Test status
Simulation time 12631862279 ps
CPU time 95.23 seconds
Started Aug 04 04:48:05 PM PDT 24
Finished Aug 04 04:49:40 PM PDT 24
Peak memory 199964 kb
Host smart-a45a11fd-c42e-4bfd-99ed-1a6f37bfb620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=657580672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.657580672
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.183908466
Short name T381
Test name
Test status
Simulation time 19778439265 ps
CPU time 134.36 seconds
Started Aug 04 04:48:05 PM PDT 24
Finished Aug 04 04:50:20 PM PDT 24
Peak memory 199932 kb
Host smart-c28e6e3b-ee48-4698-a0b4-bff8c8a9ab35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=183908466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.183908466
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3676821783
Short name T272
Test name
Test status
Simulation time 134829282413 ps
CPU time 620.97 seconds
Started Aug 04 04:48:03 PM PDT 24
Finished Aug 04 04:58:25 PM PDT 24
Peak memory 199892 kb
Host smart-e5c2d87d-6929-42ea-85ce-1ebbe3e00172
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3676821783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3676821783
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.316422264
Short name T142
Test name
Test status
Simulation time 145437377935 ps
CPU time 2125.8 seconds
Started Aug 04 04:48:03 PM PDT 24
Finished Aug 04 05:23:29 PM PDT 24
Peak memory 215456 kb
Host smart-b97686a4-5943-440f-a37a-43e433d9f3f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=316422264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.316422264
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.3915476097
Short name T427
Test name
Test status
Simulation time 144610734829 ps
CPU time 2520.13 seconds
Started Aug 04 04:48:01 PM PDT 24
Finished Aug 04 05:30:02 PM PDT 24
Peak memory 215556 kb
Host smart-5833abbb-c119-475a-abcd-d10760376fed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3915476097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3915476097
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3897838882
Short name T93
Test name
Test status
Simulation time 2366071033 ps
CPU time 94.91 seconds
Started Aug 04 04:48:01 PM PDT 24
Finished Aug 04 04:49:36 PM PDT 24
Peak memory 199928 kb
Host smart-6df13828-8cc1-4e07-b032-0a41008fe536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897838882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3897838882
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.592223071
Short name T448
Test name
Test status
Simulation time 14888603 ps
CPU time 0.6 seconds
Started Aug 04 04:50:52 PM PDT 24
Finished Aug 04 04:50:53 PM PDT 24
Peak memory 195456 kb
Host smart-ce0ac385-7bda-40f1-94c4-b3eab8b75cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592223071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.592223071
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2267728899
Short name T46
Test name
Test status
Simulation time 2156531585 ps
CPU time 35.04 seconds
Started Aug 04 04:50:47 PM PDT 24
Finished Aug 04 04:51:22 PM PDT 24
Peak memory 199816 kb
Host smart-673be395-dbf2-4be0-a1da-13728469c5d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267728899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2267728899
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2907436257
Short name T166
Test name
Test status
Simulation time 9435537240 ps
CPU time 466.13 seconds
Started Aug 04 04:50:48 PM PDT 24
Finished Aug 04 04:58:34 PM PDT 24
Peak memory 689408 kb
Host smart-92eab804-3422-4190-b694-411a5819a955
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2907436257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2907436257
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2973471623
Short name T45
Test name
Test status
Simulation time 1937305708 ps
CPU time 28.58 seconds
Started Aug 04 04:50:54 PM PDT 24
Finished Aug 04 04:51:22 PM PDT 24
Peak memory 199860 kb
Host smart-a7ee0b62-7c6f-438e-8825-4fd87524e435
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973471623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2973471623
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2739484936
Short name T333
Test name
Test status
Simulation time 33577551980 ps
CPU time 112.29 seconds
Started Aug 04 04:50:49 PM PDT 24
Finished Aug 04 04:52:41 PM PDT 24
Peak memory 199888 kb
Host smart-838d5a94-23e2-41d9-abbe-f1f30b787636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739484936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2739484936
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2024904194
Short name T261
Test name
Test status
Simulation time 776650670 ps
CPU time 9.61 seconds
Started Aug 04 04:50:54 PM PDT 24
Finished Aug 04 04:51:04 PM PDT 24
Peak memory 199872 kb
Host smart-120838ca-411e-4a95-ae6e-7239e2c0cafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024904194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2024904194
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2225615740
Short name T520
Test name
Test status
Simulation time 29171632702 ps
CPU time 895.98 seconds
Started Aug 04 04:50:52 PM PDT 24
Finished Aug 04 05:05:48 PM PDT 24
Peak memory 679024 kb
Host smart-be1eb1f5-69e0-4740-a46b-ab8495725330
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225615740 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2225615740
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3333903947
Short name T188
Test name
Test status
Simulation time 2333303203 ps
CPU time 31.27 seconds
Started Aug 04 04:50:52 PM PDT 24
Finished Aug 04 04:51:23 PM PDT 24
Peak memory 199908 kb
Host smart-a2452acb-4172-4f0b-9de6-7e53ff8f0d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333903947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3333903947
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1587090792
Short name T240
Test name
Test status
Simulation time 17662450 ps
CPU time 0.59 seconds
Started Aug 04 04:50:55 PM PDT 24
Finished Aug 04 04:50:56 PM PDT 24
Peak memory 196592 kb
Host smart-cba1c5d6-47bb-49ae-8b76-770e4e85b351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587090792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1587090792
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.424776343
Short name T437
Test name
Test status
Simulation time 1514555667 ps
CPU time 95.67 seconds
Started Aug 04 04:50:52 PM PDT 24
Finished Aug 04 04:52:28 PM PDT 24
Peak memory 199872 kb
Host smart-be43c9b4-e145-4eef-a871-3211d1190eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424776343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.424776343
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2568725259
Short name T336
Test name
Test status
Simulation time 5036081874 ps
CPU time 10.88 seconds
Started Aug 04 04:50:53 PM PDT 24
Finished Aug 04 04:51:04 PM PDT 24
Peak memory 199956 kb
Host smart-68aefa88-fbc5-4fec-9fa2-0c3c2f968276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568725259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2568725259
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1450776912
Short name T155
Test name
Test status
Simulation time 16138470266 ps
CPU time 717.57 seconds
Started Aug 04 04:50:51 PM PDT 24
Finished Aug 04 05:02:49 PM PDT 24
Peak memory 702444 kb
Host smart-83884cbb-a434-47f9-9225-264a808d4f99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450776912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1450776912
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2030427181
Short name T352
Test name
Test status
Simulation time 26196503135 ps
CPU time 114.09 seconds
Started Aug 04 04:50:52 PM PDT 24
Finished Aug 04 04:52:46 PM PDT 24
Peak memory 199988 kb
Host smart-a1428fc6-4dd7-4520-a223-ad05c3319bc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030427181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2030427181
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.4165260862
Short name T147
Test name
Test status
Simulation time 43504065151 ps
CPU time 74.38 seconds
Started Aug 04 04:50:54 PM PDT 24
Finished Aug 04 04:52:08 PM PDT 24
Peak memory 200016 kb
Host smart-17cbf3ab-e201-4f54-b764-3d22e454cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165260862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.4165260862
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3569853325
Short name T344
Test name
Test status
Simulation time 1973818009 ps
CPU time 12.84 seconds
Started Aug 04 04:50:55 PM PDT 24
Finished Aug 04 04:51:08 PM PDT 24
Peak memory 199836 kb
Host smart-0172e7f2-29c6-462e-b7d2-1ce975a47aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569853325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3569853325
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1839644029
Short name T87
Test name
Test status
Simulation time 3547359306 ps
CPU time 25.21 seconds
Started Aug 04 04:50:54 PM PDT 24
Finished Aug 04 04:51:20 PM PDT 24
Peak memory 199952 kb
Host smart-8e603544-f053-4572-ad3e-250aee5d233d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839644029 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1839644029
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2385074033
Short name T459
Test name
Test status
Simulation time 177581006 ps
CPU time 5.36 seconds
Started Aug 04 04:50:55 PM PDT 24
Finished Aug 04 04:51:00 PM PDT 24
Peak memory 199884 kb
Host smart-9223a65c-c77e-43cf-82f9-4d2e4d6b4d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385074033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2385074033
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2929251037
Short name T212
Test name
Test status
Simulation time 11257916 ps
CPU time 0.55 seconds
Started Aug 04 04:50:57 PM PDT 24
Finished Aug 04 04:50:58 PM PDT 24
Peak memory 195896 kb
Host smart-4a809af2-4b40-48cd-a507-93ec3b11fa56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929251037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2929251037
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2894475232
Short name T210
Test name
Test status
Simulation time 702902125 ps
CPU time 23.18 seconds
Started Aug 04 04:50:59 PM PDT 24
Finished Aug 04 04:51:22 PM PDT 24
Peak memory 199764 kb
Host smart-cb93b6c7-5dac-4696-a120-e623142bf0de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894475232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2894475232
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1693685381
Short name T475
Test name
Test status
Simulation time 3691125754 ps
CPU time 18.4 seconds
Started Aug 04 04:50:58 PM PDT 24
Finished Aug 04 04:51:16 PM PDT 24
Peak memory 199920 kb
Host smart-b4c38993-0913-49e3-b43b-b795edac459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693685381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1693685381
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3329868453
Short name T199
Test name
Test status
Simulation time 43113978 ps
CPU time 2.66 seconds
Started Aug 04 04:50:58 PM PDT 24
Finished Aug 04 04:51:01 PM PDT 24
Peak memory 215756 kb
Host smart-884bd485-b8fd-4277-b7b1-719d17c0e791
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3329868453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3329868453
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.4196457747
Short name T222
Test name
Test status
Simulation time 1693641179 ps
CPU time 27.12 seconds
Started Aug 04 04:50:58 PM PDT 24
Finished Aug 04 04:51:25 PM PDT 24
Peak memory 199832 kb
Host smart-c55a3696-7893-4209-b236-95b75e2a9365
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196457747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.4196457747
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3895590404
Short name T385
Test name
Test status
Simulation time 1479337873 ps
CPU time 95.88 seconds
Started Aug 04 04:50:55 PM PDT 24
Finished Aug 04 04:52:31 PM PDT 24
Peak memory 199820 kb
Host smart-cc3e6dcf-efcf-4220-a1cd-94b61be43a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895590404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3895590404
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2207695906
Short name T54
Test name
Test status
Simulation time 1362837444 ps
CPU time 10 seconds
Started Aug 04 04:50:55 PM PDT 24
Finished Aug 04 04:51:06 PM PDT 24
Peak memory 199764 kb
Host smart-5703eb5b-539e-4136-bd9c-aed2ace19bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207695906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2207695906
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.502746917
Short name T526
Test name
Test status
Simulation time 16266335932 ps
CPU time 246.22 seconds
Started Aug 04 04:50:58 PM PDT 24
Finished Aug 04 04:55:04 PM PDT 24
Peak memory 199936 kb
Host smart-7ec0b857-1699-4f19-99f5-7d78fdee520d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502746917 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.502746917
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.515834814
Short name T521
Test name
Test status
Simulation time 16644716563 ps
CPU time 53.96 seconds
Started Aug 04 04:50:57 PM PDT 24
Finished Aug 04 04:51:51 PM PDT 24
Peak memory 199984 kb
Host smart-cff539eb-1d63-457d-8c37-dc04691ee660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515834814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.515834814
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2575059180
Short name T404
Test name
Test status
Simulation time 162221503 ps
CPU time 0.63 seconds
Started Aug 04 04:51:08 PM PDT 24
Finished Aug 04 04:51:09 PM PDT 24
Peak memory 194800 kb
Host smart-008c72ce-4e57-402d-8329-c062a3b216dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575059180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2575059180
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3156072247
Short name T426
Test name
Test status
Simulation time 1021504733 ps
CPU time 15.23 seconds
Started Aug 04 04:51:02 PM PDT 24
Finished Aug 04 04:51:17 PM PDT 24
Peak memory 199836 kb
Host smart-128ae1fb-5252-4dda-8d72-48cbaebb37cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156072247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3156072247
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3313943208
Short name T56
Test name
Test status
Simulation time 4697424090 ps
CPU time 23.17 seconds
Started Aug 04 04:51:01 PM PDT 24
Finished Aug 04 04:51:24 PM PDT 24
Peak memory 199888 kb
Host smart-442b0310-e590-4f82-ab12-a80c9782bce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313943208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3313943208
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2392272046
Short name T251
Test name
Test status
Simulation time 23797041110 ps
CPU time 1233.48 seconds
Started Aug 04 04:51:01 PM PDT 24
Finished Aug 04 05:11:35 PM PDT 24
Peak memory 763460 kb
Host smart-43e990b2-9f3d-47b9-a8e6-3eeec83161d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392272046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2392272046
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.270935154
Short name T302
Test name
Test status
Simulation time 1797427991 ps
CPU time 49.87 seconds
Started Aug 04 04:51:06 PM PDT 24
Finished Aug 04 04:51:56 PM PDT 24
Peak memory 199860 kb
Host smart-43df972d-2fa9-43b5-be3f-e272a0e9799e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270935154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.270935154
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3331421969
Short name T228
Test name
Test status
Simulation time 16593675713 ps
CPU time 120.87 seconds
Started Aug 04 04:51:01 PM PDT 24
Finished Aug 04 04:53:02 PM PDT 24
Peak memory 199916 kb
Host smart-db9a874e-24db-4f6a-b7a1-2f09e4df8d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331421969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3331421969
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.655186832
Short name T311
Test name
Test status
Simulation time 1743505300 ps
CPU time 2.71 seconds
Started Aug 04 04:51:01 PM PDT 24
Finished Aug 04 04:51:04 PM PDT 24
Peak memory 199856 kb
Host smart-1c992280-2dd0-48af-9a50-74ab31e84458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655186832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.655186832
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3518068423
Short name T359
Test name
Test status
Simulation time 180116082804 ps
CPU time 3660.82 seconds
Started Aug 04 04:51:09 PM PDT 24
Finished Aug 04 05:52:10 PM PDT 24
Peak memory 816028 kb
Host smart-604c3ddb-0583-4054-b7aa-c455964a6346
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518068423 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3518068423
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3512574965
Short name T94
Test name
Test status
Simulation time 9765271020 ps
CPU time 93.45 seconds
Started Aug 04 04:51:07 PM PDT 24
Finished Aug 04 04:52:40 PM PDT 24
Peak memory 199884 kb
Host smart-e8b63140-80e6-4e07-a729-f42a98c757ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512574965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3512574965
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3001142948
Short name T190
Test name
Test status
Simulation time 17730620 ps
CPU time 0.61 seconds
Started Aug 04 04:51:14 PM PDT 24
Finished Aug 04 04:51:15 PM PDT 24
Peak memory 195832 kb
Host smart-51b90169-b79e-4a49-a4ab-2fb7b003ce15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001142948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3001142948
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1322703972
Short name T331
Test name
Test status
Simulation time 1341708629 ps
CPU time 85.72 seconds
Started Aug 04 04:51:04 PM PDT 24
Finished Aug 04 04:52:30 PM PDT 24
Peak memory 199756 kb
Host smart-04b1056b-62a0-4174-8ff0-627245818a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1322703972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1322703972
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3184307808
Short name T260
Test name
Test status
Simulation time 891005161 ps
CPU time 129.09 seconds
Started Aug 04 04:51:05 PM PDT 24
Finished Aug 04 04:53:14 PM PDT 24
Peak memory 569960 kb
Host smart-f955f154-404b-4eac-a630-48f425f140fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3184307808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3184307808
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1866122193
Short name T6
Test name
Test status
Simulation time 69667790449 ps
CPU time 106.04 seconds
Started Aug 04 04:51:11 PM PDT 24
Finished Aug 04 04:52:57 PM PDT 24
Peak memory 199920 kb
Host smart-6c936c03-7a77-43ed-8785-b61e30877446
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866122193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1866122193
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2895886870
Short name T516
Test name
Test status
Simulation time 40902601833 ps
CPU time 151.92 seconds
Started Aug 04 04:51:06 PM PDT 24
Finished Aug 04 04:53:38 PM PDT 24
Peak memory 200172 kb
Host smart-2dc1606e-f520-4abb-9135-8e1d09b97c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895886870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2895886870
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.4117519126
Short name T80
Test name
Test status
Simulation time 444348846 ps
CPU time 5.72 seconds
Started Aug 04 04:51:06 PM PDT 24
Finished Aug 04 04:51:12 PM PDT 24
Peak memory 199872 kb
Host smart-25c463b2-5bc8-4b6b-8939-23371ae22946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117519126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.4117519126
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2116520376
Short name T47
Test name
Test status
Simulation time 2291231509 ps
CPU time 106.71 seconds
Started Aug 04 04:51:10 PM PDT 24
Finished Aug 04 04:52:56 PM PDT 24
Peak memory 199804 kb
Host smart-f1808395-7798-4173-8077-916141ca8dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116520376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2116520376
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3898339031
Short name T376
Test name
Test status
Simulation time 12105440 ps
CPU time 0.59 seconds
Started Aug 04 04:51:18 PM PDT 24
Finished Aug 04 04:51:19 PM PDT 24
Peak memory 194800 kb
Host smart-e05f711b-2190-4802-8710-fef967e97036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898339031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3898339031
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1694490472
Short name T195
Test name
Test status
Simulation time 1740455045 ps
CPU time 56.45 seconds
Started Aug 04 04:51:12 PM PDT 24
Finished Aug 04 04:52:09 PM PDT 24
Peak memory 199776 kb
Host smart-f1b791df-4693-4e3a-a8f6-f5761dde6bca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694490472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1694490472
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2726240519
Short name T216
Test name
Test status
Simulation time 26900255765 ps
CPU time 92.75 seconds
Started Aug 04 04:51:11 PM PDT 24
Finished Aug 04 04:52:44 PM PDT 24
Peak memory 199960 kb
Host smart-e84dc266-4d0d-48c3-aac5-379d5e58f5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726240519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2726240519
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2923724273
Short name T306
Test name
Test status
Simulation time 2377404462 ps
CPU time 212.75 seconds
Started Aug 04 04:51:12 PM PDT 24
Finished Aug 04 04:54:45 PM PDT 24
Peak memory 630352 kb
Host smart-96953175-f9c6-4ef3-8f29-006fa4b0a48b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923724273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2923724273
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3727071948
Short name T275
Test name
Test status
Simulation time 2480161831 ps
CPU time 34.39 seconds
Started Aug 04 04:51:19 PM PDT 24
Finished Aug 04 04:51:54 PM PDT 24
Peak memory 199892 kb
Host smart-66eae4e8-c3d9-4423-a959-b8362ac02362
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727071948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3727071948
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3219695092
Short name T388
Test name
Test status
Simulation time 1893507744 ps
CPU time 5.2 seconds
Started Aug 04 04:51:12 PM PDT 24
Finished Aug 04 04:51:17 PM PDT 24
Peak memory 199788 kb
Host smart-b6c0bf48-7a71-4831-b4ce-383368b61308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219695092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3219695092
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3971059090
Short name T424
Test name
Test status
Simulation time 2816651192 ps
CPU time 13.31 seconds
Started Aug 04 04:51:12 PM PDT 24
Finished Aug 04 04:51:26 PM PDT 24
Peak memory 199856 kb
Host smart-749fafeb-caae-44dd-a526-28de075bb8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971059090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3971059090
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3442838348
Short name T90
Test name
Test status
Simulation time 76448636203 ps
CPU time 1166.96 seconds
Started Aug 04 04:51:20 PM PDT 24
Finished Aug 04 05:10:47 PM PDT 24
Peak memory 725964 kb
Host smart-bfe359af-1db4-44c6-baf1-e3c95c418fe5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442838348 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3442838348
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3023225732
Short name T270
Test name
Test status
Simulation time 4439897314 ps
CPU time 61.7 seconds
Started Aug 04 04:51:18 PM PDT 24
Finished Aug 04 04:52:20 PM PDT 24
Peak memory 199956 kb
Host smart-f8e90cd1-13b4-4892-a02a-e07874f2c1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023225732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3023225732
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1800196745
Short name T524
Test name
Test status
Simulation time 14524928 ps
CPU time 0.57 seconds
Started Aug 04 04:51:21 PM PDT 24
Finished Aug 04 04:51:22 PM PDT 24
Peak memory 194880 kb
Host smart-5743bfe3-6a40-4a9b-a910-ae002e2ba727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800196745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1800196745
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1775557906
Short name T384
Test name
Test status
Simulation time 524282282 ps
CPU time 29.93 seconds
Started Aug 04 04:51:18 PM PDT 24
Finished Aug 04 04:51:48 PM PDT 24
Peak memory 199828 kb
Host smart-84aa42b2-4cf2-4e55-92b6-10dd6e5c3a5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775557906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1775557906
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.4023110276
Short name T417
Test name
Test status
Simulation time 8017582478 ps
CPU time 48.84 seconds
Started Aug 04 04:51:19 PM PDT 24
Finished Aug 04 04:52:08 PM PDT 24
Peak memory 199972 kb
Host smart-fb58e6ea-cd47-462a-a58d-8006e6eccfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023110276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.4023110276
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.852807717
Short name T225
Test name
Test status
Simulation time 1317316023 ps
CPU time 242.93 seconds
Started Aug 04 04:51:19 PM PDT 24
Finished Aug 04 04:55:22 PM PDT 24
Peak memory 611936 kb
Host smart-2c4cbb05-65a9-4110-9339-4d051773643f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852807717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.852807717
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3479165363
Short name T442
Test name
Test status
Simulation time 5659909495 ps
CPU time 43.89 seconds
Started Aug 04 04:51:16 PM PDT 24
Finished Aug 04 04:52:00 PM PDT 24
Peak memory 199868 kb
Host smart-8c624a22-d937-4749-b178-87e9455b884e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479165363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3479165363
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1097749725
Short name T170
Test name
Test status
Simulation time 1500048340 ps
CPU time 22.71 seconds
Started Aug 04 04:51:19 PM PDT 24
Finished Aug 04 04:51:41 PM PDT 24
Peak memory 199812 kb
Host smart-1dd64aea-c635-4251-a3e1-a0f0905cd8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097749725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1097749725
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2101691439
Short name T246
Test name
Test status
Simulation time 158760995 ps
CPU time 6.96 seconds
Started Aug 04 04:51:18 PM PDT 24
Finished Aug 04 04:51:25 PM PDT 24
Peak memory 199872 kb
Host smart-0de345e2-3327-4d51-9ff1-70dd74528cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101691439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2101691439
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3296827999
Short name T32
Test name
Test status
Simulation time 62779466380 ps
CPU time 2009.37 seconds
Started Aug 04 04:51:20 PM PDT 24
Finished Aug 04 05:24:50 PM PDT 24
Peak memory 757552 kb
Host smart-b82fe830-edef-4fd6-8636-68456746b2ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296827999 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3296827999
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3255792192
Short name T234
Test name
Test status
Simulation time 14105649006 ps
CPU time 52.51 seconds
Started Aug 04 04:51:20 PM PDT 24
Finished Aug 04 04:52:12 PM PDT 24
Peak memory 199920 kb
Host smart-00d4d878-3a60-4c15-b99f-71389c2d1405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255792192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3255792192
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4218216460
Short name T181
Test name
Test status
Simulation time 57627272 ps
CPU time 0.6 seconds
Started Aug 04 04:51:25 PM PDT 24
Finished Aug 04 04:51:26 PM PDT 24
Peak memory 196512 kb
Host smart-84eae519-4bf7-4976-8da0-833d45c4d1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218216460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4218216460
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.219100205
Short name T4
Test name
Test status
Simulation time 1320703494 ps
CPU time 74.04 seconds
Started Aug 04 04:51:19 PM PDT 24
Finished Aug 04 04:52:33 PM PDT 24
Peak memory 199800 kb
Host smart-5d4088ca-5dae-4f21-a4e1-ffe551c78eb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219100205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.219100205
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3509180886
Short name T287
Test name
Test status
Simulation time 1750901751 ps
CPU time 33.67 seconds
Started Aug 04 04:51:24 PM PDT 24
Finished Aug 04 04:51:57 PM PDT 24
Peak memory 200104 kb
Host smart-8c646125-2f32-435c-bffa-eaec81f3e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509180886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3509180886
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2864714279
Short name T42
Test name
Test status
Simulation time 2043988290 ps
CPU time 90.36 seconds
Started Aug 04 04:51:19 PM PDT 24
Finished Aug 04 04:52:50 PM PDT 24
Peak memory 428244 kb
Host smart-c972d8e9-f55d-480f-8469-9797a02c9cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864714279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2864714279
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3850073686
Short name T464
Test name
Test status
Simulation time 2317127534 ps
CPU time 124.27 seconds
Started Aug 04 04:51:23 PM PDT 24
Finished Aug 04 04:53:27 PM PDT 24
Peak memory 199912 kb
Host smart-be9508a8-19cd-497f-a168-26cd97c8dd62
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850073686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3850073686
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3610765775
Short name T342
Test name
Test status
Simulation time 17490338350 ps
CPU time 174.83 seconds
Started Aug 04 04:51:21 PM PDT 24
Finished Aug 04 04:54:16 PM PDT 24
Peak memory 208164 kb
Host smart-e3e2d52b-da29-431e-b69c-e76a1b525920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610765775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3610765775
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3078691145
Short name T38
Test name
Test status
Simulation time 459402213 ps
CPU time 5.79 seconds
Started Aug 04 04:51:20 PM PDT 24
Finished Aug 04 04:51:26 PM PDT 24
Peak memory 199784 kb
Host smart-9c012794-eb3c-4ca5-8cf5-115e82633e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078691145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3078691145
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.705909134
Short name T465
Test name
Test status
Simulation time 343533635855 ps
CPU time 690.89 seconds
Started Aug 04 04:51:26 PM PDT 24
Finished Aug 04 05:02:57 PM PDT 24
Peak memory 208100 kb
Host smart-243db1f1-9361-4f86-973c-d170b22b60e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705909134 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.705909134
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3649087907
Short name T510
Test name
Test status
Simulation time 772195064 ps
CPU time 14.55 seconds
Started Aug 04 04:51:23 PM PDT 24
Finished Aug 04 04:51:38 PM PDT 24
Peak memory 199732 kb
Host smart-b4cb5767-7bd0-4ba0-ab3f-4c5b3c1f8c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649087907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3649087907
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1273796912
Short name T268
Test name
Test status
Simulation time 178163016 ps
CPU time 0.63 seconds
Started Aug 04 04:51:30 PM PDT 24
Finished Aug 04 04:51:31 PM PDT 24
Peak memory 195856 kb
Host smart-2430ccd5-56f2-4e89-8034-6d1fa2d491ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273796912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1273796912
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2785811538
Short name T511
Test name
Test status
Simulation time 5415639937 ps
CPU time 73.12 seconds
Started Aug 04 04:51:25 PM PDT 24
Finished Aug 04 04:52:38 PM PDT 24
Peak memory 199808 kb
Host smart-ffaca827-05ad-4e47-b8b8-fb1afe52f272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785811538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2785811538
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.928758314
Short name T412
Test name
Test status
Simulation time 310766884 ps
CPU time 17.41 seconds
Started Aug 04 04:51:25 PM PDT 24
Finished Aug 04 04:51:43 PM PDT 24
Peak memory 199876 kb
Host smart-aba1627c-a5bd-4153-adb0-a65be040cf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928758314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.928758314
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.181944722
Short name T369
Test name
Test status
Simulation time 9202645375 ps
CPU time 417.45 seconds
Started Aug 04 04:51:26 PM PDT 24
Finished Aug 04 04:58:23 PM PDT 24
Peak memory 660288 kb
Host smart-e2f0edce-e4ca-46eb-ac87-77f836149c4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181944722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.181944722
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3560062878
Short name T282
Test name
Test status
Simulation time 4346237148 ps
CPU time 81.62 seconds
Started Aug 04 04:51:31 PM PDT 24
Finished Aug 04 04:52:52 PM PDT 24
Peak memory 200244 kb
Host smart-b02b7853-20e7-41c6-b52d-ed789783c1b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560062878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3560062878
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3851936188
Short name T278
Test name
Test status
Simulation time 3299264591 ps
CPU time 101.73 seconds
Started Aug 04 04:51:26 PM PDT 24
Finished Aug 04 04:53:07 PM PDT 24
Peak memory 199936 kb
Host smart-83508b58-d369-483b-8bf9-7a6d57a1664e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851936188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3851936188
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3965644955
Short name T303
Test name
Test status
Simulation time 820513310 ps
CPU time 10.22 seconds
Started Aug 04 04:51:25 PM PDT 24
Finished Aug 04 04:51:35 PM PDT 24
Peak memory 199836 kb
Host smart-30a18313-822b-4dcc-a5a9-2892baf1b280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965644955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3965644955
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3406020487
Short name T219
Test name
Test status
Simulation time 30344477901 ps
CPU time 129.05 seconds
Started Aug 04 04:51:30 PM PDT 24
Finished Aug 04 04:53:39 PM PDT 24
Peak memory 199976 kb
Host smart-46bb0f02-99b5-49b0-89b6-9d68ddc9cad9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406020487 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3406020487
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2227255372
Short name T396
Test name
Test status
Simulation time 3997898973 ps
CPU time 19.48 seconds
Started Aug 04 04:51:29 PM PDT 24
Finished Aug 04 04:51:49 PM PDT 24
Peak memory 199936 kb
Host smart-d0a94f78-ff1d-469c-bc1d-ba720a1aee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227255372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2227255372
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2983679125
Short name T497
Test name
Test status
Simulation time 25926965 ps
CPU time 0.65 seconds
Started Aug 04 04:51:36 PM PDT 24
Finished Aug 04 04:51:36 PM PDT 24
Peak memory 196504 kb
Host smart-c56498d7-d399-44ef-88a9-fe4270cb64fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983679125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2983679125
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3732031596
Short name T309
Test name
Test status
Simulation time 1967240767 ps
CPU time 32.38 seconds
Started Aug 04 04:51:31 PM PDT 24
Finished Aug 04 04:52:03 PM PDT 24
Peak memory 199876 kb
Host smart-baa975ab-fe40-49c1-8007-d5b6acb8a3b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732031596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3732031596
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2843529243
Short name T259
Test name
Test status
Simulation time 12620701482 ps
CPU time 80.27 seconds
Started Aug 04 04:51:33 PM PDT 24
Finished Aug 04 04:52:53 PM PDT 24
Peak memory 199948 kb
Host smart-6abfb6e4-ebb1-4066-a736-e2559f89c599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843529243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2843529243
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2187899750
Short name T362
Test name
Test status
Simulation time 30526291687 ps
CPU time 1324.2 seconds
Started Aug 04 04:51:34 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 752264 kb
Host smart-5c3f8582-8648-45b9-8281-0930d547f138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187899750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2187899750
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3369633552
Short name T522
Test name
Test status
Simulation time 3287349459 ps
CPU time 90.34 seconds
Started Aug 04 04:51:32 PM PDT 24
Finished Aug 04 04:53:03 PM PDT 24
Peak memory 199988 kb
Host smart-402e94c0-9bc6-4598-8439-cedbd06d572b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369633552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3369633552
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1721941308
Short name T421
Test name
Test status
Simulation time 12737399680 ps
CPU time 182.7 seconds
Started Aug 04 04:51:31 PM PDT 24
Finished Aug 04 04:54:33 PM PDT 24
Peak memory 200012 kb
Host smart-bb147c26-e915-4e06-beb9-47f7a276cf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721941308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1721941308
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2589775908
Short name T292
Test name
Test status
Simulation time 340160647 ps
CPU time 5.77 seconds
Started Aug 04 04:51:30 PM PDT 24
Finished Aug 04 04:51:36 PM PDT 24
Peak memory 199860 kb
Host smart-60264a9a-4d5a-4ab5-ac49-ff4677603d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589775908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2589775908
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.4102545432
Short name T408
Test name
Test status
Simulation time 40390759284 ps
CPU time 1378.43 seconds
Started Aug 04 04:51:35 PM PDT 24
Finished Aug 04 05:14:33 PM PDT 24
Peak memory 726068 kb
Host smart-85d05ea3-dd1a-4285-bf3e-0b262263e981
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102545432 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4102545432
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4178852165
Short name T439
Test name
Test status
Simulation time 283385984 ps
CPU time 17.85 seconds
Started Aug 04 04:51:35 PM PDT 24
Finished Aug 04 04:51:53 PM PDT 24
Peak memory 199728 kb
Host smart-dcfad068-1013-46ee-a370-1a563f1106aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178852165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4178852165
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4083704257
Short name T233
Test name
Test status
Simulation time 30660101 ps
CPU time 0.56 seconds
Started Aug 04 04:48:20 PM PDT 24
Finished Aug 04 04:48:21 PM PDT 24
Peak memory 195484 kb
Host smart-bdbd05b2-2953-4c43-a55e-c78dfdb594af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083704257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4083704257
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3319557836
Short name T389
Test name
Test status
Simulation time 7154671096 ps
CPU time 24.42 seconds
Started Aug 04 04:48:10 PM PDT 24
Finished Aug 04 04:48:35 PM PDT 24
Peak memory 199908 kb
Host smart-511c31c2-e315-4428-8d12-dca4ad2d0319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319557836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3319557836
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3164471352
Short name T149
Test name
Test status
Simulation time 2105822257 ps
CPU time 53.35 seconds
Started Aug 04 04:48:12 PM PDT 24
Finished Aug 04 04:49:05 PM PDT 24
Peak memory 199804 kb
Host smart-ea136e72-b34a-4e17-8c83-3d9cf23940a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164471352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3164471352
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.884309912
Short name T347
Test name
Test status
Simulation time 12490844 ps
CPU time 0.7 seconds
Started Aug 04 04:48:09 PM PDT 24
Finished Aug 04 04:48:10 PM PDT 24
Peak memory 198104 kb
Host smart-0eefddfe-4004-41de-afbf-63c53a2f322c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884309912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.884309912
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1959123388
Short name T378
Test name
Test status
Simulation time 23156023199 ps
CPU time 74.51 seconds
Started Aug 04 04:48:13 PM PDT 24
Finished Aug 04 04:49:28 PM PDT 24
Peak memory 200032 kb
Host smart-a06e56b8-8488-4924-a273-86b6ffa42cca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959123388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1959123388
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2511335882
Short name T209
Test name
Test status
Simulation time 2218644396 ps
CPU time 65.01 seconds
Started Aug 04 04:48:08 PM PDT 24
Finished Aug 04 04:49:13 PM PDT 24
Peak memory 199804 kb
Host smart-9754eaf7-4ddf-4e81-ba1f-a365c29fee34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511335882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2511335882
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1859625656
Short name T68
Test name
Test status
Simulation time 113474681 ps
CPU time 0.79 seconds
Started Aug 04 04:48:24 PM PDT 24
Finished Aug 04 04:48:24 PM PDT 24
Peak memory 218520 kb
Host smart-815f1b36-e861-4285-9a64-d292f143cebd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859625656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1859625656
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1325190147
Short name T39
Test name
Test status
Simulation time 908147955 ps
CPU time 10.81 seconds
Started Aug 04 04:48:08 PM PDT 24
Finished Aug 04 04:48:19 PM PDT 24
Peak memory 199828 kb
Host smart-366f9eda-595d-4f78-9692-9388b0e06945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325190147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1325190147
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2610565081
Short name T430
Test name
Test status
Simulation time 497699726816 ps
CPU time 2665.72 seconds
Started Aug 04 04:48:16 PM PDT 24
Finished Aug 04 05:32:42 PM PDT 24
Peak memory 776228 kb
Host smart-4a09ea2d-dc21-4a51-9369-8d43340d7161
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610565081 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2610565081
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1249552836
Short name T77
Test name
Test status
Simulation time 96351478192 ps
CPU time 3474.89 seconds
Started Aug 04 04:48:17 PM PDT 24
Finished Aug 04 05:46:12 PM PDT 24
Peak memory 815636 kb
Host smart-485c2828-06fd-4b2f-92eb-a723eece91af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249552836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1249552836
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.3275886175
Short name T289
Test name
Test status
Simulation time 13988556336 ps
CPU time 64.35 seconds
Started Aug 04 04:48:15 PM PDT 24
Finished Aug 04 04:49:20 PM PDT 24
Peak memory 199968 kb
Host smart-61341e5e-d596-4a52-bb61-3b084c1d2705
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3275886175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.3275886175
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2659154995
Short name T49
Test name
Test status
Simulation time 27170055692 ps
CPU time 105.71 seconds
Started Aug 04 04:48:16 PM PDT 24
Finished Aug 04 04:50:02 PM PDT 24
Peak memory 199916 kb
Host smart-964dd90e-12fe-40fe-8beb-6ea09108744d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2659154995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2659154995
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1325035152
Short name T456
Test name
Test status
Simulation time 31629915673 ps
CPU time 124.49 seconds
Started Aug 04 04:48:15 PM PDT 24
Finished Aug 04 04:50:20 PM PDT 24
Peak memory 200012 kb
Host smart-307077aa-49cf-46e6-921d-d5b60c7cf532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1325035152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1325035152
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.288209102
Short name T358
Test name
Test status
Simulation time 174240755708 ps
CPU time 631.88 seconds
Started Aug 04 04:48:16 PM PDT 24
Finished Aug 04 04:58:48 PM PDT 24
Peak memory 199968 kb
Host smart-3b6550c7-2631-48c5-ad14-04263fc8af1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=288209102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.288209102
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2904562990
Short name T505
Test name
Test status
Simulation time 176854528121 ps
CPU time 2249 seconds
Started Aug 04 04:48:15 PM PDT 24
Finished Aug 04 05:25:45 PM PDT 24
Peak memory 208140 kb
Host smart-0e232d6d-de77-4f6c-8b82-129ffd5062c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2904562990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2904562990
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2113081462
Short name T37
Test name
Test status
Simulation time 166504286373 ps
CPU time 2245.2 seconds
Started Aug 04 04:48:16 PM PDT 24
Finished Aug 04 05:25:41 PM PDT 24
Peak memory 215908 kb
Host smart-2f51739e-9732-4da5-91d7-4aeb9eb492bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2113081462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2113081462
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3326686756
Short name T340
Test name
Test status
Simulation time 3146455006 ps
CPU time 44.76 seconds
Started Aug 04 04:48:13 PM PDT 24
Finished Aug 04 04:48:58 PM PDT 24
Peak memory 199852 kb
Host smart-e4248381-5f45-4cf3-93c8-78668dd3ac1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326686756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3326686756
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4106295559
Short name T370
Test name
Test status
Simulation time 12618364 ps
CPU time 0.65 seconds
Started Aug 04 04:51:40 PM PDT 24
Finished Aug 04 04:51:41 PM PDT 24
Peak memory 196496 kb
Host smart-c82e56f4-ba88-47b6-9130-de522a6f5cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106295559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4106295559
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.312875147
Short name T453
Test name
Test status
Simulation time 3890066344 ps
CPU time 35.92 seconds
Started Aug 04 04:51:36 PM PDT 24
Finished Aug 04 04:52:12 PM PDT 24
Peak memory 208160 kb
Host smart-d6c32e22-773c-4296-854d-0c37d125417c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312875147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.312875147
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2679566287
Short name T447
Test name
Test status
Simulation time 716723527 ps
CPU time 40.53 seconds
Started Aug 04 04:51:37 PM PDT 24
Finished Aug 04 04:52:18 PM PDT 24
Peak memory 199832 kb
Host smart-ca17c5ce-782f-4624-b046-16e04990e6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679566287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2679566287
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3348955013
Short name T391
Test name
Test status
Simulation time 19852197089 ps
CPU time 1001.2 seconds
Started Aug 04 04:51:36 PM PDT 24
Finished Aug 04 05:08:17 PM PDT 24
Peak memory 691228 kb
Host smart-18f3b89d-6197-4ade-9cac-4cac4baca61d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348955013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3348955013
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3684672070
Short name T315
Test name
Test status
Simulation time 2100832552 ps
CPU time 28.58 seconds
Started Aug 04 04:51:36 PM PDT 24
Finished Aug 04 04:52:05 PM PDT 24
Peak memory 199756 kb
Host smart-1adabae3-bb4c-4d8d-8dbb-f2efc1bf0c13
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684672070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3684672070
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1000793881
Short name T375
Test name
Test status
Simulation time 9258503010 ps
CPU time 127.13 seconds
Started Aug 04 04:51:35 PM PDT 24
Finished Aug 04 04:53:42 PM PDT 24
Peak memory 199892 kb
Host smart-1afee407-dd0c-4907-b948-c240f976f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000793881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1000793881
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3498151759
Short name T455
Test name
Test status
Simulation time 5077221580 ps
CPU time 11.3 seconds
Started Aug 04 04:51:36 PM PDT 24
Finished Aug 04 04:51:48 PM PDT 24
Peak memory 199960 kb
Host smart-08c61b93-81d3-423e-87f7-de6a7fe1cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498151759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3498151759
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2842612910
Short name T413
Test name
Test status
Simulation time 39398810225 ps
CPU time 755.83 seconds
Started Aug 04 04:51:40 PM PDT 24
Finished Aug 04 05:04:16 PM PDT 24
Peak memory 216308 kb
Host smart-dae30118-a07a-4e83-8cec-7ed4287d84aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842612910 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2842612910
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3600976021
Short name T474
Test name
Test status
Simulation time 24310602623 ps
CPU time 27.32 seconds
Started Aug 04 04:51:39 PM PDT 24
Finished Aug 04 04:52:06 PM PDT 24
Peak memory 200052 kb
Host smart-331e2a52-f6a4-49a6-99df-6917a36aecdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600976021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3600976021
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.677702268
Short name T503
Test name
Test status
Simulation time 34995773 ps
CPU time 0.56 seconds
Started Aug 04 04:51:46 PM PDT 24
Finished Aug 04 04:51:47 PM PDT 24
Peak memory 195812 kb
Host smart-0d81096c-36f5-4d9f-b53c-e46af490e668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677702268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.677702268
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3306237517
Short name T383
Test name
Test status
Simulation time 3681429330 ps
CPU time 48.22 seconds
Started Aug 04 04:51:43 PM PDT 24
Finished Aug 04 04:52:31 PM PDT 24
Peak memory 199888 kb
Host smart-c1e01bf9-50a3-4dda-bd0c-3235f619e50d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306237517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3306237517
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.691090993
Short name T297
Test name
Test status
Simulation time 4438306928 ps
CPU time 57.23 seconds
Started Aug 04 04:51:40 PM PDT 24
Finished Aug 04 04:52:37 PM PDT 24
Peak memory 199884 kb
Host smart-6b0691f1-d3ac-4267-b9e8-82de72379be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691090993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.691090993
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1815043141
Short name T1
Test name
Test status
Simulation time 2723484617 ps
CPU time 323.37 seconds
Started Aug 04 04:51:40 PM PDT 24
Finished Aug 04 04:57:04 PM PDT 24
Peak memory 493144 kb
Host smart-20446467-5de2-46b6-ab45-ef9ce41a82c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815043141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1815043141
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1312095564
Short name T152
Test name
Test status
Simulation time 719891684 ps
CPU time 43.03 seconds
Started Aug 04 04:51:40 PM PDT 24
Finished Aug 04 04:52:23 PM PDT 24
Peak memory 199788 kb
Host smart-8e9df152-da54-4cfb-b10a-40e05cde5bd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312095564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1312095564
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3151672487
Short name T457
Test name
Test status
Simulation time 676567132 ps
CPU time 9.91 seconds
Started Aug 04 04:51:40 PM PDT 24
Finished Aug 04 04:51:50 PM PDT 24
Peak memory 199748 kb
Host smart-cbc8f92c-a56c-4c1e-91cb-4648e7ea74cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151672487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3151672487
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2427767885
Short name T317
Test name
Test status
Simulation time 42522687 ps
CPU time 1.86 seconds
Started Aug 04 04:51:39 PM PDT 24
Finished Aug 04 04:51:41 PM PDT 24
Peak memory 199784 kb
Host smart-28809550-e644-4c95-ae48-9faa141f8a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427767885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2427767885
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2782675027
Short name T529
Test name
Test status
Simulation time 40069075724 ps
CPU time 1254.15 seconds
Started Aug 04 04:51:45 PM PDT 24
Finished Aug 04 05:12:39 PM PDT 24
Peak memory 724092 kb
Host smart-f188e048-2c61-4df9-a614-3f2714ebdc1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782675027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2782675027
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1930635956
Short name T20
Test name
Test status
Simulation time 3944634058 ps
CPU time 53.06 seconds
Started Aug 04 04:51:39 PM PDT 24
Finished Aug 04 04:52:32 PM PDT 24
Peak memory 199960 kb
Host smart-74833521-e975-4971-8fb4-f5babed3f83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930635956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1930635956
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.142904085
Short name T158
Test name
Test status
Simulation time 39900387 ps
CPU time 0.64 seconds
Started Aug 04 04:51:51 PM PDT 24
Finished Aug 04 04:51:51 PM PDT 24
Peak memory 195924 kb
Host smart-fc55374c-95ce-42dc-a5d6-7bc536c13948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142904085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.142904085
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1986307801
Short name T196
Test name
Test status
Simulation time 1460478740 ps
CPU time 82.57 seconds
Started Aug 04 04:51:47 PM PDT 24
Finished Aug 04 04:53:10 PM PDT 24
Peak memory 199816 kb
Host smart-d0f271ef-c79e-4fe8-a9c3-e701588dd425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1986307801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1986307801
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1286840969
Short name T332
Test name
Test status
Simulation time 10151533257 ps
CPU time 27.03 seconds
Started Aug 04 04:51:46 PM PDT 24
Finished Aug 04 04:52:13 PM PDT 24
Peak memory 208060 kb
Host smart-e56188d9-c811-423c-a0a1-8ea29157fc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286840969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1286840969
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4145674688
Short name T372
Test name
Test status
Simulation time 26729523324 ps
CPU time 1230.82 seconds
Started Aug 04 04:51:48 PM PDT 24
Finished Aug 04 05:12:19 PM PDT 24
Peak memory 703228 kb
Host smart-bc7c88ba-f63b-465a-91a8-2d3999e423bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145674688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4145674688
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.583903888
Short name T157
Test name
Test status
Simulation time 45674349604 ps
CPU time 139.53 seconds
Started Aug 04 04:51:47 PM PDT 24
Finished Aug 04 04:54:07 PM PDT 24
Peak memory 199864 kb
Host smart-fb87b809-3fef-4e40-87cc-c3dfa143dcc4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583903888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.583903888
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1640188345
Short name T312
Test name
Test status
Simulation time 4216070344 ps
CPU time 59.02 seconds
Started Aug 04 04:51:45 PM PDT 24
Finished Aug 04 04:52:44 PM PDT 24
Peak memory 199976 kb
Host smart-f9c59375-5c81-4acb-809f-06732260bff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640188345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1640188345
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1211803287
Short name T433
Test name
Test status
Simulation time 587708583 ps
CPU time 6.12 seconds
Started Aug 04 04:51:46 PM PDT 24
Finished Aug 04 04:51:52 PM PDT 24
Peak memory 199836 kb
Host smart-4ff2080c-a046-4a83-bc58-a9e7805d4292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211803287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1211803287
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2080567584
Short name T127
Test name
Test status
Simulation time 74538178016 ps
CPU time 1672 seconds
Started Aug 04 04:51:49 PM PDT 24
Finished Aug 04 05:19:41 PM PDT 24
Peak memory 757928 kb
Host smart-face4329-d11b-4957-a9c0-46afdf514686
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080567584 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2080567584
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3206626952
Short name T256
Test name
Test status
Simulation time 7935812802 ps
CPU time 106.04 seconds
Started Aug 04 04:51:47 PM PDT 24
Finished Aug 04 04:53:33 PM PDT 24
Peak memory 199896 kb
Host smart-2d819088-81eb-41ce-b52e-94ecbf829321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206626952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3206626952
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2957950370
Short name T444
Test name
Test status
Simulation time 25564443 ps
CPU time 0.59 seconds
Started Aug 04 04:51:53 PM PDT 24
Finished Aug 04 04:51:54 PM PDT 24
Peak memory 195480 kb
Host smart-7193e374-f09a-403f-8b49-16860a105899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957950370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2957950370
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.978432087
Short name T293
Test name
Test status
Simulation time 1120650416 ps
CPU time 67.15 seconds
Started Aug 04 04:51:50 PM PDT 24
Finished Aug 04 04:52:57 PM PDT 24
Peak memory 199852 kb
Host smart-11be5006-5c4b-47cb-8725-c345eb31c8af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978432087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.978432087
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1498759473
Short name T296
Test name
Test status
Simulation time 2231431505 ps
CPU time 9.28 seconds
Started Aug 04 04:51:52 PM PDT 24
Finished Aug 04 04:52:01 PM PDT 24
Peak memory 199856 kb
Host smart-deed3b70-fd8a-49eb-a1af-0f0d9402e5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498759473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1498759473
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.31621421
Short name T471
Test name
Test status
Simulation time 4319363991 ps
CPU time 781.22 seconds
Started Aug 04 04:51:53 PM PDT 24
Finished Aug 04 05:04:54 PM PDT 24
Peak memory 744280 kb
Host smart-5c841cf2-dd91-45f1-906a-a62938c2da61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31621421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.31621421
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.166745183
Short name T428
Test name
Test status
Simulation time 5195889542 ps
CPU time 92.53 seconds
Started Aug 04 04:51:51 PM PDT 24
Finished Aug 04 04:53:23 PM PDT 24
Peak memory 199952 kb
Host smart-f11d6258-c85c-4715-a440-f9538ff14eca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166745183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.166745183
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3516400744
Short name T248
Test name
Test status
Simulation time 7378316353 ps
CPU time 108.08 seconds
Started Aug 04 04:51:52 PM PDT 24
Finished Aug 04 04:53:40 PM PDT 24
Peak memory 199868 kb
Host smart-4fad35a6-1291-416c-9e3b-c2f4d2ef22da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516400744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3516400744
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.645410669
Short name T182
Test name
Test status
Simulation time 800763994 ps
CPU time 13.38 seconds
Started Aug 04 04:51:50 PM PDT 24
Finished Aug 04 04:52:03 PM PDT 24
Peak memory 199864 kb
Host smart-2debb87a-97cd-4a77-a7d8-9becf6bacd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645410669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.645410669
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.889090063
Short name T61
Test name
Test status
Simulation time 27028452250 ps
CPU time 69.85 seconds
Started Aug 04 04:51:49 PM PDT 24
Finished Aug 04 04:52:59 PM PDT 24
Peak memory 208164 kb
Host smart-3ad9cb26-1202-49fd-bc5b-6d5a7732ca38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889090063 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.889090063
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3207212558
Short name T274
Test name
Test status
Simulation time 14336407187 ps
CPU time 92.85 seconds
Started Aug 04 04:51:50 PM PDT 24
Finished Aug 04 04:53:23 PM PDT 24
Peak memory 200044 kb
Host smart-e6fed19b-04bb-4ac8-88ff-6c5d0d0809df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207212558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3207212558
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2334717472
Short name T411
Test name
Test status
Simulation time 59460601 ps
CPU time 0.58 seconds
Started Aug 04 04:51:54 PM PDT 24
Finished Aug 04 04:51:54 PM PDT 24
Peak memory 195868 kb
Host smart-dd243be4-749c-484d-9165-b39ca07c373f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334717472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2334717472
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.4117045772
Short name T350
Test name
Test status
Simulation time 88766008 ps
CPU time 0.99 seconds
Started Aug 04 04:51:57 PM PDT 24
Finished Aug 04 04:51:58 PM PDT 24
Peak memory 199420 kb
Host smart-2d04913c-0952-4414-9512-dba2ba4ef110
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117045772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.4117045772
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1909147779
Short name T476
Test name
Test status
Simulation time 2280131174 ps
CPU time 61.34 seconds
Started Aug 04 04:51:55 PM PDT 24
Finished Aug 04 04:52:56 PM PDT 24
Peak memory 199880 kb
Host smart-96daddbb-4f91-4d06-88bc-029500925c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909147779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1909147779
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1525465943
Short name T299
Test name
Test status
Simulation time 4756844970 ps
CPU time 794.56 seconds
Started Aug 04 04:51:55 PM PDT 24
Finished Aug 04 05:05:09 PM PDT 24
Peak memory 718916 kb
Host smart-261e42a8-9282-45cc-bb2c-9fbc44a6d32d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525465943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1525465943
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.716536393
Short name T452
Test name
Test status
Simulation time 5557498886 ps
CPU time 77.59 seconds
Started Aug 04 04:51:54 PM PDT 24
Finished Aug 04 04:53:11 PM PDT 24
Peak memory 199828 kb
Host smart-75b3bb0d-1ba6-427f-9848-464924b4f428
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716536393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.716536393
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1400703697
Short name T399
Test name
Test status
Simulation time 11202945860 ps
CPU time 203.13 seconds
Started Aug 04 04:51:54 PM PDT 24
Finished Aug 04 04:55:18 PM PDT 24
Peak memory 199888 kb
Host smart-e217318c-bbcc-4c5a-9370-974c1c76569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400703697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1400703697
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3427263425
Short name T318
Test name
Test status
Simulation time 460584137 ps
CPU time 5.66 seconds
Started Aug 04 04:51:57 PM PDT 24
Finished Aug 04 04:52:03 PM PDT 24
Peak memory 199804 kb
Host smart-13c5db63-131e-4c2d-b75e-c4f33594126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427263425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3427263425
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3717710270
Short name T197
Test name
Test status
Simulation time 14154645312 ps
CPU time 784.51 seconds
Started Aug 04 04:51:57 PM PDT 24
Finished Aug 04 05:05:02 PM PDT 24
Peak memory 695200 kb
Host smart-e8839e5b-6105-47e7-9fe5-2cb404422e48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717710270 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3717710270
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.950103276
Short name T211
Test name
Test status
Simulation time 6950248241 ps
CPU time 120.71 seconds
Started Aug 04 04:51:55 PM PDT 24
Finished Aug 04 04:53:56 PM PDT 24
Peak memory 199940 kb
Host smart-bebc7799-2f42-447f-9462-e7debac1b0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950103276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.950103276
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2845160306
Short name T67
Test name
Test status
Simulation time 42553332 ps
CPU time 0.6 seconds
Started Aug 04 04:51:57 PM PDT 24
Finished Aug 04 04:51:57 PM PDT 24
Peak memory 195864 kb
Host smart-f8000e8d-f9c7-426f-9386-b924ae7c953d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845160306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2845160306
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3330951351
Short name T478
Test name
Test status
Simulation time 348100440 ps
CPU time 12.94 seconds
Started Aug 04 04:51:58 PM PDT 24
Finished Aug 04 04:52:11 PM PDT 24
Peak memory 199764 kb
Host smart-1938af18-b93e-4e3f-a4bc-7142698984f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3330951351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3330951351
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3452661117
Short name T242
Test name
Test status
Simulation time 4840999301 ps
CPU time 26.41 seconds
Started Aug 04 04:51:57 PM PDT 24
Finished Aug 04 04:52:24 PM PDT 24
Peak memory 199876 kb
Host smart-3d4e9e2e-5e1c-47fe-b298-4d4a64020b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452661117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3452661117
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1461742096
Short name T462
Test name
Test status
Simulation time 2634665719 ps
CPU time 68.91 seconds
Started Aug 04 04:52:01 PM PDT 24
Finished Aug 04 04:53:10 PM PDT 24
Peak memory 344548 kb
Host smart-63060789-267b-4fb6-bf71-f5cce3875a68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1461742096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1461742096
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3071914427
Short name T153
Test name
Test status
Simulation time 894710628 ps
CPU time 30.13 seconds
Started Aug 04 04:51:59 PM PDT 24
Finished Aug 04 04:52:29 PM PDT 24
Peak memory 199864 kb
Host smart-b806b8e9-12ec-4de1-9045-4414a6372e6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071914427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3071914427
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4175395861
Short name T43
Test name
Test status
Simulation time 9128927456 ps
CPU time 115.8 seconds
Started Aug 04 04:52:00 PM PDT 24
Finished Aug 04 04:53:56 PM PDT 24
Peak memory 200184 kb
Host smart-06b3b3a2-eb83-4f02-a182-7d50e0c0c025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175395861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4175395861
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3143404526
Short name T377
Test name
Test status
Simulation time 1162620192 ps
CPU time 14.82 seconds
Started Aug 04 04:51:57 PM PDT 24
Finished Aug 04 04:52:12 PM PDT 24
Peak memory 199828 kb
Host smart-c7489554-cf42-4fad-baa1-552c3d2c2af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143404526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3143404526
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.260453597
Short name T89
Test name
Test status
Simulation time 79791013233 ps
CPU time 146.5 seconds
Started Aug 04 04:52:00 PM PDT 24
Finished Aug 04 04:54:27 PM PDT 24
Peak memory 216340 kb
Host smart-21046613-ec4d-4c7d-b704-d35b45ade749
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260453597 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.260453597
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3458678745
Short name T472
Test name
Test status
Simulation time 11622120255 ps
CPU time 70.3 seconds
Started Aug 04 04:51:58 PM PDT 24
Finished Aug 04 04:53:08 PM PDT 24
Peak memory 199884 kb
Host smart-5f2126b8-aff5-46db-8812-ff339081827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458678745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3458678745
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.51611116
Short name T393
Test name
Test status
Simulation time 23500092 ps
CPU time 0.61 seconds
Started Aug 04 04:52:09 PM PDT 24
Finished Aug 04 04:52:10 PM PDT 24
Peak memory 195864 kb
Host smart-493c608d-53ce-4da7-9167-1e38c930a2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51611116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.51611116
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2641565924
Short name T208
Test name
Test status
Simulation time 1388159713 ps
CPU time 36.54 seconds
Started Aug 04 04:52:01 PM PDT 24
Finished Aug 04 04:52:38 PM PDT 24
Peak memory 199892 kb
Host smart-9cccd0e0-4ab6-44dd-92b5-c36015f95427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641565924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2641565924
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3493706897
Short name T339
Test name
Test status
Simulation time 1701755059 ps
CPU time 22.62 seconds
Started Aug 04 04:52:04 PM PDT 24
Finished Aug 04 04:52:27 PM PDT 24
Peak memory 199836 kb
Host smart-77edf93b-02a0-49c8-b153-2f8754b869eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493706897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3493706897
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3820587649
Short name T323
Test name
Test status
Simulation time 4232499861 ps
CPU time 357.83 seconds
Started Aug 04 04:52:00 PM PDT 24
Finished Aug 04 04:57:58 PM PDT 24
Peak memory 640328 kb
Host smart-2c7dc4bb-02fb-41bd-a700-932ff5e0d77a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820587649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3820587649
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1598285760
Short name T156
Test name
Test status
Simulation time 16784335234 ps
CPU time 81.45 seconds
Started Aug 04 04:52:06 PM PDT 24
Finished Aug 04 04:53:28 PM PDT 24
Peak memory 199884 kb
Host smart-e6d77ac4-b090-4fb2-9d2f-c92c68581bd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598285760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1598285760
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.831662118
Short name T346
Test name
Test status
Simulation time 19451559879 ps
CPU time 179.38 seconds
Started Aug 04 04:52:01 PM PDT 24
Finished Aug 04 04:55:00 PM PDT 24
Peak memory 216272 kb
Host smart-2766b680-9f85-4c39-8ff7-4dceaa1967b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831662118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.831662118
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.590173678
Short name T491
Test name
Test status
Simulation time 676579283 ps
CPU time 11.05 seconds
Started Aug 04 04:51:58 PM PDT 24
Finished Aug 04 04:52:09 PM PDT 24
Peak memory 199896 kb
Host smart-4dfb412f-6af4-4933-8f44-27012833e16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590173678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.590173678
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.609618928
Short name T125
Test name
Test status
Simulation time 5539535546 ps
CPU time 77.89 seconds
Started Aug 04 04:52:05 PM PDT 24
Finished Aug 04 04:53:23 PM PDT 24
Peak memory 199944 kb
Host smart-65815077-6acd-4ddc-8e4b-7bd3621b504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609618928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.609618928
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1695282347
Short name T267
Test name
Test status
Simulation time 21080147 ps
CPU time 0.59 seconds
Started Aug 04 04:52:09 PM PDT 24
Finished Aug 04 04:52:10 PM PDT 24
Peak memory 195488 kb
Host smart-5ad269f2-3f56-4a66-9ae0-486aad03fa46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695282347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1695282347
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3991734977
Short name T436
Test name
Test status
Simulation time 6661220691 ps
CPU time 30.49 seconds
Started Aug 04 04:52:10 PM PDT 24
Finished Aug 04 04:52:41 PM PDT 24
Peak memory 216176 kb
Host smart-a99e7cbd-3818-4a39-b033-e6efba857faf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3991734977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3991734977
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1135235898
Short name T264
Test name
Test status
Simulation time 3767614012 ps
CPU time 71.07 seconds
Started Aug 04 04:52:11 PM PDT 24
Finished Aug 04 04:53:22 PM PDT 24
Peak memory 199836 kb
Host smart-abf940cb-1f5c-4158-9142-f8ce5f51c283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135235898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1135235898
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2737184538
Short name T531
Test name
Test status
Simulation time 13148637957 ps
CPU time 664.93 seconds
Started Aug 04 04:52:09 PM PDT 24
Finished Aug 04 05:03:15 PM PDT 24
Peak memory 729696 kb
Host smart-8706d6c1-03f6-4b0f-a045-67c3564f1f2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737184538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2737184538
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.884689512
Short name T382
Test name
Test status
Simulation time 8542695107 ps
CPU time 101.18 seconds
Started Aug 04 04:52:09 PM PDT 24
Finished Aug 04 04:53:51 PM PDT 24
Peak memory 199940 kb
Host smart-36c8c327-b109-4b73-b971-ed2bc25e153e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884689512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.884689512
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1753246999
Short name T144
Test name
Test status
Simulation time 2857990773 ps
CPU time 168.94 seconds
Started Aug 04 04:52:12 PM PDT 24
Finished Aug 04 04:55:01 PM PDT 24
Peak memory 200024 kb
Host smart-4a3c8f8f-e496-405a-a460-3ce28e6fcf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753246999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1753246999
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.161646754
Short name T406
Test name
Test status
Simulation time 297680259 ps
CPU time 12.93 seconds
Started Aug 04 04:52:08 PM PDT 24
Finished Aug 04 04:52:21 PM PDT 24
Peak memory 199860 kb
Host smart-18b18850-e79a-4144-aac6-43d7638b106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161646754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.161646754
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.39975921
Short name T440
Test name
Test status
Simulation time 65846116303 ps
CPU time 1511.16 seconds
Started Aug 04 04:52:10 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 713544 kb
Host smart-dd30d4f2-d447-4ba2-9994-5a6a0c81c7fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39975921 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.39975921
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.392655443
Short name T338
Test name
Test status
Simulation time 10644138977 ps
CPU time 35.9 seconds
Started Aug 04 04:52:11 PM PDT 24
Finished Aug 04 04:52:47 PM PDT 24
Peak memory 199940 kb
Host smart-553edfad-06be-4bcc-b0d0-b1b2f302db7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392655443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.392655443
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.586018100
Short name T513
Test name
Test status
Simulation time 13797054 ps
CPU time 0.59 seconds
Started Aug 04 04:52:13 PM PDT 24
Finished Aug 04 04:52:14 PM PDT 24
Peak memory 194792 kb
Host smart-c43abc79-0677-4561-9c94-1caf850aff94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586018100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.586018100
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3768033058
Short name T243
Test name
Test status
Simulation time 345384445 ps
CPU time 11.14 seconds
Started Aug 04 04:52:14 PM PDT 24
Finished Aug 04 04:52:26 PM PDT 24
Peak memory 199732 kb
Host smart-606b59a8-5564-4b10-81b4-1f28a3940196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3768033058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3768033058
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.562958067
Short name T341
Test name
Test status
Simulation time 1331246181 ps
CPU time 76.76 seconds
Started Aug 04 04:52:16 PM PDT 24
Finished Aug 04 04:53:33 PM PDT 24
Peak memory 199880 kb
Host smart-f2adaf6c-c49e-429c-8790-c466b1704a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562958067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.562958067
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2951421750
Short name T44
Test name
Test status
Simulation time 7839786311 ps
CPU time 731.26 seconds
Started Aug 04 04:52:13 PM PDT 24
Finished Aug 04 05:04:24 PM PDT 24
Peak memory 701952 kb
Host smart-3839fd6e-9247-4ec0-9f16-c5413f6d9949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951421750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2951421750
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.907271217
Short name T63
Test name
Test status
Simulation time 6384621306 ps
CPU time 66.93 seconds
Started Aug 04 04:52:16 PM PDT 24
Finished Aug 04 04:53:23 PM PDT 24
Peak memory 199936 kb
Host smart-6ef55382-fb6c-4b14-832e-77aa688cf735
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907271217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.907271217
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2608074882
Short name T21
Test name
Test status
Simulation time 3248263377 ps
CPU time 59.05 seconds
Started Aug 04 04:52:08 PM PDT 24
Finished Aug 04 04:53:08 PM PDT 24
Peak memory 199920 kb
Host smart-fcf46bba-8b4a-4084-936d-f0d87a22f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608074882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2608074882
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.64776130
Short name T423
Test name
Test status
Simulation time 292108323 ps
CPU time 13.74 seconds
Started Aug 04 04:52:12 PM PDT 24
Finished Aug 04 04:52:25 PM PDT 24
Peak memory 199860 kb
Host smart-e866dfed-4e53-4eb5-8466-bdade4866dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64776130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.64776130
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4174726544
Short name T85
Test name
Test status
Simulation time 1232289723521 ps
CPU time 1904.33 seconds
Started Aug 04 04:52:14 PM PDT 24
Finished Aug 04 05:23:59 PM PDT 24
Peak memory 687472 kb
Host smart-3c5d544e-eb76-4f37-9c70-9e78cf9bd884
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174726544 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4174726544
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2780324906
Short name T343
Test name
Test status
Simulation time 13473960772 ps
CPU time 65.36 seconds
Started Aug 04 04:52:14 PM PDT 24
Finished Aug 04 04:53:19 PM PDT 24
Peak memory 199880 kb
Host smart-8c53d604-dc5d-4da0-874f-554adb518a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780324906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2780324906
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.4265272267
Short name T73
Test name
Test status
Simulation time 46301070 ps
CPU time 0.61 seconds
Started Aug 04 04:52:19 PM PDT 24
Finished Aug 04 04:52:20 PM PDT 24
Peak memory 195904 kb
Host smart-829e4d94-e71d-4ec9-9b41-bddcaa4f6047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265272267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.4265272267
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1576886007
Short name T168
Test name
Test status
Simulation time 1362305605 ps
CPU time 78.97 seconds
Started Aug 04 04:52:17 PM PDT 24
Finished Aug 04 04:53:36 PM PDT 24
Peak memory 199724 kb
Host smart-52432ed6-91ec-4613-be99-52b93def5684
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1576886007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1576886007
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.210144834
Short name T255
Test name
Test status
Simulation time 406615680 ps
CPU time 5.84 seconds
Started Aug 04 04:52:21 PM PDT 24
Finished Aug 04 04:52:27 PM PDT 24
Peak memory 199772 kb
Host smart-2c1a3e26-a40d-4d49-805e-26594dfb3349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210144834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.210144834
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2137058054
Short name T450
Test name
Test status
Simulation time 5290021518 ps
CPU time 1021.64 seconds
Started Aug 04 04:52:17 PM PDT 24
Finished Aug 04 05:09:19 PM PDT 24
Peak memory 711920 kb
Host smart-4eb774cf-4379-4b86-8564-002c9a22a9d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137058054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2137058054
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.4212527153
Short name T214
Test name
Test status
Simulation time 4582661284 ps
CPU time 120.41 seconds
Started Aug 04 04:52:19 PM PDT 24
Finished Aug 04 04:54:19 PM PDT 24
Peak memory 199952 kb
Host smart-69d7ec46-2a23-48da-9204-2771fc9e9d43
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212527153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4212527153
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2080987514
Short name T485
Test name
Test status
Simulation time 1252668196 ps
CPU time 73.86 seconds
Started Aug 04 04:52:17 PM PDT 24
Finished Aug 04 04:53:31 PM PDT 24
Peak memory 199832 kb
Host smart-22c09b0f-4472-482f-99f2-3e8d11b73b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080987514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2080987514
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.674429305
Short name T500
Test name
Test status
Simulation time 103349276 ps
CPU time 2.5 seconds
Started Aug 04 04:52:17 PM PDT 24
Finished Aug 04 04:52:20 PM PDT 24
Peak memory 199868 kb
Host smart-59cf8d73-06d0-4e72-b17c-47d24d66ab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674429305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.674429305
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.314932109
Short name T527
Test name
Test status
Simulation time 143269968451 ps
CPU time 5031.42 seconds
Started Aug 04 04:52:21 PM PDT 24
Finished Aug 04 06:16:13 PM PDT 24
Peak memory 801412 kb
Host smart-2eabaca6-7d75-4daf-bef2-0c3b7490afb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314932109 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.314932109
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1325939483
Short name T394
Test name
Test status
Simulation time 5761647127 ps
CPU time 104.45 seconds
Started Aug 04 04:52:21 PM PDT 24
Finished Aug 04 04:54:05 PM PDT 24
Peak memory 199936 kb
Host smart-3822e006-1c5e-4e57-8e2f-ea80603413ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325939483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1325939483
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1971241628
Short name T357
Test name
Test status
Simulation time 40619721 ps
CPU time 0.55 seconds
Started Aug 04 04:48:23 PM PDT 24
Finished Aug 04 04:48:24 PM PDT 24
Peak memory 195540 kb
Host smart-9057f7d0-7a3b-4f92-a129-8af1590c9063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971241628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1971241628
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1069038354
Short name T441
Test name
Test status
Simulation time 511893744 ps
CPU time 31.14 seconds
Started Aug 04 04:48:20 PM PDT 24
Finished Aug 04 04:48:51 PM PDT 24
Peak memory 199760 kb
Host smart-a6561a5b-1276-4836-857c-b0454837db7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069038354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1069038354
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3736651841
Short name T167
Test name
Test status
Simulation time 1795996370 ps
CPU time 16.85 seconds
Started Aug 04 04:48:19 PM PDT 24
Finished Aug 04 04:48:36 PM PDT 24
Peak memory 199784 kb
Host smart-25f4417b-7d92-421c-9fb3-506707ac5d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736651841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3736651841
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1135758212
Short name T244
Test name
Test status
Simulation time 8703312345 ps
CPU time 303.49 seconds
Started Aug 04 04:48:20 PM PDT 24
Finished Aug 04 04:53:23 PM PDT 24
Peak memory 651548 kb
Host smart-c46e1c83-1a55-4a8d-8808-dae717d00c3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135758212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1135758212
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.667820636
Short name T183
Test name
Test status
Simulation time 1754612975 ps
CPU time 96.71 seconds
Started Aug 04 04:48:19 PM PDT 24
Finished Aug 04 04:49:56 PM PDT 24
Peak memory 199784 kb
Host smart-75a32b41-a35e-4f81-b28b-9ed1eb53014b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667820636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.667820636
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3243009442
Short name T429
Test name
Test status
Simulation time 9803279740 ps
CPU time 150.9 seconds
Started Aug 04 04:48:21 PM PDT 24
Finished Aug 04 04:50:52 PM PDT 24
Peak memory 200236 kb
Host smart-045fa7af-634a-4020-bda7-d2c5b2e97ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243009442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3243009442
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3611462986
Short name T179
Test name
Test status
Simulation time 5077670225 ps
CPU time 10.88 seconds
Started Aug 04 04:48:19 PM PDT 24
Finished Aug 04 04:48:30 PM PDT 24
Peak memory 200004 kb
Host smart-dcc77d6e-beac-4a49-bf6f-1b76ee819852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611462986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3611462986
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2719703044
Short name T227
Test name
Test status
Simulation time 15597161878 ps
CPU time 176.2 seconds
Started Aug 04 04:48:23 PM PDT 24
Finished Aug 04 04:51:20 PM PDT 24
Peak memory 200200 kb
Host smart-e1b0738d-5c2d-4fef-97a5-b5de23919e16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719703044 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2719703044
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2920763232
Short name T26
Test name
Test status
Simulation time 53752723290 ps
CPU time 1301.74 seconds
Started Aug 04 04:48:23 PM PDT 24
Finished Aug 04 05:10:05 PM PDT 24
Peak memory 214996 kb
Host smart-eb30a519-9790-4687-88d3-7e1c1555d903
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920763232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2920763232
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1203404750
Short name T380
Test name
Test status
Simulation time 170256105916 ps
CPU time 102.6 seconds
Started Aug 04 04:48:23 PM PDT 24
Finished Aug 04 04:50:06 PM PDT 24
Peak memory 199992 kb
Host smart-d52649ae-02f3-4cdd-9fb2-51338255057f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203404750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1203404750
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1571568630
Short name T498
Test name
Test status
Simulation time 18970576 ps
CPU time 0.61 seconds
Started Aug 04 04:48:37 PM PDT 24
Finished Aug 04 04:48:38 PM PDT 24
Peak memory 196568 kb
Host smart-f9650830-84a5-4172-a855-a325900aa296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571568630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1571568630
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3221274638
Short name T349
Test name
Test status
Simulation time 3034346051 ps
CPU time 26.05 seconds
Started Aug 04 04:48:27 PM PDT 24
Finished Aug 04 04:48:54 PM PDT 24
Peak memory 199968 kb
Host smart-3239ea95-b3b3-46c2-afd1-da60db99e408
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221274638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3221274638
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.120580764
Short name T401
Test name
Test status
Simulation time 4213560902 ps
CPU time 15.52 seconds
Started Aug 04 04:48:26 PM PDT 24
Finished Aug 04 04:48:41 PM PDT 24
Peak memory 199976 kb
Host smart-416ca783-712d-4fcd-9674-31b808504b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120580764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.120580764
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3195492454
Short name T201
Test name
Test status
Simulation time 18356513151 ps
CPU time 699.15 seconds
Started Aug 04 04:48:26 PM PDT 24
Finished Aug 04 05:00:06 PM PDT 24
Peak memory 690276 kb
Host smart-74f52fa3-f93a-4137-82a9-38d4f6131610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3195492454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3195492454
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2296494158
Short name T241
Test name
Test status
Simulation time 4451452113 ps
CPU time 58.81 seconds
Started Aug 04 04:48:29 PM PDT 24
Finished Aug 04 04:49:27 PM PDT 24
Peak memory 200028 kb
Host smart-c3c1b811-f52b-4e51-aef1-8ee159adb89b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296494158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2296494158
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.290817437
Short name T348
Test name
Test status
Simulation time 21191798342 ps
CPU time 26.54 seconds
Started Aug 04 04:48:22 PM PDT 24
Finished Aug 04 04:48:48 PM PDT 24
Peak memory 199948 kb
Host smart-06167712-9c5a-4c93-ae46-749d346680bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290817437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.290817437
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2574056197
Short name T316
Test name
Test status
Simulation time 462632254 ps
CPU time 5.53 seconds
Started Aug 04 04:48:23 PM PDT 24
Finished Aug 04 04:48:28 PM PDT 24
Peak memory 199824 kb
Host smart-e1fd675f-1c62-4217-a913-0b7a134af492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574056197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2574056197
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2653269172
Short name T215
Test name
Test status
Simulation time 9308781547 ps
CPU time 896.22 seconds
Started Aug 04 04:48:30 PM PDT 24
Finished Aug 04 05:03:27 PM PDT 24
Peak memory 667804 kb
Host smart-f3e4b30d-208e-445c-a0c1-e1942ec5477f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653269172 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2653269172
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.216129403
Short name T12
Test name
Test status
Simulation time 43807552713 ps
CPU time 1255.91 seconds
Started Aug 04 04:48:32 PM PDT 24
Finished Aug 04 05:09:28 PM PDT 24
Peak memory 623888 kb
Host smart-0bb17b8b-45ca-4bfb-b075-c98d4848f2a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216129403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.216129403
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1157737933
Short name T319
Test name
Test status
Simulation time 8596594643 ps
CPU time 37.78 seconds
Started Aug 04 04:48:27 PM PDT 24
Finished Aug 04 04:49:04 PM PDT 24
Peak memory 200028 kb
Host smart-cc623836-d188-46ce-a6bd-d4fd8d7c9d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157737933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1157737933
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1284558717
Short name T266
Test name
Test status
Simulation time 42485881 ps
CPU time 0.6 seconds
Started Aug 04 04:48:43 PM PDT 24
Finished Aug 04 04:48:43 PM PDT 24
Peak memory 196608 kb
Host smart-264b46a0-3ca5-41e4-ba7d-1d71426dd8e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284558717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1284558717
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.141187542
Short name T509
Test name
Test status
Simulation time 1567736146 ps
CPU time 84.8 seconds
Started Aug 04 04:48:31 PM PDT 24
Finished Aug 04 04:49:56 PM PDT 24
Peak memory 199840 kb
Host smart-3fcb2482-ba10-46ae-af27-c33abed2ed96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141187542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.141187542
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2178467017
Short name T480
Test name
Test status
Simulation time 1772762844 ps
CPU time 44.51 seconds
Started Aug 04 04:48:30 PM PDT 24
Finished Aug 04 04:49:15 PM PDT 24
Peak memory 199876 kb
Host smart-a6c5a14a-9865-4be3-ae95-cc25f9c53404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178467017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2178467017
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.4118936170
Short name T165
Test name
Test status
Simulation time 4169829585 ps
CPU time 779.57 seconds
Started Aug 04 04:48:32 PM PDT 24
Finished Aug 04 05:01:31 PM PDT 24
Peak memory 717400 kb
Host smart-11681c14-12a7-444b-be2a-217d492b2db7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118936170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.4118936170
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.483741966
Short name T164
Test name
Test status
Simulation time 7378528322 ps
CPU time 101.84 seconds
Started Aug 04 04:48:35 PM PDT 24
Finished Aug 04 04:50:17 PM PDT 24
Peak memory 199872 kb
Host smart-31203719-9f4e-44c4-beb7-bb326d247df5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483741966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.483741966
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3541523163
Short name T493
Test name
Test status
Simulation time 12151131640 ps
CPU time 153.78 seconds
Started Aug 04 04:48:32 PM PDT 24
Finished Aug 04 04:51:06 PM PDT 24
Peak memory 199960 kb
Host smart-b79efa9c-786c-4a5b-87f9-3efd37c2bf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541523163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3541523163
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2773523130
Short name T445
Test name
Test status
Simulation time 1962674141 ps
CPU time 13.15 seconds
Started Aug 04 04:48:30 PM PDT 24
Finished Aug 04 04:48:43 PM PDT 24
Peak memory 199832 kb
Host smart-d0dc7aeb-a1b7-4f9c-9691-7d83529baccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773523130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2773523130
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3434732035
Short name T84
Test name
Test status
Simulation time 66820666208 ps
CPU time 2569.22 seconds
Started Aug 04 04:48:37 PM PDT 24
Finished Aug 04 05:31:27 PM PDT 24
Peak memory 741608 kb
Host smart-8ae8a1d3-f708-450b-91ae-747b42e67d91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434732035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3434732035
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2242400871
Short name T163
Test name
Test status
Simulation time 3226333230 ps
CPU time 51.2 seconds
Started Aug 04 04:48:34 PM PDT 24
Finished Aug 04 04:49:26 PM PDT 24
Peak memory 199940 kb
Host smart-679bf216-bc65-47ce-a6e3-5a2e4b5d9662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242400871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2242400871
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.817657499
Short name T374
Test name
Test status
Simulation time 72609306 ps
CPU time 0.58 seconds
Started Aug 04 04:48:48 PM PDT 24
Finished Aug 04 04:48:49 PM PDT 24
Peak memory 195540 kb
Host smart-a65b6f02-1791-4416-878c-56782a1f08be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817657499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.817657499
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3202094561
Short name T501
Test name
Test status
Simulation time 2415976134 ps
CPU time 73.96 seconds
Started Aug 04 04:48:42 PM PDT 24
Finished Aug 04 04:49:56 PM PDT 24
Peak memory 199980 kb
Host smart-907c6fbb-fa7a-4c9e-8a0b-d036412e591e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202094561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3202094561
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.954802198
Short name T418
Test name
Test status
Simulation time 2974975817 ps
CPU time 26.06 seconds
Started Aug 04 04:48:43 PM PDT 24
Finished Aug 04 04:49:09 PM PDT 24
Peak memory 199964 kb
Host smart-a1ca8b70-1c2a-4d8a-88c7-0e0057ad543e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954802198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.954802198
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.719114829
Short name T328
Test name
Test status
Simulation time 8088372470 ps
CPU time 308.83 seconds
Started Aug 04 04:48:41 PM PDT 24
Finished Aug 04 04:53:50 PM PDT 24
Peak memory 651524 kb
Host smart-05b8de73-5214-4eea-9fda-16228a9cddec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719114829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.719114829
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2857631525
Short name T301
Test name
Test status
Simulation time 4698470432 ps
CPU time 85.5 seconds
Started Aug 04 04:48:45 PM PDT 24
Finished Aug 04 04:50:11 PM PDT 24
Peak memory 199964 kb
Host smart-34c6983d-c757-4a90-9c54-33b58deb8732
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857631525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2857631525
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3330186651
Short name T432
Test name
Test status
Simulation time 7299408607 ps
CPU time 70.55 seconds
Started Aug 04 04:48:41 PM PDT 24
Finished Aug 04 04:49:52 PM PDT 24
Peak memory 199896 kb
Host smart-efcff7ad-4cd0-4848-87ca-420394e0f96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330186651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3330186651
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1761370670
Short name T410
Test name
Test status
Simulation time 3572970669 ps
CPU time 16.4 seconds
Started Aug 04 04:48:41 PM PDT 24
Finished Aug 04 04:48:58 PM PDT 24
Peak memory 199992 kb
Host smart-860a23e3-ddc5-4924-8184-3b205e5b490a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761370670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1761370670
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1619724611
Short name T298
Test name
Test status
Simulation time 38679324357 ps
CPU time 1122.52 seconds
Started Aug 04 04:48:48 PM PDT 24
Finished Aug 04 05:07:31 PM PDT 24
Peak memory 680716 kb
Host smart-fe18caf8-088f-45dd-bb69-6664cb47ca81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619724611 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1619724611
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1698228754
Short name T18
Test name
Test status
Simulation time 404161339344 ps
CPU time 2270.49 seconds
Started Aug 04 04:48:48 PM PDT 24
Finished Aug 04 05:26:39 PM PDT 24
Peak memory 747216 kb
Host smart-88ccde13-0260-4e43-9c7a-ed0d70e21aae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698228754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1698228754
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2766583773
Short name T460
Test name
Test status
Simulation time 1693590047 ps
CPU time 7.72 seconds
Started Aug 04 04:48:51 PM PDT 24
Finished Aug 04 04:48:59 PM PDT 24
Peak memory 199844 kb
Host smart-2d24908b-8362-4195-b311-beae96038b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766583773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2766583773
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2378723937
Short name T466
Test name
Test status
Simulation time 22471253 ps
CPU time 0.59 seconds
Started Aug 04 04:48:58 PM PDT 24
Finished Aug 04 04:48:58 PM PDT 24
Peak memory 195804 kb
Host smart-af2b20af-95a7-403e-8f6c-c761b30d6239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378723937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2378723937
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3938355361
Short name T446
Test name
Test status
Simulation time 1083609334 ps
CPU time 62.73 seconds
Started Aug 04 04:48:53 PM PDT 24
Finished Aug 04 04:49:55 PM PDT 24
Peak memory 199776 kb
Host smart-cffdb69a-c407-4376-8419-1f7d8667454d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938355361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3938355361
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3783450425
Short name T40
Test name
Test status
Simulation time 16783796570 ps
CPU time 53.04 seconds
Started Aug 04 04:48:51 PM PDT 24
Finished Aug 04 04:49:44 PM PDT 24
Peak memory 216228 kb
Host smart-d203d2ef-04a3-40e6-be4f-17ece0ff471e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783450425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3783450425
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.985029666
Short name T324
Test name
Test status
Simulation time 101685522 ps
CPU time 0.93 seconds
Started Aug 04 04:48:51 PM PDT 24
Finished Aug 04 04:48:52 PM PDT 24
Peak memory 199676 kb
Host smart-b2778034-f519-4bcc-b8e7-2ee36ce1912e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985029666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.985029666
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3930109199
Short name T515
Test name
Test status
Simulation time 13623614022 ps
CPU time 92.56 seconds
Started Aug 04 04:48:54 PM PDT 24
Finished Aug 04 04:50:26 PM PDT 24
Peak memory 199876 kb
Host smart-5567a0a6-40ff-461d-990c-a9e004ab2563
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930109199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3930109199
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3198512049
Short name T365
Test name
Test status
Simulation time 8298018879 ps
CPU time 117.44 seconds
Started Aug 04 04:48:47 PM PDT 24
Finished Aug 04 04:50:44 PM PDT 24
Peak memory 199880 kb
Host smart-c01b51db-049b-4fdf-b0a2-b5ac0fcf727d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198512049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3198512049
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2738217772
Short name T468
Test name
Test status
Simulation time 732768948 ps
CPU time 12.38 seconds
Started Aug 04 04:48:48 PM PDT 24
Finished Aug 04 04:49:01 PM PDT 24
Peak memory 199780 kb
Host smart-b5b28278-a5d3-4bc1-bc1b-61dd5e24bf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738217772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2738217772
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1751877000
Short name T483
Test name
Test status
Simulation time 640492465645 ps
CPU time 4717.43 seconds
Started Aug 04 04:48:56 PM PDT 24
Finished Aug 04 06:07:34 PM PDT 24
Peak memory 793368 kb
Host smart-94289f45-9372-4acc-bd90-35f114b35c10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751877000 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1751877000
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.595045338
Short name T15
Test name
Test status
Simulation time 99134544717 ps
CPU time 5890.51 seconds
Started Aug 04 04:48:56 PM PDT 24
Finished Aug 04 06:27:07 PM PDT 24
Peak memory 885980 kb
Host smart-9d95fd70-586a-4631-b614-1ca85b92721f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=595045338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.595045338
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3484357463
Short name T329
Test name
Test status
Simulation time 8249809242 ps
CPU time 64.08 seconds
Started Aug 04 04:48:54 PM PDT 24
Finished Aug 04 04:49:58 PM PDT 24
Peak memory 199924 kb
Host smart-fc9211bb-6f74-487a-a7bd-ae0a3975b63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484357463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3484357463
Directory /workspace/9.hmac_wipe_secret/latest
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