Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
19603038 |
1 |
|
|
T1 |
10076 |
|
T2 |
6379 |
|
T3 |
4394 |
all_values[1] |
19603038 |
1 |
|
|
T1 |
10076 |
|
T2 |
6379 |
|
T3 |
4394 |
all_values[2] |
19603038 |
1 |
|
|
T1 |
10076 |
|
T2 |
6379 |
|
T3 |
4394 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
263671 |
1 |
|
|
T4 |
24 |
|
T5 |
229 |
|
T7 |
22 |
auto[1] |
58545443 |
1 |
|
|
T1 |
30228 |
|
T2 |
19137 |
|
T3 |
13182 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50178117 |
1 |
|
|
T1 |
25897 |
|
T2 |
19002 |
|
T3 |
10486 |
auto[1] |
8630997 |
1 |
|
|
T1 |
4331 |
|
T2 |
135 |
|
T3 |
2696 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
78853 |
1 |
|
|
T8 |
3393 |
|
T28 |
1813 |
|
T29 |
813 |
all_values[0] |
auto[0] |
auto[1] |
436 |
1 |
|
|
T8 |
11 |
|
T28 |
2 |
|
T29 |
12 |
all_values[0] |
auto[1] |
auto[0] |
19502527 |
1 |
|
|
T1 |
10051 |
|
T2 |
6244 |
|
T3 |
4392 |
all_values[0] |
auto[1] |
auto[1] |
21222 |
1 |
|
|
T1 |
25 |
|
T2 |
135 |
|
T3 |
2 |
all_values[1] |
auto[0] |
auto[0] |
75857 |
1 |
|
|
T4 |
24 |
|
T5 |
229 |
|
T7 |
11 |
all_values[1] |
auto[0] |
auto[1] |
228 |
1 |
|
|
T8 |
5 |
|
T29 |
8 |
|
T21 |
4 |
all_values[1] |
auto[1] |
auto[0] |
19526558 |
1 |
|
|
T1 |
10076 |
|
T2 |
6379 |
|
T3 |
4394 |
all_values[1] |
auto[1] |
auto[1] |
395 |
1 |
|
|
T8 |
2 |
|
T56 |
2 |
|
T29 |
5 |
all_values[2] |
auto[0] |
auto[0] |
54245 |
1 |
|
|
T7 |
4 |
|
T8 |
7 |
|
T29 |
1126 |
all_values[2] |
auto[0] |
auto[1] |
54052 |
1 |
|
|
T7 |
7 |
|
T8 |
8 |
|
T56 |
2 |
all_values[2] |
auto[1] |
auto[0] |
10940077 |
1 |
|
|
T1 |
5770 |
|
T2 |
6379 |
|
T3 |
1700 |
all_values[2] |
auto[1] |
auto[1] |
8554664 |
1 |
|
|
T1 |
4306 |
|
T3 |
2694 |
|
T4 |
802 |