Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139807

1

T1

40

T3

4

T4

736

auto[1]

139668

1

T1

26

T2

146

T3

2

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	105093	1			T1	33		T3	3		T4	707
len_1026_2046	5654	1			T4	64		T7	2		T8	27
len_514_1022	5122	1			T4	16		T8	16		T68	2
len_2_510	3361	1			T4	12		T7	3		T8	14
len_2056	190	1			T7	5		T21	2		T130	1
len_2048	313	1			T4	2		T7	2		T8	1
len_2040	199	1			T24	10		T21	1		T130	2
len_1032	185	1			T7	2		T51	2		T21	1
len_1024	1827	1			T2	73		T4	3		T6	81
len_1016	202	1			T24	1		T89	1		T21	10
len_520	351	1			T24	2		T89	1		T131	2
len_512	388	1			T4	3		T7	1		T8	2
len_504	206	1			T24	2		T88	2		T21	1
len_8	1128	1			T8	2		T88	2		T89	1
len_0	15518	1			T4	1		T7	8		T8	79

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

135

1

T5

2

T19

2

T52

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	54284	1			T1	20		T3	2		T4	341
auto[0]	len_1026_2046	3194	1			T4	15		T7	1		T8	6
auto[0]	len_514_1022	2606	1			T4	5		T8	5		T68	2
auto[0]	len_2_510	2456	1			T4	2		T7	1		T8	4
auto[0]	len_2056	110	1			T7	3		T21	2		T130	1
auto[0]	len_2048	184	1			T4	1		T7	2		T24	2
auto[0]	len_2040	85	1			T24	3		T21	1		T130	1
auto[0]	len_1032	87	1			T7	2		T21	1		T53	1
auto[0]	len_1024	297	1			T4	1		T5	1		T8	1
auto[0]	len_1016	121	1			T24	1		T89	1		T21	8
auto[0]	len_520	155	1			T24	2		T89	1		T132	2
auto[0]	len_512	243	1			T4	2		T7	1		T8	1
auto[0]	len_504	104	1			T88	2		T21	1		T133	2
auto[0]	len_8	29	1			T88	2		T89	1		T133	1
auto[0]	len_0	5948	1			T4	1		T7	3		T8	4
auto[1]	len_2050_plus	50809	1			T1	13		T3	1		T4	366
auto[1]	len_1026_2046	2460	1			T4	49		T7	1		T8	21
auto[1]	len_514_1022	2516	1			T4	11		T8	11		T29	6
auto[1]	len_2_510	905	1			T4	10		T7	2		T8	10
auto[1]	len_2056	80	1			T7	2		T26	2		T134	2
auto[1]	len_2048	129	1			T4	1		T8	1		T24	1
auto[1]	len_2040	114	1			T24	7		T130	1		T9	1
auto[1]	len_1032	98	1			T51	2		T53	3		T9	4
auto[1]	len_1024	1530	1			T2	73		T4	2		T6	81
auto[1]	len_1016	81	1			T21	2		T53	1		T132	2
auto[1]	len_520	196	1			T131	2		T9	3		T50	3
auto[1]	len_512	145	1			T4	1		T8	1		T21	1
auto[1]	len_504	102	1			T24	2		T53	2		T26	2
auto[1]	len_8	1099	1			T8	2		T91	8		T135	6
auto[1]	len_0	9570	1			T7	5		T8	75		T24	3

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

83

1

T19

2

T52

1

T130

2

auto[1]

len_upper

52

1

T5

2

T136

2

T137

2