Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4998655 1 T1 14 T2 3183 T3 859
auto[1] 3193867 1 T1 20 T3 1 T4 2150


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3212003 1 T1 13 T3 860 T4 2306
auto[1] 4980519 1 T1 21 T2 3183 T4 1030


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3570013 1 T1 19 T3 859 T4 1508
auto[1] 4622509 1 T1 15 T2 3183 T3 1


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4877412 1 T1 16 T2 3183 T3 22
auto[1] 3315110 1 T1 18 T3 838 T4 1728


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7341919 1 T1 20 T2 1928 T3 750
fifo_depth[1] 128645 1 T1 1 T2 221 T3 52
fifo_depth[2] 99788 1 T1 2 T2 204 T3 43
fifo_depth[3] 81795 1 T2 196 T3 13 T4 28
fifo_depth[4] 76021 1 T1 1 T2 194 T3 2
fifo_depth[5] 61571 1 T1 2 T2 162 T4 15
fifo_depth[6] 49842 1 T1 5 T2 116 T4 17
fifo_depth[7] 33601 1 T2 85 T4 12 T6 100


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 850603 1 T1 14 T2 1255 T3 110
auto[1] 7341919 1 T1 20 T2 1928 T3 750


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8177228 1 T1 34 T2 3183 T3 860
auto[1] 15294 1 T25 38 T26 1275 T118 200


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 46600 1 T4 39 T5 2 T8 98
auto[0] auto[0] auto[0] auto[0] auto[1] 48258 1 T3 110 T4 15 T5 2
auto[0] auto[0] auto[0] auto[1] auto[0] 38623 1 T1 1 T4 6 T5 1
auto[0] auto[0] auto[0] auto[1] auto[1] 40646 1 T4 24 T7 11 T8 14
auto[0] auto[0] auto[1] auto[0] auto[0] 128737 1 T1 2 T4 3 T5 1
auto[0] auto[0] auto[1] auto[0] auto[1] 35420 1 T1 1 T4 35 T5 1
auto[0] auto[0] auto[1] auto[1] auto[0] 47601 1 T1 2 T7 13 T8 25
auto[0] auto[0] auto[1] auto[1] auto[1] 42718 1 T1 4 T8 16 T68 163
auto[0] auto[1] auto[0] auto[0] auto[0] 56977 1 T5 2 T7 19 T8 85
auto[0] auto[1] auto[0] auto[0] auto[1] 41910 1 T4 1 T5 1 T7 7
auto[0] auto[1] auto[0] auto[1] auto[0] 46584 1 T4 15 T5 1 T8 179
auto[0] auto[1] auto[0] auto[1] auto[1] 54491 1 T1 1 T4 30 T8 208
auto[0] auto[1] auto[1] auto[0] auto[0] 59418 1 T2 1255 T4 1 T6 1052
auto[0] auto[1] auto[1] auto[0] auto[1] 54378 1 T7 36 T8 76 T24 12
auto[0] auto[1] auto[1] auto[1] auto[0] 52310 1 T1 1 T4 36 T7 4
auto[0] auto[1] auto[1] auto[1] auto[1] 55932 1 T1 2 T4 12 T8 48
auto[1] auto[0] auto[0] auto[0] auto[0] 194441 1 T1 2 T3 21 T4 516
auto[1] auto[0] auto[0] auto[0] auto[1] 200591 1 T1 1 T3 728 T4 64
auto[1] auto[0] auto[0] auto[1] auto[0] 191272 1 T4 230 T7 11 T8 545
auto[1] auto[0] auto[0] auto[1] auto[1] 208618 1 T1 1 T4 307 T5 1
auto[1] auto[0] auto[1] auto[0] auto[0] 1768343 1 T1 2 T4 121 T5 1
auto[1] auto[0] auto[1] auto[0] auto[1] 196805 1 T1 1 T4 86 T5 4
auto[1] auto[0] auto[1] auto[1] auto[0] 194486 1 T1 1 T5 1 T7 54
auto[1] auto[0] auto[1] auto[1] auto[1] 186854 1 T1 1 T4 62 T5 1
auto[1] auto[1] auto[0] auto[0] auto[0] 528494 1 T4 16 T5 3 T7 19
auto[1] auto[1] auto[0] auto[0] auto[1] 507236 1 T1 2 T4 13 T5 1
auto[1] auto[1] auto[0] auto[1] auto[0] 472292 1 T1 4 T3 1 T4 209
auto[1] auto[1] auto[0] auto[1] auto[1] 534970 1 T1 1 T4 821 T5 3
auto[1] auto[1] auto[1] auto[0] auto[0] 571439 1 T1 1 T2 1928 T4 276
auto[1] auto[1] auto[1] auto[0] auto[1] 559608 1 T1 2 T5 2 T7 66
auto[1] auto[1] auto[1] auto[1] auto[0] 479795 1 T4 140 T5 2 T7 15
auto[1] auto[1] auto[1] auto[1] auto[1] 546675 1 T1 1 T4 258 T8 2850


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 239125 1 T1 2 T3 21 T4 555
auto[0] auto[0] auto[0] auto[0] auto[1] 247614 1 T1 1 T3 838 T4 79
auto[0] auto[0] auto[0] auto[1] auto[0] 228373 1 T1 1 T4 236 T5 1
auto[0] auto[0] auto[0] auto[1] auto[1] 248483 1 T1 1 T4 331 T5 1
auto[0] auto[0] auto[1] auto[0] auto[0] 1896481 1 T1 4 T4 124 T5 2
auto[0] auto[0] auto[1] auto[0] auto[1] 231491 1 T1 2 T4 121 T5 5
auto[0] auto[0] auto[1] auto[1] auto[0] 241512 1 T1 3 T5 1 T7 67
auto[0] auto[0] auto[1] auto[1] auto[1] 227511 1 T1 5 T4 62 T5 1
auto[0] auto[1] auto[0] auto[0] auto[0] 584202 1 T4 16 T5 5 T7 38
auto[0] auto[1] auto[0] auto[0] auto[1] 548976 1 T1 2 T4 14 T5 2
auto[0] auto[1] auto[0] auto[1] auto[0] 518811 1 T1 4 T3 1 T4 224
auto[0] auto[1] auto[0] auto[1] auto[1] 587925 1 T1 2 T4 851 T5 3
auto[0] auto[1] auto[1] auto[0] auto[0] 630513 1 T1 1 T2 3183 T4 277
auto[0] auto[1] auto[1] auto[0] auto[1] 612948 1 T1 2 T5 2 T7 102
auto[0] auto[1] auto[1] auto[1] auto[0] 531508 1 T1 1 T4 176 T5 2
auto[0] auto[1] auto[1] auto[1] auto[1] 601755 1 T1 3 T4 270 T8 2898
auto[1] auto[0] auto[0] auto[0] auto[0] 1916 1 T26 317 T48 24 T138 408
auto[1] auto[0] auto[0] auto[0] auto[1] 1235 1 T26 131 T118 5 T50 48
auto[1] auto[0] auto[0] auto[1] auto[0] 1522 1 T26 134 T50 58 T48 6
auto[1] auto[0] auto[0] auto[1] auto[1] 781 1 T26 36 T50 24 T138 353
auto[1] auto[0] auto[1] auto[0] auto[0] 599 1 T49 46 T139 4 T22 21
auto[1] auto[0] auto[1] auto[0] auto[1] 734 1 T26 28 T50 4 T48 1
auto[1] auto[0] auto[1] auto[1] auto[0] 575 1 T26 3 T50 63 T140 203
auto[1] auto[0] auto[1] auto[1] auto[1] 2061 1 T26 489 T118 14 T50 19
auto[1] auto[1] auto[0] auto[0] auto[0] 1269 1 T26 86 T138 3 T140 66
auto[1] auto[1] auto[0] auto[0] auto[1] 170 1 T50 4 T48 16 T140 36
auto[1] auto[1] auto[0] auto[1] auto[0] 65 1 T26 5 T141 4 T138 1
auto[1] auto[1] auto[0] auto[1] auto[1] 1536 1 T25 2 T26 32 T50 11
auto[1] auto[1] auto[1] auto[0] auto[0] 344 1 T26 6 T118 180 T50 23
auto[1] auto[1] auto[1] auto[0] auto[1] 1038 1 T25 36 T50 15 T49 78
auto[1] auto[1] auto[1] auto[1] auto[0] 597 1 T50 3 T48 46 T138 217
auto[1] auto[1] auto[1] auto[1] auto[1] 852 1 T26 8 T118 1 T50 11


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 194441 1 T1 2 T3 21 T4 516
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 200591 1 T1 1 T3 728 T4 64
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 191272 1 T4 230 T7 11 T8 545
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 208618 1 T1 1 T4 307 T5 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1768343 1 T1 2 T4 121 T5 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 196805 1 T1 1 T4 86 T5 4
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 194486 1 T1 1 T5 1 T7 54
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 186854 1 T1 1 T4 62 T5 1
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 528494 1 T4 16 T5 3 T7 19
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 507236 1 T1 2 T4 13 T5 1
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 472292 1 T1 4 T3 1 T4 209
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 534970 1 T1 1 T4 821 T5 3
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 571439 1 T1 1 T2 1928 T4 276
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 559608 1 T1 2 T5 2 T7 66
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 479795 1 T4 140 T5 2 T7 15
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 546675 1 T1 1 T4 258 T8 2850
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 4190 1 T4 3 T8 57 T24 4
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 4507 1 T3 52 T8 14 T12 10
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 4116 1 T4 1 T8 12 T29 38
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 4894 1 T4 3 T7 1 T8 9
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 38966 1 T1 1 T7 2 T8 14
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 4574 1 T4 4 T7 4 T8 17
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 4242 1 T8 20 T28 4 T68 10
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 4124 1 T8 13 T68 23 T29 38
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6848 1 T7 2 T8 52 T28 3
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6465 1 T7 1 T8 4 T29 20
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6922 1 T4 1 T8 91 T68 11
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6988 1 T4 23 T8 116 T28 27
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8829 1 T2 221 T6 145 T17 178
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 7997 1 T7 6 T8 50 T24 2
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 6851 1 T4 4 T8 32 T51 1
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 8132 1 T8 45 T51 2 T29 1
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3532 1 T4 8 T8 25 T24 3
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3620 1 T3 43 T8 12 T12 4
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3572 1 T8 4 T29 2 T21 8
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 4053 1 T4 5 T7 3 T8 4
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 23908 1 T7 7 T8 2 T28 27
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3653 1 T4 6 T7 1 T8 7
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3739 1 T7 2 T8 4 T28 4
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3114 1 T1 1 T8 3 T68 24
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 6041 1 T7 5 T8 25 T28 3
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5569 1 T8 7 T29 4 T21 21
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 6108 1 T8 51 T24 2 T68 14
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 6026 1 T4 6 T8 56 T28 10
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 7068 1 T2 204 T6 130 T17 174
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 7097 1 T7 6 T8 17 T24 2
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 5930 1 T4 4 T8 21 T51 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 6758 1 T1 1 T8 3 T29 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2651 1 T4 3 T8 6 T24 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2829 1 T3 13 T4 1 T8 6
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2855 1 T24 1 T29 2 T21 6
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 3267 1 T4 6 T7 3 T8 1
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 17022 1 T7 1 T8 1 T28 4
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 3065 1 T4 6 T7 1 T8 4
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 3053 1 T7 4 T8 1 T28 3
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2627 1 T68 35 T29 1 T21 39
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 5228 1 T7 2 T8 6 T24 2
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4937 1 T5 1 T8 1 T29 2
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 5534 1 T4 5 T8 14 T68 17
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 5341 1 T4 1 T8 30 T28 6
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 6016 1 T2 196 T6 129 T17 181
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 6249 1 T7 6 T8 7 T21 30
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 5216 1 T4 6 T7 1 T8 5
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 5905 1 T21 39 T91 91 T52 2
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2751 1 T4 19 T8 6 T24 2
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2894 1 T3 2 T4 2 T8 4
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 3056 1 T4 3 T21 3 T90 7
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 3279 1 T4 3 T7 2 T68 44
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 12549 1 T1 1 T7 2 T8 2
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 3165 1 T4 5 T7 2 T24 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 3166 1 T7 1 T68 12 T29 10
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2703 1 T68 32 T29 6 T21 43
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 5021 1 T7 2 T8 2 T68 12
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4841 1 T7 1 T8 11 T21 22
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 5377 1 T4 5 T8 12 T68 19
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 5020 1 T8 3 T28 1 T53 1
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5621 1 T2 194 T6 123 T17 165
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 6121 1 T7 5 T8 1 T24 2
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 5029 1 T4 6 T7 3 T8 1
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 5428 1 T4 7 T29 13 T21 33
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 2131 1 T4 1 T24 2 T68 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 2243 1 T4 1 T8 2 T28 1
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 2206 1 T24 1 T21 6 T90 13
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 2390 1 T4 1 T7 1 T68 31
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 9152 1 T7 1 T8 1 T68 22
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 2516 1 T4 5 T7 1 T21 14
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 2415 1 T7 1 T68 5 T29 9
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 2009 1 T1 1 T68 25 T21 35
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 4297 1 T7 2 T24 1 T68 14
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 4251 1 T7 1 T21 17 T53 1
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 4599 1 T4 3 T24 1 T68 11
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 4346 1 T8 2 T21 1 T91 13
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4881 1 T2 162 T6 136 T17 167
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 5038 1 T7 3 T8 1 T24 1
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 4351 1 T1 1 T4 4 T24 1
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 4746 1 T21 25 T91 64 T135 25
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1908 1 T4 2 T5 1 T8 4
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1922 1 T4 3 T8 4 T68 33
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1734 1 T1 1 T21 2 T90 13
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 2248 1 T4 3 T7 1 T68 26
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 6525 1 T8 5 T68 15 T89 1413
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 2142 1 T1 1 T4 5 T7 2
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 2152 1 T1 1 T7 2 T68 6
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1496 1 T1 2 T68 16 T21 30
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3557 1 T7 3 T24 1 T68 14
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3587 1 T7 1 T21 13 T91 28
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3627 1 T4 1 T8 1 T68 12
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3633 1 T8 1 T91 12 T135 111
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 4057 1 T2 116 T6 144 T17 159
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3900 1 T7 5 T24 1 T21 12
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3456 1 T4 3 T68 6 T21 12
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 3898 1 T21 18 T91 80 T135 23
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1218 1 T4 1 T26 9 T78 2
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1537 1 T4 3 T8 2 T68 21
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1089 1 T24 2 T21 3 T90 7
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1397 1 T4 1 T68 24 T21 20
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4095 1 T5 1 T7 1 T8 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1333 1 T4 3 T21 7 T26 19
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1356 1 T7 2 T68 1 T29 3
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1035 1 T68 6 T21 13 T26 20
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2502 1 T24 2 T68 10 T21 11
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2448 1 T21 9 T91 16 T79 2
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2494 1 T24 1 T68 7 T91 5
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2551 1 T91 1 T135 70 T25 3
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2836 1 T2 85 T6 100 T17 142
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2681 1 T7 3 T24 1 T21 6
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2362 1 T4 3 T68 3 T21 3
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2667 1 T4 1 T21 4 T91 53

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