Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19603038	1			T1	10076		T2	6379		T3	4394
all_pins[1]	19603038	1			T1	10076		T2	6379		T3	4394
all_pins[2]	19603038	1			T1	10076		T2	6379		T3	4394

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	50231923	1			T1	25895		T2	19002		T3	10486
values[0x1]	8577191	1			T1	4333		T2	135		T3	2696
transitions[0x0=>0x1]	8576995	1			T1	4333		T2	135		T3	2696
transitions[0x1=>0x0]	8577011	1			T1	4333		T2	135		T3	2696

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19580937	1			T1	10049		T2	6244		T3	4392
all_pins[0]	values[0x1]	22101	1			T1	27		T2	135		T3	2
all_pins[0]	transitions[0x0=>0x1]	22012	1			T1	27		T2	135		T3	2
all_pins[0]	transitions[0x1=>0x0]	8554591	1			T1	4306		T3	2694		T4	802
all_pins[1]	values[0x0]	19602612	1			T1	10076		T2	6379		T3	4394
all_pins[1]	values[0x1]	426	1			T8	2		T56	2		T29	5
all_pins[1]	transitions[0x0=>0x1]	375	1			T8	2		T56	1		T29	3
all_pins[1]	transitions[0x1=>0x0]	22050	1			T1	27		T2	135		T3	2
all_pins[2]	values[0x0]	11048374	1			T1	5770		T2	6379		T3	1700
all_pins[2]	values[0x1]	8554664	1			T1	4306		T3	2694		T4	802
all_pins[2]	transitions[0x0=>0x1]	8554608	1			T1	4306		T3	2694		T4	802
all_pins[2]	transitions[0x1=>0x0]	370	1			T8	2		T56	1		T29	5