Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1106 1 T8 21 T56 4 T29 29
all_values[1] 1106 1 T8 21 T56 4 T29 29
all_values[2] 1106 1 T8 21 T56 4 T29 29


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1620 1 T8 31 T56 1 T29 48
auto[1] 1698 1 T8 32 T56 11 T29 39


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1131 1 T8 23 T56 2 T29 26
auto[1] 2187 1 T8 40 T56 10 T29 61


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1862 1 T8 38 T56 6 T29 48
auto[1] 1456 1 T8 25 T56 6 T29 39


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 194 1 T8 3 T29 7 T21 8
all_values[0] auto[0] auto[0] auto[1] 127 1 T8 2 T29 6 T21 4
all_values[0] auto[0] auto[1] auto[0] 211 1 T8 5 T56 1 T29 4
all_values[0] auto[0] auto[1] auto[1] 99 1 T8 2 T56 1 T29 3
all_values[0] auto[1] auto[0] auto[1] 253 1 T8 5 T29 6 T21 5
all_values[0] auto[1] auto[1] auto[1] 222 1 T8 4 T56 2 T29 3
all_values[1] auto[0] auto[0] auto[0] 173 1 T8 4 T29 5 T21 3
all_values[1] auto[0] auto[0] auto[1] 118 1 T8 1 T29 3 T21 3
all_values[1] auto[0] auto[1] auto[0] 192 1 T8 7 T56 1 T29 5
all_values[1] auto[0] auto[1] auto[1] 159 1 T8 2 T56 1 T29 3
all_values[1] auto[1] auto[0] auto[1] 229 1 T8 4 T29 5 T21 6
all_values[1] auto[1] auto[1] auto[1] 235 1 T8 3 T56 2 T29 8
all_values[2] auto[0] auto[0] auto[0] 179 1 T8 2 T29 2 T21 5
all_values[2] auto[0] auto[0] auto[1] 98 1 T8 6 T29 3 T21 2
all_values[2] auto[0] auto[1] auto[0] 182 1 T8 2 T29 3 T21 3
all_values[2] auto[0] auto[1] auto[1] 130 1 T8 2 T56 2 T29 4
all_values[2] auto[1] auto[0] auto[1] 249 1 T8 4 T56 1 T29 11
all_values[2] auto[1] auto[1] auto[1] 268 1 T8 5 T56 1 T29 6


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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