Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4839	1			T1	6		T3	1		T4	8
sha2_none	4777	1			T1	5		T4	7		T5	4
sha2_512	8171	1			T1	1		T4	6		T17	225
sha2_384	7890	1			T1	12		T4	11		T6	180
sha2_256	6883	1			T1	10		T2	135		T3	3

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20137

1

T1

14

T2

135

T3

4

auto[1]

12869

1

T1

21

T4

19

T5

12

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12686

1

T1

13

T3

4

T4

21

auto[1]

20320

1

T1

22

T2

135

T4

19

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17162

1

T1

15

T2

135

T4

19

disabled

15844

1

T1

20

T3

4

T4

21

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5114	1			T1	7		T4	6		T5	7
key_none	8224	1			T1	8		T3	2		T4	3
key_1024	4722	1			T1	4		T4	7		T6	60
key_512	4247	1			T1	6		T2	45		T4	11
key_384	3781	1			T1	2		T2	90		T4	6
key_256	3500	1			T1	6		T4	3		T5	3
key_128	3324	1			T1	2		T3	2		T4	3

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20355

1

T1

16

T2

135

T3

3

auto[1]

12651

1

T1

19

T3

1

T4

16

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

32817

1

T1

35

T2

135

T3

3

disabled

189

1

T3

1

T8

5

T29

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1805

1

T4

1

T5

5

T7

2

enabled

auto[0]

auto[0]

auto[1]

1713

1

T1

2

T4

1

T5

2

enabled

auto[0]

auto[1]

auto[0]

1817

1

T1

4

T4

4

T5

3

enabled

auto[0]

auto[1]

auto[1]

1820

1

T1

2

T4

2

T5

3

enabled

auto[1]

auto[0]

auto[0]

4483

1

T1

1

T2

135

T4

4

enabled

auto[1]

auto[0]

auto[1]

1821

1

T1

2

T5

2

T7

2

enabled

auto[1]

auto[1]

auto[0]

1893

1

T1

1

T4

3

T5

2

enabled

auto[1]

auto[1]

auto[1]

1810

1

T1

3

T4

4

T8

17

disabled

auto[0]

auto[0]

auto[0]

1393

1

T1

2

T3

3

T4

6

disabled

auto[0]

auto[0]

auto[1]

1373

1

T1

1

T3

1

T4

2

disabled

auto[0]

auto[1]

auto[0]

1400

1

T1

1

T4

2

T5

1

disabled

auto[0]

auto[1]

auto[1]

1365

1

T1

1

T4

3

T5

1

disabled

auto[1]

auto[0]

auto[0]

6187

1

T1

4

T4

4

T5

2

disabled

auto[1]

auto[0]

auto[1]

1362

1

T1

2

T4

3

T5

6

disabled

auto[1]

auto[1]

auto[0]

1377

1

T1

3

T5

1

T7

3

disabled

auto[1]

auto[1]

auto[1]

1387

1

T1

6

T4

1

T5

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17083

1

T1

15

T2

135

T4

19

enabled

disabled

79

1

T29

2

T21

1

T129

1

disabled

disabled

110

1

T3

1

T8

5

T29

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15734

1

T1

20

T3

3

T4

21

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1258	1			T1	1		T4	2		T5	2
key_invalid	sha2_none	954	1			T5	1		T8	8		T56	2
key_invalid	sha2_512	958	1			T4	1		T5	2		T7	1
key_invalid	sha2_384	914	1			T1	5		T4	2		T5	1
key_invalid	sha2_256	901	1			T4	1		T5	1		T7	2
key_none	sha2_invalid	583	1			T3	1		T4	1		T5	2
key_none	sha2_none	636	1			T1	1		T5	1		T7	1
key_none	sha2_512	2618	1			T5	3		T8	10		T24	1
key_none	sha2_384	2622	1			T1	4		T4	2		T5	2
key_none	sha2_256	1712	1			T1	3		T3	1		T5	3
key_1024	sha2_invalid	622	1			T1	2		T4	1		T8	7
key_1024	sha2_none	629	1			T1	1		T4	1		T8	10
key_1024	sha2_512	1813	1			T4	2		T17	225		T5	1
key_1024	sha2_384	985	1			T4	1		T6	60		T5	1
key_512	sha2_invalid	573	1			T1	1		T4	1		T5	1
key_512	sha2_none	678	1			T1	1		T4	4		T7	1
key_512	sha2_512	696	1			T1	1		T4	1		T5	1
key_512	sha2_384	1311	1			T4	3		T6	120		T8	7
key_512	sha2_256	925	1			T1	3		T2	45		T4	2
key_384	sha2_invalid	575	1			T1	1		T4	1		T5	1
key_384	sha2_none	610	1			T4	1		T8	6		T56	1
key_384	sha2_512	711	1			T4	1		T5	1		T7	1
key_384	sha2_384	691	1			T4	1		T5	1		T8	6
key_384	sha2_256	1149	1			T1	1		T2	90		T4	2
key_256	sha2_invalid	625	1			T1	1		T4	2		T7	2
key_256	sha2_none	626	1			T1	1		T5	1		T8	7
key_256	sha2_512	651	1			T5	1		T7	1		T8	2
key_256	sha2_384	688	1			T1	3		T4	1		T8	8
key_256	sha2_256	858	1			T1	1		T5	1		T7	2
key_128	sha2_invalid	577	1			T5	1		T8	4		T56	1
key_128	sha2_none	626	1			T1	1		T5	1		T8	3
key_128	sha2_512	705	1			T4	1		T5	2		T8	6
key_128	sha2_384	663	1			T4	1		T5	4		T7	1
key_128	sha2_256	698	1			T1	1		T3	2		T4	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

625

1

T1

1

T4

2

T5

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1258	1			T1	1		T4	2		T5	2
key_invalid	sha2_none	954	1			T5	1		T8	8		T56	2
key_invalid	sha2_512	958	1			T4	1		T5	2		T7	1
key_invalid	sha2_384	914	1			T1	5		T4	2		T5	1
key_invalid	sha2_256	901	1			T4	1		T5	1		T7	2
key_none	sha2_invalid	583	1			T3	1		T4	1		T5	2
key_none	sha2_none	636	1			T1	1		T5	1		T7	1
key_none	sha2_512	2618	1			T5	3		T8	10		T24	1
key_none	sha2_384	2622	1			T1	4		T4	2		T5	2
key_none	sha2_256	1712	1			T1	3		T3	1		T5	3
key_1024	sha2_invalid	622	1			T1	2		T4	1		T8	7
key_1024	sha2_none	629	1			T1	1		T4	1		T8	10
key_1024	sha2_512	1813	1			T4	2		T17	225		T5	1
key_1024	sha2_384	985	1			T4	1		T6	60		T5	1
key_1024	sha2_256	625	1			T1	1		T4	2		T5	1
key_512	sha2_invalid	573	1			T1	1		T4	1		T5	1
key_512	sha2_none	678	1			T1	1		T4	4		T7	1
key_512	sha2_512	696	1			T1	1		T4	1		T5	1
key_512	sha2_384	1311	1			T4	3		T6	120		T8	7
key_512	sha2_256	925	1			T1	3		T2	45		T4	2
key_384	sha2_invalid	575	1			T1	1		T4	1		T5	1
key_384	sha2_none	610	1			T4	1		T8	6		T56	1
key_384	sha2_512	711	1			T4	1		T5	1		T7	1
key_384	sha2_384	691	1			T4	1		T5	1		T8	6
key_384	sha2_256	1149	1			T1	1		T2	90		T4	2
key_256	sha2_invalid	625	1			T1	1		T4	2		T7	2
key_256	sha2_none	626	1			T1	1		T5	1		T8	7
key_256	sha2_512	651	1			T5	1		T7	1		T8	2
key_256	sha2_384	688	1			T1	3		T4	1		T8	8
key_256	sha2_256	858	1			T1	1		T5	1		T7	2
key_128	sha2_invalid	577	1			T5	1		T8	4		T56	1
key_128	sha2_none	626	1			T1	1		T5	1		T8	3
key_128	sha2_512	705	1			T4	1		T5	2		T8	6
key_128	sha2_384	663	1			T4	1		T5	4		T7	1
key_128	sha2_256	698	1			T1	1		T3	2		T4	1