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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.46 95.40 97.22 100.00 100.00 98.27 98.48 99.85


Total test records in report: 660
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T533 /workspace/coverage/cover_reg_top/13.hmac_intr_test.519360995 Aug 05 04:59:19 PM PDT 24 Aug 05 04:59:20 PM PDT 24 11821521 ps
T109 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3504167355 Aug 05 04:58:57 PM PDT 24 Aug 05 04:58:59 PM PDT 24 167176009 ps
T110 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1980626672 Aug 05 04:58:39 PM PDT 24 Aug 05 04:58:41 PM PDT 24 434485619 ps
T534 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1322998393 Aug 05 04:59:11 PM PDT 24 Aug 05 04:59:12 PM PDT 24 14307492 ps
T97 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2876155209 Aug 05 04:58:49 PM PDT 24 Aug 05 04:59:01 PM PDT 24 4389427678 ps
T535 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1653023173 Aug 05 04:59:05 PM PDT 24 Aug 05 04:59:09 PM PDT 24 30237408 ps
T536 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3067332719 Aug 05 04:58:54 PM PDT 24 Aug 05 04:59:47 PM PDT 24 22692738292 ps
T66 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.124311303 Aug 05 04:58:33 PM PDT 24 Aug 05 04:58:35 PM PDT 24 1288483422 ps
T67 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1316228143 Aug 05 04:58:53 PM PDT 24 Aug 05 04:58:57 PM PDT 24 247382401 ps
T111 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.165832651 Aug 05 04:59:13 PM PDT 24 Aug 05 04:59:15 PM PDT 24 292546363 ps
T112 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2340769646 Aug 05 04:58:41 PM PDT 24 Aug 05 04:58:43 PM PDT 24 40668355 ps
T537 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2237805714 Aug 05 04:59:22 PM PDT 24 Aug 05 04:59:23 PM PDT 24 26685594 ps
T538 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2193007731 Aug 05 04:59:04 PM PDT 24 Aug 05 04:59:05 PM PDT 24 19979171 ps
T539 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1474844580 Aug 05 04:58:44 PM PDT 24 Aug 05 04:58:45 PM PDT 24 23260137 ps
T540 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1725788603 Aug 05 04:58:43 PM PDT 24 Aug 05 04:58:45 PM PDT 24 297380528 ps
T98 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2221577162 Aug 05 04:58:48 PM PDT 24 Aug 05 04:58:49 PM PDT 24 202627377 ps
T119 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2933861293 Aug 05 04:58:56 PM PDT 24 Aug 05 04:58:58 PM PDT 24 197573230 ps
T541 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1477956595 Aug 05 04:59:04 PM PDT 24 Aug 05 04:59:06 PM PDT 24 151205089 ps
T542 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3181753188 Aug 05 04:59:20 PM PDT 24 Aug 05 04:59:29 PM PDT 24 287500507 ps
T543 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1879278363 Aug 05 04:59:29 PM PDT 24 Aug 05 04:59:35 PM PDT 24 40260594 ps
T544 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2735726243 Aug 05 04:58:59 PM PDT 24 Aug 05 04:58:59 PM PDT 24 15092565 ps
T123 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3235753360 Aug 05 04:58:44 PM PDT 24 Aug 05 04:58:48 PM PDT 24 130759755 ps
T545 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1612462582 Aug 05 04:59:27 PM PDT 24 Aug 05 04:59:27 PM PDT 24 15836842 ps
T69 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1694935444 Aug 05 04:58:56 PM PDT 24 Aug 05 04:59:00 PM PDT 24 218669473 ps
T120 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2873925082 Aug 05 04:59:16 PM PDT 24 Aug 05 04:59:20 PM PDT 24 278462449 ps
T113 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3898737666 Aug 05 04:58:42 PM PDT 24 Aug 05 04:58:43 PM PDT 24 49695049 ps
T546 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3135497917 Aug 05 04:58:42 PM PDT 24 Aug 05 04:58:44 PM PDT 24 60904994 ps
T547 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2693534867 Aug 05 04:59:01 PM PDT 24 Aug 05 04:59:02 PM PDT 24 24259642 ps
T548 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3065581947 Aug 05 04:59:10 PM PDT 24 Aug 05 04:59:11 PM PDT 24 13178962 ps
T549 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2640291888 Aug 05 04:58:42 PM PDT 24 Aug 05 04:58:43 PM PDT 24 76479834 ps
T99 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3158421505 Aug 05 04:59:11 PM PDT 24 Aug 05 04:59:12 PM PDT 24 54404505 ps
T550 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.704424086 Aug 05 04:58:51 PM PDT 24 Aug 05 04:58:54 PM PDT 24 223469129 ps
T551 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.698394373 Aug 05 04:58:49 PM PDT 24 Aug 05 04:58:50 PM PDT 24 43106498 ps
T552 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2324891849 Aug 05 04:59:02 PM PDT 24 Aug 05 04:59:03 PM PDT 24 157049178 ps
T127 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1610149491 Aug 05 04:58:52 PM PDT 24 Aug 05 04:58:55 PM PDT 24 326544249 ps
T553 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3100880875 Aug 05 04:59:08 PM PDT 24 Aug 05 04:59:11 PM PDT 24 1472248313 ps
T554 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.949107854 Aug 05 04:58:56 PM PDT 24 Aug 05 04:58:59 PM PDT 24 356522882 ps
T114 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1316453759 Aug 05 04:59:21 PM PDT 24 Aug 05 04:59:23 PM PDT 24 873213301 ps
T555 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2936830606 Aug 05 04:58:35 PM PDT 24 Aug 05 04:58:36 PM PDT 24 47712885 ps
T121 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.531244398 Aug 05 04:58:53 PM PDT 24 Aug 05 04:58:58 PM PDT 24 1001169420 ps
T115 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4096072661 Aug 05 04:58:37 PM PDT 24 Aug 05 04:58:38 PM PDT 24 94066658 ps
T556 /workspace/coverage/cover_reg_top/15.hmac_intr_test.934158187 Aug 05 04:59:04 PM PDT 24 Aug 05 04:59:04 PM PDT 24 71893708 ps
T128 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2745856421 Aug 05 04:59:17 PM PDT 24 Aug 05 04:59:21 PM PDT 24 415835111 ps
T557 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.264962970 Aug 05 04:58:58 PM PDT 24 Aug 05 04:58:59 PM PDT 24 131819349 ps
T558 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2622747141 Aug 05 04:59:13 PM PDT 24 Aug 05 04:59:13 PM PDT 24 101542138 ps
T559 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1369764525 Aug 05 04:59:21 PM PDT 24 Aug 05 04:59:22 PM PDT 24 31064240 ps
T560 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.815954231 Aug 05 04:58:42 PM PDT 24 Aug 05 04:58:47 PM PDT 24 108213563 ps
T561 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.4273854647 Aug 05 04:58:46 PM PDT 24 Aug 05 04:58:47 PM PDT 24 21039321 ps
T562 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3302855594 Aug 05 04:59:34 PM PDT 24 Aug 05 04:59:35 PM PDT 24 17386288 ps
T563 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.913844050 Aug 05 04:58:49 PM PDT 24 Aug 05 04:58:53 PM PDT 24 185343808 ps
T564 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3655884745 Aug 05 04:58:55 PM PDT 24 Aug 05 04:59:01 PM PDT 24 714383223 ps
T565 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3070870846 Aug 05 04:59:03 PM PDT 24 Aug 05 04:59:03 PM PDT 24 21284119 ps
T122 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1415461684 Aug 05 04:58:39 PM PDT 24 Aug 05 04:58:41 PM PDT 24 171660756 ps
T566 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1273010730 Aug 05 04:59:25 PM PDT 24 Aug 05 05:09:52 PM PDT 24 717582950288 ps
T100 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.455973518 Aug 05 04:58:58 PM PDT 24 Aug 05 04:58:59 PM PDT 24 25617979 ps
T567 /workspace/coverage/cover_reg_top/41.hmac_intr_test.285134056 Aug 05 04:59:04 PM PDT 24 Aug 05 04:59:05 PM PDT 24 58185056 ps
T568 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1006348034 Aug 05 04:59:37 PM PDT 24 Aug 05 04:59:38 PM PDT 24 49517226 ps
T569 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1081354547 Aug 05 04:59:28 PM PDT 24 Aug 05 04:59:29 PM PDT 24 40718596 ps
T570 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.327351006 Aug 05 04:58:51 PM PDT 24 Aug 05 04:58:56 PM PDT 24 114793484 ps
T101 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1192957253 Aug 05 04:58:46 PM PDT 24 Aug 05 04:58:51 PM PDT 24 401427751 ps
T571 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1971642520 Aug 05 04:59:25 PM PDT 24 Aug 05 04:59:27 PM PDT 24 115002690 ps
T572 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3701966987 Aug 05 04:58:41 PM PDT 24 Aug 05 04:58:42 PM PDT 24 37018905 ps
T573 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4002742107 Aug 05 04:58:52 PM PDT 24 Aug 05 04:59:03 PM PDT 24 3888449271 ps
T574 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1458575859 Aug 05 04:59:19 PM PDT 24 Aug 05 04:59:21 PM PDT 24 117405235 ps
T575 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2240655139 Aug 05 04:59:01 PM PDT 24 Aug 05 04:59:02 PM PDT 24 19204109 ps
T576 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.213619314 Aug 05 04:58:41 PM PDT 24 Aug 05 04:58:44 PM PDT 24 192876934 ps
T124 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3227130151 Aug 05 04:59:00 PM PDT 24 Aug 05 04:59:03 PM PDT 24 216028601 ps
T577 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.501118977 Aug 05 04:58:58 PM PDT 24 Aug 05 04:58:59 PM PDT 24 91801074 ps
T578 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1563952766 Aug 05 04:59:23 PM PDT 24 Aug 05 04:59:24 PM PDT 24 45575365 ps
T579 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1650494253 Aug 05 04:59:12 PM PDT 24 Aug 05 04:59:13 PM PDT 24 11755279 ps
T580 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.82454153 Aug 05 04:58:49 PM PDT 24 Aug 05 04:58:53 PM PDT 24 717735902 ps
T581 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1401998725 Aug 05 04:58:47 PM PDT 24 Aug 05 04:58:50 PM PDT 24 93178678 ps
T582 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1528994829 Aug 05 04:58:44 PM PDT 24 Aug 05 04:58:45 PM PDT 24 56355676 ps
T583 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2762652950 Aug 05 04:58:40 PM PDT 24 Aug 05 04:58:42 PM PDT 24 62018964 ps
T584 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3940507621 Aug 05 04:59:25 PM PDT 24 Aug 05 04:59:26 PM PDT 24 29041883 ps
T585 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.309280007 Aug 05 04:58:54 PM PDT 24 Aug 05 04:58:57 PM PDT 24 387521891 ps
T586 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1361914717 Aug 05 04:59:29 PM PDT 24 Aug 05 04:59:33 PM PDT 24 130586944 ps
T587 /workspace/coverage/cover_reg_top/21.hmac_intr_test.958246238 Aug 05 04:59:18 PM PDT 24 Aug 05 04:59:18 PM PDT 24 25626520 ps
T102 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.164437435 Aug 05 04:59:29 PM PDT 24 Aug 05 04:59:29 PM PDT 24 13461525 ps
T588 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3205217733 Aug 05 04:58:47 PM PDT 24 Aug 05 04:58:49 PM PDT 24 404820959 ps
T589 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3912634393 Aug 05 04:59:05 PM PDT 24 Aug 05 04:59:06 PM PDT 24 55979985 ps
T590 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3125582875 Aug 05 04:59:05 PM PDT 24 Aug 05 04:59:07 PM PDT 24 47095094 ps
T591 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1672511559 Aug 05 04:59:14 PM PDT 24 Aug 05 04:59:14 PM PDT 24 13657817 ps
T592 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1513449883 Aug 05 04:59:29 PM PDT 24 Aug 05 04:59:30 PM PDT 24 26401622 ps
T593 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1484255794 Aug 05 04:58:58 PM PDT 24 Aug 05 04:58:58 PM PDT 24 13160198 ps
T594 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4045830511 Aug 05 04:58:58 PM PDT 24 Aug 05 04:58:59 PM PDT 24 31830132 ps
T595 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3747974552 Aug 05 04:58:30 PM PDT 24 Aug 05 04:58:30 PM PDT 24 36416778 ps
T596 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3316364700 Aug 05 04:58:41 PM PDT 24 Aug 05 04:58:43 PM PDT 24 48370725 ps
T597 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2201833424 Aug 05 04:59:16 PM PDT 24 Aug 05 04:59:17 PM PDT 24 16153338 ps
T103 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1211429682 Aug 05 04:58:39 PM PDT 24 Aug 05 04:58:40 PM PDT 24 137434604 ps
T598 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3285693369 Aug 05 04:58:27 PM PDT 24 Aug 05 04:58:28 PM PDT 24 15208245 ps
T599 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3818216392 Aug 05 04:59:02 PM PDT 24 Aug 05 04:59:03 PM PDT 24 82434333 ps
T600 /workspace/coverage/cover_reg_top/40.hmac_intr_test.4243327337 Aug 05 04:59:22 PM PDT 24 Aug 05 04:59:22 PM PDT 24 15365108 ps
T104 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3287525075 Aug 05 04:58:43 PM PDT 24 Aug 05 04:58:44 PM PDT 24 62454088 ps
T601 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.998250139 Aug 05 04:59:30 PM PDT 24 Aug 05 04:59:32 PM PDT 24 97168981 ps
T602 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3998729274 Aug 05 04:59:10 PM PDT 24 Aug 05 04:59:11 PM PDT 24 27355097 ps
T603 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2841786029 Aug 05 04:59:00 PM PDT 24 Aug 05 04:59:01 PM PDT 24 36474756 ps
T604 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4115786981 Aug 05 04:58:51 PM PDT 24 Aug 05 04:58:53 PM PDT 24 2387292628 ps
T605 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1412661595 Aug 05 04:58:49 PM PDT 24 Aug 05 04:58:50 PM PDT 24 16995310 ps
T606 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2049892874 Aug 05 04:58:37 PM PDT 24 Aug 05 05:16:45 PM PDT 24 73474258728 ps
T607 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1386971640 Aug 05 04:59:09 PM PDT 24 Aug 05 04:59:11 PM PDT 24 52332259 ps
T608 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.948677088 Aug 05 04:59:13 PM PDT 24 Aug 05 05:13:11 PM PDT 24 156343664398 ps
T609 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2463633130 Aug 05 04:59:01 PM PDT 24 Aug 05 04:59:01 PM PDT 24 12559082 ps
T125 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.780280546 Aug 05 04:58:49 PM PDT 24 Aug 05 04:58:51 PM PDT 24 101327204 ps
T610 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2780433100 Aug 05 04:59:06 PM PDT 24 Aug 05 04:59:07 PM PDT 24 14393947 ps
T105 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.505949631 Aug 05 04:59:09 PM PDT 24 Aug 05 04:59:10 PM PDT 24 50976621 ps
T611 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2287491779 Aug 05 04:59:24 PM PDT 24 Aug 05 04:59:25 PM PDT 24 40401905 ps
T612 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2576919078 Aug 05 04:59:25 PM PDT 24 Aug 05 04:59:28 PM PDT 24 299002218 ps
T613 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3742295734 Aug 05 04:58:49 PM PDT 24 Aug 05 04:58:50 PM PDT 24 30957734 ps
T614 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.705090128 Aug 05 04:58:42 PM PDT 24 Aug 05 04:58:44 PM PDT 24 38441307 ps
T615 /workspace/coverage/cover_reg_top/14.hmac_intr_test.407449810 Aug 05 04:59:00 PM PDT 24 Aug 05 04:59:01 PM PDT 24 11588272 ps
T616 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2602283881 Aug 05 04:58:42 PM PDT 24 Aug 05 04:58:43 PM PDT 24 17092080 ps
T617 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.603583368 Aug 05 04:58:48 PM PDT 24 Aug 05 04:58:49 PM PDT 24 58526180 ps
T618 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2991213978 Aug 05 04:58:42 PM PDT 24 Aug 05 04:58:46 PM PDT 24 206942342 ps
T619 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3042115258 Aug 05 04:59:03 PM PDT 24 Aug 05 04:59:07 PM PDT 24 365431317 ps
T620 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1560766319 Aug 05 04:59:11 PM PDT 24 Aug 05 04:59:11 PM PDT 24 17044550 ps
T106 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3586884916 Aug 05 04:59:09 PM PDT 24 Aug 05 04:59:10 PM PDT 24 48801604 ps
T621 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1065816225 Aug 05 04:59:04 PM PDT 24 Aug 05 04:59:06 PM PDT 24 93279302 ps
T622 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.45990839 Aug 05 04:58:47 PM PDT 24 Aug 05 04:58:50 PM PDT 24 334224676 ps
T126 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3712470160 Aug 05 04:58:42 PM PDT 24 Aug 05 04:58:46 PM PDT 24 356638561 ps
T623 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3819980058 Aug 05 04:59:16 PM PDT 24 Aug 05 04:59:17 PM PDT 24 13606476 ps
T624 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2142620145 Aug 05 04:58:45 PM PDT 24 Aug 05 04:58:47 PM PDT 24 80088088 ps
T625 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1912827824 Aug 05 04:58:47 PM PDT 24 Aug 05 04:58:48 PM PDT 24 46380457 ps
T626 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3215861286 Aug 05 04:58:41 PM PDT 24 Aug 05 04:58:43 PM PDT 24 438763375 ps
T627 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3897339497 Aug 05 04:59:23 PM PDT 24 Aug 05 04:59:24 PM PDT 24 41680294 ps
T107 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2301279628 Aug 05 04:59:16 PM PDT 24 Aug 05 04:59:17 PM PDT 24 35255366 ps
T628 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2020150469 Aug 05 04:59:23 PM PDT 24 Aug 05 04:59:27 PM PDT 24 1010473024 ps
T629 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4209252198 Aug 05 04:59:15 PM PDT 24 Aug 05 04:59:17 PM PDT 24 98587624 ps
T630 /workspace/coverage/cover_reg_top/11.hmac_intr_test.4099369447 Aug 05 04:58:57 PM PDT 24 Aug 05 04:58:58 PM PDT 24 12334638 ps
T108 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.609645675 Aug 05 04:58:46 PM PDT 24 Aug 05 04:58:47 PM PDT 24 164464679 ps
T631 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3213319540 Aug 05 04:58:50 PM PDT 24 Aug 05 04:58:52 PM PDT 24 33088341 ps
T632 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1269444577 Aug 05 04:59:04 PM PDT 24 Aug 05 04:59:04 PM PDT 24 44462049 ps
T633 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2622931598 Aug 05 04:58:36 PM PDT 24 Aug 05 04:58:38 PM PDT 24 904024163 ps
T634 /workspace/coverage/cover_reg_top/25.hmac_intr_test.864817072 Aug 05 04:59:04 PM PDT 24 Aug 05 04:59:05 PM PDT 24 12732134 ps
T635 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1142883686 Aug 05 04:58:34 PM PDT 24 Aug 05 04:58:37 PM PDT 24 407156027 ps
T636 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2595041224 Aug 05 04:58:33 PM PDT 24 Aug 05 04:58:35 PM PDT 24 168093384 ps
T637 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2319932066 Aug 05 04:59:03 PM PDT 24 Aug 05 04:59:04 PM PDT 24 116654381 ps
T638 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1109533074 Aug 05 04:59:08 PM PDT 24 Aug 05 04:59:08 PM PDT 24 15149568 ps
T639 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3250296610 Aug 05 04:59:30 PM PDT 24 Aug 05 04:59:33 PM PDT 24 55146820 ps
T640 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2862569190 Aug 05 04:59:20 PM PDT 24 Aug 05 04:59:21 PM PDT 24 107390318 ps
T641 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1204411466 Aug 05 04:58:57 PM PDT 24 Aug 05 04:58:58 PM PDT 24 34053929 ps
T642 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3245331976 Aug 05 04:59:16 PM PDT 24 Aug 05 04:59:17 PM PDT 24 41294141 ps
T643 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.58165871 Aug 05 04:58:42 PM PDT 24 Aug 05 04:58:45 PM PDT 24 2227632459 ps
T644 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1926310307 Aug 05 04:58:56 PM PDT 24 Aug 05 04:58:58 PM PDT 24 1077693396 ps
T645 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.814018260 Aug 05 04:58:46 PM PDT 24 Aug 05 04:58:49 PM PDT 24 182623551 ps
T646 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1341540394 Aug 05 04:59:25 PM PDT 24 Aug 05 04:59:26 PM PDT 24 113987675 ps
T647 /workspace/coverage/cover_reg_top/44.hmac_intr_test.520494107 Aug 05 04:59:27 PM PDT 24 Aug 05 04:59:27 PM PDT 24 51368392 ps
T648 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2948474202 Aug 05 04:59:09 PM PDT 24 Aug 05 04:59:10 PM PDT 24 59801815 ps
T649 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1135906508 Aug 05 04:58:50 PM PDT 24 Aug 05 04:58:52 PM PDT 24 154998773 ps
T650 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3315369897 Aug 05 04:59:08 PM PDT 24 Aug 05 04:59:09 PM PDT 24 103838224 ps
T651 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2931186066 Aug 05 04:58:59 PM PDT 24 Aug 05 04:58:59 PM PDT 24 73179937 ps
T652 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1236604646 Aug 05 04:58:50 PM PDT 24 Aug 05 04:59:01 PM PDT 24 1459901782 ps
T653 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3098133064 Aug 05 04:59:15 PM PDT 24 Aug 05 04:59:19 PM PDT 24 1343347708 ps
T654 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2069004035 Aug 05 04:59:04 PM PDT 24 Aug 05 04:59:05 PM PDT 24 264033843 ps
T655 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1349581598 Aug 05 04:58:51 PM PDT 24 Aug 05 04:58:51 PM PDT 24 40638340 ps
T656 /workspace/coverage/cover_reg_top/35.hmac_intr_test.4064291004 Aug 05 04:59:28 PM PDT 24 Aug 05 04:59:28 PM PDT 24 33739295 ps
T657 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2694424491 Aug 05 04:59:00 PM PDT 24 Aug 05 04:59:01 PM PDT 24 51457221 ps
T658 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3745395677 Aug 05 04:59:30 PM PDT 24 Aug 05 04:59:32 PM PDT 24 33896351 ps
T659 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2313018874 Aug 05 04:58:50 PM PDT 24 Aug 05 04:58:51 PM PDT 24 43761256 ps
T660 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1063559011 Aug 05 04:59:20 PM PDT 24 Aug 05 04:59:22 PM PDT 24 532568727 ps

Test location /workspace/coverage/default/45.hmac_stress_all.1057151966
Short name T8
Test name
Test status
Simulation time 104164844859 ps
CPU time 1431.49 seconds
Started Aug 05 05:42:46 PM PDT 24
Finished Aug 05 06:06:37 PM PDT 24
Peak memory 687612 kb
Host smart-10c851aa-b4e2-40e5-9eca-0c5aadcd1eb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057151966 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1057151966
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1358885908
Short name T22
Test name
Test status
Simulation time 201380614655 ps
CPU time 7404.81 seconds
Started Aug 05 05:41:46 PM PDT 24
Finished Aug 05 07:45:12 PM PDT 24
Peak memory 904796 kb
Host smart-aab56c28-ce65-4cd1-b7a9-d5178ffffdcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1358885908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1358885908
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2126927525
Short name T4
Test name
Test status
Simulation time 8701983878 ps
CPU time 39.51 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:44 PM PDT 24
Peak memory 200016 kb
Host smart-4b3ca4e9-0a0c-40d4-8374-a8d835ae18ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126927525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2126927525
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3519293787
Short name T26
Test name
Test status
Simulation time 6271564872 ps
CPU time 352.03 seconds
Started Aug 05 05:42:12 PM PDT 24
Finished Aug 05 05:48:04 PM PDT 24
Peak memory 216352 kb
Host smart-117361cf-52ad-4492-8bd5-a6033b73f443
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519293787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3519293787
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1316228143
Short name T67
Test name
Test status
Simulation time 247382401 ps
CPU time 3.84 seconds
Started Aug 05 04:58:53 PM PDT 24
Finished Aug 05 04:58:57 PM PDT 24
Peak memory 200136 kb
Host smart-462f3094-f83c-46b3-af95-357c0a9e3f59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316228143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1316228143
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3980828977
Short name T9
Test name
Test status
Simulation time 54549288178 ps
CPU time 1436.68 seconds
Started Aug 05 05:41:34 PM PDT 24
Finished Aug 05 06:05:31 PM PDT 24
Peak memory 732036 kb
Host smart-753acbdd-a76e-4a99-a0d7-a8d7ecb17a40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980828977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3980828977
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1675601130
Short name T13
Test name
Test status
Simulation time 122542309489 ps
CPU time 2560.36 seconds
Started Aug 05 05:41:44 PM PDT 24
Finished Aug 05 06:24:24 PM PDT 24
Peak memory 772692 kb
Host smart-31221aba-3bb3-4540-9575-aebad26fcedb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675601130 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1675601130
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_alert_test.293464486
Short name T154
Test name
Test status
Simulation time 17471260 ps
CPU time 0.6 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 05:41:25 PM PDT 24
Peak memory 195808 kb
Host smart-47f0c0d8-8e4e-40d3-b6f2-dba2cc203fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293464486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.293464486
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2221577162
Short name T98
Test name
Test status
Simulation time 202627377 ps
CPU time 0.93 seconds
Started Aug 05 04:58:48 PM PDT 24
Finished Aug 05 04:58:49 PM PDT 24
Peak memory 199840 kb
Host smart-75d72d42-c819-4975-9148-6b7ba0dc3046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221577162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2221577162
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1805206987
Short name T34
Test name
Test status
Simulation time 393419116 ps
CPU time 0.87 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 05:41:28 PM PDT 24
Peak memory 218448 kb
Host smart-4e20127f-b259-4844-bc0a-1c40f7397791
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805206987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1805206987
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1694935444
Short name T69
Test name
Test status
Simulation time 218669473 ps
CPU time 3.85 seconds
Started Aug 05 04:58:56 PM PDT 24
Finished Aug 05 04:59:00 PM PDT 24
Peak memory 200136 kb
Host smart-e90c2731-62dd-45cb-83ea-92a4ed1a1f38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694935444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1694935444
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2188284174
Short name T21
Test name
Test status
Simulation time 27066143290 ps
CPU time 388.46 seconds
Started Aug 05 05:42:15 PM PDT 24
Finished Aug 05 05:48:43 PM PDT 24
Peak memory 199972 kb
Host smart-8b7994cd-133b-4755-8af3-9bf3df5869e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188284174 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2188284174
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.531244398
Short name T121
Test name
Test status
Simulation time 1001169420 ps
CPU time 4.33 seconds
Started Aug 05 04:58:53 PM PDT 24
Finished Aug 05 04:58:58 PM PDT 24
Peak memory 200136 kb
Host smart-98b32156-58ed-41ce-98ed-1b54219c9fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531244398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.531244398
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.881982196
Short name T88
Test name
Test status
Simulation time 238483650590 ps
CPU time 568.52 seconds
Started Aug 05 05:41:44 PM PDT 24
Finished Aug 05 05:51:13 PM PDT 24
Peak memory 199992 kb
Host smart-5037cac4-dfd4-42ee-a724-8523d88c1d87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=881982196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.881982196
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2492045082
Short name T136
Test name
Test status
Simulation time 9465413817 ps
CPU time 37.31 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:42:40 PM PDT 24
Peak memory 216432 kb
Host smart-5430171a-e807-4b95-8cbf-7526fdf4c96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492045082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2492045082
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.814018260
Short name T645
Test name
Test status
Simulation time 182623551 ps
CPU time 3.34 seconds
Started Aug 05 04:58:46 PM PDT 24
Finished Aug 05 04:58:49 PM PDT 24
Peak memory 200056 kb
Host smart-e99e8eb7-5de0-4221-814a-bd9dd91e9623
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814018260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.814018260
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1236604646
Short name T652
Test name
Test status
Simulation time 1459901782 ps
CPU time 11.12 seconds
Started Aug 05 04:58:50 PM PDT 24
Finished Aug 05 04:59:01 PM PDT 24
Peak memory 200060 kb
Host smart-5dbb003b-cfe7-42a4-8083-d8d984f59788
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236604646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1236604646
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2936830606
Short name T555
Test name
Test status
Simulation time 47712885 ps
CPU time 0.79 seconds
Started Aug 05 04:58:35 PM PDT 24
Finished Aug 05 04:58:36 PM PDT 24
Peak memory 197740 kb
Host smart-f8fd5865-ca64-437a-9826-0e990aff4992
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936830606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2936830606
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.213619314
Short name T576
Test name
Test status
Simulation time 192876934 ps
CPU time 3.33 seconds
Started Aug 05 04:58:41 PM PDT 24
Finished Aug 05 04:58:44 PM PDT 24
Peak memory 215516 kb
Host smart-fc0c67bc-2e7b-4378-a506-4f3a7d96e149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213619314 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.213619314
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2240655139
Short name T575
Test name
Test status
Simulation time 19204109 ps
CPU time 0.62 seconds
Started Aug 05 04:59:01 PM PDT 24
Finished Aug 05 04:59:02 PM PDT 24
Peak memory 195024 kb
Host smart-23fc8dd3-127f-40c2-ad25-2cdf1059aa00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240655139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2240655139
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3898737666
Short name T113
Test name
Test status
Simulation time 49695049 ps
CPU time 1.14 seconds
Started Aug 05 04:58:42 PM PDT 24
Finished Aug 05 04:58:43 PM PDT 24
Peak memory 200152 kb
Host smart-cfc79df2-026d-4942-b976-34467339ca8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898737666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3898737666
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.913844050
Short name T563
Test name
Test status
Simulation time 185343808 ps
CPU time 3.33 seconds
Started Aug 05 04:58:49 PM PDT 24
Finished Aug 05 04:58:53 PM PDT 24
Peak memory 200124 kb
Host smart-f8a5afbc-1cf8-4683-a968-1cf797bbcbc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913844050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.913844050
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2595041224
Short name T636
Test name
Test status
Simulation time 168093384 ps
CPU time 2.79 seconds
Started Aug 05 04:58:33 PM PDT 24
Finished Aug 05 04:58:35 PM PDT 24
Peak memory 200128 kb
Host smart-d1fbcf0b-a44d-4219-9305-44ea5e4197a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595041224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2595041224
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.815954231
Short name T560
Test name
Test status
Simulation time 108213563 ps
CPU time 5.55 seconds
Started Aug 05 04:58:42 PM PDT 24
Finished Aug 05 04:58:47 PM PDT 24
Peak memory 200020 kb
Host smart-efe590f9-262c-40a4-965a-93ea275a216a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815954231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.815954231
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3655884745
Short name T564
Test name
Test status
Simulation time 714383223 ps
CPU time 5.71 seconds
Started Aug 05 04:58:55 PM PDT 24
Finished Aug 05 04:59:01 PM PDT 24
Peak memory 200152 kb
Host smart-071bcd84-0d9d-4036-b4e5-edc6611405bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655884745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3655884745
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.609645675
Short name T108
Test name
Test status
Simulation time 164464679 ps
CPU time 0.94 seconds
Started Aug 05 04:58:46 PM PDT 24
Finished Aug 05 04:58:47 PM PDT 24
Peak memory 199764 kb
Host smart-bbb1d462-aa14-4b17-9457-49f5dca27941
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609645675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.609645675
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2640291888
Short name T549
Test name
Test status
Simulation time 76479834 ps
CPU time 1.33 seconds
Started Aug 05 04:58:42 PM PDT 24
Finished Aug 05 04:58:43 PM PDT 24
Peak memory 200132 kb
Host smart-c255b3e6-6f6f-4c0b-8d14-2e75d9584728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640291888 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2640291888
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1204411466
Short name T641
Test name
Test status
Simulation time 34053929 ps
CPU time 0.71 seconds
Started Aug 05 04:58:57 PM PDT 24
Finished Aug 05 04:58:58 PM PDT 24
Peak memory 198300 kb
Host smart-77d666d0-af3f-46ee-ad9f-178d10f16302
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204411466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1204411466
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3285693369
Short name T598
Test name
Test status
Simulation time 15208245 ps
CPU time 0.62 seconds
Started Aug 05 04:58:27 PM PDT 24
Finished Aug 05 04:58:28 PM PDT 24
Peak memory 195168 kb
Host smart-ea3767ea-6043-4bcc-a5f5-bec1c253f90d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285693369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3285693369
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4096072661
Short name T115
Test name
Test status
Simulation time 94066658 ps
CPU time 1.18 seconds
Started Aug 05 04:58:37 PM PDT 24
Finished Aug 05 04:58:38 PM PDT 24
Peak memory 198576 kb
Host smart-2fe3cdcb-6317-468a-a4ae-197010bdee0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096072661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.4096072661
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.603583368
Short name T617
Test name
Test status
Simulation time 58526180 ps
CPU time 1.45 seconds
Started Aug 05 04:58:48 PM PDT 24
Finished Aug 05 04:58:49 PM PDT 24
Peak memory 200064 kb
Host smart-41ece4c8-8cbc-4b0c-9805-f5dc06c02800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603583368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.603583368
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2142620145
Short name T624
Test name
Test status
Simulation time 80088088 ps
CPU time 1.93 seconds
Started Aug 05 04:58:45 PM PDT 24
Finished Aug 05 04:58:47 PM PDT 24
Peak memory 200184 kb
Host smart-2f5fdfc1-a505-49d6-91fb-08375e030460
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142620145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2142620145
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.949107854
Short name T554
Test name
Test status
Simulation time 356522882 ps
CPU time 2.41 seconds
Started Aug 05 04:58:56 PM PDT 24
Finished Aug 05 04:58:59 PM PDT 24
Peak memory 200188 kb
Host smart-3b55656c-dea9-4b1d-9ada-81101baea416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949107854 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.949107854
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3315369897
Short name T650
Test name
Test status
Simulation time 103838224 ps
CPU time 0.83 seconds
Started Aug 05 04:59:08 PM PDT 24
Finished Aug 05 04:59:09 PM PDT 24
Peak memory 199996 kb
Host smart-b31791f2-1d7d-458a-b9f9-7085ac5fccd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315369897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3315369897
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1412661595
Short name T605
Test name
Test status
Simulation time 16995310 ps
CPU time 0.67 seconds
Started Aug 05 04:58:49 PM PDT 24
Finished Aug 05 04:58:50 PM PDT 24
Peak memory 195040 kb
Host smart-660162af-0a22-4ee5-b9c8-fa7e80d9a4f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412661595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1412661595
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1926310307
Short name T644
Test name
Test status
Simulation time 1077693396 ps
CPU time 2.39 seconds
Started Aug 05 04:58:56 PM PDT 24
Finished Aug 05 04:58:58 PM PDT 24
Peak memory 200076 kb
Host smart-f3bf31cb-8908-4647-948a-3e54e31a73d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926310307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1926310307
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1528994829
Short name T582
Test name
Test status
Simulation time 56355676 ps
CPU time 1.39 seconds
Started Aug 05 04:58:44 PM PDT 24
Finished Aug 05 04:58:45 PM PDT 24
Peak memory 200124 kb
Host smart-acdf21bc-59d9-4e37-8990-9f2bb8cc910c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528994829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1528994829
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3042115258
Short name T619
Test name
Test status
Simulation time 365431317 ps
CPU time 3.17 seconds
Started Aug 05 04:59:03 PM PDT 24
Finished Aug 05 04:59:07 PM PDT 24
Peak memory 200360 kb
Host smart-4aba3d6d-2fcb-4940-bdee-15ab207d393b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042115258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3042115258
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1386971640
Short name T607
Test name
Test status
Simulation time 52332259 ps
CPU time 1.74 seconds
Started Aug 05 04:59:09 PM PDT 24
Finished Aug 05 04:59:11 PM PDT 24
Peak memory 200160 kb
Host smart-53a7c724-3a38-419c-b4f0-43009d8b3a93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386971640 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1386971640
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3586884916
Short name T106
Test name
Test status
Simulation time 48801604 ps
CPU time 0.77 seconds
Started Aug 05 04:59:09 PM PDT 24
Finished Aug 05 04:59:10 PM PDT 24
Peak memory 199316 kb
Host smart-ba810787-aac1-48ca-8311-efc1b863b2d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586884916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3586884916
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.4099369447
Short name T630
Test name
Test status
Simulation time 12334638 ps
CPU time 0.63 seconds
Started Aug 05 04:58:57 PM PDT 24
Finished Aug 05 04:58:58 PM PDT 24
Peak memory 195056 kb
Host smart-535e3fc9-b52a-4a48-8f2d-996b4083bc43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099369447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.4099369447
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.501118977
Short name T577
Test name
Test status
Simulation time 91801074 ps
CPU time 1 seconds
Started Aug 05 04:58:58 PM PDT 24
Finished Aug 05 04:58:59 PM PDT 24
Peak memory 198704 kb
Host smart-0ad6534c-fabb-4290-a965-d1b75fee484b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501118977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.501118977
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3213319540
Short name T631
Test name
Test status
Simulation time 33088341 ps
CPU time 1.68 seconds
Started Aug 05 04:58:50 PM PDT 24
Finished Aug 05 04:58:52 PM PDT 24
Peak memory 200048 kb
Host smart-5ba01be9-2520-499b-907f-6e04517a1253
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213319540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3213319540
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1458575859
Short name T574
Test name
Test status
Simulation time 117405235 ps
CPU time 1.74 seconds
Started Aug 05 04:59:19 PM PDT 24
Finished Aug 05 04:59:21 PM PDT 24
Peak memory 200148 kb
Host smart-4461241d-6d15-4559-ae69-072a382b096b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458575859 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1458575859
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2931186066
Short name T651
Test name
Test status
Simulation time 73179937 ps
CPU time 0.72 seconds
Started Aug 05 04:58:59 PM PDT 24
Finished Aug 05 04:58:59 PM PDT 24
Peak memory 198444 kb
Host smart-dda9d8f8-f11b-46cd-9da6-0318179a98ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931186066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2931186066
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2948474202
Short name T648
Test name
Test status
Simulation time 59801815 ps
CPU time 0.6 seconds
Started Aug 05 04:59:09 PM PDT 24
Finished Aug 05 04:59:10 PM PDT 24
Peak memory 195160 kb
Host smart-3eb9a839-7a14-402d-8dcc-ae0b50d1b28c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948474202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2948474202
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2841786029
Short name T603
Test name
Test status
Simulation time 36474756 ps
CPU time 1.58 seconds
Started Aug 05 04:59:00 PM PDT 24
Finished Aug 05 04:59:01 PM PDT 24
Peak memory 200136 kb
Host smart-d9b2f948-aa1b-45a1-a40d-12527486cf76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841786029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2841786029
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.264962970
Short name T557
Test name
Test status
Simulation time 131819349 ps
CPU time 1.56 seconds
Started Aug 05 04:58:58 PM PDT 24
Finished Aug 05 04:58:59 PM PDT 24
Peak memory 200076 kb
Host smart-7b8baa3a-7112-4e7b-8025-8a97f56c8077
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264962970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.264962970
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1610149491
Short name T127
Test name
Test status
Simulation time 326544249 ps
CPU time 3.07 seconds
Started Aug 05 04:58:52 PM PDT 24
Finished Aug 05 04:58:55 PM PDT 24
Peak memory 200128 kb
Host smart-143a8d51-3fe7-47dc-9e61-9177afe1e25c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610149491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1610149491
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2324891849
Short name T552
Test name
Test status
Simulation time 157049178 ps
CPU time 1.51 seconds
Started Aug 05 04:59:02 PM PDT 24
Finished Aug 05 04:59:03 PM PDT 24
Peak memory 200192 kb
Host smart-ca30781d-e882-4a72-ac19-4bee78566c8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324891849 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2324891849
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.455973518
Short name T100
Test name
Test status
Simulation time 25617979 ps
CPU time 0.85 seconds
Started Aug 05 04:58:58 PM PDT 24
Finished Aug 05 04:58:59 PM PDT 24
Peak memory 199748 kb
Host smart-44e30202-c9e5-4166-9e28-3d959e1cf0c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455973518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.455973518
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.519360995
Short name T533
Test name
Test status
Simulation time 11821521 ps
CPU time 0.58 seconds
Started Aug 05 04:59:19 PM PDT 24
Finished Aug 05 04:59:20 PM PDT 24
Peak memory 194980 kb
Host smart-42ec8a43-6d04-43eb-8e75-7fbcd1f583cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519360995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.519360995
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.165832651
Short name T111
Test name
Test status
Simulation time 292546363 ps
CPU time 1.8 seconds
Started Aug 05 04:59:13 PM PDT 24
Finished Aug 05 04:59:15 PM PDT 24
Peak memory 200112 kb
Host smart-322d7d85-cef7-42ae-9998-13850451d4e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165832651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.165832651
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3181753188
Short name T542
Test name
Test status
Simulation time 287500507 ps
CPU time 4.06 seconds
Started Aug 05 04:59:20 PM PDT 24
Finished Aug 05 04:59:29 PM PDT 24
Peak memory 200148 kb
Host smart-ebd32071-2ada-4a0c-a500-9763357180c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181753188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3181753188
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4209252198
Short name T629
Test name
Test status
Simulation time 98587624 ps
CPU time 1.97 seconds
Started Aug 05 04:59:15 PM PDT 24
Finished Aug 05 04:59:17 PM PDT 24
Peak memory 200208 kb
Host smart-1fb7da42-c927-46ad-b60c-fccd6ef73d54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209252198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4209252198
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1879278363
Short name T543
Test name
Test status
Simulation time 40260594 ps
CPU time 1.21 seconds
Started Aug 05 04:59:29 PM PDT 24
Finished Aug 05 04:59:35 PM PDT 24
Peak memory 199912 kb
Host smart-1dcaf6f0-df3a-44aa-a7a1-a3e0fe244e68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879278363 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1879278363
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2694424491
Short name T657
Test name
Test status
Simulation time 51457221 ps
CPU time 0.85 seconds
Started Aug 05 04:59:00 PM PDT 24
Finished Aug 05 04:59:01 PM PDT 24
Peak memory 199356 kb
Host smart-2d248a44-674a-4804-93a1-a297624270fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694424491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2694424491
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.407449810
Short name T615
Test name
Test status
Simulation time 11588272 ps
CPU time 0.63 seconds
Started Aug 05 04:59:00 PM PDT 24
Finished Aug 05 04:59:01 PM PDT 24
Peak memory 195144 kb
Host smart-6dcc5f70-477f-4e94-9d78-0285fdd63edd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407449810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.407449810
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3745395677
Short name T658
Test name
Test status
Simulation time 33896351 ps
CPU time 1.68 seconds
Started Aug 05 04:59:30 PM PDT 24
Finished Aug 05 04:59:32 PM PDT 24
Peak memory 200124 kb
Host smart-9a22847b-799c-4764-9d59-8f51dd6c0bcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745395677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3745395677
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2020150469
Short name T628
Test name
Test status
Simulation time 1010473024 ps
CPU time 4.51 seconds
Started Aug 05 04:59:23 PM PDT 24
Finished Aug 05 04:59:27 PM PDT 24
Peak memory 200144 kb
Host smart-e324db47-f5b2-4285-88d5-3caa16c7cddd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020150469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2020150469
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3098133064
Short name T653
Test name
Test status
Simulation time 1343347708 ps
CPU time 4.21 seconds
Started Aug 05 04:59:15 PM PDT 24
Finished Aug 05 04:59:19 PM PDT 24
Peak memory 200128 kb
Host smart-f3b9e74b-0749-4578-a48d-5567d295fb79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098133064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3098133064
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.948677088
Short name T608
Test name
Test status
Simulation time 156343664398 ps
CPU time 837.7 seconds
Started Aug 05 04:59:13 PM PDT 24
Finished Aug 05 05:13:11 PM PDT 24
Peak memory 224800 kb
Host smart-ffacea8d-6e06-49a9-b50e-e1707eacb5a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948677088 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.948677088
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.164437435
Short name T102
Test name
Test status
Simulation time 13461525 ps
CPU time 0.72 seconds
Started Aug 05 04:59:29 PM PDT 24
Finished Aug 05 04:59:29 PM PDT 24
Peak memory 197720 kb
Host smart-0ec5074b-2e64-404d-9d67-e5a870189698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164437435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.164437435
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.934158187
Short name T556
Test name
Test status
Simulation time 71893708 ps
CPU time 0.58 seconds
Started Aug 05 04:59:04 PM PDT 24
Finished Aug 05 04:59:04 PM PDT 24
Peak memory 195076 kb
Host smart-8c50d21d-56d1-4383-999d-5d865fb0a233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934158187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.934158187
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1316453759
Short name T114
Test name
Test status
Simulation time 873213301 ps
CPU time 2.32 seconds
Started Aug 05 04:59:21 PM PDT 24
Finished Aug 05 04:59:23 PM PDT 24
Peak memory 200128 kb
Host smart-715f19ae-f71d-4f73-ab8f-6563e835bf28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316453759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1316453759
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1341540394
Short name T646
Test name
Test status
Simulation time 113987675 ps
CPU time 1.57 seconds
Started Aug 05 04:59:25 PM PDT 24
Finished Aug 05 04:59:26 PM PDT 24
Peak memory 200084 kb
Host smart-49decb36-b120-4f07-bccc-3c0231a66702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341540394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1341540394
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2745856421
Short name T128
Test name
Test status
Simulation time 415835111 ps
CPU time 3.81 seconds
Started Aug 05 04:59:17 PM PDT 24
Finished Aug 05 04:59:21 PM PDT 24
Peak memory 200160 kb
Host smart-4b0f7af4-9519-4019-a277-19c4fbe1f16f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745856421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2745856421
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1273010730
Short name T566
Test name
Test status
Simulation time 717582950288 ps
CPU time 627.16 seconds
Started Aug 05 04:59:25 PM PDT 24
Finished Aug 05 05:09:52 PM PDT 24
Peak memory 224812 kb
Host smart-53c81b8c-127e-480d-928f-82b59b9f9dc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273010730 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1273010730
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2862569190
Short name T640
Test name
Test status
Simulation time 107390318 ps
CPU time 0.97 seconds
Started Aug 05 04:59:20 PM PDT 24
Finished Aug 05 04:59:21 PM PDT 24
Peak memory 200000 kb
Host smart-8b4e7c08-4bdb-4ffa-992a-9eb264148898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862569190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2862569190
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1484255794
Short name T593
Test name
Test status
Simulation time 13160198 ps
CPU time 0.6 seconds
Started Aug 05 04:58:58 PM PDT 24
Finished Aug 05 04:58:58 PM PDT 24
Peak memory 194980 kb
Host smart-76c3e8c6-8742-42e2-9e1c-735bf8310e93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484255794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1484255794
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1063559011
Short name T660
Test name
Test status
Simulation time 532568727 ps
CPU time 2.1 seconds
Started Aug 05 04:59:20 PM PDT 24
Finished Aug 05 04:59:22 PM PDT 24
Peak memory 200092 kb
Host smart-5d767f9d-6d9c-4bbf-a10c-ea7b04ff77cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063559011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1063559011
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3250296610
Short name T639
Test name
Test status
Simulation time 55146820 ps
CPU time 2.83 seconds
Started Aug 05 04:59:30 PM PDT 24
Finished Aug 05 04:59:33 PM PDT 24
Peak memory 200076 kb
Host smart-854064f7-2199-4768-8611-483663c19ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250296610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3250296610
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1065816225
Short name T621
Test name
Test status
Simulation time 93279302 ps
CPU time 1.66 seconds
Started Aug 05 04:59:04 PM PDT 24
Finished Aug 05 04:59:06 PM PDT 24
Peak memory 200180 kb
Host smart-92e5c5dd-af7a-420a-882a-655a649167b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065816225 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1065816225
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2301279628
Short name T107
Test name
Test status
Simulation time 35255366 ps
CPU time 0.9 seconds
Started Aug 05 04:59:16 PM PDT 24
Finished Aug 05 04:59:17 PM PDT 24
Peak memory 199860 kb
Host smart-a3f32791-cb9c-4d41-8da2-2952a6fd6037
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301279628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2301279628
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2693534867
Short name T547
Test name
Test status
Simulation time 24259642 ps
CPU time 0.6 seconds
Started Aug 05 04:59:01 PM PDT 24
Finished Aug 05 04:59:02 PM PDT 24
Peak memory 195044 kb
Host smart-2264ad37-00fb-4287-8a13-db0dca622960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693534867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2693534867
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2576919078
Short name T612
Test name
Test status
Simulation time 299002218 ps
CPU time 2.51 seconds
Started Aug 05 04:59:25 PM PDT 24
Finished Aug 05 04:59:28 PM PDT 24
Peak memory 200092 kb
Host smart-31465f30-8864-49e4-a8ef-24130968361a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576919078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2576919078
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1361914717
Short name T586
Test name
Test status
Simulation time 130586944 ps
CPU time 3.29 seconds
Started Aug 05 04:59:29 PM PDT 24
Finished Aug 05 04:59:33 PM PDT 24
Peak memory 200128 kb
Host smart-5cbd4bfc-b034-4af2-860b-6f5212c10576
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361914717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1361914717
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2933861293
Short name T119
Test name
Test status
Simulation time 197573230 ps
CPU time 1.84 seconds
Started Aug 05 04:58:56 PM PDT 24
Finished Aug 05 04:58:58 PM PDT 24
Peak memory 200124 kb
Host smart-365d0057-3215-4337-a6eb-82a232dafb55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933861293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2933861293
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1081354547
Short name T569
Test name
Test status
Simulation time 40718596 ps
CPU time 1.22 seconds
Started Aug 05 04:59:28 PM PDT 24
Finished Aug 05 04:59:29 PM PDT 24
Peak memory 200184 kb
Host smart-a2f17175-13d0-499a-ab94-8189829109a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081354547 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1081354547
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2069004035
Short name T654
Test name
Test status
Simulation time 264033843 ps
CPU time 0.88 seconds
Started Aug 05 04:59:04 PM PDT 24
Finished Aug 05 04:59:05 PM PDT 24
Peak memory 199660 kb
Host smart-f054d3d6-b25f-4e40-8b78-21312b7857ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069004035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2069004035
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1109533074
Short name T638
Test name
Test status
Simulation time 15149568 ps
CPU time 0.57 seconds
Started Aug 05 04:59:08 PM PDT 24
Finished Aug 05 04:59:08 PM PDT 24
Peak memory 195076 kb
Host smart-4dd02478-fb99-4679-a6fe-27ec5f8b2351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109533074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1109533074
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2287491779
Short name T611
Test name
Test status
Simulation time 40401905 ps
CPU time 1.11 seconds
Started Aug 05 04:59:24 PM PDT 24
Finished Aug 05 04:59:25 PM PDT 24
Peak memory 199952 kb
Host smart-6911ec95-9a06-450c-8d4e-437356d3ed34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287491779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2287491779
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3125582875
Short name T590
Test name
Test status
Simulation time 47095094 ps
CPU time 2.31 seconds
Started Aug 05 04:59:05 PM PDT 24
Finished Aug 05 04:59:07 PM PDT 24
Peak memory 200076 kb
Host smart-87433afe-07b0-4fdc-b205-2fe9210db69a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125582875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3125582875
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2873925082
Short name T120
Test name
Test status
Simulation time 278462449 ps
CPU time 3.91 seconds
Started Aug 05 04:59:16 PM PDT 24
Finished Aug 05 04:59:20 PM PDT 24
Peak memory 200172 kb
Host smart-764653bd-ffe8-47ca-9ce5-1ec72a099a11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873925082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2873925082
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1477956595
Short name T541
Test name
Test status
Simulation time 151205089 ps
CPU time 1.76 seconds
Started Aug 05 04:59:04 PM PDT 24
Finished Aug 05 04:59:06 PM PDT 24
Peak memory 200120 kb
Host smart-6cd6a8ec-e356-4176-ac40-e368bcc08e8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477956595 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1477956595
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3940507621
Short name T584
Test name
Test status
Simulation time 29041883 ps
CPU time 0.66 seconds
Started Aug 05 04:59:25 PM PDT 24
Finished Aug 05 04:59:26 PM PDT 24
Peak memory 197544 kb
Host smart-e8f83e9e-29d1-453e-89b2-2e2e941b4435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940507621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3940507621
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3819980058
Short name T623
Test name
Test status
Simulation time 13606476 ps
CPU time 0.61 seconds
Started Aug 05 04:59:16 PM PDT 24
Finished Aug 05 04:59:17 PM PDT 24
Peak memory 194980 kb
Host smart-32870b42-2d49-4475-b86b-d42c7c534254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819980058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3819980058
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1971642520
Short name T571
Test name
Test status
Simulation time 115002690 ps
CPU time 2.26 seconds
Started Aug 05 04:59:25 PM PDT 24
Finished Aug 05 04:59:27 PM PDT 24
Peak memory 200204 kb
Host smart-aaa1c90c-d7d5-4c9d-acfc-b67e3bdcf3cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971642520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1971642520
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.998250139
Short name T601
Test name
Test status
Simulation time 97168981 ps
CPU time 2.12 seconds
Started Aug 05 04:59:30 PM PDT 24
Finished Aug 05 04:59:32 PM PDT 24
Peak memory 200080 kb
Host smart-a0ab3c28-417f-4f8e-af43-9801bb484182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998250139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.998250139
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3227130151
Short name T124
Test name
Test status
Simulation time 216028601 ps
CPU time 2.88 seconds
Started Aug 05 04:59:00 PM PDT 24
Finished Aug 05 04:59:03 PM PDT 24
Peak memory 200060 kb
Host smart-fc843cbc-14d9-4cec-be04-4eeba64123c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227130151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3227130151
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1142883686
Short name T635
Test name
Test status
Simulation time 407156027 ps
CPU time 3.07 seconds
Started Aug 05 04:58:34 PM PDT 24
Finished Aug 05 04:58:37 PM PDT 24
Peak memory 200012 kb
Host smart-1d8abce9-3674-4a06-b62e-f9625c8643ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142883686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1142883686
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2876155209
Short name T97
Test name
Test status
Simulation time 4389427678 ps
CPU time 11.26 seconds
Started Aug 05 04:58:49 PM PDT 24
Finished Aug 05 04:59:01 PM PDT 24
Peak memory 199660 kb
Host smart-f5d60850-de95-4a31-be65-8aa69c2e6bb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876155209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2876155209
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1257424896
Short name T96
Test name
Test status
Simulation time 39227481 ps
CPU time 1.01 seconds
Started Aug 05 04:58:53 PM PDT 24
Finished Aug 05 04:58:54 PM PDT 24
Peak memory 199964 kb
Host smart-f658de8f-f772-4256-a495-374b410d5ada
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257424896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1257424896
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2049892874
Short name T606
Test name
Test status
Simulation time 73474258728 ps
CPU time 1087.06 seconds
Started Aug 05 04:58:37 PM PDT 24
Finished Aug 05 05:16:45 PM PDT 24
Peak memory 216596 kb
Host smart-d94e28c7-82d9-4c50-898f-efa4f7bb505a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049892874 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2049892874
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1474844580
Short name T539
Test name
Test status
Simulation time 23260137 ps
CPU time 0.71 seconds
Started Aug 05 04:58:44 PM PDT 24
Finished Aug 05 04:58:45 PM PDT 24
Peak memory 198096 kb
Host smart-0777b7ac-9a26-44c9-9ff7-fbe2e09df4b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474844580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1474844580
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2735726243
Short name T544
Test name
Test status
Simulation time 15092565 ps
CPU time 0.62 seconds
Started Aug 05 04:58:59 PM PDT 24
Finished Aug 05 04:58:59 PM PDT 24
Peak memory 195076 kb
Host smart-3c065809-fe97-46a0-8f32-9216852db76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735726243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2735726243
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.4273854647
Short name T561
Test name
Test status
Simulation time 21039321 ps
CPU time 1.04 seconds
Started Aug 05 04:58:46 PM PDT 24
Finished Aug 05 04:58:47 PM PDT 24
Peak memory 198796 kb
Host smart-ad950751-773f-4de7-aa73-e1a06dc68fb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273854647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.4273854647
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2762652950
Short name T583
Test name
Test status
Simulation time 62018964 ps
CPU time 1.45 seconds
Started Aug 05 04:58:40 PM PDT 24
Finished Aug 05 04:58:42 PM PDT 24
Peak memory 200208 kb
Host smart-191768b3-0a69-4647-aaf7-0f1d380f2359
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762652950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2762652950
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.124311303
Short name T66
Test name
Test status
Simulation time 1288483422 ps
CPU time 1.89 seconds
Started Aug 05 04:58:33 PM PDT 24
Finished Aug 05 04:58:35 PM PDT 24
Peak memory 200176 kb
Host smart-a8642626-220a-42c8-ba79-23575790f9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124311303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.124311303
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2193007731
Short name T538
Test name
Test status
Simulation time 19979171 ps
CPU time 0.58 seconds
Started Aug 05 04:59:04 PM PDT 24
Finished Aug 05 04:59:05 PM PDT 24
Peak memory 195056 kb
Host smart-9b61b2c4-1c86-4380-a19f-eb462e1314f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193007731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2193007731
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.958246238
Short name T587
Test name
Test status
Simulation time 25626520 ps
CPU time 0.57 seconds
Started Aug 05 04:59:18 PM PDT 24
Finished Aug 05 04:59:18 PM PDT 24
Peak memory 195092 kb
Host smart-7e4d021c-f032-48e7-9024-57d2eff75795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958246238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.958246238
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3818216392
Short name T599
Test name
Test status
Simulation time 82434333 ps
CPU time 0.63 seconds
Started Aug 05 04:59:02 PM PDT 24
Finished Aug 05 04:59:03 PM PDT 24
Peak memory 195120 kb
Host smart-4f78beab-4524-44f9-9323-e0cdd01e84ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818216392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3818216392
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1322998393
Short name T534
Test name
Test status
Simulation time 14307492 ps
CPU time 0.59 seconds
Started Aug 05 04:59:11 PM PDT 24
Finished Aug 05 04:59:12 PM PDT 24
Peak memory 194972 kb
Host smart-eb496a6d-27e3-43f0-b982-ba81f078debb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322998393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1322998393
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3070870846
Short name T565
Test name
Test status
Simulation time 21284119 ps
CPU time 0.57 seconds
Started Aug 05 04:59:03 PM PDT 24
Finished Aug 05 04:59:03 PM PDT 24
Peak memory 195064 kb
Host smart-49f27cdf-7443-410a-97e2-52875bb58d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070870846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3070870846
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.864817072
Short name T634
Test name
Test status
Simulation time 12732134 ps
CPU time 0.6 seconds
Started Aug 05 04:59:04 PM PDT 24
Finished Aug 05 04:59:05 PM PDT 24
Peak memory 195212 kb
Host smart-71917049-0b8d-4353-8284-ff514a2a4683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864817072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.864817072
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1653023173
Short name T535
Test name
Test status
Simulation time 30237408 ps
CPU time 0.65 seconds
Started Aug 05 04:59:05 PM PDT 24
Finished Aug 05 04:59:09 PM PDT 24
Peak memory 194984 kb
Host smart-186f06b5-361f-4417-8c79-acb876b70e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653023173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1653023173
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3998729274
Short name T602
Test name
Test status
Simulation time 27355097 ps
CPU time 0.57 seconds
Started Aug 05 04:59:10 PM PDT 24
Finished Aug 05 04:59:11 PM PDT 24
Peak memory 194972 kb
Host smart-b90c6ab5-65bc-45ca-bf91-0639b99acee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998729274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3998729274
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2201833424
Short name T597
Test name
Test status
Simulation time 16153338 ps
CPU time 0.59 seconds
Started Aug 05 04:59:16 PM PDT 24
Finished Aug 05 04:59:17 PM PDT 24
Peak memory 195024 kb
Host smart-cae8c52e-7483-49f1-9c7f-f355253abb1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201833424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2201833424
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2622747141
Short name T558
Test name
Test status
Simulation time 101542138 ps
CPU time 0.58 seconds
Started Aug 05 04:59:13 PM PDT 24
Finished Aug 05 04:59:13 PM PDT 24
Peak memory 195068 kb
Host smart-2724f7a3-858c-4b58-8b5f-a43f9db9c9b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622747141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2622747141
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.45990839
Short name T622
Test name
Test status
Simulation time 334224676 ps
CPU time 3.21 seconds
Started Aug 05 04:58:47 PM PDT 24
Finished Aug 05 04:58:50 PM PDT 24
Peak memory 200024 kb
Host smart-2457581a-dd00-440a-9575-267361b35987
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45990839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.45990839
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.327351006
Short name T570
Test name
Test status
Simulation time 114793484 ps
CPU time 5.01 seconds
Started Aug 05 04:58:51 PM PDT 24
Finished Aug 05 04:58:56 PM PDT 24
Peak memory 198712 kb
Host smart-2949de0a-08bf-4439-b8de-d08d3b8aa6b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327351006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.327351006
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1211429682
Short name T103
Test name
Test status
Simulation time 137434604 ps
CPU time 0.98 seconds
Started Aug 05 04:58:39 PM PDT 24
Finished Aug 05 04:58:40 PM PDT 24
Peak memory 198940 kb
Host smart-04862f0a-366e-44a7-b68a-ef17d8b8b6f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211429682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1211429682
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.309280007
Short name T585
Test name
Test status
Simulation time 387521891 ps
CPU time 2.78 seconds
Started Aug 05 04:58:54 PM PDT 24
Finished Aug 05 04:58:57 PM PDT 24
Peak memory 208648 kb
Host smart-305b9267-49c9-4b5b-b4b9-caa5a069f5a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309280007 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.309280007
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3708251895
Short name T95
Test name
Test status
Simulation time 14642169 ps
CPU time 0.79 seconds
Started Aug 05 04:58:45 PM PDT 24
Finished Aug 05 04:58:46 PM PDT 24
Peak memory 199588 kb
Host smart-1d5d0de2-051d-4a7d-b9c8-1642adf8dd2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708251895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3708251895
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2602283881
Short name T616
Test name
Test status
Simulation time 17092080 ps
CPU time 0.59 seconds
Started Aug 05 04:58:42 PM PDT 24
Finished Aug 05 04:58:43 PM PDT 24
Peak memory 195060 kb
Host smart-a20e88a8-f8dd-4c4b-93bc-b41baea6fe6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602283881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2602283881
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1980626672
Short name T110
Test name
Test status
Simulation time 434485619 ps
CPU time 1.84 seconds
Started Aug 05 04:58:39 PM PDT 24
Finished Aug 05 04:58:41 PM PDT 24
Peak memory 199512 kb
Host smart-6b294835-5045-4bc9-a9e4-2fb7a3bd22af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980626672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1980626672
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1725788603
Short name T540
Test name
Test status
Simulation time 297380528 ps
CPU time 2.7 seconds
Started Aug 05 04:58:43 PM PDT 24
Finished Aug 05 04:58:45 PM PDT 24
Peak memory 200220 kb
Host smart-2915b6a0-2d57-45f2-a1f3-416955fc6701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725788603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1725788603
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.780280546
Short name T125
Test name
Test status
Simulation time 101327204 ps
CPU time 1.62 seconds
Started Aug 05 04:58:49 PM PDT 24
Finished Aug 05 04:58:51 PM PDT 24
Peak memory 200188 kb
Host smart-f7a91fd4-efed-436f-bda6-e03c2dacadfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780280546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.780280546
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2214818062
Short name T531
Test name
Test status
Simulation time 13800802 ps
CPU time 0.59 seconds
Started Aug 05 04:59:03 PM PDT 24
Finished Aug 05 04:59:09 PM PDT 24
Peak memory 194968 kb
Host smart-99f165d6-e73e-4c63-95f2-21a20eec05c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214818062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2214818062
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1369764525
Short name T559
Test name
Test status
Simulation time 31064240 ps
CPU time 0.56 seconds
Started Aug 05 04:59:21 PM PDT 24
Finished Aug 05 04:59:22 PM PDT 24
Peak memory 195016 kb
Host smart-0f2dd5fd-12cd-4a33-a638-9b9a3a92b10e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369764525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1369764525
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1560766319
Short name T620
Test name
Test status
Simulation time 17044550 ps
CPU time 0.69 seconds
Started Aug 05 04:59:11 PM PDT 24
Finished Aug 05 04:59:11 PM PDT 24
Peak memory 195044 kb
Host smart-0206f812-f974-4cad-aba9-de2ca628a9b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560766319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1560766319
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1672511559
Short name T591
Test name
Test status
Simulation time 13657817 ps
CPU time 0.61 seconds
Started Aug 05 04:59:14 PM PDT 24
Finished Aug 05 04:59:14 PM PDT 24
Peak memory 194992 kb
Host smart-bd1f0b40-6846-4e45-8527-b2b47a00b2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672511559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1672511559
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2780433100
Short name T610
Test name
Test status
Simulation time 14393947 ps
CPU time 0.58 seconds
Started Aug 05 04:59:06 PM PDT 24
Finished Aug 05 04:59:07 PM PDT 24
Peak memory 194948 kb
Host smart-caa3f69b-ccd1-4fc6-a6c7-b51d772e02a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780433100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2780433100
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.4064291004
Short name T656
Test name
Test status
Simulation time 33739295 ps
CPU time 0.58 seconds
Started Aug 05 04:59:28 PM PDT 24
Finished Aug 05 04:59:28 PM PDT 24
Peak memory 195100 kb
Host smart-5e8cb9e8-314c-4a2b-bf10-80ed21e4f450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064291004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.4064291004
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3897339497
Short name T627
Test name
Test status
Simulation time 41680294 ps
CPU time 0.55 seconds
Started Aug 05 04:59:23 PM PDT 24
Finished Aug 05 04:59:24 PM PDT 24
Peak memory 194956 kb
Host smart-c3ce9d83-b826-4d5d-9a8d-70c6581f95dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897339497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3897339497
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1650494253
Short name T579
Test name
Test status
Simulation time 11755279 ps
CPU time 0.58 seconds
Started Aug 05 04:59:12 PM PDT 24
Finished Aug 05 04:59:13 PM PDT 24
Peak memory 194952 kb
Host smart-fed7624f-0920-4398-893d-abb3926a3103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650494253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1650494253
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2237805714
Short name T537
Test name
Test status
Simulation time 26685594 ps
CPU time 0.56 seconds
Started Aug 05 04:59:22 PM PDT 24
Finished Aug 05 04:59:23 PM PDT 24
Peak memory 195040 kb
Host smart-f371c28d-de60-4041-ac50-dcedae85b304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237805714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2237805714
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3065581947
Short name T548
Test name
Test status
Simulation time 13178962 ps
CPU time 0.57 seconds
Started Aug 05 04:59:10 PM PDT 24
Finished Aug 05 04:59:11 PM PDT 24
Peak memory 195060 kb
Host smart-834c19fe-85b6-4314-9859-f5b8922a2f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065581947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3065581947
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1192957253
Short name T101
Test name
Test status
Simulation time 401427751 ps
CPU time 5.39 seconds
Started Aug 05 04:58:46 PM PDT 24
Finished Aug 05 04:58:51 PM PDT 24
Peak memory 199328 kb
Host smart-a36d6594-6a92-40e3-963a-f17084fe9fb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192957253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1192957253
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4002742107
Short name T573
Test name
Test status
Simulation time 3888449271 ps
CPU time 10.56 seconds
Started Aug 05 04:58:52 PM PDT 24
Finished Aug 05 04:59:03 PM PDT 24
Peak memory 200272 kb
Host smart-f9192e31-d7e9-4898-a355-2397fef1d10f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002742107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4002742107
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.875915268
Short name T532
Test name
Test status
Simulation time 42596409 ps
CPU time 0.77 seconds
Started Aug 05 04:58:43 PM PDT 24
Finished Aug 05 04:58:44 PM PDT 24
Peak memory 198352 kb
Host smart-e911095a-4d93-4635-afb6-c3143f62ae3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875915268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.875915268
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.705090128
Short name T614
Test name
Test status
Simulation time 38441307 ps
CPU time 1.31 seconds
Started Aug 05 04:58:42 PM PDT 24
Finished Aug 05 04:58:44 PM PDT 24
Peak memory 200088 kb
Host smart-abe89d39-cd28-4b99-9799-70c10f20bc23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705090128 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.705090128
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2319932066
Short name T637
Test name
Test status
Simulation time 116654381 ps
CPU time 0.94 seconds
Started Aug 05 04:59:03 PM PDT 24
Finished Aug 05 04:59:04 PM PDT 24
Peak memory 199892 kb
Host smart-4be2f110-7606-49b5-8108-c0b007b7ceae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319932066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2319932066
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3747974552
Short name T595
Test name
Test status
Simulation time 36416778 ps
CPU time 0.54 seconds
Started Aug 05 04:58:30 PM PDT 24
Finished Aug 05 04:58:30 PM PDT 24
Peak memory 195036 kb
Host smart-8edd5566-2f57-40d7-b4c8-8d21dba605d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747974552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3747974552
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2340769646
Short name T112
Test name
Test status
Simulation time 40668355 ps
CPU time 1.55 seconds
Started Aug 05 04:58:41 PM PDT 24
Finished Aug 05 04:58:43 PM PDT 24
Peak memory 199884 kb
Host smart-7fc39c4e-48c3-4e03-bcfb-10d544b1817f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340769646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2340769646
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.58165871
Short name T643
Test name
Test status
Simulation time 2227632459 ps
CPU time 2.74 seconds
Started Aug 05 04:58:42 PM PDT 24
Finished Aug 05 04:58:45 PM PDT 24
Peak memory 200332 kb
Host smart-1c39579e-bf2c-453d-9474-5ed990fa3378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58165871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.58165871
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3235753360
Short name T123
Test name
Test status
Simulation time 130759755 ps
CPU time 4.19 seconds
Started Aug 05 04:58:44 PM PDT 24
Finished Aug 05 04:58:48 PM PDT 24
Peak memory 200144 kb
Host smart-2c01d44c-37be-419f-828b-1dd8ba139fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235753360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3235753360
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.4243327337
Short name T600
Test name
Test status
Simulation time 15365108 ps
CPU time 0.57 seconds
Started Aug 05 04:59:22 PM PDT 24
Finished Aug 05 04:59:22 PM PDT 24
Peak memory 195060 kb
Host smart-d4cd68f7-c4ea-4764-86d6-cf1a231a90b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243327337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4243327337
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.285134056
Short name T567
Test name
Test status
Simulation time 58185056 ps
CPU time 0.65 seconds
Started Aug 05 04:59:04 PM PDT 24
Finished Aug 05 04:59:05 PM PDT 24
Peak memory 195112 kb
Host smart-f96e3c37-a656-4355-a9c3-f34fcef5a68c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285134056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.285134056
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1269444577
Short name T632
Test name
Test status
Simulation time 44462049 ps
CPU time 0.6 seconds
Started Aug 05 04:59:04 PM PDT 24
Finished Aug 05 04:59:04 PM PDT 24
Peak memory 195188 kb
Host smart-857d6619-6491-4a9a-a97b-8dd2b39a34a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269444577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1269444577
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1513449883
Short name T592
Test name
Test status
Simulation time 26401622 ps
CPU time 0.61 seconds
Started Aug 05 04:59:29 PM PDT 24
Finished Aug 05 04:59:30 PM PDT 24
Peak memory 195108 kb
Host smart-122d4c82-bafe-4ba3-b2ed-de03518ea8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513449883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1513449883
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.520494107
Short name T647
Test name
Test status
Simulation time 51368392 ps
CPU time 0.55 seconds
Started Aug 05 04:59:27 PM PDT 24
Finished Aug 05 04:59:27 PM PDT 24
Peak memory 195040 kb
Host smart-bab1b123-4201-4ffc-a81c-83030b8c2ab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520494107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.520494107
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1612462582
Short name T545
Test name
Test status
Simulation time 15836842 ps
CPU time 0.63 seconds
Started Aug 05 04:59:27 PM PDT 24
Finished Aug 05 04:59:27 PM PDT 24
Peak memory 195012 kb
Host smart-47d1f4c7-8839-4894-b76b-2c7aaaf86669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612462582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1612462582
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3302855594
Short name T562
Test name
Test status
Simulation time 17386288 ps
CPU time 0.58 seconds
Started Aug 05 04:59:34 PM PDT 24
Finished Aug 05 04:59:35 PM PDT 24
Peak memory 195004 kb
Host smart-97a2e857-7e79-4e46-9ff2-fb3e3a15abba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302855594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3302855594
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3245331976
Short name T642
Test name
Test status
Simulation time 41294141 ps
CPU time 0.62 seconds
Started Aug 05 04:59:16 PM PDT 24
Finished Aug 05 04:59:17 PM PDT 24
Peak memory 195076 kb
Host smart-593be84f-eae5-467e-a2fc-72befd9c38c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245331976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3245331976
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1006348034
Short name T568
Test name
Test status
Simulation time 49517226 ps
CPU time 0.59 seconds
Started Aug 05 04:59:37 PM PDT 24
Finished Aug 05 04:59:38 PM PDT 24
Peak memory 195104 kb
Host smart-cb587a54-c670-4671-ae95-1123e692dea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006348034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1006348034
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1563952766
Short name T578
Test name
Test status
Simulation time 45575365 ps
CPU time 0.62 seconds
Started Aug 05 04:59:23 PM PDT 24
Finished Aug 05 04:59:24 PM PDT 24
Peak memory 195060 kb
Host smart-ece62352-1fdd-485b-905c-35cb9e9690f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563952766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1563952766
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1135906508
Short name T649
Test name
Test status
Simulation time 154998773 ps
CPU time 2.53 seconds
Started Aug 05 04:58:50 PM PDT 24
Finished Aug 05 04:58:52 PM PDT 24
Peak memory 200212 kb
Host smart-bf7a73ef-506a-450e-8609-c3e9409d565f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135906508 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1135906508
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.505949631
Short name T105
Test name
Test status
Simulation time 50976621 ps
CPU time 0.79 seconds
Started Aug 05 04:59:09 PM PDT 24
Finished Aug 05 04:59:10 PM PDT 24
Peak memory 199936 kb
Host smart-35ffa794-3296-4a1f-a4e7-5378ac7ab6bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505949631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.505949631
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3912634393
Short name T589
Test name
Test status
Simulation time 55979985 ps
CPU time 0.62 seconds
Started Aug 05 04:59:05 PM PDT 24
Finished Aug 05 04:59:06 PM PDT 24
Peak memory 195088 kb
Host smart-8f99350b-04bf-4cc3-8641-3a796c18e2fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912634393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3912634393
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3504167355
Short name T109
Test name
Test status
Simulation time 167176009 ps
CPU time 2.17 seconds
Started Aug 05 04:58:57 PM PDT 24
Finished Aug 05 04:58:59 PM PDT 24
Peak memory 200128 kb
Host smart-7e843ff5-856c-4439-a3da-95d3fab44567
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504167355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3504167355
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.704424086
Short name T550
Test name
Test status
Simulation time 223469129 ps
CPU time 2.89 seconds
Started Aug 05 04:58:51 PM PDT 24
Finished Aug 05 04:58:54 PM PDT 24
Peak memory 200120 kb
Host smart-6acea08d-8d72-4113-aa6a-00288a032ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704424086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.704424086
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2979126733
Short name T65
Test name
Test status
Simulation time 163188615 ps
CPU time 1.89 seconds
Started Aug 05 04:58:47 PM PDT 24
Finished Aug 05 04:58:49 PM PDT 24
Peak memory 200136 kb
Host smart-80a57990-da16-42f6-a54f-534746bac026
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979126733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2979126733
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1401998725
Short name T581
Test name
Test status
Simulation time 93178678 ps
CPU time 2.39 seconds
Started Aug 05 04:58:47 PM PDT 24
Finished Aug 05 04:58:50 PM PDT 24
Peak memory 200168 kb
Host smart-186cfffa-2790-40ca-9204-041813bef15a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401998725 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1401998725
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3287525075
Short name T104
Test name
Test status
Simulation time 62454088 ps
CPU time 0.7 seconds
Started Aug 05 04:58:43 PM PDT 24
Finished Aug 05 04:58:44 PM PDT 24
Peak memory 198228 kb
Host smart-4eac1cb0-35d3-4607-83f1-0d03bca89b18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287525075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3287525075
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3742295734
Short name T613
Test name
Test status
Simulation time 30957734 ps
CPU time 0.58 seconds
Started Aug 05 04:58:49 PM PDT 24
Finished Aug 05 04:58:50 PM PDT 24
Peak memory 195020 kb
Host smart-778178d3-e257-48d9-a12c-286ee3f7b9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742295734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3742295734
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3316364700
Short name T596
Test name
Test status
Simulation time 48370725 ps
CPU time 1.25 seconds
Started Aug 05 04:58:41 PM PDT 24
Finished Aug 05 04:58:43 PM PDT 24
Peak memory 200032 kb
Host smart-7d5fc0e9-6dc5-43e9-a1dd-52f4fbb16f11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316364700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3316364700
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3135497917
Short name T546
Test name
Test status
Simulation time 60904994 ps
CPU time 1.73 seconds
Started Aug 05 04:58:42 PM PDT 24
Finished Aug 05 04:58:44 PM PDT 24
Peak memory 200244 kb
Host smart-5625ab64-6484-4e40-9882-bfe02101716d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135497917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3135497917
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3712470160
Short name T126
Test name
Test status
Simulation time 356638561 ps
CPU time 4.17 seconds
Started Aug 05 04:58:42 PM PDT 24
Finished Aug 05 04:58:46 PM PDT 24
Peak memory 200136 kb
Host smart-0524d4b2-fa87-46bb-920f-759cb2e8685b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712470160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3712470160
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3067332719
Short name T536
Test name
Test status
Simulation time 22692738292 ps
CPU time 52.94 seconds
Started Aug 05 04:58:54 PM PDT 24
Finished Aug 05 04:59:47 PM PDT 24
Peak memory 215884 kb
Host smart-ebbf2fbc-f07c-459f-803c-8fed2f0b0880
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067332719 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3067332719
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1912827824
Short name T625
Test name
Test status
Simulation time 46380457 ps
CPU time 0.7 seconds
Started Aug 05 04:58:47 PM PDT 24
Finished Aug 05 04:58:48 PM PDT 24
Peak memory 198228 kb
Host smart-4f6b98bd-056a-4f19-9c71-932949d8f494
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912827824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1912827824
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3701966987
Short name T572
Test name
Test status
Simulation time 37018905 ps
CPU time 0.61 seconds
Started Aug 05 04:58:41 PM PDT 24
Finished Aug 05 04:58:42 PM PDT 24
Peak memory 195076 kb
Host smart-d8dbdd9c-7b02-41f4-ba65-ae223a837dbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701966987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3701966987
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3215861286
Short name T626
Test name
Test status
Simulation time 438763375 ps
CPU time 1.66 seconds
Started Aug 05 04:58:41 PM PDT 24
Finished Aug 05 04:58:43 PM PDT 24
Peak memory 200152 kb
Host smart-637ef886-f561-49d0-8061-91be9b6d7f80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215861286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3215861286
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.82454153
Short name T580
Test name
Test status
Simulation time 717735902 ps
CPU time 3.79 seconds
Started Aug 05 04:58:49 PM PDT 24
Finished Aug 05 04:58:53 PM PDT 24
Peak memory 200160 kb
Host smart-f6be50a0-2b0e-43d9-be08-752799b6b3f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82454153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.82454153
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1415461684
Short name T122
Test name
Test status
Simulation time 171660756 ps
CPU time 1.7 seconds
Started Aug 05 04:58:39 PM PDT 24
Finished Aug 05 04:58:41 PM PDT 24
Peak memory 200168 kb
Host smart-201989d5-5840-42be-a082-f2c0a92c4c43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415461684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1415461684
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.698394373
Short name T551
Test name
Test status
Simulation time 43106498 ps
CPU time 1.15 seconds
Started Aug 05 04:58:49 PM PDT 24
Finished Aug 05 04:58:50 PM PDT 24
Peak memory 199948 kb
Host smart-e6a8f884-b9da-4592-944b-d0fee3c1c56d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698394373 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.698394373
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4045830511
Short name T594
Test name
Test status
Simulation time 31830132 ps
CPU time 0.96 seconds
Started Aug 05 04:58:58 PM PDT 24
Finished Aug 05 04:58:59 PM PDT 24
Peak memory 199576 kb
Host smart-d3984963-f419-489b-ac2a-75d7bb182f9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045830511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.4045830511
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1349581598
Short name T655
Test name
Test status
Simulation time 40638340 ps
CPU time 0.66 seconds
Started Aug 05 04:58:51 PM PDT 24
Finished Aug 05 04:58:51 PM PDT 24
Peak memory 195076 kb
Host smart-46e1f7d8-375c-4399-810b-fb22e75eaedd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349581598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1349581598
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3205217733
Short name T588
Test name
Test status
Simulation time 404820959 ps
CPU time 1.85 seconds
Started Aug 05 04:58:47 PM PDT 24
Finished Aug 05 04:58:49 PM PDT 24
Peak memory 200124 kb
Host smart-3cc263a9-1996-442f-b4cf-f55e53f09c4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205217733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3205217733
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2991213978
Short name T618
Test name
Test status
Simulation time 206942342 ps
CPU time 3.94 seconds
Started Aug 05 04:58:42 PM PDT 24
Finished Aug 05 04:58:46 PM PDT 24
Peak memory 200228 kb
Host smart-7b2717a1-99ec-41d1-b89d-b1d513ce4b56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991213978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2991213978
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2622931598
Short name T633
Test name
Test status
Simulation time 904024163 ps
CPU time 1.83 seconds
Started Aug 05 04:58:36 PM PDT 24
Finished Aug 05 04:58:38 PM PDT 24
Peak memory 200052 kb
Host smart-2d9b924b-52fc-4432-848b-d60e5028b2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622931598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2622931598
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2313018874
Short name T659
Test name
Test status
Simulation time 43761256 ps
CPU time 1.37 seconds
Started Aug 05 04:58:50 PM PDT 24
Finished Aug 05 04:58:51 PM PDT 24
Peak memory 200148 kb
Host smart-9a3f6021-8249-4f0d-bcb7-52e0a3faccc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313018874 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2313018874
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3158421505
Short name T99
Test name
Test status
Simulation time 54404505 ps
CPU time 0.78 seconds
Started Aug 05 04:59:11 PM PDT 24
Finished Aug 05 04:59:12 PM PDT 24
Peak memory 199988 kb
Host smart-e7c1c737-781f-4d6c-8dc8-7141386cd1e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158421505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3158421505
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2463633130
Short name T609
Test name
Test status
Simulation time 12559082 ps
CPU time 0.58 seconds
Started Aug 05 04:59:01 PM PDT 24
Finished Aug 05 04:59:01 PM PDT 24
Peak memory 195124 kb
Host smart-cd6f0bdd-db0b-416e-be8f-14443266a9ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463633130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2463633130
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4115786981
Short name T604
Test name
Test status
Simulation time 2387292628 ps
CPU time 2.46 seconds
Started Aug 05 04:58:51 PM PDT 24
Finished Aug 05 04:58:53 PM PDT 24
Peak memory 200112 kb
Host smart-965db91f-2fb2-4968-a776-688240c9f5a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115786981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4115786981
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3100880875
Short name T553
Test name
Test status
Simulation time 1472248313 ps
CPU time 3.59 seconds
Started Aug 05 04:59:08 PM PDT 24
Finished Aug 05 04:59:11 PM PDT 24
Peak memory 200096 kb
Host smart-6eb59fd9-97d7-43f2-a3b4-cf6b31b467ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100880875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3100880875
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3052187132
Short name T494
Test name
Test status
Simulation time 10480062 ps
CPU time 0.57 seconds
Started Aug 05 05:41:35 PM PDT 24
Finished Aug 05 05:41:36 PM PDT 24
Peak memory 194876 kb
Host smart-b445fc76-7c9e-46bf-9e92-e8cce25105fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052187132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3052187132
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3444442736
Short name T457
Test name
Test status
Simulation time 1022275450 ps
CPU time 59.54 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:42:26 PM PDT 24
Peak memory 199904 kb
Host smart-e987c5ea-6397-4a5b-b9fe-df8199ce4486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444442736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3444442736
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3944456822
Short name T268
Test name
Test status
Simulation time 2512714821 ps
CPU time 45.91 seconds
Started Aug 05 05:41:33 PM PDT 24
Finished Aug 05 05:42:19 PM PDT 24
Peak memory 200056 kb
Host smart-6bd4819f-2214-4968-a163-9fb6255def75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944456822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3944456822
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1072269183
Short name T304
Test name
Test status
Simulation time 8263365241 ps
CPU time 759.87 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:54:07 PM PDT 24
Peak memory 669940 kb
Host smart-92db2a09-2d86-49b1-80d8-265e20436b7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072269183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1072269183
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.340484392
Short name T131
Test name
Test status
Simulation time 710839962 ps
CPU time 38.51 seconds
Started Aug 05 05:41:28 PM PDT 24
Finished Aug 05 05:42:06 PM PDT 24
Peak memory 199836 kb
Host smart-47f5a896-d68f-4451-9be0-ef81a7b6b7df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340484392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.340484392
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.550634143
Short name T248
Test name
Test status
Simulation time 142563664 ps
CPU time 2.54 seconds
Started Aug 05 05:41:30 PM PDT 24
Finished Aug 05 05:41:33 PM PDT 24
Peak memory 199824 kb
Host smart-4ed50a38-fd14-40f2-a9aa-c51acc29a338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550634143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.550634143
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.370271756
Short name T459
Test name
Test status
Simulation time 623575035 ps
CPU time 10.45 seconds
Started Aug 05 05:41:19 PM PDT 24
Finished Aug 05 05:41:30 PM PDT 24
Peak memory 199844 kb
Host smart-985cb623-8a7b-40e5-87d5-f7b033ab00b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370271756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.370271756
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1286643565
Short name T39
Test name
Test status
Simulation time 24689674101 ps
CPU time 4168.99 seconds
Started Aug 05 05:41:39 PM PDT 24
Finished Aug 05 06:51:09 PM PDT 24
Peak memory 878908 kb
Host smart-d01b7119-a4c2-416f-826b-0137b7af1cb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286643565 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1286643565
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2354584383
Short name T2
Test name
Test status
Simulation time 4420477353 ps
CPU time 38.21 seconds
Started Aug 05 05:41:33 PM PDT 24
Finished Aug 05 05:42:12 PM PDT 24
Peak memory 200020 kb
Host smart-01b1cc7d-0e2a-4c39-8f1e-c11c1429fcc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2354584383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2354584383
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2539228230
Short name T40
Test name
Test status
Simulation time 18401803778 ps
CPU time 55.48 seconds
Started Aug 05 05:41:21 PM PDT 24
Finished Aug 05 05:42:16 PM PDT 24
Peak memory 200016 kb
Host smart-2783918e-f2e7-4989-aee5-9f4e313be0a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2539228230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2539228230
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1578400980
Short name T329
Test name
Test status
Simulation time 7829032664 ps
CPU time 92.5 seconds
Started Aug 05 05:41:37 PM PDT 24
Finished Aug 05 05:43:10 PM PDT 24
Peak memory 199964 kb
Host smart-6e702d0d-d404-4e5e-85d0-0c7552db241b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1578400980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1578400980
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.267744826
Short name T173
Test name
Test status
Simulation time 41873558492 ps
CPU time 2270.5 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 06:19:18 PM PDT 24
Peak memory 215468 kb
Host smart-f3ac8d58-0607-45c5-87b8-a99e3a8f36c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=267744826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.267744826
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.570857266
Short name T287
Test name
Test status
Simulation time 412295492114 ps
CPU time 2565.15 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 06:24:11 PM PDT 24
Peak memory 215532 kb
Host smart-cfae6b0c-898c-450d-8ef4-2e8ebbe1787d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=570857266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.570857266
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1691307258
Short name T413
Test name
Test status
Simulation time 1340497940 ps
CPU time 24 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:41:53 PM PDT 24
Peak memory 199960 kb
Host smart-e309238b-4d6d-439c-886a-0a3b4b478695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691307258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1691307258
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3127947943
Short name T282
Test name
Test status
Simulation time 1060683646 ps
CPU time 60.95 seconds
Started Aug 05 05:41:31 PM PDT 24
Finished Aug 05 05:42:32 PM PDT 24
Peak memory 199856 kb
Host smart-25bd9115-660a-42d7-8040-f25e516edc12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3127947943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3127947943
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3410802015
Short name T333
Test name
Test status
Simulation time 651492560 ps
CPU time 8.98 seconds
Started Aug 05 05:41:33 PM PDT 24
Finished Aug 05 05:41:42 PM PDT 24
Peak memory 199992 kb
Host smart-e04b300b-4ae0-4517-ab70-6791b2737d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410802015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3410802015
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3725709856
Short name T198
Test name
Test status
Simulation time 4779744713 ps
CPU time 940.57 seconds
Started Aug 05 05:41:24 PM PDT 24
Finished Aug 05 05:57:05 PM PDT 24
Peak memory 759076 kb
Host smart-6778ea45-72d7-4fdb-bf3d-1e2df7f955da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725709856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3725709856
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1869077383
Short name T449
Test name
Test status
Simulation time 8581287781 ps
CPU time 84.92 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 05:42:52 PM PDT 24
Peak memory 199896 kb
Host smart-45314de2-8837-40a1-bac5-3ad94e3d19ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869077383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1869077383
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2145401039
Short name T263
Test name
Test status
Simulation time 10081803378 ps
CPU time 90.93 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 05:42:58 PM PDT 24
Peak memory 200084 kb
Host smart-7e263189-90b1-48d7-bfe3-b2dffebb9770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145401039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2145401039
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2465929069
Short name T60
Test name
Test status
Simulation time 57790671 ps
CPU time 0.95 seconds
Started Aug 05 05:41:38 PM PDT 24
Finished Aug 05 05:41:39 PM PDT 24
Peak memory 218496 kb
Host smart-980aff8b-93cb-43b0-95f0-e5e76d12fe66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465929069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2465929069
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3657614382
Short name T487
Test name
Test status
Simulation time 444802843 ps
CPU time 10.19 seconds
Started Aug 05 05:41:44 PM PDT 24
Finished Aug 05 05:41:54 PM PDT 24
Peak memory 199916 kb
Host smart-3591b459-734a-4d72-befe-35aa404ca95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657614382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3657614382
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3262998051
Short name T118
Test name
Test status
Simulation time 101100629056 ps
CPU time 2565.56 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 06:24:22 PM PDT 24
Peak memory 784912 kb
Host smart-be2a5082-b841-4686-9849-9047aceac076
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262998051 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3262998051
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.4098822292
Short name T72
Test name
Test status
Simulation time 186823774583 ps
CPU time 3408.88 seconds
Started Aug 05 05:41:33 PM PDT 24
Finished Aug 05 06:38:22 PM PDT 24
Peak memory 750228 kb
Host smart-c0ea5004-6f3c-4592-bc95-324bc1bff456
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098822292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.4098822292
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1241362994
Short name T227
Test name
Test status
Simulation time 4314184248 ps
CPU time 66.31 seconds
Started Aug 05 05:41:32 PM PDT 24
Finished Aug 05 05:42:38 PM PDT 24
Peak memory 200024 kb
Host smart-86e66258-adbd-4e25-9e0a-ed0da0e2468c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1241362994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1241362994
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.4232068008
Short name T188
Test name
Test status
Simulation time 2629707414 ps
CPU time 87.57 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 199992 kb
Host smart-5e88f3d6-89b1-44c8-989c-48ffe393f82c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4232068008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.4232068008
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.129043828
Short name T355
Test name
Test status
Simulation time 6047017320 ps
CPU time 78.79 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:42:45 PM PDT 24
Peak memory 200024 kb
Host smart-b141b8d6-174a-404e-aace-67c68c976ab2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=129043828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.129043828
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.182304090
Short name T440
Test name
Test status
Simulation time 38614344299 ps
CPU time 525.08 seconds
Started Aug 05 05:41:30 PM PDT 24
Finished Aug 05 05:50:15 PM PDT 24
Peak memory 200024 kb
Host smart-ff2a8666-6c08-4b98-9bec-8391cffcaaa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=182304090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.182304090
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3224521867
Short name T89
Test name
Test status
Simulation time 80464346355 ps
CPU time 2175.47 seconds
Started Aug 05 05:41:33 PM PDT 24
Finished Aug 05 06:17:49 PM PDT 24
Peak memory 215740 kb
Host smart-7c596820-17f3-4a07-9901-c2fe494abc10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3224521867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3224521867
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.413767103
Short name T258
Test name
Test status
Simulation time 618604880127 ps
CPU time 2241.63 seconds
Started Aug 05 05:41:47 PM PDT 24
Finished Aug 05 06:19:09 PM PDT 24
Peak memory 215496 kb
Host smart-e698496e-6948-4d1f-a680-a991aac018aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=413767103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.413767103
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.4040069586
Short name T297
Test name
Test status
Simulation time 678977590 ps
CPU time 20.71 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:41:50 PM PDT 24
Peak memory 199856 kb
Host smart-7f2acf70-5eb6-40d4-84dd-545da848e39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040069586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.4040069586
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1765087571
Short name T201
Test name
Test status
Simulation time 26812357 ps
CPU time 0.61 seconds
Started Aug 05 05:41:52 PM PDT 24
Finished Aug 05 05:41:53 PM PDT 24
Peak memory 195560 kb
Host smart-2b5c395d-5061-4331-9a0d-6b42c5de8a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765087571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1765087571
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.78062812
Short name T274
Test name
Test status
Simulation time 1067951836 ps
CPU time 60.93 seconds
Started Aug 05 05:41:47 PM PDT 24
Finished Aug 05 05:42:48 PM PDT 24
Peak memory 200080 kb
Host smart-843be5c1-96ba-4415-ae98-a301c220c69f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78062812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.78062812
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1441390994
Short name T141
Test name
Test status
Simulation time 1633969894 ps
CPU time 21.43 seconds
Started Aug 05 05:41:56 PM PDT 24
Finished Aug 05 05:42:18 PM PDT 24
Peak memory 199884 kb
Host smart-81162d28-a3dc-4542-8e23-228f5b43914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441390994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1441390994
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2436583006
Short name T213
Test name
Test status
Simulation time 1172715880 ps
CPU time 213.36 seconds
Started Aug 05 05:41:54 PM PDT 24
Finished Aug 05 05:45:28 PM PDT 24
Peak memory 623984 kb
Host smart-ff323792-814b-4f1c-9a4f-fafaf4cadfe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436583006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2436583006
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.659311476
Short name T183
Test name
Test status
Simulation time 2726591378 ps
CPU time 163.24 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:44:47 PM PDT 24
Peak memory 200068 kb
Host smart-ebfe93fc-a0f0-4e0a-ac31-41b36cf17878
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659311476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.659311476
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.4191978450
Short name T68
Test name
Test status
Simulation time 3999812476 ps
CPU time 115.41 seconds
Started Aug 05 05:41:51 PM PDT 24
Finished Aug 05 05:43:46 PM PDT 24
Peak memory 200084 kb
Host smart-743faf32-99b6-4140-8755-7a3e946f64e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191978450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.4191978450
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.274162879
Short name T478
Test name
Test status
Simulation time 580514806 ps
CPU time 9.83 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:42:13 PM PDT 24
Peak memory 199908 kb
Host smart-8d56a061-ed4e-4914-95ba-0dbfdab9c7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274162879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.274162879
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1337609684
Short name T151
Test name
Test status
Simulation time 247345007873 ps
CPU time 619.99 seconds
Started Aug 05 05:41:54 PM PDT 24
Finished Aug 05 05:52:14 PM PDT 24
Peak memory 200012 kb
Host smart-0f485d8e-5020-4ab1-b656-4aca665b7d52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337609684 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1337609684
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.903287302
Short name T479
Test name
Test status
Simulation time 2011744479 ps
CPU time 86.26 seconds
Started Aug 05 05:42:00 PM PDT 24
Finished Aug 05 05:43:27 PM PDT 24
Peak memory 199892 kb
Host smart-f0573cae-44be-40bb-aa4a-e1cbc6deb172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903287302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.903287302
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1085685994
Short name T385
Test name
Test status
Simulation time 22569344 ps
CPU time 0.61 seconds
Started Aug 05 05:41:53 PM PDT 24
Finished Aug 05 05:41:54 PM PDT 24
Peak memory 195956 kb
Host smart-a681d1fc-f520-47e8-abb5-8ec45d85d957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085685994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1085685994
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2916603269
Short name T273
Test name
Test status
Simulation time 902317532 ps
CPU time 51.89 seconds
Started Aug 05 05:41:51 PM PDT 24
Finished Aug 05 05:42:43 PM PDT 24
Peak memory 199948 kb
Host smart-1116c692-6b1a-4c8d-8e04-091a515e73b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916603269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2916603269
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3322846502
Short name T521
Test name
Test status
Simulation time 287422428 ps
CPU time 6.76 seconds
Started Aug 05 05:41:51 PM PDT 24
Finished Aug 05 05:41:58 PM PDT 24
Peak memory 199884 kb
Host smart-9ae84516-44f2-46e1-a1d4-53736a8b199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322846502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3322846502
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3453958876
Short name T420
Test name
Test status
Simulation time 1847299825 ps
CPU time 377.89 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:48:16 PM PDT 24
Peak memory 670984 kb
Host smart-b1be1e1d-ca16-4c08-9c9b-1174c73dcc0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453958876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3453958876
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.483064322
Short name T308
Test name
Test status
Simulation time 18388377132 ps
CPU time 157.79 seconds
Started Aug 05 05:41:51 PM PDT 24
Finished Aug 05 05:44:29 PM PDT 24
Peak memory 200064 kb
Host smart-9510b052-fdf7-41f3-9f4b-a40f97e41da1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483064322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.483064322
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3702619215
Short name T277
Test name
Test status
Simulation time 131053713626 ps
CPU time 117.1 seconds
Started Aug 05 05:41:50 PM PDT 24
Finished Aug 05 05:43:47 PM PDT 24
Peak memory 200348 kb
Host smart-e46633dc-d2fa-4db1-bc52-459a8a6e069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702619215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3702619215
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3252552926
Short name T246
Test name
Test status
Simulation time 239252308 ps
CPU time 10.26 seconds
Started Aug 05 05:41:59 PM PDT 24
Finished Aug 05 05:42:09 PM PDT 24
Peak memory 199988 kb
Host smart-763735c9-7671-43f6-935a-3e2ddfcb6b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252552926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3252552926
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1778618144
Short name T431
Test name
Test status
Simulation time 66564047585 ps
CPU time 1293.93 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 06:03:36 PM PDT 24
Peak memory 740508 kb
Host smart-602ce6e1-36eb-458b-a80d-25d3de77ee5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778618144 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1778618144
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.251160366
Short name T28
Test name
Test status
Simulation time 19320747537 ps
CPU time 84.2 seconds
Started Aug 05 05:41:46 PM PDT 24
Finished Aug 05 05:43:10 PM PDT 24
Peak memory 199976 kb
Host smart-c3bdcadc-18fb-491e-9b5a-daf4b48bee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251160366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.251160366
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2868262579
Short name T249
Test name
Test status
Simulation time 178791979 ps
CPU time 0.62 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 05:42:02 PM PDT 24
Peak memory 195536 kb
Host smart-bdabfae2-f62d-4bb4-9755-adfdcfb33bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868262579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2868262579
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1076794358
Short name T368
Test name
Test status
Simulation time 7298410911 ps
CPU time 69.73 seconds
Started Aug 05 05:41:51 PM PDT 24
Finished Aug 05 05:43:01 PM PDT 24
Peak memory 200016 kb
Host smart-09c6c4ec-0814-4817-88a3-a638c8b70d3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1076794358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1076794358
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.52854576
Short name T43
Test name
Test status
Simulation time 39491779136 ps
CPU time 997.79 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:58:36 PM PDT 24
Peak memory 747492 kb
Host smart-81fdf16c-587c-4a1e-a7fe-21d50d9adb29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52854576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.52854576
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.442014808
Short name T171
Test name
Test status
Simulation time 46834718345 ps
CPU time 195.74 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:45:14 PM PDT 24
Peak memory 200032 kb
Host smart-64ceb885-7834-4683-a822-f5b663d81d2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442014808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.442014808
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1788409029
Short name T219
Test name
Test status
Simulation time 10993555125 ps
CPU time 153.79 seconds
Started Aug 05 05:41:52 PM PDT 24
Finished Aug 05 05:44:26 PM PDT 24
Peak memory 208172 kb
Host smart-f4d77491-37ae-4eb4-9a6c-eaeb9088609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788409029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1788409029
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.4276204005
Short name T209
Test name
Test status
Simulation time 979701349 ps
CPU time 4.78 seconds
Started Aug 05 05:41:50 PM PDT 24
Finished Aug 05 05:41:55 PM PDT 24
Peak memory 199936 kb
Host smart-30c16f8d-7d7c-4cf1-80d7-5cd391b2775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276204005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4276204005
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2260546030
Short name T359
Test name
Test status
Simulation time 23496798112 ps
CPU time 2759.45 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 06:28:03 PM PDT 24
Peak memory 767788 kb
Host smart-572c885b-465e-4a0d-8ddd-93fe8fcf24cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260546030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2260546030
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.949128160
Short name T330
Test name
Test status
Simulation time 13640998910 ps
CPU time 10.3 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:42:09 PM PDT 24
Peak memory 199972 kb
Host smart-36c9ecbe-1df6-472c-abc6-6db4e3f721c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949128160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.949128160
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3521159302
Short name T247
Test name
Test status
Simulation time 29840794 ps
CPU time 0.6 seconds
Started Aug 05 05:41:56 PM PDT 24
Finished Aug 05 05:41:56 PM PDT 24
Peak memory 194840 kb
Host smart-69b03e63-a619-48bb-ac34-9ac0b27eee82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521159302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3521159302
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.4246283352
Short name T27
Test name
Test status
Simulation time 478201343 ps
CPU time 12.98 seconds
Started Aug 05 05:41:56 PM PDT 24
Finished Aug 05 05:42:09 PM PDT 24
Peak memory 199932 kb
Host smart-535c32f0-5960-4fdd-a00a-6c6d97925647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246283352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.4246283352
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.569507763
Short name T523
Test name
Test status
Simulation time 3984564459 ps
CPU time 28.82 seconds
Started Aug 05 05:41:57 PM PDT 24
Finished Aug 05 05:42:26 PM PDT 24
Peak memory 200044 kb
Host smart-38a6efb3-23fa-42fd-a2b1-17782ada58e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569507763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.569507763
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2524475400
Short name T406
Test name
Test status
Simulation time 30278704786 ps
CPU time 983.89 seconds
Started Aug 05 05:41:56 PM PDT 24
Finished Aug 05 05:58:20 PM PDT 24
Peak memory 743388 kb
Host smart-3c813b20-986c-464d-8543-7a55fbe85cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524475400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2524475400
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.76078686
Short name T75
Test name
Test status
Simulation time 12364646830 ps
CPU time 79.33 seconds
Started Aug 05 05:41:53 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 199992 kb
Host smart-f7d22ed4-c30e-4bd1-ba10-35af638dbb96
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76078686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.76078686
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3461522804
Short name T229
Test name
Test status
Simulation time 6357433299 ps
CPU time 81.77 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:43:20 PM PDT 24
Peak memory 200080 kb
Host smart-a57d5d59-78dc-46e7-8419-727cd1dacb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461522804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3461522804
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2951578199
Short name T388
Test name
Test status
Simulation time 587958944 ps
CPU time 8.02 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:42:06 PM PDT 24
Peak memory 199912 kb
Host smart-64d92724-1eae-47f6-8266-cc153e9a6841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951578199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2951578199
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.582062587
Short name T50
Test name
Test status
Simulation time 14007605600 ps
CPU time 1326.6 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 06:04:05 PM PDT 24
Peak memory 735216 kb
Host smart-e930c23e-fb19-4aee-8cb6-0fe59abea954
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582062587 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.582062587
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3027251909
Short name T473
Test name
Test status
Simulation time 2219443453 ps
CPU time 40.67 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 05:42:42 PM PDT 24
Peak memory 199960 kb
Host smart-da37d89d-03ec-4df9-9b81-8f1c3e6ec5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027251909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3027251909
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3431349849
Short name T205
Test name
Test status
Simulation time 50087430 ps
CPU time 0.63 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:41:59 PM PDT 24
Peak memory 195960 kb
Host smart-50b17d3d-97e7-4161-8d78-52d205ceb4ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431349849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3431349849
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2440115307
Short name T314
Test name
Test status
Simulation time 1207840591 ps
CPU time 68.39 seconds
Started Aug 05 05:41:57 PM PDT 24
Finished Aug 05 05:43:06 PM PDT 24
Peak memory 199872 kb
Host smart-07a03a09-3479-4ddd-8198-182191cb32e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440115307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2440115307
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.702326914
Short name T169
Test name
Test status
Simulation time 230579261 ps
CPU time 13.24 seconds
Started Aug 05 05:41:59 PM PDT 24
Finished Aug 05 05:42:12 PM PDT 24
Peak memory 199892 kb
Host smart-f19e7a71-f49f-4658-86d1-cc81b44758dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702326914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.702326914
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4182082917
Short name T348
Test name
Test status
Simulation time 868921816 ps
CPU time 142.49 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 05:44:24 PM PDT 24
Peak memory 576884 kb
Host smart-a34b6f0f-a027-4ee9-a0f0-22a911e213d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182082917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4182082917
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.161066810
Short name T346
Test name
Test status
Simulation time 8046511220 ps
CPU time 99.7 seconds
Started Aug 05 05:42:02 PM PDT 24
Finished Aug 05 05:43:42 PM PDT 24
Peak memory 199996 kb
Host smart-abec7f6e-66c2-4e37-a877-c47560490663
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161066810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.161066810
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1589489385
Short name T404
Test name
Test status
Simulation time 55288787512 ps
CPU time 200.31 seconds
Started Aug 05 05:41:51 PM PDT 24
Finished Aug 05 05:45:11 PM PDT 24
Peak memory 216328 kb
Host smart-7bae12a9-721e-4067-9878-2c894bb47f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589489385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1589489385
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3483760051
Short name T528
Test name
Test status
Simulation time 1176819047 ps
CPU time 13.56 seconds
Started Aug 05 05:41:57 PM PDT 24
Finished Aug 05 05:42:11 PM PDT 24
Peak memory 199908 kb
Host smart-c9a04430-8578-44d4-97ca-078e010a445b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483760051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3483760051
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3656032958
Short name T85
Test name
Test status
Simulation time 54530235887 ps
CPU time 187.67 seconds
Started Aug 05 05:42:02 PM PDT 24
Finished Aug 05 05:45:10 PM PDT 24
Peak memory 199956 kb
Host smart-16cf7bf6-b1eb-425c-9605-7ec67d434261
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656032958 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3656032958
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1421721124
Short name T223
Test name
Test status
Simulation time 1205280453 ps
CPU time 64.38 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:42:52 PM PDT 24
Peak memory 199896 kb
Host smart-6a4dbed8-5a48-4772-8181-dec6609a3a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421721124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1421721124
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.79844877
Short name T290
Test name
Test status
Simulation time 14025892 ps
CPU time 0.61 seconds
Started Aug 05 05:42:00 PM PDT 24
Finished Aug 05 05:42:01 PM PDT 24
Peak memory 194956 kb
Host smart-7447a4af-9201-4d02-9f25-4c31921febe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79844877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.79844877
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1441021726
Short name T144
Test name
Test status
Simulation time 797576528 ps
CPU time 11.96 seconds
Started Aug 05 05:41:54 PM PDT 24
Finished Aug 05 05:42:06 PM PDT 24
Peak memory 199892 kb
Host smart-a3e4f648-919c-4e4e-93bd-87031c4ad09c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1441021726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1441021726
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1326226003
Short name T475
Test name
Test status
Simulation time 6320492347 ps
CPU time 24.9 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 05:42:26 PM PDT 24
Peak memory 199980 kb
Host smart-978bcb07-9682-47b7-96b6-a0ff2c0d8ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326226003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1326226003
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3876967110
Short name T149
Test name
Test status
Simulation time 11904646382 ps
CPU time 496.64 seconds
Started Aug 05 05:41:56 PM PDT 24
Finished Aug 05 05:50:12 PM PDT 24
Peak memory 675248 kb
Host smart-afb134a7-0089-4136-bae4-3eaba7de9dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876967110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3876967110
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.4255231331
Short name T63
Test name
Test status
Simulation time 1321883198 ps
CPU time 77.62 seconds
Started Aug 05 05:42:00 PM PDT 24
Finished Aug 05 05:43:18 PM PDT 24
Peak memory 199848 kb
Host smart-59ea5014-d1e5-4700-9387-1ef6768e0010
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255231331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.4255231331
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3343219180
Short name T321
Test name
Test status
Simulation time 15406166616 ps
CPU time 86.64 seconds
Started Aug 05 05:41:59 PM PDT 24
Finished Aug 05 05:43:26 PM PDT 24
Peak memory 200064 kb
Host smart-cdae7751-f2d0-48e0-9530-899c66580e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343219180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3343219180
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2273638598
Short name T264
Test name
Test status
Simulation time 3530667504 ps
CPU time 6.95 seconds
Started Aug 05 05:42:02 PM PDT 24
Finished Aug 05 05:42:09 PM PDT 24
Peak memory 200056 kb
Host smart-73562ba2-8b1a-4ee3-baa3-c12bf499aca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273638598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2273638598
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2166142608
Short name T383
Test name
Test status
Simulation time 9059953740 ps
CPU time 478.05 seconds
Started Aug 05 05:41:59 PM PDT 24
Finished Aug 05 05:49:57 PM PDT 24
Peak memory 200084 kb
Host smart-80800924-d301-4303-b9a1-31c97365fc15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166142608 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2166142608
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1830019875
Short name T33
Test name
Test status
Simulation time 9486925116 ps
CPU time 118.74 seconds
Started Aug 05 05:41:57 PM PDT 24
Finished Aug 05 05:43:56 PM PDT 24
Peak memory 200000 kb
Host smart-b3acc77a-f3a0-4bd4-94c1-58c27226b558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830019875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1830019875
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3614512134
Short name T456
Test name
Test status
Simulation time 17313509 ps
CPU time 0.59 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 05:42:01 PM PDT 24
Peak memory 195960 kb
Host smart-87831093-c667-44ba-9ffb-479f072e1174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614512134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3614512134
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2958489821
Short name T255
Test name
Test status
Simulation time 1356320039 ps
CPU time 76.9 seconds
Started Aug 05 05:41:57 PM PDT 24
Finished Aug 05 05:43:14 PM PDT 24
Peak memory 199840 kb
Host smart-9caf629e-fe95-46eb-8d4e-c610f5b4ff9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958489821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2958489821
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.632430561
Short name T294
Test name
Test status
Simulation time 5110838490 ps
CPU time 66.28 seconds
Started Aug 05 05:42:00 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 200004 kb
Host smart-cbf9f8c6-124a-4bb2-997c-590fcc5e9c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632430561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.632430561
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2340665086
Short name T477
Test name
Test status
Simulation time 9520778974 ps
CPU time 397.47 seconds
Started Aug 05 05:41:50 PM PDT 24
Finished Aug 05 05:48:27 PM PDT 24
Peak memory 455352 kb
Host smart-3bbf8414-786b-40aa-aadf-2f3791f599d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340665086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2340665086
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2574312644
Short name T266
Test name
Test status
Simulation time 4625965725 ps
CPU time 18.5 seconds
Started Aug 05 05:42:06 PM PDT 24
Finished Aug 05 05:42:24 PM PDT 24
Peak memory 199980 kb
Host smart-d0d6f65e-7187-4089-92c5-11880422ef4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574312644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2574312644
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2017066890
Short name T427
Test name
Test status
Simulation time 2664248551 ps
CPU time 45.82 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:42:49 PM PDT 24
Peak memory 200028 kb
Host smart-ace5d806-5eeb-48cb-890a-0225e822285a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017066890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2017066890
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1749154558
Short name T233
Test name
Test status
Simulation time 384754612 ps
CPU time 7.18 seconds
Started Aug 05 05:42:00 PM PDT 24
Finished Aug 05 05:42:08 PM PDT 24
Peak memory 199912 kb
Host smart-a0b7e86b-ee35-4331-a1dd-73f45ecbee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749154558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1749154558
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2125818781
Short name T46
Test name
Test status
Simulation time 18029541008 ps
CPU time 1711.26 seconds
Started Aug 05 05:41:57 PM PDT 24
Finished Aug 05 06:10:29 PM PDT 24
Peak memory 764484 kb
Host smart-5ff062c6-5df6-4063-806b-b66ee91bd5b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125818781 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2125818781
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3555469364
Short name T293
Test name
Test status
Simulation time 10181795668 ps
CPU time 41.14 seconds
Started Aug 05 05:42:02 PM PDT 24
Finished Aug 05 05:42:43 PM PDT 24
Peak memory 200036 kb
Host smart-c6acfdef-426d-4b20-b3bd-7ffecdab43ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555469364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3555469364
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2277187468
Short name T145
Test name
Test status
Simulation time 13449157 ps
CPU time 0.58 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 05:42:02 PM PDT 24
Peak memory 195588 kb
Host smart-c581b2aa-35e8-4bf4-a764-5f4992631245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277187468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2277187468
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.585189457
Short name T225
Test name
Test status
Simulation time 3719849887 ps
CPU time 101.26 seconds
Started Aug 05 05:42:02 PM PDT 24
Finished Aug 05 05:43:43 PM PDT 24
Peak memory 199988 kb
Host smart-005110ff-c10b-4e81-9bef-b6f4fea50cf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585189457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.585189457
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2903500797
Short name T79
Test name
Test status
Simulation time 1348897816 ps
CPU time 19.89 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:42:24 PM PDT 24
Peak memory 199888 kb
Host smart-01c7853b-9a7d-49ac-b6c0-e503aad99a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903500797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2903500797
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2145430914
Short name T339
Test name
Test status
Simulation time 15052446518 ps
CPU time 1758.35 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 06:11:21 PM PDT 24
Peak memory 802848 kb
Host smart-7b54f084-bd59-4466-939b-8b47af6f0e9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145430914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2145430914
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1560015712
Short name T41
Test name
Test status
Simulation time 9271827165 ps
CPU time 111.5 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:43:55 PM PDT 24
Peak memory 200088 kb
Host smart-921583c4-2da3-411a-86ad-b6285a749a9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560015712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1560015712
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1126224536
Short name T316
Test name
Test status
Simulation time 1022583291 ps
CPU time 15.07 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:20 PM PDT 24
Peak memory 199916 kb
Host smart-8c8546ed-c5d1-403b-a77a-dd1661c10015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126224536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1126224536
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2633285586
Short name T283
Test name
Test status
Simulation time 271512967 ps
CPU time 12.87 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:42:17 PM PDT 24
Peak memory 199892 kb
Host smart-73701721-8267-4455-a332-f37f25ba33ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633285586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2633285586
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.4211299392
Short name T401
Test name
Test status
Simulation time 52905261428 ps
CPU time 3951.32 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 06:47:57 PM PDT 24
Peak memory 802128 kb
Host smart-e7a4e125-b22c-42d9-9ec8-7c5042cc4d4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211299392 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.4211299392
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3756091101
Short name T474
Test name
Test status
Simulation time 34611229428 ps
CPU time 111.64 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:43:56 PM PDT 24
Peak memory 200036 kb
Host smart-c4b9437b-ee82-4e4e-a088-f154656000c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756091101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3756091101
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1775103874
Short name T513
Test name
Test status
Simulation time 43685077 ps
CPU time 0.56 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:42:03 PM PDT 24
Peak memory 194912 kb
Host smart-060d1267-a093-481e-b750-ea935b94fcde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775103874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1775103874
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1469759102
Short name T336
Test name
Test status
Simulation time 1358031985 ps
CPU time 39.42 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:42:46 PM PDT 24
Peak memory 199848 kb
Host smart-9f079684-68d2-4bfb-9c4a-668e873262d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469759102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1469759102
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2093620395
Short name T45
Test name
Test status
Simulation time 1229073697 ps
CPU time 11.94 seconds
Started Aug 05 05:42:08 PM PDT 24
Finished Aug 05 05:42:20 PM PDT 24
Peak memory 199820 kb
Host smart-ba6ef1d1-ff9f-4a73-b6e8-65d6b067091b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093620395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2093620395
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3682091139
Short name T91
Test name
Test status
Simulation time 4067198523 ps
CPU time 645.24 seconds
Started Aug 05 05:42:00 PM PDT 24
Finished Aug 05 05:52:46 PM PDT 24
Peak memory 676280 kb
Host smart-71c095f7-6f94-4c68-83ca-298343cb7939
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682091139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3682091139
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3874760037
Short name T454
Test name
Test status
Simulation time 19828547181 ps
CPU time 237.3 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:46:02 PM PDT 24
Peak memory 199976 kb
Host smart-dde56fa6-1e45-4e4c-a17b-2dc35bd2401e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874760037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3874760037
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1854421323
Short name T74
Test name
Test status
Simulation time 4157479038 ps
CPU time 36.95 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:42:41 PM PDT 24
Peak memory 199948 kb
Host smart-da49a69b-b06c-4944-87b5-fc50f85a4881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854421323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1854421323
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.4052488141
Short name T530
Test name
Test status
Simulation time 136048605 ps
CPU time 2.68 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:42:06 PM PDT 24
Peak memory 199852 kb
Host smart-39c05fbe-f459-447c-aff2-c6a4f7da58ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052488141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.4052488141
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2320401847
Short name T344
Test name
Test status
Simulation time 351285196807 ps
CPU time 2851.89 seconds
Started Aug 05 05:42:08 PM PDT 24
Finished Aug 05 06:29:40 PM PDT 24
Peak memory 774192 kb
Host smart-2b99b663-3174-431f-abae-e1bbd9eb293b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320401847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2320401847
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3514673594
Short name T76
Test name
Test status
Simulation time 474708362 ps
CPU time 6.17 seconds
Started Aug 05 05:42:09 PM PDT 24
Finished Aug 05 05:42:15 PM PDT 24
Peak memory 199796 kb
Host smart-ce888183-aced-40a2-ba6d-3f58d2860696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514673594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3514673594
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3644242096
Short name T514
Test name
Test status
Simulation time 40937374 ps
CPU time 0.6 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:13 PM PDT 24
Peak memory 194932 kb
Host smart-29164619-81d0-4011-b973-8e21c1e80ff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644242096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3644242096
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.4116892367
Short name T471
Test name
Test status
Simulation time 7957281097 ps
CPU time 81.76 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 200028 kb
Host smart-ed082af4-8bbf-4d74-a125-61da78dd79ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116892367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4116892367
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.4235315106
Short name T357
Test name
Test status
Simulation time 2965347894 ps
CPU time 40.45 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:46 PM PDT 24
Peak memory 199992 kb
Host smart-cbd2d5d6-b3a2-4cb9-afb7-ad391f3f7be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235315106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.4235315106
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.461604451
Short name T135
Test name
Test status
Simulation time 13178397768 ps
CPU time 434.47 seconds
Started Aug 05 05:42:09 PM PDT 24
Finished Aug 05 05:49:24 PM PDT 24
Peak memory 479336 kb
Host smart-4e898dd9-95d6-4918-a798-9fbecc92dfd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461604451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.461604451
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1741006286
Short name T394
Test name
Test status
Simulation time 3141321595 ps
CPU time 42.97 seconds
Started Aug 05 05:42:06 PM PDT 24
Finished Aug 05 05:42:49 PM PDT 24
Peak memory 199952 kb
Host smart-9ccc8bbd-8ef1-4178-8d86-2c84d89b7d39
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741006286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1741006286
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1800019938
Short name T12
Test name
Test status
Simulation time 1617540168 ps
CPU time 14.88 seconds
Started Aug 05 05:42:10 PM PDT 24
Finished Aug 05 05:42:25 PM PDT 24
Peak memory 199888 kb
Host smart-4b91eb3e-37c5-4f58-b4d5-5c8ee187d646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800019938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1800019938
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3472556459
Short name T460
Test name
Test status
Simulation time 765104487 ps
CPU time 12.85 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:18 PM PDT 24
Peak memory 199880 kb
Host smart-c61661d0-67ff-4acd-abf2-e6b2cd546522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472556459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3472556459
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1189411326
Short name T493
Test name
Test status
Simulation time 39621806758 ps
CPU time 697.09 seconds
Started Aug 05 05:42:11 PM PDT 24
Finished Aug 05 05:53:49 PM PDT 24
Peak memory 208228 kb
Host smart-e559ee94-d4a2-4c28-8471-a44468475d47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189411326 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1189411326
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1256766455
Short name T510
Test name
Test status
Simulation time 6507890270 ps
CPU time 20.77 seconds
Started Aug 05 05:42:09 PM PDT 24
Finished Aug 05 05:42:30 PM PDT 24
Peak memory 199980 kb
Host smart-d2bf580e-6707-4667-9b4e-1e2935d69316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256766455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1256766455
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1418265285
Short name T500
Test name
Test status
Simulation time 84368952 ps
CPU time 0.61 seconds
Started Aug 05 05:41:40 PM PDT 24
Finished Aug 05 05:41:41 PM PDT 24
Peak memory 195924 kb
Host smart-6b7a0710-3050-4cb2-969c-4fdc53d95a28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418265285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1418265285
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3396600545
Short name T265
Test name
Test status
Simulation time 2427084502 ps
CPU time 66.62 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:43:05 PM PDT 24
Peak memory 199980 kb
Host smart-5588a7f4-59e8-4faf-977b-3b07a54c4c3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3396600545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3396600545
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3645231584
Short name T526
Test name
Test status
Simulation time 5904993367 ps
CPU time 25.92 seconds
Started Aug 05 05:41:42 PM PDT 24
Finished Aug 05 05:42:08 PM PDT 24
Peak memory 199980 kb
Host smart-a5005d12-5f06-4dea-9576-cd2d2cb6292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645231584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3645231584
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1780185644
Short name T337
Test name
Test status
Simulation time 6459500229 ps
CPU time 354.82 seconds
Started Aug 05 05:41:27 PM PDT 24
Finished Aug 05 05:47:22 PM PDT 24
Peak memory 674776 kb
Host smart-5dcc44fd-c29d-4d66-83d0-af154573e5ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780185644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1780185644
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2174050705
Short name T482
Test name
Test status
Simulation time 3803018950 ps
CPU time 43.96 seconds
Started Aug 05 05:41:35 PM PDT 24
Finished Aug 05 05:42:19 PM PDT 24
Peak memory 199960 kb
Host smart-3ddd3189-77c0-400a-ae0a-ced5c48c90b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174050705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2174050705
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.429622990
Short name T315
Test name
Test status
Simulation time 31447547584 ps
CPU time 36.27 seconds
Started Aug 05 05:41:34 PM PDT 24
Finished Aug 05 05:42:11 PM PDT 24
Peak memory 200064 kb
Host smart-cb5b625e-05c3-480f-9146-993e5aaaddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429622990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.429622990
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.991435094
Short name T58
Test name
Test status
Simulation time 36993062 ps
CPU time 0.83 seconds
Started Aug 05 05:41:26 PM PDT 24
Finished Aug 05 05:41:27 PM PDT 24
Peak memory 218560 kb
Host smart-f5ccf677-bd84-4a2a-9fca-3d4eb3002427
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991435094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.991435094
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3727753150
Short name T187
Test name
Test status
Simulation time 395162484 ps
CPU time 4.92 seconds
Started Aug 05 05:41:25 PM PDT 24
Finished Aug 05 05:41:31 PM PDT 24
Peak memory 199964 kb
Host smart-efdcef7c-b691-43e9-82ac-1af3c55e1bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727753150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3727753150
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3631624439
Short name T520
Test name
Test status
Simulation time 64264796119 ps
CPU time 872.52 seconds
Started Aug 05 05:41:51 PM PDT 24
Finished Aug 05 05:56:23 PM PDT 24
Peak memory 199968 kb
Host smart-d8d45771-664c-4d78-a1cd-176a9982ddbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631624439 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3631624439
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.957313708
Short name T70
Test name
Test status
Simulation time 294151516897 ps
CPU time 2236.79 seconds
Started Aug 05 05:41:43 PM PDT 24
Finished Aug 05 06:19:01 PM PDT 24
Peak memory 761540 kb
Host smart-c524e380-0b29-4dbc-9edc-a1c4d79dc62a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957313708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.957313708
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1982010498
Short name T306
Test name
Test status
Simulation time 6962658623 ps
CPU time 66.44 seconds
Started Aug 05 05:41:50 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 200072 kb
Host smart-31ed32c1-7c7d-43e6-a135-c01e93e737f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1982010498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1982010498
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1501176859
Short name T6
Test name
Test status
Simulation time 13517832034 ps
CPU time 61.1 seconds
Started Aug 05 05:41:30 PM PDT 24
Finished Aug 05 05:42:31 PM PDT 24
Peak memory 200028 kb
Host smart-2c7a5b36-bf3e-42ef-808e-40205ac4f072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1501176859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1501176859
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1442537659
Short name T166
Test name
Test status
Simulation time 11269445229 ps
CPU time 87.51 seconds
Started Aug 05 05:41:40 PM PDT 24
Finished Aug 05 05:43:08 PM PDT 24
Peak memory 200072 kb
Host smart-98747eaa-7d0d-4331-87b7-a62ffc01271f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1442537659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1442537659
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3201961824
Short name T230
Test name
Test status
Simulation time 109036332546 ps
CPU time 718.09 seconds
Started Aug 05 05:41:36 PM PDT 24
Finished Aug 05 05:53:34 PM PDT 24
Peak memory 200032 kb
Host smart-f5937d0c-778f-48e6-85bb-6935d5355da9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3201961824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3201961824
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2797856216
Short name T445
Test name
Test status
Simulation time 137605705731 ps
CPU time 2369.45 seconds
Started Aug 05 05:41:41 PM PDT 24
Finished Aug 05 06:21:11 PM PDT 24
Peak memory 216048 kb
Host smart-3201efe9-7d38-4ac3-9303-a70dc3141348
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2797856216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2797856216
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.875464752
Short name T184
Test name
Test status
Simulation time 569957946264 ps
CPU time 2456.14 seconds
Started Aug 05 05:41:42 PM PDT 24
Finished Aug 05 06:22:38 PM PDT 24
Peak memory 216392 kb
Host smart-3ac71a16-c30a-4dfd-9e10-df5f375db9f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=875464752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.875464752
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2797157153
Short name T465
Test name
Test status
Simulation time 15246368146 ps
CPU time 71.29 seconds
Started Aug 05 05:41:45 PM PDT 24
Finished Aug 05 05:42:57 PM PDT 24
Peak memory 200048 kb
Host smart-28bb7fe5-dce0-43f0-ba63-14247e91daaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797157153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2797157153
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3090872713
Short name T410
Test name
Test status
Simulation time 24775743 ps
CPU time 0.59 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:06 PM PDT 24
Peak memory 194956 kb
Host smart-431d0377-60e6-47c0-bed3-1da542de433c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090872713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3090872713
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.480579162
Short name T190
Test name
Test status
Simulation time 4930822160 ps
CPU time 92.67 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:43:36 PM PDT 24
Peak memory 216356 kb
Host smart-9114ee32-5577-4976-a553-bee2398ed73b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480579162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.480579162
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1096654914
Short name T160
Test name
Test status
Simulation time 1029556469 ps
CPU time 168.05 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:44:52 PM PDT 24
Peak memory 454988 kb
Host smart-c2681400-1920-493a-8579-4c1f60126f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096654914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1096654914
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1342183253
Short name T164
Test name
Test status
Simulation time 562466648 ps
CPU time 7.91 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:21 PM PDT 24
Peak memory 199876 kb
Host smart-4b55ec77-0d21-42ac-9ec0-c56109d58c05
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342183253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1342183253
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1648318463
Short name T458
Test name
Test status
Simulation time 10168999229 ps
CPU time 142.18 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:44:28 PM PDT 24
Peak memory 208168 kb
Host smart-110533e7-821d-4ba6-af91-70cef0de5f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648318463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1648318463
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.973420768
Short name T335
Test name
Test status
Simulation time 200498695 ps
CPU time 8.28 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:42:11 PM PDT 24
Peak memory 199924 kb
Host smart-405df73d-c253-4a40-9193-c460db115585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973420768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.973420768
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1817769783
Short name T407
Test name
Test status
Simulation time 19328473156 ps
CPU time 613.84 seconds
Started Aug 05 05:42:08 PM PDT 24
Finished Aug 05 05:52:22 PM PDT 24
Peak memory 626732 kb
Host smart-3420426a-38f7-4251-a700-79cd4348ef76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817769783 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1817769783
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.943950260
Short name T93
Test name
Test status
Simulation time 1924407515 ps
CPU time 92.67 seconds
Started Aug 05 05:42:06 PM PDT 24
Finished Aug 05 05:43:39 PM PDT 24
Peak memory 199832 kb
Host smart-6f381569-3301-4458-bc8c-4990dc5b5c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943950260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.943950260
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3904939822
Short name T450
Test name
Test status
Simulation time 23275169 ps
CPU time 0.57 seconds
Started Aug 05 05:42:11 PM PDT 24
Finished Aug 05 05:42:11 PM PDT 24
Peak memory 195688 kb
Host smart-2baa15ad-25df-46e0-a7a0-644f8224678a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904939822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3904939822
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1972733418
Short name T446
Test name
Test status
Simulation time 2447463544 ps
CPU time 12.69 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:42:16 PM PDT 24
Peak memory 200016 kb
Host smart-cc078f59-9162-49aa-9841-5f8706cd1dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972733418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1972733418
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1525966710
Short name T511
Test name
Test status
Simulation time 453206444 ps
CPU time 24.6 seconds
Started Aug 05 05:42:08 PM PDT 24
Finished Aug 05 05:42:33 PM PDT 24
Peak memory 199948 kb
Host smart-e2674784-84d6-424e-8232-2aca64da4f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525966710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1525966710
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.61698450
Short name T238
Test name
Test status
Simulation time 1497479751 ps
CPU time 304 seconds
Started Aug 05 05:42:16 PM PDT 24
Finished Aug 05 05:47:21 PM PDT 24
Peak memory 610864 kb
Host smart-70801b13-5af9-490e-bbc2-b0e31c506e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61698450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.61698450
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3821558399
Short name T239
Test name
Test status
Simulation time 543872521 ps
CPU time 30.31 seconds
Started Aug 05 05:42:02 PM PDT 24
Finished Aug 05 05:42:33 PM PDT 24
Peak memory 199864 kb
Host smart-2361cfbd-708a-4f9b-bc28-e900e25def5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821558399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3821558399
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1430407885
Short name T153
Test name
Test status
Simulation time 10761762918 ps
CPU time 107.96 seconds
Started Aug 05 05:42:06 PM PDT 24
Finished Aug 05 05:43:55 PM PDT 24
Peak memory 200036 kb
Host smart-e595d325-c477-4040-8958-3956eb8746c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430407885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1430407885
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.527796315
Short name T504
Test name
Test status
Simulation time 77707346 ps
CPU time 1.65 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:42:06 PM PDT 24
Peak memory 199912 kb
Host smart-1a7554b4-3dfa-49b3-857b-625321434977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527796315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.527796315
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1590839047
Short name T138
Test name
Test status
Simulation time 6608219026 ps
CPU time 346.29 seconds
Started Aug 05 05:42:15 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 200040 kb
Host smart-7b1ad09b-1031-4b1e-981c-1fb81873c2b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590839047 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1590839047
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2612598206
Short name T397
Test name
Test status
Simulation time 10478938844 ps
CPU time 128.24 seconds
Started Aug 05 05:42:00 PM PDT 24
Finished Aug 05 05:44:08 PM PDT 24
Peak memory 200048 kb
Host smart-6fb5fa4d-f5d1-43fa-b1ef-1578458f800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612598206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2612598206
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1480691251
Short name T489
Test name
Test status
Simulation time 71055630 ps
CPU time 0.59 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 05:42:02 PM PDT 24
Peak memory 195960 kb
Host smart-3d67afea-0b4e-4b24-9600-c3843f87f30d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480691251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1480691251
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.4192321359
Short name T378
Test name
Test status
Simulation time 788048989 ps
CPU time 45.99 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:51 PM PDT 24
Peak memory 199884 kb
Host smart-6d79f194-2ca9-4a87-ab90-42286243ad3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4192321359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.4192321359
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2929627089
Short name T307
Test name
Test status
Simulation time 5948860616 ps
CPU time 52.82 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:42:57 PM PDT 24
Peak memory 200060 kb
Host smart-451415d9-758d-4663-893c-29b046dcf632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929627089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2929627089
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3650926749
Short name T214
Test name
Test status
Simulation time 22828313 ps
CPU time 1 seconds
Started Aug 05 05:42:09 PM PDT 24
Finished Aug 05 05:42:10 PM PDT 24
Peak memory 199856 kb
Host smart-cfd522fa-b214-4a9b-aa83-0c14619d36f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650926749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3650926749
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.316130251
Short name T447
Test name
Test status
Simulation time 2880144508 ps
CPU time 158.8 seconds
Started Aug 05 05:42:06 PM PDT 24
Finished Aug 05 05:44:45 PM PDT 24
Peak memory 199988 kb
Host smart-ade443fe-23cc-49ef-b3dd-d5bc8c67c150
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316130251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.316130251
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1254234586
Short name T165
Test name
Test status
Simulation time 51230546863 ps
CPU time 72.37 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:43:16 PM PDT 24
Peak memory 200000 kb
Host smart-dcb6d1c6-46ea-4a7f-b3c4-86fc56a65d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254234586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1254234586
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.4118154097
Short name T216
Test name
Test status
Simulation time 280581440 ps
CPU time 4.13 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:42:07 PM PDT 24
Peak memory 199852 kb
Host smart-6c93ef55-eb55-4724-8364-a7fd0cec5f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118154097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.4118154097
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2942009170
Short name T116
Test name
Test status
Simulation time 73798067852 ps
CPU time 1846.94 seconds
Started Aug 05 05:42:02 PM PDT 24
Finished Aug 05 06:12:50 PM PDT 24
Peak memory 703504 kb
Host smart-dff76eca-44ce-47f1-af09-5c387b65b341
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942009170 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2942009170
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.4228828499
Short name T240
Test name
Test status
Simulation time 11669352972 ps
CPU time 157.06 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:44:43 PM PDT 24
Peak memory 200016 kb
Host smart-e0228bb6-aaa7-475f-97ac-48ad58216c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228828499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.4228828499
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.7057341
Short name T42
Test name
Test status
Simulation time 19842366 ps
CPU time 0.6 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:42:04 PM PDT 24
Peak memory 195960 kb
Host smart-6e53dc71-ce08-41e9-bb1b-6776d6539be0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7057341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.7057341
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2716788337
Short name T363
Test name
Test status
Simulation time 2734655784 ps
CPU time 40.26 seconds
Started Aug 05 05:42:00 PM PDT 24
Finished Aug 05 05:42:41 PM PDT 24
Peak memory 199996 kb
Host smart-eeee5b21-8c37-49c4-b68a-16f136de67e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716788337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2716788337
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1964347517
Short name T48
Test name
Test status
Simulation time 1262037570 ps
CPU time 36.07 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:42:40 PM PDT 24
Peak memory 199888 kb
Host smart-7327b223-ed25-49e6-863b-0ab05442c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964347517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1964347517
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2905816492
Short name T345
Test name
Test status
Simulation time 6038179571 ps
CPU time 1144.61 seconds
Started Aug 05 05:42:11 PM PDT 24
Finished Aug 05 06:01:16 PM PDT 24
Peak memory 749432 kb
Host smart-d567e06b-bab2-4a24-aac3-de0c06099178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2905816492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2905816492
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1393016025
Short name T61
Test name
Test status
Simulation time 16533630106 ps
CPU time 90.86 seconds
Started Aug 05 05:42:08 PM PDT 24
Finished Aug 05 05:43:39 PM PDT 24
Peak memory 199920 kb
Host smart-7a514cb8-0637-4c54-9866-86fbce6695b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393016025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1393016025
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3432886813
Short name T31
Test name
Test status
Simulation time 153579595 ps
CPU time 3.1 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:42:11 PM PDT 24
Peak memory 199892 kb
Host smart-e34cba2a-0a3a-4922-8a66-a945dc285504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432886813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3432886813
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1248711048
Short name T320
Test name
Test status
Simulation time 2784999128 ps
CPU time 9.05 seconds
Started Aug 05 05:42:14 PM PDT 24
Finished Aug 05 05:42:23 PM PDT 24
Peak memory 200024 kb
Host smart-eb03509d-2177-4c64-bb8d-b3222ab7d28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248711048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1248711048
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1439198709
Short name T437
Test name
Test status
Simulation time 19115543325 ps
CPU time 2620.96 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 06:25:44 PM PDT 24
Peak memory 791616 kb
Host smart-3f3fe369-0bf8-4420-bdb2-431b6e78d8a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439198709 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1439198709
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1051752460
Short name T455
Test name
Test status
Simulation time 13531489968 ps
CPU time 28.76 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:34 PM PDT 24
Peak memory 200036 kb
Host smart-f91bf7d1-133d-412a-b88d-4b5dd89f3981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051752460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1051752460
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.712748421
Short name T371
Test name
Test status
Simulation time 23550133 ps
CPU time 0.59 seconds
Started Aug 05 05:42:15 PM PDT 24
Finished Aug 05 05:42:16 PM PDT 24
Peak memory 196544 kb
Host smart-3049512f-d635-426c-b064-6f1b54e8c69b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712748421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.712748421
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2515965971
Short name T186
Test name
Test status
Simulation time 1282196309 ps
CPU time 69.87 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 05:43:11 PM PDT 24
Peak memory 199904 kb
Host smart-df07c714-dab7-4dbf-8878-44475016b870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515965971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2515965971
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.650073702
Short name T278
Test name
Test status
Simulation time 621776178 ps
CPU time 4.63 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 05:42:06 PM PDT 24
Peak memory 200064 kb
Host smart-7b61a3d6-d14e-450b-b15b-0f12af701d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650073702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.650073702
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3277920006
Short name T353
Test name
Test status
Simulation time 19965869706 ps
CPU time 1075.05 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 06:00:02 PM PDT 24
Peak memory 754008 kb
Host smart-cc6e1c19-57c1-4224-9a62-1ac345ded2cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277920006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3277920006
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.4258080620
Short name T467
Test name
Test status
Simulation time 94126464589 ps
CPU time 287.5 seconds
Started Aug 05 05:42:06 PM PDT 24
Finished Aug 05 05:46:53 PM PDT 24
Peak memory 200008 kb
Host smart-e8b165b4-3dca-4efc-a7b1-f9384560fbf7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258080620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.4258080620
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1726090466
Short name T271
Test name
Test status
Simulation time 2572299309 ps
CPU time 34.82 seconds
Started Aug 05 05:42:15 PM PDT 24
Finished Aug 05 05:42:49 PM PDT 24
Peak memory 200000 kb
Host smart-b534c859-b787-4388-98b4-55b43836e27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726090466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1726090466
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.842509839
Short name T289
Test name
Test status
Simulation time 727938251 ps
CPU time 5.38 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:11 PM PDT 24
Peak memory 199884 kb
Host smart-99e7fbe6-2026-452d-b876-e15845adcb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842509839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.842509839
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.4210802081
Short name T400
Test name
Test status
Simulation time 35354263610 ps
CPU time 460.68 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:49:48 PM PDT 24
Peak memory 351776 kb
Host smart-d53fff7b-4ad5-4867-97b3-ac466cb27dbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210802081 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4210802081
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.4057822180
Short name T387
Test name
Test status
Simulation time 1646713169 ps
CPU time 54.44 seconds
Started Aug 05 05:42:17 PM PDT 24
Finished Aug 05 05:43:12 PM PDT 24
Peak memory 199948 kb
Host smart-fe255502-40d3-4fec-b8a5-174f13690086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057822180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.4057822180
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.406652473
Short name T260
Test name
Test status
Simulation time 19396990 ps
CPU time 0.6 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:42:04 PM PDT 24
Peak memory 195580 kb
Host smart-e486777d-6eb6-4b25-a885-290630493304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406652473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.406652473
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.4226031505
Short name T338
Test name
Test status
Simulation time 892878402 ps
CPU time 25.19 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:31 PM PDT 24
Peak memory 199860 kb
Host smart-9287d02d-dc73-4b9b-93e4-d5820515c7f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226031505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.4226031505
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1520675289
Short name T218
Test name
Test status
Simulation time 1804819151 ps
CPU time 32.53 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:42:40 PM PDT 24
Peak memory 199888 kb
Host smart-d9621777-43d5-4f61-a4a5-c8c6e822d334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520675289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1520675289
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3572010362
Short name T280
Test name
Test status
Simulation time 20671944980 ps
CPU time 843.29 seconds
Started Aug 05 05:42:01 PM PDT 24
Finished Aug 05 05:56:04 PM PDT 24
Peak memory 689612 kb
Host smart-bdd968b5-1594-499e-9dfd-8eea88a1235f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572010362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3572010362
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3354170801
Short name T242
Test name
Test status
Simulation time 4075424830 ps
CPU time 115.47 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:44:00 PM PDT 24
Peak memory 199964 kb
Host smart-8b4e2a86-1809-4564-bb11-a3eb57240660
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354170801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3354170801
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1717870008
Short name T159
Test name
Test status
Simulation time 1354226298 ps
CPU time 37.04 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:42:41 PM PDT 24
Peak memory 199904 kb
Host smart-7bc02c7e-ac4f-4127-9b39-c4af64c143b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717870008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1717870008
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.186544085
Short name T256
Test name
Test status
Simulation time 3044014927 ps
CPU time 9.49 seconds
Started Aug 05 05:42:06 PM PDT 24
Finished Aug 05 05:42:16 PM PDT 24
Peak memory 200036 kb
Host smart-c5e3eeda-8cb9-41b7-939a-9c7ad76a3ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186544085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.186544085
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1766354246
Short name T415
Test name
Test status
Simulation time 5681894342 ps
CPU time 76.81 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 199968 kb
Host smart-2f612a38-07eb-4f5c-ae7a-20544c278746
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766354246 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1766354246
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3389424306
Short name T92
Test name
Test status
Simulation time 23808159112 ps
CPU time 79.13 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:43:23 PM PDT 24
Peak memory 200056 kb
Host smart-7f276594-31e8-4b8c-bbd6-b557cf6e93a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389424306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3389424306
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1495926886
Short name T390
Test name
Test status
Simulation time 24184840 ps
CPU time 0.6 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:06 PM PDT 24
Peak memory 195960 kb
Host smart-46982373-bb1b-4974-9441-f2eddccf901f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495926886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1495926886
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.652912403
Short name T286
Test name
Test status
Simulation time 8235807618 ps
CPU time 130.59 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:44:16 PM PDT 24
Peak memory 200160 kb
Host smart-697e8eb8-e4a6-4151-85d4-908243703894
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652912403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.652912403
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2142442953
Short name T480
Test name
Test status
Simulation time 429429182 ps
CPU time 6.07 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:19 PM PDT 24
Peak memory 199800 kb
Host smart-83840c1d-91fe-467d-999a-9a717e943f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142442953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2142442953
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.497749248
Short name T317
Test name
Test status
Simulation time 9953205737 ps
CPU time 1185.04 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 06:01:50 PM PDT 24
Peak memory 675552 kb
Host smart-29ba1f5f-9b07-4c72-9124-d75b085397e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497749248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.497749248
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.4232208275
Short name T147
Test name
Test status
Simulation time 12507269727 ps
CPU time 83.07 seconds
Started Aug 05 05:42:02 PM PDT 24
Finished Aug 05 05:43:25 PM PDT 24
Peak memory 200032 kb
Host smart-1c7a7691-dcfb-4fe7-bf14-ab5b96922e2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232208275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4232208275
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1598552523
Short name T452
Test name
Test status
Simulation time 2577123616 ps
CPU time 139.25 seconds
Started Aug 05 05:42:16 PM PDT 24
Finished Aug 05 05:44:35 PM PDT 24
Peak memory 200020 kb
Host smart-e18d090d-947e-4b7f-a584-192706a85f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598552523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1598552523
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.844551413
Short name T237
Test name
Test status
Simulation time 847637930 ps
CPU time 9.92 seconds
Started Aug 05 05:42:02 PM PDT 24
Finished Aug 05 05:42:12 PM PDT 24
Peak memory 199916 kb
Host smart-c590449f-0955-43ea-ae6b-fee52b8164fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844551413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.844551413
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.487374396
Short name T517
Test name
Test status
Simulation time 170021340397 ps
CPU time 1062.5 seconds
Started Aug 05 05:42:02 PM PDT 24
Finished Aug 05 05:59:44 PM PDT 24
Peak memory 697248 kb
Host smart-3ad8ab92-e373-4a72-8894-f8114dafa265
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487374396 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.487374396
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3316168142
Short name T426
Test name
Test status
Simulation time 22116427789 ps
CPU time 19.24 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:42:27 PM PDT 24
Peak memory 199972 kb
Host smart-8460066a-c9ae-460d-b587-e772b5ac95b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316168142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3316168142
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1170573743
Short name T364
Test name
Test status
Simulation time 67942409 ps
CPU time 0.59 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:06 PM PDT 24
Peak memory 195520 kb
Host smart-df0e31de-6093-4453-81fc-d02c00f8e9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170573743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1170573743
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2612451350
Short name T435
Test name
Test status
Simulation time 2456929325 ps
CPU time 75.22 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:43:20 PM PDT 24
Peak memory 200024 kb
Host smart-af32401c-e0ce-448b-91ca-d69bfb377f48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612451350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2612451350
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.471985615
Short name T369
Test name
Test status
Simulation time 13992090695 ps
CPU time 66.72 seconds
Started Aug 05 05:42:10 PM PDT 24
Finished Aug 05 05:43:17 PM PDT 24
Peak memory 216424 kb
Host smart-6cf2ad51-e517-496d-b891-a6618f13153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471985615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.471985615
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2470246135
Short name T299
Test name
Test status
Simulation time 851514131 ps
CPU time 176.03 seconds
Started Aug 05 05:42:10 PM PDT 24
Finished Aug 05 05:45:06 PM PDT 24
Peak memory 455456 kb
Host smart-bce3c51b-1dba-4b65-b554-9bfeb6b97b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2470246135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2470246135
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.169250989
Short name T525
Test name
Test status
Simulation time 9867842580 ps
CPU time 155.06 seconds
Started Aug 05 05:42:09 PM PDT 24
Finished Aug 05 05:44:45 PM PDT 24
Peak memory 200036 kb
Host smart-b14da063-bb05-4be4-b0c7-ca97dd61d758
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169250989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.169250989
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.335337592
Short name T399
Test name
Test status
Simulation time 5771882305 ps
CPU time 109.72 seconds
Started Aug 05 05:42:12 PM PDT 24
Finished Aug 05 05:44:02 PM PDT 24
Peak memory 199976 kb
Host smart-5b8fe137-8bb2-402f-8137-0c25eeeb5f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335337592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.335337592
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.4090439420
Short name T373
Test name
Test status
Simulation time 1248764457 ps
CPU time 6.4 seconds
Started Aug 05 05:42:11 PM PDT 24
Finished Aug 05 05:42:17 PM PDT 24
Peak memory 199952 kb
Host smart-fb7a0bc9-9610-487e-bbae-7e4e773f9d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090439420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4090439420
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3946373150
Short name T172
Test name
Test status
Simulation time 94545505026 ps
CPU time 1356.79 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 06:04:42 PM PDT 24
Peak memory 765964 kb
Host smart-1e897d93-8a93-488c-be50-896dc8f60d8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946373150 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3946373150
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.434352072
Short name T295
Test name
Test status
Simulation time 4903988601 ps
CPU time 84.5 seconds
Started Aug 05 05:42:11 PM PDT 24
Finished Aug 05 05:43:35 PM PDT 24
Peak memory 200064 kb
Host smart-e8a521f2-d580-45f8-aea2-74baaf6f4be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434352072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.434352072
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2094552018
Short name T55
Test name
Test status
Simulation time 27542456 ps
CPU time 0.6 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:42:05 PM PDT 24
Peak memory 196632 kb
Host smart-f81fbba9-ed5b-42a0-956f-47cb86eace24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094552018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2094552018
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3301796363
Short name T193
Test name
Test status
Simulation time 2374196131 ps
CPU time 62.25 seconds
Started Aug 05 05:42:10 PM PDT 24
Finished Aug 05 05:43:13 PM PDT 24
Peak memory 199984 kb
Host smart-af445011-ac97-4eac-aca9-ef097a432740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301796363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3301796363
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3038141898
Short name T155
Test name
Test status
Simulation time 2599001058 ps
CPU time 45.74 seconds
Started Aug 05 05:42:06 PM PDT 24
Finished Aug 05 05:42:52 PM PDT 24
Peak memory 200100 kb
Host smart-56fb63a3-ddcc-411c-ad48-23edd3de7e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038141898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3038141898
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.525158810
Short name T392
Test name
Test status
Simulation time 3323399157 ps
CPU time 505.84 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:50:33 PM PDT 24
Peak memory 661416 kb
Host smart-56741d52-7fc5-4ee4-bfb8-7e3d58f63d12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525158810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.525158810
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1169470430
Short name T3
Test name
Test status
Simulation time 3118727632 ps
CPU time 22.31 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:35 PM PDT 24
Peak memory 199952 kb
Host smart-463249b5-ccc4-4e38-9d22-301b665a8162
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169470430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1169470430
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2638237035
Short name T262
Test name
Test status
Simulation time 37421266647 ps
CPU time 166.29 seconds
Started Aug 05 05:42:12 PM PDT 24
Finished Aug 05 05:44:58 PM PDT 24
Peak memory 200040 kb
Host smart-37d2d12c-85f5-46e6-84b1-2f1fcf33dc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638237035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2638237035
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3329682893
Short name T7
Test name
Test status
Simulation time 332965983 ps
CPU time 7.22 seconds
Started Aug 05 05:42:10 PM PDT 24
Finished Aug 05 05:42:17 PM PDT 24
Peak memory 199956 kb
Host smart-bbe87591-ef68-4db5-acc7-cbb6aa548351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329682893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3329682893
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3945199928
Short name T419
Test name
Test status
Simulation time 161970512064 ps
CPU time 111.53 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:43:56 PM PDT 24
Peak memory 200080 kb
Host smart-cefd0ee9-770e-404c-9924-096e983355bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945199928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3945199928
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1495643874
Short name T499
Test name
Test status
Simulation time 19270454 ps
CPU time 0.59 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:42:08 PM PDT 24
Peak memory 194940 kb
Host smart-8f0e9712-4eab-409f-bb75-eff449f23de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495643874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1495643874
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1319447421
Short name T323
Test name
Test status
Simulation time 6141745031 ps
CPU time 90.2 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:43:37 PM PDT 24
Peak memory 200020 kb
Host smart-46deb723-3a10-4bcf-bd37-b826808a1ef8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319447421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1319447421
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1713116055
Short name T507
Test name
Test status
Simulation time 295532509 ps
CPU time 2.73 seconds
Started Aug 05 05:42:06 PM PDT 24
Finished Aug 05 05:42:09 PM PDT 24
Peak memory 199884 kb
Host smart-eab6900e-5487-4c52-a489-f8c864493f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713116055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1713116055
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3580058212
Short name T462
Test name
Test status
Simulation time 286380637 ps
CPU time 25.39 seconds
Started Aug 05 05:42:08 PM PDT 24
Finished Aug 05 05:42:34 PM PDT 24
Peak memory 235936 kb
Host smart-21e5896d-0a96-417e-a939-1aada8c1e02d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580058212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3580058212
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.4118615069
Short name T405
Test name
Test status
Simulation time 60343337285 ps
CPU time 254.63 seconds
Started Aug 05 05:42:08 PM PDT 24
Finished Aug 05 05:46:23 PM PDT 24
Peak memory 200040 kb
Host smart-fd58368d-2465-47cc-a7f2-df5952cbe9b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118615069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.4118615069
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1703470560
Short name T167
Test name
Test status
Simulation time 21847793942 ps
CPU time 156.93 seconds
Started Aug 05 05:42:19 PM PDT 24
Finished Aug 05 05:44:56 PM PDT 24
Peak memory 199980 kb
Host smart-503aaf5c-1e37-40d7-949f-d507632367c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703470560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1703470560
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2071834374
Short name T174
Test name
Test status
Simulation time 109427030 ps
CPU time 1.8 seconds
Started Aug 05 05:42:08 PM PDT 24
Finished Aug 05 05:42:10 PM PDT 24
Peak memory 199836 kb
Host smart-3a1afad1-18ec-4b05-a488-638593ae901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071834374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2071834374
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3904280180
Short name T411
Test name
Test status
Simulation time 723757950516 ps
CPU time 4007.2 seconds
Started Aug 05 05:42:10 PM PDT 24
Finished Aug 05 06:48:58 PM PDT 24
Peak memory 876060 kb
Host smart-86186b53-51f3-4f6c-a0c6-10be5a4e2165
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904280180 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3904280180
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2314622929
Short name T429
Test name
Test status
Simulation time 2039579968 ps
CPU time 109.89 seconds
Started Aug 05 05:42:08 PM PDT 24
Finished Aug 05 05:43:58 PM PDT 24
Peak memory 199920 kb
Host smart-fce4fb9f-1bfe-4708-86e3-a6d040bf09bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314622929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2314622929
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3177749517
Short name T203
Test name
Test status
Simulation time 12148961 ps
CPU time 0.57 seconds
Started Aug 05 05:41:42 PM PDT 24
Finished Aug 05 05:41:43 PM PDT 24
Peak memory 194964 kb
Host smart-866754b6-d134-4958-8e1c-135a384968b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177749517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3177749517
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1733899192
Short name T175
Test name
Test status
Simulation time 6952381541 ps
CPU time 88.48 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:42:58 PM PDT 24
Peak memory 199988 kb
Host smart-31b1691a-8310-4f7d-a286-b866e4a55224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733899192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1733899192
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1993700478
Short name T328
Test name
Test status
Simulation time 66164896 ps
CPU time 3.58 seconds
Started Aug 05 05:41:45 PM PDT 24
Finished Aug 05 05:41:49 PM PDT 24
Peak memory 199848 kb
Host smart-42664858-2fb4-4d77-b777-68b2aff8a6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993700478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1993700478
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2471136791
Short name T192
Test name
Test status
Simulation time 5476603947 ps
CPU time 1072.78 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:59:22 PM PDT 24
Peak memory 736756 kb
Host smart-44d17506-88d1-4640-b6e2-43eba561772c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2471136791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2471136791
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.212955985
Short name T375
Test name
Test status
Simulation time 10573863312 ps
CPU time 182.26 seconds
Started Aug 05 05:41:40 PM PDT 24
Finished Aug 05 05:44:43 PM PDT 24
Peak memory 200088 kb
Host smart-aa867ec8-f5a4-4104-857c-c29c1f3c5578
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212955985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.212955985
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.382365260
Short name T30
Test name
Test status
Simulation time 22148651021 ps
CPU time 89.06 seconds
Started Aug 05 05:41:40 PM PDT 24
Finished Aug 05 05:43:09 PM PDT 24
Peak memory 200032 kb
Host smart-192f1f83-0f71-443b-a593-42aee82a1318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382365260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.382365260
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1199005349
Short name T59
Test name
Test status
Simulation time 100111114 ps
CPU time 1.06 seconds
Started Aug 05 05:41:47 PM PDT 24
Finished Aug 05 05:41:49 PM PDT 24
Peak memory 219688 kb
Host smart-45116eca-e163-4919-aa53-973ce9cd9eb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199005349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1199005349
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.4110856814
Short name T381
Test name
Test status
Simulation time 179281976 ps
CPU time 1.83 seconds
Started Aug 05 05:41:32 PM PDT 24
Finished Aug 05 05:41:34 PM PDT 24
Peak memory 199856 kb
Host smart-0c74e25a-f59b-4629-a61e-b4c6cd6f3d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110856814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.4110856814
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1778751416
Short name T370
Test name
Test status
Simulation time 15103590376 ps
CPU time 201.99 seconds
Started Aug 05 05:41:30 PM PDT 24
Finished Aug 05 05:44:52 PM PDT 24
Peak memory 208244 kb
Host smart-9ce22340-9fc5-441f-bd9f-97aed8a2e6a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778751416 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1778751416
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1785216772
Short name T71
Test name
Test status
Simulation time 312812456608 ps
CPU time 678.33 seconds
Started Aug 05 05:41:36 PM PDT 24
Finished Aug 05 05:52:54 PM PDT 24
Peak memory 339380 kb
Host smart-0d47af2f-884c-4fba-830d-2969cc23ecc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785216772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1785216772
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.4282405763
Short name T325
Test name
Test status
Simulation time 5857566673 ps
CPU time 69.1 seconds
Started Aug 05 05:41:41 PM PDT 24
Finished Aug 05 05:42:50 PM PDT 24
Peak memory 199992 kb
Host smart-4eda885f-3294-415e-920c-d220bbb41eb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4282405763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.4282405763
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.2268598825
Short name T292
Test name
Test status
Simulation time 13018729590 ps
CPU time 109.02 seconds
Started Aug 05 05:41:28 PM PDT 24
Finished Aug 05 05:43:17 PM PDT 24
Peak memory 200032 kb
Host smart-bbc0afbb-7a0a-4408-bfef-10527999010b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2268598825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2268598825
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2469754643
Short name T17
Test name
Test status
Simulation time 4714850132 ps
CPU time 82.63 seconds
Started Aug 05 05:41:31 PM PDT 24
Finished Aug 05 05:42:53 PM PDT 24
Peak memory 200024 kb
Host smart-0b87b9f7-befe-4af2-84c7-fb5b98386b2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2469754643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2469754643
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.1562029943
Short name T451
Test name
Test status
Simulation time 257119321439 ps
CPU time 643.42 seconds
Started Aug 05 05:41:31 PM PDT 24
Finished Aug 05 05:52:14 PM PDT 24
Peak memory 200040 kb
Host smart-493c27a8-5a51-4bc3-b82a-cc52f1f20eee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1562029943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1562029943
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.4204159385
Short name T395
Test name
Test status
Simulation time 40170986757 ps
CPU time 2196.21 seconds
Started Aug 05 05:41:35 PM PDT 24
Finished Aug 05 06:18:12 PM PDT 24
Peak memory 215384 kb
Host smart-105d3bad-6792-43f9-8f19-a0efb8596fe4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4204159385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.4204159385
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.4273199295
Short name T47
Test name
Test status
Simulation time 339024162901 ps
CPU time 2257.94 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 06:19:07 PM PDT 24
Peak memory 216396 kb
Host smart-85b5567e-9c0d-4c6d-896f-8cccf2e6676b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4273199295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.4273199295
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3121339889
Short name T243
Test name
Test status
Simulation time 1627715833 ps
CPU time 23.38 seconds
Started Aug 05 05:41:42 PM PDT 24
Finished Aug 05 05:42:06 PM PDT 24
Peak memory 199936 kb
Host smart-0a753b46-9dae-4c0c-b0c2-adfc41cb366c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121339889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3121339889
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3198280987
Short name T272
Test name
Test status
Simulation time 23803035 ps
CPU time 0.59 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:42:08 PM PDT 24
Peak memory 195288 kb
Host smart-544baa42-df1d-4b22-bf66-dc65e1713657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198280987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3198280987
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1859300497
Short name T476
Test name
Test status
Simulation time 1434953378 ps
CPU time 77.15 seconds
Started Aug 05 05:42:03 PM PDT 24
Finished Aug 05 05:43:21 PM PDT 24
Peak memory 199852 kb
Host smart-3dd6f51e-d0e0-48a5-9545-edd9db190a90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859300497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1859300497
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.924177921
Short name T332
Test name
Test status
Simulation time 2009224202 ps
CPU time 18.32 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:42:26 PM PDT 24
Peak memory 199896 kb
Host smart-c3f39ea6-2e82-4e1d-ae06-1b2dc5d73109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924177921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.924177921
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3461091056
Short name T226
Test name
Test status
Simulation time 1003036029 ps
CPU time 154.35 seconds
Started Aug 05 05:42:16 PM PDT 24
Finished Aug 05 05:44:51 PM PDT 24
Peak memory 608464 kb
Host smart-039ee439-13f7-42f9-a977-1d09a6fc5e8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461091056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3461091056
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2168208327
Short name T146
Test name
Test status
Simulation time 7361943354 ps
CPU time 101.54 seconds
Started Aug 05 05:42:11 PM PDT 24
Finished Aug 05 05:43:52 PM PDT 24
Peak memory 200040 kb
Host smart-b9f01dff-bc55-4482-bcfb-96ba918d7bb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168208327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2168208327
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1463629172
Short name T409
Test name
Test status
Simulation time 49209064320 ps
CPU time 182.92 seconds
Started Aug 05 05:42:16 PM PDT 24
Finished Aug 05 05:45:19 PM PDT 24
Peak memory 200032 kb
Host smart-56a7d1d6-a479-436d-9874-113f5afe7253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463629172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1463629172
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2196864942
Short name T318
Test name
Test status
Simulation time 612873486 ps
CPU time 10.81 seconds
Started Aug 05 05:42:04 PM PDT 24
Finished Aug 05 05:42:15 PM PDT 24
Peak memory 199884 kb
Host smart-6b045a99-b93d-4887-be2d-d17fcd8adec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196864942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2196864942
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.118731881
Short name T56
Test name
Test status
Simulation time 13320438623 ps
CPU time 75.04 seconds
Started Aug 05 05:42:08 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 200060 kb
Host smart-340e3b0a-20e9-4cd0-b320-6150fb60981f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118731881 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.118731881
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3496907025
Short name T207
Test name
Test status
Simulation time 2468896987 ps
CPU time 33.49 seconds
Started Aug 05 05:42:09 PM PDT 24
Finished Aug 05 05:42:42 PM PDT 24
Peak memory 200064 kb
Host smart-ca85b469-ad96-4d41-bd44-aa8725a5c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496907025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3496907025
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3470269642
Short name T382
Test name
Test status
Simulation time 41739590 ps
CPU time 0.57 seconds
Started Aug 05 05:42:18 PM PDT 24
Finished Aug 05 05:42:18 PM PDT 24
Peak memory 194944 kb
Host smart-47e7ae74-a7be-4f8a-adbe-2847f9eac56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470269642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3470269642
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3310507234
Short name T5
Test name
Test status
Simulation time 10285080858 ps
CPU time 65.84 seconds
Started Aug 05 05:42:14 PM PDT 24
Finished Aug 05 05:43:20 PM PDT 24
Peak memory 200044 kb
Host smart-c51fcc65-644b-40cb-be0b-b74203364000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310507234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3310507234
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.4242738279
Short name T324
Test name
Test status
Simulation time 122927834 ps
CPU time 6.32 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:20 PM PDT 24
Peak memory 199828 kb
Host smart-19ecb93a-d92d-4d46-b7c0-69a60ed3dcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242738279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4242738279
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3750438011
Short name T221
Test name
Test status
Simulation time 4170292699 ps
CPU time 825.65 seconds
Started Aug 05 05:42:09 PM PDT 24
Finished Aug 05 05:55:55 PM PDT 24
Peak memory 705408 kb
Host smart-651ed503-1efa-4c82-a456-590c1774e65a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750438011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3750438011
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1822021612
Short name T157
Test name
Test status
Simulation time 358863111 ps
CPU time 5.24 seconds
Started Aug 05 05:42:17 PM PDT 24
Finished Aug 05 05:42:22 PM PDT 24
Peak memory 199848 kb
Host smart-27801aac-25ae-4a00-991b-7ac11f616439
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822021612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1822021612
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2159091484
Short name T502
Test name
Test status
Simulation time 17208201290 ps
CPU time 196.28 seconds
Started Aug 05 05:42:07 PM PDT 24
Finished Aug 05 05:45:24 PM PDT 24
Peak memory 215728 kb
Host smart-8c21088f-10b7-49c9-89e4-0644b47821b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159091484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2159091484
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1713730925
Short name T206
Test name
Test status
Simulation time 492342656 ps
CPU time 6.67 seconds
Started Aug 05 05:42:05 PM PDT 24
Finished Aug 05 05:42:12 PM PDT 24
Peak memory 199876 kb
Host smart-1ea3a679-3feb-45a9-b374-9f1bad10b279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713730925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1713730925
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.506600195
Short name T139
Test name
Test status
Simulation time 15000609913 ps
CPU time 1587.97 seconds
Started Aug 05 05:42:14 PM PDT 24
Finished Aug 05 06:08:42 PM PDT 24
Peak memory 768992 kb
Host smart-c7c3bfe7-e1a0-4408-9280-6252e200d6cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506600195 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.506600195
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1144048059
Short name T402
Test name
Test status
Simulation time 1389669446 ps
CPU time 66.66 seconds
Started Aug 05 05:42:14 PM PDT 24
Finished Aug 05 05:43:21 PM PDT 24
Peak memory 199916 kb
Host smart-6abd77b6-a0fa-485a-9388-14636ed51660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144048059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1144048059
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.802243572
Short name T245
Test name
Test status
Simulation time 18463301 ps
CPU time 0.58 seconds
Started Aug 05 05:42:18 PM PDT 24
Finished Aug 05 05:42:19 PM PDT 24
Peak memory 194956 kb
Host smart-d54b1398-266f-48e0-bd9a-8fd5a425a13e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802243572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.802243572
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1703212087
Short name T251
Test name
Test status
Simulation time 746741216 ps
CPU time 47.7 seconds
Started Aug 05 05:42:20 PM PDT 24
Finished Aug 05 05:43:08 PM PDT 24
Peak memory 199956 kb
Host smart-ac2d0c0d-028f-43dd-96ae-135fd645e3fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703212087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1703212087
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1486894655
Short name T64
Test name
Test status
Simulation time 175265381 ps
CPU time 2.95 seconds
Started Aug 05 05:42:19 PM PDT 24
Finished Aug 05 05:42:22 PM PDT 24
Peak memory 199908 kb
Host smart-cfad97e3-3079-445d-874c-bbcceeeae81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486894655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1486894655
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1905492857
Short name T505
Test name
Test status
Simulation time 25576737957 ps
CPU time 451.29 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:49:45 PM PDT 24
Peak memory 487860 kb
Host smart-dca4973f-efd3-4b5e-8c8f-9770f40ea638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1905492857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1905492857
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1572235777
Short name T77
Test name
Test status
Simulation time 41835263580 ps
CPU time 85.55 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:43:38 PM PDT 24
Peak memory 200068 kb
Host smart-3450400f-4800-46c9-a85c-a42cc3ccb0df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572235777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1572235777
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3995632108
Short name T386
Test name
Test status
Simulation time 8817562961 ps
CPU time 115.84 seconds
Started Aug 05 05:42:15 PM PDT 24
Finished Aug 05 05:44:11 PM PDT 24
Peak memory 200040 kb
Host smart-ee871295-3d6b-4d1a-b190-669660620180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995632108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3995632108
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2430746567
Short name T53
Test name
Test status
Simulation time 4945647476 ps
CPU time 14.54 seconds
Started Aug 05 05:42:18 PM PDT 24
Finished Aug 05 05:42:33 PM PDT 24
Peak memory 200020 kb
Host smart-2efdd928-635a-49f6-bfea-fed22763d665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430746567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2430746567
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.763414926
Short name T86
Test name
Test status
Simulation time 45735968875 ps
CPU time 100.77 seconds
Started Aug 05 05:42:17 PM PDT 24
Finished Aug 05 05:43:58 PM PDT 24
Peak memory 208328 kb
Host smart-bf6cfc56-8585-455c-869d-6416ef7401d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763414926 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.763414926
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1388010104
Short name T32
Test name
Test status
Simulation time 726470655 ps
CPU time 12.76 seconds
Started Aug 05 05:42:15 PM PDT 24
Finished Aug 05 05:42:28 PM PDT 24
Peak memory 199896 kb
Host smart-856baef3-bc98-4032-8f5a-c0a34da14e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388010104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1388010104
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3256810890
Short name T433
Test name
Test status
Simulation time 43432674 ps
CPU time 0.58 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:14 PM PDT 24
Peak memory 195988 kb
Host smart-1cf7f258-1f00-4e90-b4b5-25263fc6c20b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256810890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3256810890
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.921597040
Short name T87
Test name
Test status
Simulation time 1481672808 ps
CPU time 20.9 seconds
Started Aug 05 05:42:15 PM PDT 24
Finished Aug 05 05:42:36 PM PDT 24
Peak memory 199952 kb
Host smart-55dc74b2-387f-4383-b3ec-a24b0a593972
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=921597040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.921597040
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2223400208
Short name T417
Test name
Test status
Simulation time 1532981252 ps
CPU time 20.06 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:33 PM PDT 24
Peak memory 199884 kb
Host smart-abfdb408-e454-46a7-9174-6f8c8a88dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223400208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2223400208
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2669097330
Short name T228
Test name
Test status
Simulation time 3959588446 ps
CPU time 721.16 seconds
Started Aug 05 05:42:14 PM PDT 24
Finished Aug 05 05:54:16 PM PDT 24
Peak memory 686952 kb
Host smart-56110cab-bf71-4258-8dbd-fea9a961f5b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669097330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2669097330
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3672550935
Short name T377
Test name
Test status
Simulation time 5367678539 ps
CPU time 24.68 seconds
Started Aug 05 05:42:22 PM PDT 24
Finished Aug 05 05:42:47 PM PDT 24
Peak memory 200004 kb
Host smart-d5763ead-1195-4dd1-89f2-a3cb2ee1db54
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672550935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3672550935
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2766563432
Short name T80
Test name
Test status
Simulation time 9778129349 ps
CPU time 175.04 seconds
Started Aug 05 05:42:19 PM PDT 24
Finished Aug 05 05:45:14 PM PDT 24
Peak memory 200064 kb
Host smart-a3164286-f881-4777-a0f1-3de7778f3043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766563432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2766563432
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.471286572
Short name T396
Test name
Test status
Simulation time 1252564364 ps
CPU time 7.54 seconds
Started Aug 05 05:42:18 PM PDT 24
Finished Aug 05 05:42:25 PM PDT 24
Peak memory 199920 kb
Host smart-b7c1515b-b48b-43fe-85a3-f5e66910af56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471286572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.471286572
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2497637058
Short name T83
Test name
Test status
Simulation time 146480653457 ps
CPU time 1017.08 seconds
Started Aug 05 05:42:12 PM PDT 24
Finished Aug 05 05:59:09 PM PDT 24
Peak memory 609144 kb
Host smart-afbfb16c-7217-4150-944e-317a90ff4f5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497637058 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2497637058
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2949483868
Short name T150
Test name
Test status
Simulation time 98237882 ps
CPU time 5.38 seconds
Started Aug 05 05:42:22 PM PDT 24
Finished Aug 05 05:42:28 PM PDT 24
Peak memory 199780 kb
Host smart-c9ec663e-5814-4762-ae48-0e62bc74bd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949483868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2949483868
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3255898019
Short name T35
Test name
Test status
Simulation time 48412008 ps
CPU time 0.58 seconds
Started Aug 05 05:42:16 PM PDT 24
Finished Aug 05 05:42:17 PM PDT 24
Peak memory 195924 kb
Host smart-89bac822-f1e1-4b52-bab5-62765f099705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255898019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3255898019
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3036737430
Short name T380
Test name
Test status
Simulation time 1578803554 ps
CPU time 88.12 seconds
Started Aug 05 05:42:11 PM PDT 24
Finished Aug 05 05:43:39 PM PDT 24
Peak memory 199908 kb
Host smart-bd78b43e-9310-4321-b3e6-2552df5a4017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3036737430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3036737430
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.4150859697
Short name T310
Test name
Test status
Simulation time 11905733486 ps
CPU time 39.73 seconds
Started Aug 05 05:42:17 PM PDT 24
Finished Aug 05 05:42:57 PM PDT 24
Peak memory 208112 kb
Host smart-9d6293dd-79d4-4fce-8c7c-8049980d8c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150859697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.4150859697
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2883783967
Short name T291
Test name
Test status
Simulation time 3235688442 ps
CPU time 548.7 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:51:27 PM PDT 24
Peak memory 669216 kb
Host smart-f8bd47e4-ff51-475e-84bc-51fbdf0887f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883783967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2883783967
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3894322482
Short name T398
Test name
Test status
Simulation time 17952386504 ps
CPU time 216.63 seconds
Started Aug 05 05:42:15 PM PDT 24
Finished Aug 05 05:45:52 PM PDT 24
Peak memory 200036 kb
Host smart-27b4a588-db31-442f-b21e-a682e86e7e9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894322482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3894322482
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3994348057
Short name T342
Test name
Test status
Simulation time 34950597216 ps
CPU time 112.43 seconds
Started Aug 05 05:42:18 PM PDT 24
Finished Aug 05 05:44:11 PM PDT 24
Peak memory 200028 kb
Host smart-7e0eeaf6-40db-46cc-ad2a-18f9149a6048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994348057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3994348057
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3741850090
Short name T267
Test name
Test status
Simulation time 2232236311 ps
CPU time 14.18 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:28 PM PDT 24
Peak memory 200024 kb
Host smart-ec2c5dc0-3f15-4e5a-8d24-00dd490e5a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741850090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3741850090
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2761684176
Short name T448
Test name
Test status
Simulation time 81737807483 ps
CPU time 1920.13 seconds
Started Aug 05 05:42:16 PM PDT 24
Finished Aug 05 06:14:16 PM PDT 24
Peak memory 715280 kb
Host smart-599b8a66-ea82-40e6-b676-3792ce50b85c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761684176 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2761684176
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1797941661
Short name T196
Test name
Test status
Simulation time 6471094692 ps
CPU time 114.34 seconds
Started Aug 05 05:42:19 PM PDT 24
Finished Aug 05 05:44:14 PM PDT 24
Peak memory 200008 kb
Host smart-7e3c0042-cd0c-46f2-ade7-4dc571d5636e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797941661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1797941661
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2092159362
Short name T349
Test name
Test status
Simulation time 31307719 ps
CPU time 0.54 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:14 PM PDT 24
Peak memory 195652 kb
Host smart-cb57be10-1b1b-498e-8723-9073afb35dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092159362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2092159362
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1202934866
Short name T366
Test name
Test status
Simulation time 2689404997 ps
CPU time 32.25 seconds
Started Aug 05 05:42:15 PM PDT 24
Finished Aug 05 05:42:47 PM PDT 24
Peak memory 200012 kb
Host smart-e81dd31e-f38a-45f7-bd71-94ac62bda89d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202934866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1202934866
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3168708950
Short name T350
Test name
Test status
Simulation time 471577805 ps
CPU time 25.45 seconds
Started Aug 05 05:42:17 PM PDT 24
Finished Aug 05 05:42:42 PM PDT 24
Peak memory 199892 kb
Host smart-c0d52fa2-aa6e-46d9-803a-5755c038c90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168708950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3168708950
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3117220762
Short name T302
Test name
Test status
Simulation time 83050274 ps
CPU time 5.26 seconds
Started Aug 05 05:42:22 PM PDT 24
Finished Aug 05 05:42:28 PM PDT 24
Peak memory 208124 kb
Host smart-77b44ff0-dac5-414c-b068-923a3d447279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117220762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3117220762
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1220508706
Short name T252
Test name
Test status
Simulation time 2595768886 ps
CPU time 17.21 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:31 PM PDT 24
Peak memory 200004 kb
Host smart-1fba5898-de96-4a7b-a9a3-ed56ed3fef84
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220508706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1220508706
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.334464842
Short name T506
Test name
Test status
Simulation time 47657913938 ps
CPU time 156.69 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:44:50 PM PDT 24
Peak memory 200012 kb
Host smart-dcd21cb2-1a77-40c5-b7ad-4d65456cfc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334464842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.334464842
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.905492333
Short name T51
Test name
Test status
Simulation time 689899114 ps
CPU time 3.48 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:17 PM PDT 24
Peak memory 199852 kb
Host smart-03dca5e2-9ff7-4ed8-b0cb-a8e03910a9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905492333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.905492333
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2742085906
Short name T194
Test name
Test status
Simulation time 122842000 ps
CPU time 6.77 seconds
Started Aug 05 05:42:18 PM PDT 24
Finished Aug 05 05:42:25 PM PDT 24
Peak memory 199908 kb
Host smart-c7a611c5-336e-4dca-9e98-8dee5c957fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742085906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2742085906
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1425711299
Short name T484
Test name
Test status
Simulation time 33390725 ps
CPU time 0.55 seconds
Started Aug 05 05:42:17 PM PDT 24
Finished Aug 05 05:42:18 PM PDT 24
Peak memory 195532 kb
Host smart-6490d796-0aa4-429f-b87a-448fd13a7c16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425711299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1425711299
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3584218680
Short name T156
Test name
Test status
Simulation time 3381584404 ps
CPU time 48.34 seconds
Started Aug 05 05:42:16 PM PDT 24
Finished Aug 05 05:43:04 PM PDT 24
Peak memory 200016 kb
Host smart-5715dc11-64f8-4906-baa3-0d1f3e252b3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584218680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3584218680
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1490364828
Short name T391
Test name
Test status
Simulation time 2009962970 ps
CPU time 27.98 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:41 PM PDT 24
Peak memory 199908 kb
Host smart-30865e82-9759-49fd-a578-0206040ff8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490364828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1490364828
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2342973343
Short name T361
Test name
Test status
Simulation time 2343605678 ps
CPU time 31.47 seconds
Started Aug 05 05:42:24 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 229020 kb
Host smart-2d17eb59-3fc3-46ab-94c0-970d76b3a9ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342973343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2342973343
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2896942420
Short name T78
Test name
Test status
Simulation time 3482612937 ps
CPU time 177.63 seconds
Started Aug 05 05:42:27 PM PDT 24
Finished Aug 05 05:45:25 PM PDT 24
Peak memory 200008 kb
Host smart-3b2076c7-f37a-4132-91fe-edbf64f848d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896942420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2896942420
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2146199998
Short name T200
Test name
Test status
Simulation time 11543477081 ps
CPU time 171.08 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:45:04 PM PDT 24
Peak memory 200200 kb
Host smart-e046cba0-6fd7-4857-9c66-8ee6666ced94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146199998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2146199998
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3568187618
Short name T384
Test name
Test status
Simulation time 129271805 ps
CPU time 0.66 seconds
Started Aug 05 05:42:25 PM PDT 24
Finished Aug 05 05:42:26 PM PDT 24
Peak memory 196600 kb
Host smart-b58fe6e0-6185-4f48-888b-55d15745252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568187618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3568187618
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.4207112843
Short name T117
Test name
Test status
Simulation time 154312546735 ps
CPU time 963.92 seconds
Started Aug 05 05:42:19 PM PDT 24
Finished Aug 05 05:58:23 PM PDT 24
Peak memory 521252 kb
Host smart-0fdafe1f-aae0-4600-9435-05b749f255f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207112843 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.4207112843
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2441368998
Short name T269
Test name
Test status
Simulation time 1076512653 ps
CPU time 55.7 seconds
Started Aug 05 05:42:20 PM PDT 24
Finished Aug 05 05:43:15 PM PDT 24
Peak memory 199960 kb
Host smart-60483b07-06c2-4e26-8715-70342d7735d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441368998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2441368998
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2489344528
Short name T257
Test name
Test status
Simulation time 43665229 ps
CPU time 0.62 seconds
Started Aug 05 05:42:32 PM PDT 24
Finished Aug 05 05:42:33 PM PDT 24
Peak memory 195992 kb
Host smart-23a221aa-389d-4198-92b3-ed3dd9dad73e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489344528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2489344528
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.976487764
Short name T376
Test name
Test status
Simulation time 3273335298 ps
CPU time 39.54 seconds
Started Aug 05 05:42:21 PM PDT 24
Finished Aug 05 05:43:01 PM PDT 24
Peak memory 200008 kb
Host smart-6635dcbf-418d-4855-821c-3125510caaba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976487764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.976487764
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.772213168
Short name T421
Test name
Test status
Simulation time 11970464893 ps
CPU time 59.76 seconds
Started Aug 05 05:42:27 PM PDT 24
Finished Aug 05 05:43:27 PM PDT 24
Peak memory 200172 kb
Host smart-3453451d-77c2-4216-9c56-6dcf8d9ca041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772213168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.772213168
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3170831842
Short name T300
Test name
Test status
Simulation time 3001297567 ps
CPU time 458.01 seconds
Started Aug 05 05:42:21 PM PDT 24
Finished Aug 05 05:49:59 PM PDT 24
Peak memory 672332 kb
Host smart-c9353c1a-7787-42ea-8c98-9fd8460e1b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170831842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3170831842
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1070643809
Short name T309
Test name
Test status
Simulation time 207421236 ps
CPU time 5.96 seconds
Started Aug 05 05:42:24 PM PDT 24
Finished Aug 05 05:42:30 PM PDT 24
Peak memory 199792 kb
Host smart-3fc19e2e-b1b2-4d80-816d-4d056542b34f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070643809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1070643809
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2076369291
Short name T423
Test name
Test status
Simulation time 11752147322 ps
CPU time 160.18 seconds
Started Aug 05 05:42:32 PM PDT 24
Finished Aug 05 05:45:13 PM PDT 24
Peak memory 199972 kb
Host smart-d7f38a2a-35b4-40d8-babb-b8ce812775e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076369291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2076369291
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2894370503
Short name T236
Test name
Test status
Simulation time 2688799480 ps
CPU time 8.28 seconds
Started Aug 05 05:42:13 PM PDT 24
Finished Aug 05 05:42:21 PM PDT 24
Peak memory 200088 kb
Host smart-9e9ed294-63cf-4623-af75-3d06ac5e955a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894370503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2894370503
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2317852196
Short name T296
Test name
Test status
Simulation time 64068059194 ps
CPU time 1038.77 seconds
Started Aug 05 05:42:35 PM PDT 24
Finished Aug 05 05:59:54 PM PDT 24
Peak memory 694836 kb
Host smart-bcdfe0d9-5ec0-4427-b699-62601e4c433f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317852196 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2317852196
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.304914571
Short name T62
Test name
Test status
Simulation time 30110541262 ps
CPU time 97.96 seconds
Started Aug 05 05:42:32 PM PDT 24
Finished Aug 05 05:44:11 PM PDT 24
Peak memory 200044 kb
Host smart-65e07be0-f6a1-462b-a682-a7ff90a34498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304914571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.304914571
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2270180830
Short name T158
Test name
Test status
Simulation time 49696361 ps
CPU time 0.58 seconds
Started Aug 05 05:42:32 PM PDT 24
Finished Aug 05 05:42:33 PM PDT 24
Peak memory 196000 kb
Host smart-5608ef80-dbb8-476e-8fbd-75285274fdca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270180830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2270180830
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2095161123
Short name T298
Test name
Test status
Simulation time 3089471755 ps
CPU time 43.71 seconds
Started Aug 05 05:42:27 PM PDT 24
Finished Aug 05 05:43:11 PM PDT 24
Peak memory 200036 kb
Host smart-81c710c7-a7d0-4fac-8809-37baee23cf8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095161123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2095161123
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1390721791
Short name T259
Test name
Test status
Simulation time 616769432 ps
CPU time 3.4 seconds
Started Aug 05 05:42:32 PM PDT 24
Finished Aug 05 05:42:36 PM PDT 24
Peak memory 199888 kb
Host smart-a35d4d3f-f23c-49c7-a036-772775fa59b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390721791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1390721791
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3611467563
Short name T288
Test name
Test status
Simulation time 65985924579 ps
CPU time 1423.81 seconds
Started Aug 05 05:42:22 PM PDT 24
Finished Aug 05 06:06:06 PM PDT 24
Peak memory 743936 kb
Host smart-5ab291de-b71d-4456-a86a-b3070ee82e22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611467563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3611467563
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2023476117
Short name T170
Test name
Test status
Simulation time 10028964103 ps
CPU time 61.79 seconds
Started Aug 05 05:42:18 PM PDT 24
Finished Aug 05 05:43:20 PM PDT 24
Peak memory 199960 kb
Host smart-c5dc009a-42e3-41ef-b644-7735e853307e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023476117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2023476117
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3087635179
Short name T235
Test name
Test status
Simulation time 19488699200 ps
CPU time 145.97 seconds
Started Aug 05 05:42:32 PM PDT 24
Finished Aug 05 05:44:58 PM PDT 24
Peak memory 216264 kb
Host smart-250dfd57-6d12-4006-b643-5a5460230e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087635179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3087635179
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.599471033
Short name T244
Test name
Test status
Simulation time 615458930 ps
CPU time 4.08 seconds
Started Aug 05 05:42:26 PM PDT 24
Finished Aug 05 05:42:30 PM PDT 24
Peak memory 199852 kb
Host smart-695abe46-450e-4bfc-afa3-62bef037a58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599471033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.599471033
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3111741643
Short name T84
Test name
Test status
Simulation time 39624138169 ps
CPU time 974.47 seconds
Started Aug 05 05:42:29 PM PDT 24
Finished Aug 05 05:58:43 PM PDT 24
Peak memory 679076 kb
Host smart-b77bd306-583c-48b3-9310-aa65ff70e23f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111741643 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3111741643
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2730278840
Short name T38
Test name
Test status
Simulation time 8703936570 ps
CPU time 80.39 seconds
Started Aug 05 05:42:22 PM PDT 24
Finished Aug 05 05:43:43 PM PDT 24
Peak memory 200068 kb
Host smart-87530277-e33f-41eb-ad33-448c188e94de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730278840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2730278840
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2741607201
Short name T326
Test name
Test status
Simulation time 30511160 ps
CPU time 0.58 seconds
Started Aug 05 05:42:22 PM PDT 24
Finished Aug 05 05:42:23 PM PDT 24
Peak memory 194920 kb
Host smart-c86a6fd3-58a0-464a-883b-88d2b5d4814c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741607201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2741607201
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3469891367
Short name T403
Test name
Test status
Simulation time 1470017280 ps
CPU time 86.39 seconds
Started Aug 05 05:42:23 PM PDT 24
Finished Aug 05 05:43:49 PM PDT 24
Peak memory 199940 kb
Host smart-699af6b0-981b-456c-aaa5-9877fcd9f3bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3469891367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3469891367
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.862992269
Short name T367
Test name
Test status
Simulation time 4524217484 ps
CPU time 32.62 seconds
Started Aug 05 05:42:23 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 200000 kb
Host smart-cc5d3983-d0ec-4cb9-a9ca-776a0de284a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862992269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.862992269
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.4017781844
Short name T414
Test name
Test status
Simulation time 1460544984 ps
CPU time 255.42 seconds
Started Aug 05 05:42:29 PM PDT 24
Finished Aug 05 05:46:44 PM PDT 24
Peak memory 609760 kb
Host smart-0d254786-acfe-49e7-83b5-e1a53c3254b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4017781844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.4017781844
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3870165273
Short name T412
Test name
Test status
Simulation time 44421189774 ps
CPU time 187.56 seconds
Started Aug 05 05:42:28 PM PDT 24
Finished Aug 05 05:45:36 PM PDT 24
Peak memory 200012 kb
Host smart-0acfeece-a601-4768-a277-235e572c2e60
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870165273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3870165273
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2498452174
Short name T347
Test name
Test status
Simulation time 73637360766 ps
CPU time 127.81 seconds
Started Aug 05 05:42:21 PM PDT 24
Finished Aug 05 05:44:29 PM PDT 24
Peak memory 199972 kb
Host smart-ff736ddb-cd99-4392-9f98-f71fcfaa9a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498452174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2498452174
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.767506349
Short name T182
Test name
Test status
Simulation time 301028733 ps
CPU time 4.42 seconds
Started Aug 05 05:42:30 PM PDT 24
Finished Aug 05 05:42:34 PM PDT 24
Peak memory 199908 kb
Host smart-6e68bc67-188d-4a35-9e05-0b45ac2a6e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767506349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.767506349
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1889700946
Short name T82
Test name
Test status
Simulation time 1003520564571 ps
CPU time 1105.76 seconds
Started Aug 05 05:42:24 PM PDT 24
Finished Aug 05 06:00:50 PM PDT 24
Peak memory 642960 kb
Host smart-586d24ab-e6f3-48d5-b14e-2cbed21d0233
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889700946 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1889700946
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4241121414
Short name T276
Test name
Test status
Simulation time 19938646426 ps
CPU time 67.12 seconds
Started Aug 05 05:42:27 PM PDT 24
Finished Aug 05 05:43:34 PM PDT 24
Peak memory 200020 kb
Host smart-80d1204b-2a2e-4a65-8ca6-c5e18661002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241121414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4241121414
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1421437165
Short name T143
Test name
Test status
Simulation time 16047296 ps
CPU time 0.59 seconds
Started Aug 05 05:41:28 PM PDT 24
Finished Aug 05 05:41:29 PM PDT 24
Peak memory 195900 kb
Host smart-3ad89bcf-4622-4b6d-99f9-ddea657741e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421437165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1421437165
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1388243971
Short name T519
Test name
Test status
Simulation time 6639710293 ps
CPU time 94.04 seconds
Started Aug 05 05:41:30 PM PDT 24
Finished Aug 05 05:43:05 PM PDT 24
Peak memory 200264 kb
Host smart-44651200-c48b-4d1c-89cb-c08ae457d0d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388243971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1388243971
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2114489036
Short name T340
Test name
Test status
Simulation time 1007875549 ps
CPU time 46.72 seconds
Started Aug 05 05:41:38 PM PDT 24
Finished Aug 05 05:42:25 PM PDT 24
Peak memory 199920 kb
Host smart-d920578b-5644-4c91-88e2-88576dd7fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114489036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2114489036
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3316464405
Short name T501
Test name
Test status
Simulation time 25164840717 ps
CPU time 1208.06 seconds
Started Aug 05 05:41:37 PM PDT 24
Finished Aug 05 06:01:45 PM PDT 24
Peak memory 764988 kb
Host smart-6cf3afe8-ea14-4c25-b262-ec004f50567c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316464405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3316464405
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.452731925
Short name T503
Test name
Test status
Simulation time 94697243347 ps
CPU time 261.03 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:46:09 PM PDT 24
Peak memory 200020 kb
Host smart-7f9f54a5-32c6-4d0a-8918-a54006ed5dc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452731925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.452731925
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1441161093
Short name T422
Test name
Test status
Simulation time 2807128510 ps
CPU time 157.59 seconds
Started Aug 05 05:41:44 PM PDT 24
Finished Aug 05 05:44:22 PM PDT 24
Peak memory 200020 kb
Host smart-c2aacc99-b4ba-4526-925b-c16e73fcca4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441161093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1441161093
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.66137406
Short name T57
Test name
Test status
Simulation time 286904265 ps
CPU time 1.01 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:41:49 PM PDT 24
Peak memory 219480 kb
Host smart-1cece432-6600-4573-90ff-bbc5693edab0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66137406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.66137406
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2648542412
Short name T334
Test name
Test status
Simulation time 97855787 ps
CPU time 4.82 seconds
Started Aug 05 05:41:42 PM PDT 24
Finished Aug 05 05:41:46 PM PDT 24
Peak memory 199868 kb
Host smart-0732741b-98af-4501-ad95-01d4c67cebb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648542412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2648542412
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3361836469
Short name T486
Test name
Test status
Simulation time 14184667790 ps
CPU time 714.64 seconds
Started Aug 05 05:41:47 PM PDT 24
Finished Aug 05 05:53:42 PM PDT 24
Peak memory 200000 kb
Host smart-93af5263-f40c-47d0-b4c5-0f3bb41b92d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361836469 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3361836469
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1817793280
Short name T23
Test name
Test status
Simulation time 717282431794 ps
CPU time 1518.66 seconds
Started Aug 05 05:41:33 PM PDT 24
Finished Aug 05 06:06:52 PM PDT 24
Peak memory 650232 kb
Host smart-3fc2dac8-52e7-4268-83fd-9fb1992f77a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817793280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1817793280
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1203303153
Short name T261
Test name
Test status
Simulation time 6031023184 ps
CPU time 46.3 seconds
Started Aug 05 05:41:39 PM PDT 24
Finished Aug 05 05:42:26 PM PDT 24
Peak memory 200028 kb
Host smart-1b0b6aa1-87fc-4dfc-8579-84318d2f1e13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1203303153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1203303153
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1863805270
Short name T232
Test name
Test status
Simulation time 18470705410 ps
CPU time 59.45 seconds
Started Aug 05 05:41:50 PM PDT 24
Finished Aug 05 05:42:50 PM PDT 24
Peak memory 200028 kb
Host smart-7ae8117d-59ca-4669-b89f-1573aa9373b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1863805270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1863805270
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3385435812
Short name T327
Test name
Test status
Simulation time 4026596368 ps
CPU time 65.35 seconds
Started Aug 05 05:41:41 PM PDT 24
Finished Aug 05 05:42:47 PM PDT 24
Peak memory 199956 kb
Host smart-627b1b2c-dd47-4434-8c93-0e4d985a42f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3385435812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3385435812
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1604037735
Short name T483
Test name
Test status
Simulation time 52951004477 ps
CPU time 704.32 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:53:32 PM PDT 24
Peak memory 199976 kb
Host smart-6a5bf963-be98-47d1-a299-7c99a281985d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1604037735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1604037735
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.4087616447
Short name T224
Test name
Test status
Simulation time 212402285863 ps
CPU time 2642.49 seconds
Started Aug 05 05:41:30 PM PDT 24
Finished Aug 05 06:25:32 PM PDT 24
Peak memory 200336 kb
Host smart-9d2a3dbb-19b8-4d62-8a05-2ae4c5c452b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4087616447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.4087616447
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3219078986
Short name T133
Test name
Test status
Simulation time 269614382689 ps
CPU time 2316.64 seconds
Started Aug 05 05:41:39 PM PDT 24
Finished Aug 05 06:20:16 PM PDT 24
Peak memory 215464 kb
Host smart-1dbbedb2-4721-485e-b1e2-c68420f1315f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3219078986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3219078986
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2182635874
Short name T439
Test name
Test status
Simulation time 6535005549 ps
CPU time 109.24 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:43:37 PM PDT 24
Peak memory 200096 kb
Host smart-973f00f8-aa25-408f-b107-5148f728c089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182635874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2182635874
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3363436030
Short name T341
Test name
Test status
Simulation time 107942685 ps
CPU time 0.58 seconds
Started Aug 05 05:42:29 PM PDT 24
Finished Aug 05 05:42:29 PM PDT 24
Peak memory 196644 kb
Host smart-3d97988a-5076-4b64-bc38-f83d5e208fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363436030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3363436030
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3865749180
Short name T177
Test name
Test status
Simulation time 2097419293 ps
CPU time 62.92 seconds
Started Aug 05 05:42:35 PM PDT 24
Finished Aug 05 05:43:38 PM PDT 24
Peak memory 199904 kb
Host smart-052ea28e-49a4-4f93-90c0-d09ce0fed2e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865749180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3865749180
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2841828476
Short name T25
Test name
Test status
Simulation time 1192764451 ps
CPU time 32.01 seconds
Started Aug 05 05:42:27 PM PDT 24
Finished Aug 05 05:42:59 PM PDT 24
Peak memory 199876 kb
Host smart-986db5f2-f64a-4082-b7b3-0caae9105057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841828476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2841828476
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.909529999
Short name T44
Test name
Test status
Simulation time 4736362687 ps
CPU time 942.51 seconds
Started Aug 05 05:42:29 PM PDT 24
Finished Aug 05 05:58:12 PM PDT 24
Peak memory 670244 kb
Host smart-70cd7581-0a50-463f-a2aa-07ec3b20d6eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909529999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.909529999
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.655224916
Short name T129
Test name
Test status
Simulation time 13457381071 ps
CPU time 79.67 seconds
Started Aug 05 05:42:27 PM PDT 24
Finished Aug 05 05:43:47 PM PDT 24
Peak memory 200028 kb
Host smart-6c268f40-a8d2-4025-92a0-19ad2bde31bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655224916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.655224916
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.4126348611
Short name T254
Test name
Test status
Simulation time 8975926381 ps
CPU time 128.75 seconds
Started Aug 05 05:42:27 PM PDT 24
Finished Aug 05 05:44:36 PM PDT 24
Peak memory 200004 kb
Host smart-93251919-df6a-4611-bb1b-59bf21fc4cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126348611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.4126348611
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2164538467
Short name T374
Test name
Test status
Simulation time 114801240 ps
CPU time 5.4 seconds
Started Aug 05 05:42:33 PM PDT 24
Finished Aug 05 05:42:39 PM PDT 24
Peak memory 199896 kb
Host smart-841e1d28-4fc3-4b9c-b434-e45de684ef45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164538467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2164538467
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2623718833
Short name T485
Test name
Test status
Simulation time 93025292269 ps
CPU time 2698.95 seconds
Started Aug 05 05:42:29 PM PDT 24
Finished Aug 05 06:27:28 PM PDT 24
Peak memory 751144 kb
Host smart-b346bae9-0dc0-41da-977f-4220180e6a25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623718833 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2623718833
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.823244627
Short name T284
Test name
Test status
Simulation time 2401798454 ps
CPU time 47.81 seconds
Started Aug 05 05:42:23 PM PDT 24
Finished Aug 05 05:43:11 PM PDT 24
Peak memory 199952 kb
Host smart-3883e730-54dd-4c8f-8fa0-ca521e6b2395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823244627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.823244627
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3759020536
Short name T463
Test name
Test status
Simulation time 14902420 ps
CPU time 0.62 seconds
Started Aug 05 05:42:30 PM PDT 24
Finished Aug 05 05:42:30 PM PDT 24
Peak memory 196620 kb
Host smart-8edafd13-9cd6-436b-899a-f6ab1347251f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759020536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3759020536
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2910236695
Short name T37
Test name
Test status
Simulation time 415978406 ps
CPU time 25.85 seconds
Started Aug 05 05:42:29 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 199820 kb
Host smart-cdc69056-41c5-4f62-a3ad-3e6c16964424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910236695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2910236695
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1794025714
Short name T191
Test name
Test status
Simulation time 1849110721 ps
CPU time 34.13 seconds
Started Aug 05 05:42:33 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 199916 kb
Host smart-d994dd18-7ae8-45cc-a839-3cdea74e623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794025714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1794025714
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.4233249163
Short name T372
Test name
Test status
Simulation time 4717048937 ps
CPU time 233.99 seconds
Started Aug 05 05:42:33 PM PDT 24
Finished Aug 05 05:46:27 PM PDT 24
Peak memory 449768 kb
Host smart-fb0aa40c-42e7-4410-843b-5183b215695f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4233249163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.4233249163
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2191169225
Short name T311
Test name
Test status
Simulation time 15991011773 ps
CPU time 68.94 seconds
Started Aug 05 05:42:40 PM PDT 24
Finished Aug 05 05:43:49 PM PDT 24
Peak memory 199968 kb
Host smart-62c1bfab-660e-4d71-95e3-83370be9656a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191169225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2191169225
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.671503783
Short name T279
Test name
Test status
Simulation time 12780312669 ps
CPU time 167.36 seconds
Started Aug 05 05:42:24 PM PDT 24
Finished Aug 05 05:45:11 PM PDT 24
Peak memory 199996 kb
Host smart-9a71aad0-8cda-4b1a-985b-197bb45bbca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671503783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.671503783
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.4256507605
Short name T130
Test name
Test status
Simulation time 3083663040 ps
CPU time 8.9 seconds
Started Aug 05 05:42:29 PM PDT 24
Finished Aug 05 05:42:38 PM PDT 24
Peak memory 200048 kb
Host smart-1e213795-2b48-41d8-9175-ea48b92038b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256507605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4256507605
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.271663033
Short name T438
Test name
Test status
Simulation time 4561637964 ps
CPU time 851.4 seconds
Started Aug 05 05:42:37 PM PDT 24
Finished Aug 05 05:56:49 PM PDT 24
Peak memory 693340 kb
Host smart-9951a477-1980-41f0-b79c-05a8386743d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271663033 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.271663033
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2590902845
Short name T217
Test name
Test status
Simulation time 5057782023 ps
CPU time 82.68 seconds
Started Aug 05 05:42:30 PM PDT 24
Finished Aug 05 05:43:53 PM PDT 24
Peak memory 199980 kb
Host smart-9c253a77-4512-4d96-ac5b-e325fb0628cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590902845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2590902845
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1145955548
Short name T18
Test name
Test status
Simulation time 23338857 ps
CPU time 0.57 seconds
Started Aug 05 05:42:35 PM PDT 24
Finished Aug 05 05:42:36 PM PDT 24
Peak memory 194944 kb
Host smart-cdfa34a0-286f-4fc8-88b9-7f7aea23207a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145955548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1145955548
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1143904765
Short name T354
Test name
Test status
Simulation time 263206905 ps
CPU time 8.46 seconds
Started Aug 05 05:42:28 PM PDT 24
Finished Aug 05 05:42:37 PM PDT 24
Peak memory 199900 kb
Host smart-cde26f2d-d9d2-401b-a34c-57419a0d18cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143904765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1143904765
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.26408921
Short name T49
Test name
Test status
Simulation time 2077999424 ps
CPU time 55.35 seconds
Started Aug 05 05:42:33 PM PDT 24
Finished Aug 05 05:43:29 PM PDT 24
Peak memory 199844 kb
Host smart-9160ac58-da86-4cf0-9ec6-7a191cbfa609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26408921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.26408921
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2920153299
Short name T208
Test name
Test status
Simulation time 4679105019 ps
CPU time 887.06 seconds
Started Aug 05 05:42:28 PM PDT 24
Finished Aug 05 05:57:16 PM PDT 24
Peak memory 704496 kb
Host smart-b2996d51-1312-4ee6-b26f-5990a698345b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920153299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2920153299
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3987150708
Short name T189
Test name
Test status
Simulation time 12247837497 ps
CPU time 168.57 seconds
Started Aug 05 05:42:29 PM PDT 24
Finished Aug 05 05:45:18 PM PDT 24
Peak memory 200084 kb
Host smart-83891513-c17b-44b4-9c97-02866e9d2110
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987150708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3987150708
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.544547619
Short name T275
Test name
Test status
Simulation time 4310022293 ps
CPU time 48.71 seconds
Started Aug 05 05:42:33 PM PDT 24
Finished Aug 05 05:43:22 PM PDT 24
Peak memory 200016 kb
Host smart-018fa826-8659-476d-9620-696d6a5611c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544547619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.544547619
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3812009910
Short name T222
Test name
Test status
Simulation time 1237271038 ps
CPU time 16.01 seconds
Started Aug 05 05:42:37 PM PDT 24
Finished Aug 05 05:42:53 PM PDT 24
Peak memory 199916 kb
Host smart-a1619c11-f1f5-43cd-876e-1e63de7f63fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812009910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3812009910
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2236318483
Short name T180
Test name
Test status
Simulation time 123605653768 ps
CPU time 1147.82 seconds
Started Aug 05 05:42:30 PM PDT 24
Finished Aug 05 06:01:38 PM PDT 24
Peak memory 718420 kb
Host smart-48e557fd-624c-47bd-a329-8cb21f7d1f06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236318483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2236318483
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.469187950
Short name T518
Test name
Test status
Simulation time 347593027 ps
CPU time 17.55 seconds
Started Aug 05 05:42:30 PM PDT 24
Finished Aug 05 05:42:47 PM PDT 24
Peak memory 199848 kb
Host smart-19b81c34-ede9-4752-ab5b-9512e953f5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469187950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.469187950
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2656597805
Short name T54
Test name
Test status
Simulation time 14970667 ps
CPU time 0.59 seconds
Started Aug 05 05:42:37 PM PDT 24
Finished Aug 05 05:42:37 PM PDT 24
Peak memory 194944 kb
Host smart-250b0cba-b64c-4e15-be8b-0e1c7dc4e661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656597805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2656597805
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3575580452
Short name T1
Test name
Test status
Simulation time 1136011242 ps
CPU time 66.84 seconds
Started Aug 05 05:42:38 PM PDT 24
Finished Aug 05 05:43:45 PM PDT 24
Peak memory 199868 kb
Host smart-d6b58d2a-9758-42c6-a448-814ab2d6ab0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575580452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3575580452
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.784801993
Short name T497
Test name
Test status
Simulation time 10063315188 ps
CPU time 34.03 seconds
Started Aug 05 05:42:35 PM PDT 24
Finished Aug 05 05:43:09 PM PDT 24
Peak memory 199976 kb
Host smart-bc9a8eb7-05fd-4d9a-bf1f-65884608fb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784801993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.784801993
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1803904056
Short name T360
Test name
Test status
Simulation time 10603858643 ps
CPU time 436.49 seconds
Started Aug 05 05:42:34 PM PDT 24
Finished Aug 05 05:49:51 PM PDT 24
Peak memory 502012 kb
Host smart-6f6a74f9-9ae9-4a5f-99d9-3429976a874b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803904056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1803904056
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2572363796
Short name T508
Test name
Test status
Simulation time 17813186820 ps
CPU time 197.44 seconds
Started Aug 05 05:42:36 PM PDT 24
Finished Aug 05 05:45:53 PM PDT 24
Peak memory 200076 kb
Host smart-e0683100-9275-4c24-846d-fe6ed9ce3b0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572363796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2572363796
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.319153257
Short name T204
Test name
Test status
Simulation time 3421986690 ps
CPU time 47.36 seconds
Started Aug 05 05:42:31 PM PDT 24
Finished Aug 05 05:43:18 PM PDT 24
Peak memory 200044 kb
Host smart-220acecb-3503-42a6-9bf1-a49fc684f7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319153257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.319153257
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3990688279
Short name T285
Test name
Test status
Simulation time 5441759962 ps
CPU time 10.11 seconds
Started Aug 05 05:42:34 PM PDT 24
Finished Aug 05 05:42:44 PM PDT 24
Peak memory 200084 kb
Host smart-7da5a9f6-b0c9-45e2-aef2-0d02494088a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990688279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3990688279
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1090709635
Short name T231
Test name
Test status
Simulation time 115310778496 ps
CPU time 4928.78 seconds
Started Aug 05 05:42:35 PM PDT 24
Finished Aug 05 07:04:44 PM PDT 24
Peak memory 818536 kb
Host smart-125d1681-148a-4795-b4c2-5ccf1a3bc024
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090709635 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1090709635
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.709809889
Short name T142
Test name
Test status
Simulation time 2894926674 ps
CPU time 56.83 seconds
Started Aug 05 05:42:39 PM PDT 24
Finished Aug 05 05:43:36 PM PDT 24
Peak memory 199976 kb
Host smart-598ccc8c-de0c-49ec-95cd-79b2508e9dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709809889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.709809889
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1576517156
Short name T515
Test name
Test status
Simulation time 30275116 ps
CPU time 0.61 seconds
Started Aug 05 05:42:40 PM PDT 24
Finished Aug 05 05:42:41 PM PDT 24
Peak memory 195620 kb
Host smart-42120d4e-3fe6-41c6-9fbb-f77d01386bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576517156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1576517156
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.823456058
Short name T137
Test name
Test status
Simulation time 1574545722 ps
CPU time 88.58 seconds
Started Aug 05 05:42:32 PM PDT 24
Finished Aug 05 05:44:01 PM PDT 24
Peak memory 199900 kb
Host smart-0308d43c-7c52-4c5c-9299-640ebbf7504c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823456058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.823456058
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.788643007
Short name T425
Test name
Test status
Simulation time 1068928257 ps
CPU time 8.55 seconds
Started Aug 05 05:42:49 PM PDT 24
Finished Aug 05 05:42:58 PM PDT 24
Peak memory 199804 kb
Host smart-03171a44-b463-4fef-9724-b02d7a83ed7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788643007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.788643007
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1838094130
Short name T163
Test name
Test status
Simulation time 819409189 ps
CPU time 112.57 seconds
Started Aug 05 05:42:51 PM PDT 24
Finished Aug 05 05:44:44 PM PDT 24
Peak memory 418340 kb
Host smart-2b8009de-9eb9-4b2a-8d42-4ae7a5449de6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838094130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1838094130
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.692962061
Short name T389
Test name
Test status
Simulation time 45302757269 ps
CPU time 305.83 seconds
Started Aug 05 05:42:40 PM PDT 24
Finished Aug 05 05:47:46 PM PDT 24
Peak memory 200004 kb
Host smart-15c3e8cf-84d6-45e2-8bf4-41ddb19b0131
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692962061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.692962061
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2081604677
Short name T466
Test name
Test status
Simulation time 17078854327 ps
CPU time 79.59 seconds
Started Aug 05 05:42:35 PM PDT 24
Finished Aug 05 05:43:55 PM PDT 24
Peak memory 200068 kb
Host smart-53cb533f-e3a7-4c80-a942-601f147bf36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081604677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2081604677
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2717907583
Short name T432
Test name
Test status
Simulation time 3342814659 ps
CPU time 15.29 seconds
Started Aug 05 05:42:36 PM PDT 24
Finished Aug 05 05:42:51 PM PDT 24
Peak memory 200036 kb
Host smart-5c3e5500-a27c-4c4f-ad43-0dddc17ae9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717907583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2717907583
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1217331992
Short name T94
Test name
Test status
Simulation time 54459271002 ps
CPU time 538.68 seconds
Started Aug 05 05:42:51 PM PDT 24
Finished Aug 05 05:51:50 PM PDT 24
Peak memory 199996 kb
Host smart-d9572dfa-627c-4001-8fcb-ed214cf72f53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217331992 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1217331992
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3218019950
Short name T234
Test name
Test status
Simulation time 24722377749 ps
CPU time 42.48 seconds
Started Aug 05 05:42:50 PM PDT 24
Finished Aug 05 05:43:33 PM PDT 24
Peak memory 199948 kb
Host smart-5c97b554-7042-41ac-9a88-a5470fa87e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218019950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3218019950
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2755497334
Short name T418
Test name
Test status
Simulation time 13899803 ps
CPU time 0.61 seconds
Started Aug 05 05:42:41 PM PDT 24
Finished Aug 05 05:42:41 PM PDT 24
Peak memory 195980 kb
Host smart-7953471c-95c6-4f9f-9298-c3983a9a75e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755497334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2755497334
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2288227848
Short name T20
Test name
Test status
Simulation time 3948558258 ps
CPU time 110.21 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:44:43 PM PDT 24
Peak memory 216260 kb
Host smart-e3c4a874-34c4-4e7f-b4cd-bc7faa28ddb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288227848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2288227848
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.713150719
Short name T461
Test name
Test status
Simulation time 6409315508 ps
CPU time 18.05 seconds
Started Aug 05 05:42:41 PM PDT 24
Finished Aug 05 05:42:59 PM PDT 24
Peak memory 200048 kb
Host smart-38623f0b-0866-4c2e-8d23-376421a7e47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713150719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.713150719
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2615716361
Short name T312
Test name
Test status
Simulation time 3649575743 ps
CPU time 583.33 seconds
Started Aug 05 05:42:46 PM PDT 24
Finished Aug 05 05:52:29 PM PDT 24
Peak memory 689676 kb
Host smart-ac31c43d-521b-4d42-9fe0-a6729eee7593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615716361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2615716361
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.476835189
Short name T195
Test name
Test status
Simulation time 4715811610 ps
CPU time 11.86 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:43:04 PM PDT 24
Peak memory 200036 kb
Host smart-5a9a380f-b795-40f2-9b05-da18aa260ea6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476835189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.476835189
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.477408314
Short name T393
Test name
Test status
Simulation time 3829834349 ps
CPU time 54.03 seconds
Started Aug 05 05:42:42 PM PDT 24
Finished Aug 05 05:43:36 PM PDT 24
Peak memory 199996 kb
Host smart-b52c2626-5971-45dc-a1af-fa4f682bf21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477408314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.477408314
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2924907610
Short name T24
Test name
Test status
Simulation time 779237100 ps
CPU time 8.99 seconds
Started Aug 05 05:42:46 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 199904 kb
Host smart-7c94b0f1-9c01-4c78-91a0-6caf98a37573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924907610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2924907610
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1883484418
Short name T73
Test name
Test status
Simulation time 4573684635 ps
CPU time 20.23 seconds
Started Aug 05 05:42:40 PM PDT 24
Finished Aug 05 05:43:00 PM PDT 24
Peak memory 200200 kb
Host smart-462bb9c2-01b4-4fb2-adc5-497c8adf8f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883484418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1883484418
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.873286665
Short name T441
Test name
Test status
Simulation time 43524688 ps
CPU time 0.59 seconds
Started Aug 05 05:42:51 PM PDT 24
Finished Aug 05 05:42:52 PM PDT 24
Peak memory 195964 kb
Host smart-6a3658f8-f28e-4eac-989b-3dd8951d47cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873286665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.873286665
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3753303110
Short name T162
Test name
Test status
Simulation time 5313809433 ps
CPU time 75.23 seconds
Started Aug 05 05:42:51 PM PDT 24
Finished Aug 05 05:44:06 PM PDT 24
Peak memory 199964 kb
Host smart-3357c877-fa92-4ccd-917d-b277a90dea6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753303110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3753303110
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.4147064331
Short name T468
Test name
Test status
Simulation time 8774720088 ps
CPU time 61.23 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:43:54 PM PDT 24
Peak memory 200060 kb
Host smart-8991a4b6-dc5e-4e6c-95fa-6ec5c988f8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147064331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.4147064331
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2781125243
Short name T356
Test name
Test status
Simulation time 20359106577 ps
CPU time 887.14 seconds
Started Aug 05 05:42:46 PM PDT 24
Finished Aug 05 05:57:34 PM PDT 24
Peak memory 672768 kb
Host smart-08cb1193-da80-4b85-8af6-e03808f0202b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781125243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2781125243
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1839054538
Short name T176
Test name
Test status
Simulation time 1611848877 ps
CPU time 24.63 seconds
Started Aug 05 05:42:50 PM PDT 24
Finished Aug 05 05:43:14 PM PDT 24
Peak memory 199828 kb
Host smart-8782ac35-fdac-4e0a-8dca-dc6823c4dbaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839054538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1839054538
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1957026304
Short name T524
Test name
Test status
Simulation time 1757344021 ps
CPU time 97.77 seconds
Started Aug 05 05:42:51 PM PDT 24
Finished Aug 05 05:44:29 PM PDT 24
Peak memory 199960 kb
Host smart-4f611bcd-cd0d-4c0d-b3af-702a280b0339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957026304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1957026304
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.606592582
Short name T442
Test name
Test status
Simulation time 2810362659 ps
CPU time 11.37 seconds
Started Aug 05 05:42:49 PM PDT 24
Finished Aug 05 05:43:01 PM PDT 24
Peak memory 200008 kb
Host smart-8d45d0b9-5c44-4287-b6b7-640bd7a47616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606592582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.606592582
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3147390782
Short name T14
Test name
Test status
Simulation time 41339767408 ps
CPU time 1770.68 seconds
Started Aug 05 05:42:50 PM PDT 24
Finished Aug 05 06:12:21 PM PDT 24
Peak memory 719312 kb
Host smart-a34db675-572f-4d81-a1bf-43e8fe47c126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147390782 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3147390782
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2927171925
Short name T253
Test name
Test status
Simulation time 7234334965 ps
CPU time 18.17 seconds
Started Aug 05 05:42:51 PM PDT 24
Finished Aug 05 05:43:09 PM PDT 24
Peak memory 200032 kb
Host smart-767dfd74-78ce-4d53-b49b-e7e056d4ff06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927171925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2927171925
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1548981369
Short name T512
Test name
Test status
Simulation time 16081242 ps
CPU time 0.62 seconds
Started Aug 05 05:42:45 PM PDT 24
Finished Aug 05 05:42:45 PM PDT 24
Peak memory 196648 kb
Host smart-1b0c54a3-50fe-4edd-8bb4-19e74962f842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548981369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1548981369
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1082190955
Short name T416
Test name
Test status
Simulation time 46891354 ps
CPU time 2.68 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 199836 kb
Host smart-0c4c0a1f-7695-4979-a726-770e452bc0cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1082190955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1082190955
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.522255422
Short name T81
Test name
Test status
Simulation time 8730663896 ps
CPU time 18.48 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:43:12 PM PDT 24
Peak memory 200028 kb
Host smart-773c1524-8eb1-4df0-a9c0-c21bf07d032c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522255422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.522255422
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3072251094
Short name T152
Test name
Test status
Simulation time 1291876886 ps
CPU time 147.43 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:45:21 PM PDT 24
Peak memory 479904 kb
Host smart-512fa08e-e5a5-4f9d-80e1-21216faeb4df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072251094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3072251094
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.4240518216
Short name T490
Test name
Test status
Simulation time 2311709992 ps
CPU time 125.12 seconds
Started Aug 05 05:42:44 PM PDT 24
Finished Aug 05 05:44:50 PM PDT 24
Peak memory 200044 kb
Host smart-60dcc43d-0759-45dc-9ab0-e4fe15b541d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240518216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4240518216
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.945042151
Short name T352
Test name
Test status
Simulation time 6301387783 ps
CPU time 90.76 seconds
Started Aug 05 05:42:56 PM PDT 24
Finished Aug 05 05:44:26 PM PDT 24
Peak memory 200012 kb
Host smart-a341d4a6-d298-40a9-9fc2-9de9ab60250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945042151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.945042151
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1304357549
Short name T522
Test name
Test status
Simulation time 340502247 ps
CPU time 7.26 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:43:00 PM PDT 24
Peak memory 199904 kb
Host smart-de2bcf52-871c-459d-8591-3eaf63b1ebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304357549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1304357549
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3610528085
Short name T168
Test name
Test status
Simulation time 68908374301 ps
CPU time 1123.78 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 06:01:36 PM PDT 24
Peak memory 680252 kb
Host smart-ac1c39ef-cd06-46f3-aab2-eca84dff4198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610528085 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3610528085
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2336125275
Short name T303
Test name
Test status
Simulation time 3575561483 ps
CPU time 71.9 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:44:05 PM PDT 24
Peak memory 200056 kb
Host smart-248106a4-cab0-40ce-85de-84a769fcd3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336125275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2336125275
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1439080374
Short name T472
Test name
Test status
Simulation time 28379777 ps
CPU time 0.63 seconds
Started Aug 05 05:42:53 PM PDT 24
Finished Aug 05 05:42:53 PM PDT 24
Peak memory 194884 kb
Host smart-7672012a-02c1-4acf-81f6-b2f17f9be3f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439080374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1439080374
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3174357030
Short name T498
Test name
Test status
Simulation time 879723434 ps
CPU time 12.39 seconds
Started Aug 05 05:42:45 PM PDT 24
Finished Aug 05 05:42:58 PM PDT 24
Peak memory 199876 kb
Host smart-2079f843-60da-4ef6-8e49-73c95c984bec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3174357030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3174357030
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.730354939
Short name T36
Test name
Test status
Simulation time 4303875379 ps
CPU time 32.29 seconds
Started Aug 05 05:42:43 PM PDT 24
Finished Aug 05 05:43:16 PM PDT 24
Peak memory 200012 kb
Host smart-d84dd377-a34b-40aa-a92e-0aad2aad643d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730354939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.730354939
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.219808503
Short name T197
Test name
Test status
Simulation time 3768361200 ps
CPU time 376.75 seconds
Started Aug 05 05:42:50 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 664936 kb
Host smart-c645700e-d458-489d-a98a-37fd4e117c34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219808503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.219808503
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.4061703971
Short name T210
Test name
Test status
Simulation time 8730287333 ps
CPU time 26.74 seconds
Started Aug 05 05:42:44 PM PDT 24
Finished Aug 05 05:43:11 PM PDT 24
Peak memory 199980 kb
Host smart-5db26c6e-04d9-481f-bb89-b67fa0a4d59f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061703971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.4061703971
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1524466381
Short name T250
Test name
Test status
Simulation time 107289548206 ps
CPU time 168.81 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:45:41 PM PDT 24
Peak memory 200020 kb
Host smart-9df8b7ab-6d86-4d6d-9d98-60ee991cf4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524466381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1524466381
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2030260923
Short name T408
Test name
Test status
Simulation time 310912897 ps
CPU time 5.71 seconds
Started Aug 05 05:42:50 PM PDT 24
Finished Aug 05 05:42:56 PM PDT 24
Peak memory 199960 kb
Host smart-c335e65b-acf9-46e3-bcf9-12af5be003e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030260923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2030260923
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4092610747
Short name T29
Test name
Test status
Simulation time 214849041125 ps
CPU time 628.08 seconds
Started Aug 05 05:42:55 PM PDT 24
Finished Aug 05 05:53:23 PM PDT 24
Peak memory 200016 kb
Host smart-caaafc87-2ca3-4824-ad2b-1153c8879230
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092610747 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4092610747
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2575199700
Short name T444
Test name
Test status
Simulation time 5114208281 ps
CPU time 75.11 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:44:07 PM PDT 24
Peak memory 200044 kb
Host smart-087a88d9-10d0-4fe5-94aa-2a5d6b55ea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575199700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2575199700
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.643081664
Short name T529
Test name
Test status
Simulation time 23410758 ps
CPU time 0.61 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:42:55 PM PDT 24
Peak memory 196548 kb
Host smart-f7159a68-741d-4f27-9281-b82c210a0250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643081664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.643081664
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1417356936
Short name T424
Test name
Test status
Simulation time 568530172 ps
CPU time 15.59 seconds
Started Aug 05 05:42:51 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 199896 kb
Host smart-f6bdcce6-b390-4f30-91ce-1162d084ff7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417356936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1417356936
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4003049679
Short name T491
Test name
Test status
Simulation time 1370401480 ps
CPU time 25.21 seconds
Started Aug 05 05:42:52 PM PDT 24
Finished Aug 05 05:43:17 PM PDT 24
Peak memory 199984 kb
Host smart-61c087a2-98d8-42e6-bdd3-6f5067127be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003049679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4003049679
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4209822130
Short name T453
Test name
Test status
Simulation time 3644183182 ps
CPU time 282.22 seconds
Started Aug 05 05:42:43 PM PDT 24
Finished Aug 05 05:47:26 PM PDT 24
Peak memory 638872 kb
Host smart-8e6125ea-09e5-41fc-bac7-9933d3814a43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209822130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4209822130
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2648660772
Short name T161
Test name
Test status
Simulation time 3915046449 ps
CPU time 108.46 seconds
Started Aug 05 05:42:54 PM PDT 24
Finished Aug 05 05:44:43 PM PDT 24
Peak memory 200024 kb
Host smart-4d5caa2d-1641-4fc9-a708-cd9f6c8b096d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648660772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2648660772
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.297849615
Short name T220
Test name
Test status
Simulation time 70264385797 ps
CPU time 130.2 seconds
Started Aug 05 05:42:44 PM PDT 24
Finished Aug 05 05:44:54 PM PDT 24
Peak memory 199992 kb
Host smart-3b36ef33-0f91-4485-be55-074de3d6c71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297849615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.297849615
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3657023983
Short name T343
Test name
Test status
Simulation time 842774211 ps
CPU time 9.01 seconds
Started Aug 05 05:42:44 PM PDT 24
Finished Aug 05 05:42:53 PM PDT 24
Peak memory 199852 kb
Host smart-77dcd932-bf3a-4a58-94cb-6a8b320cd973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657023983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3657023983
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1623776482
Short name T443
Test name
Test status
Simulation time 6560705304 ps
CPU time 200.23 seconds
Started Aug 05 05:42:51 PM PDT 24
Finished Aug 05 05:46:12 PM PDT 24
Peak memory 199940 kb
Host smart-49d1a4c5-de7c-4afb-9174-93f4b40cc349
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623776482 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1623776482
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1607847864
Short name T212
Test name
Test status
Simulation time 1155537372 ps
CPU time 59.64 seconds
Started Aug 05 05:42:50 PM PDT 24
Finished Aug 05 05:43:50 PM PDT 24
Peak memory 199920 kb
Host smart-57aad84e-8966-409d-acf0-15c6adfb0cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607847864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1607847864
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.177337407
Short name T181
Test name
Test status
Simulation time 139357556 ps
CPU time 0.58 seconds
Started Aug 05 05:41:39 PM PDT 24
Finished Aug 05 05:41:40 PM PDT 24
Peak memory 195880 kb
Host smart-53d10ffa-494b-4fe1-a76d-ad05a76e05f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177337407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.177337407
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1214054676
Short name T202
Test name
Test status
Simulation time 1386932215 ps
CPU time 76.56 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:43:05 PM PDT 24
Peak memory 199888 kb
Host smart-64fdef34-5b3b-4903-b8dc-869d1ecdc564
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214054676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1214054676
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.365362442
Short name T301
Test name
Test status
Simulation time 791070589 ps
CPU time 42.2 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:42:12 PM PDT 24
Peak memory 199848 kb
Host smart-eb0b668c-0765-4b90-a104-19e72ac1d47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365362442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.365362442
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1589953638
Short name T313
Test name
Test status
Simulation time 8373785029 ps
CPU time 1518.34 seconds
Started Aug 05 05:41:42 PM PDT 24
Finished Aug 05 06:07:00 PM PDT 24
Peak memory 773816 kb
Host smart-97130821-5d8e-4681-931d-0850d1b57ab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1589953638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1589953638
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1934786456
Short name T90
Test name
Test status
Simulation time 5451811942 ps
CPU time 145.89 seconds
Started Aug 05 05:41:29 PM PDT 24
Finished Aug 05 05:43:55 PM PDT 24
Peak memory 200064 kb
Host smart-1fd91f27-926d-4838-8354-93903901a9f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934786456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1934786456
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2781231935
Short name T178
Test name
Test status
Simulation time 5198111549 ps
CPU time 142.14 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:44:11 PM PDT 24
Peak memory 216408 kb
Host smart-124d8183-0457-49a2-85db-f600840138cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781231935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2781231935
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1751792283
Short name T132
Test name
Test status
Simulation time 4069741404 ps
CPU time 13.55 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:42:02 PM PDT 24
Peak memory 200024 kb
Host smart-4047e25e-2b89-41f6-81c6-bb4c156900cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751792283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1751792283
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1293073386
Short name T140
Test name
Test status
Simulation time 14105513675 ps
CPU time 1275.53 seconds
Started Aug 05 05:41:42 PM PDT 24
Finished Aug 05 06:02:58 PM PDT 24
Peak memory 733580 kb
Host smart-b1a4e024-fa34-4c8d-b7ce-557cec58b5ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293073386 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1293073386
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2581820171
Short name T16
Test name
Test status
Simulation time 69040590079 ps
CPU time 1410.66 seconds
Started Aug 05 05:41:51 PM PDT 24
Finished Aug 05 06:05:22 PM PDT 24
Peak memory 710784 kb
Host smart-0c351f1f-b045-4c35-9bc3-2c5af8455532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2581820171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2581820171
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3024392084
Short name T199
Test name
Test status
Simulation time 7866023012 ps
CPU time 107.62 seconds
Started Aug 05 05:41:52 PM PDT 24
Finished Aug 05 05:43:40 PM PDT 24
Peak memory 200032 kb
Host smart-381d7be6-1208-4de5-a774-a158ed47f46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024392084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3024392084
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2323752237
Short name T436
Test name
Test status
Simulation time 36407733 ps
CPU time 0.56 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:41:59 PM PDT 24
Peak memory 196672 kb
Host smart-2e72ee2f-1765-4440-8e67-2e7eb7486aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323752237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2323752237
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2127693609
Short name T211
Test name
Test status
Simulation time 2623922775 ps
CPU time 38.67 seconds
Started Aug 05 05:41:49 PM PDT 24
Finished Aug 05 05:42:28 PM PDT 24
Peak memory 200016 kb
Host smart-45db5556-934b-4a74-9812-e0e89bdb97f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127693609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2127693609
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1253997353
Short name T516
Test name
Test status
Simulation time 3481333653 ps
CPU time 32.17 seconds
Started Aug 05 05:41:40 PM PDT 24
Finished Aug 05 05:42:13 PM PDT 24
Peak memory 200108 kb
Host smart-36344715-39a7-4204-b7b9-e49e91f0f1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253997353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1253997353
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1635932125
Short name T148
Test name
Test status
Simulation time 5732125226 ps
CPU time 1171.78 seconds
Started Aug 05 05:41:46 PM PDT 24
Finished Aug 05 06:01:18 PM PDT 24
Peak memory 769540 kb
Host smart-9d445aef-162c-42ee-bb76-f5b3636f03db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635932125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1635932125
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1391620360
Short name T434
Test name
Test status
Simulation time 11468514899 ps
CPU time 76.39 seconds
Started Aug 05 05:41:51 PM PDT 24
Finished Aug 05 05:43:07 PM PDT 24
Peak memory 199900 kb
Host smart-ba041f35-b52f-46da-981a-201a2918fd3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391620360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1391620360
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1596451776
Short name T379
Test name
Test status
Simulation time 3014981084 ps
CPU time 174.82 seconds
Started Aug 05 05:41:53 PM PDT 24
Finished Aug 05 05:44:48 PM PDT 24
Peak memory 199908 kb
Host smart-7302fa2d-92f5-4001-8233-5ff4321474c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596451776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1596451776
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.22814933
Short name T509
Test name
Test status
Simulation time 50602769 ps
CPU time 2.43 seconds
Started Aug 05 05:41:47 PM PDT 24
Finished Aug 05 05:41:50 PM PDT 24
Peak memory 199852 kb
Host smart-ff74c327-338e-4ac8-b750-e7681da1e051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22814933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.22814933
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1683987669
Short name T496
Test name
Test status
Simulation time 19405453296 ps
CPU time 1709.12 seconds
Started Aug 05 05:41:38 PM PDT 24
Finished Aug 05 06:10:07 PM PDT 24
Peak memory 720844 kb
Host smart-52af545d-f31c-4ac1-839f-6701a1b4905d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683987669 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1683987669
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.3355676758
Short name T15
Test name
Test status
Simulation time 889322503458 ps
CPU time 3861.11 seconds
Started Aug 05 05:41:46 PM PDT 24
Finished Aug 05 06:46:07 PM PDT 24
Peak memory 790332 kb
Host smart-2c2cb4c1-e1a8-4549-8a49-1f0b6bd86100
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3355676758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3355676758
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.677199987
Short name T351
Test name
Test status
Simulation time 3608600413 ps
CPU time 84.25 seconds
Started Aug 05 05:41:53 PM PDT 24
Finished Aug 05 05:43:17 PM PDT 24
Peak memory 200096 kb
Host smart-48e62048-f600-466a-b171-53c920d07af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677199987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.677199987
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4285069179
Short name T305
Test name
Test status
Simulation time 46880831 ps
CPU time 0.61 seconds
Started Aug 05 05:41:50 PM PDT 24
Finished Aug 05 05:41:51 PM PDT 24
Peak memory 195860 kb
Host smart-114bfd98-b963-4164-bc24-fc748c5d241e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285069179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4285069179
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3471076250
Short name T19
Test name
Test status
Simulation time 188977081 ps
CPU time 11.21 seconds
Started Aug 05 05:41:49 PM PDT 24
Finished Aug 05 05:42:00 PM PDT 24
Peak memory 199836 kb
Host smart-c47073eb-ee3b-40ea-83f8-7fbbd29bb76e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471076250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3471076250
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1587351200
Short name T428
Test name
Test status
Simulation time 3122661009 ps
CPU time 54.81 seconds
Started Aug 05 05:41:49 PM PDT 24
Finished Aug 05 05:42:44 PM PDT 24
Peak memory 199964 kb
Host smart-0e00d946-2d33-4a93-9781-17d08ad70509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587351200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1587351200
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2605713471
Short name T322
Test name
Test status
Simulation time 2127010099 ps
CPU time 457.38 seconds
Started Aug 05 05:41:43 PM PDT 24
Finished Aug 05 05:49:20 PM PDT 24
Peak memory 707232 kb
Host smart-3302d089-1cf9-4461-b10f-f794fff85191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605713471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2605713471
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2128516060
Short name T365
Test name
Test status
Simulation time 23533225997 ps
CPU time 189.37 seconds
Started Aug 05 05:41:47 PM PDT 24
Finished Aug 05 05:44:56 PM PDT 24
Peak memory 199976 kb
Host smart-fd6a0a94-2219-4034-83da-2ab8dc248497
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128516060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2128516060
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3003874358
Short name T215
Test name
Test status
Simulation time 5160990833 ps
CPU time 34.93 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:42:23 PM PDT 24
Peak memory 199888 kb
Host smart-c6d0784f-b912-4c21-8b02-2025f3c4d3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003874358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3003874358
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1688396590
Short name T430
Test name
Test status
Simulation time 996619318 ps
CPU time 11.15 seconds
Started Aug 05 05:41:53 PM PDT 24
Finished Aug 05 05:42:04 PM PDT 24
Peak memory 199852 kb
Host smart-4ced4fc0-665a-42bf-b13f-65acbab24c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688396590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1688396590
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.491037279
Short name T52
Test name
Test status
Simulation time 12745566200 ps
CPU time 231.98 seconds
Started Aug 05 05:41:50 PM PDT 24
Finished Aug 05 05:45:43 PM PDT 24
Peak memory 571656 kb
Host smart-dec837ee-7706-4fc9-9e3d-c89b64eca59c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491037279 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.491037279
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2322439216
Short name T10
Test name
Test status
Simulation time 120664419570 ps
CPU time 3101.75 seconds
Started Aug 05 05:41:47 PM PDT 24
Finished Aug 05 06:33:29 PM PDT 24
Peak memory 673700 kb
Host smart-69dcbd81-db5d-4706-9d0c-7b7afea9d53d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322439216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2322439216
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3219323224
Short name T481
Test name
Test status
Simulation time 7012047620 ps
CPU time 63.21 seconds
Started Aug 05 05:41:45 PM PDT 24
Finished Aug 05 05:42:49 PM PDT 24
Peak memory 200044 kb
Host smart-b9f3e676-868d-42e4-acef-86d6cad78e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219323224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3219323224
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.241425263
Short name T358
Test name
Test status
Simulation time 43248616 ps
CPU time 0.61 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:41:58 PM PDT 24
Peak memory 195600 kb
Host smart-3c50a462-cbfd-4e65-a503-96295cbb2ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241425263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.241425263
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2691017670
Short name T464
Test name
Test status
Simulation time 2128574003 ps
CPU time 30.52 seconds
Started Aug 05 05:41:32 PM PDT 24
Finished Aug 05 05:42:03 PM PDT 24
Peak memory 199840 kb
Host smart-b884815b-ff8b-459f-b5bd-29739f6ee901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691017670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2691017670
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.339100099
Short name T331
Test name
Test status
Simulation time 1351006052 ps
CPU time 18.06 seconds
Started Aug 05 05:41:45 PM PDT 24
Finished Aug 05 05:42:04 PM PDT 24
Peak memory 199872 kb
Host smart-47734b64-dd19-45b0-ac70-ecd5287c0629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339100099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.339100099
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2435181001
Short name T185
Test name
Test status
Simulation time 8961645655 ps
CPU time 433.2 seconds
Started Aug 05 05:41:51 PM PDT 24
Finished Aug 05 05:49:04 PM PDT 24
Peak memory 661268 kb
Host smart-6f26d8a6-72c6-4af2-b585-0ff9f0b1f808
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435181001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2435181001
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3212589195
Short name T362
Test name
Test status
Simulation time 7682320441 ps
CPU time 71.5 seconds
Started Aug 05 05:41:42 PM PDT 24
Finished Aug 05 05:42:54 PM PDT 24
Peak memory 200012 kb
Host smart-48e8cb90-df06-4afd-81d8-a2ea8feb1173
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212589195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3212589195
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2389692510
Short name T469
Test name
Test status
Simulation time 25065624491 ps
CPU time 99.38 seconds
Started Aug 05 05:41:47 PM PDT 24
Finished Aug 05 05:43:26 PM PDT 24
Peak memory 199888 kb
Host smart-6dd621e6-a028-4c7c-b100-4c0d76d885d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389692510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2389692510
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.432794703
Short name T241
Test name
Test status
Simulation time 3041286460 ps
CPU time 7.04 seconds
Started Aug 05 05:41:36 PM PDT 24
Finished Aug 05 05:41:44 PM PDT 24
Peak memory 199924 kb
Host smart-3b9319a0-6ec1-40e9-8834-da04ba2f9213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432794703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.432794703
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2623149868
Short name T495
Test name
Test status
Simulation time 104548685179 ps
CPU time 3249.42 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 06:35:57 PM PDT 24
Peak memory 833708 kb
Host smart-2104871b-cb7b-49d1-8665-f12281d216e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623149868 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2623149868
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3804966012
Short name T470
Test name
Test status
Simulation time 16590905518 ps
CPU time 107.04 seconds
Started Aug 05 05:41:43 PM PDT 24
Finished Aug 05 05:43:30 PM PDT 24
Peak memory 199988 kb
Host smart-00a425cf-253a-42a8-a6ec-d51e1c145c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804966012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3804966012
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3323471793
Short name T179
Test name
Test status
Simulation time 32640199 ps
CPU time 0.59 seconds
Started Aug 05 05:41:55 PM PDT 24
Finished Aug 05 05:41:56 PM PDT 24
Peak memory 195980 kb
Host smart-3b947474-ab82-48f3-9df9-b399d48279aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323471793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3323471793
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1392416607
Short name T319
Test name
Test status
Simulation time 1686220975 ps
CPU time 93.61 seconds
Started Aug 05 05:41:50 PM PDT 24
Finished Aug 05 05:43:24 PM PDT 24
Peak memory 199928 kb
Host smart-b35f5aa3-c3a2-4405-b889-e4227861a77d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392416607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1392416607
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4038140267
Short name T492
Test name
Test status
Simulation time 975319744 ps
CPU time 19.65 seconds
Started Aug 05 05:41:55 PM PDT 24
Finished Aug 05 05:42:14 PM PDT 24
Peak memory 199932 kb
Host smart-76ce7882-e38b-441a-ac20-4bbdf1b3a9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038140267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4038140267
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2255499412
Short name T134
Test name
Test status
Simulation time 5159260146 ps
CPU time 406.22 seconds
Started Aug 05 05:41:48 PM PDT 24
Finished Aug 05 05:48:35 PM PDT 24
Peak memory 666188 kb
Host smart-03337c6d-de1a-496a-9213-8b104bc06372
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2255499412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2255499412
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2973210537
Short name T488
Test name
Test status
Simulation time 2797797849 ps
CPU time 150.6 seconds
Started Aug 05 05:41:53 PM PDT 24
Finished Aug 05 05:44:24 PM PDT 24
Peak memory 200040 kb
Host smart-0c8ec267-02ec-4969-a1de-ac701b4db6b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973210537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2973210537
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3438818296
Short name T527
Test name
Test status
Simulation time 4246527537 ps
CPU time 127.43 seconds
Started Aug 05 05:41:58 PM PDT 24
Finished Aug 05 05:44:06 PM PDT 24
Peak memory 200040 kb
Host smart-44672f79-7061-4452-99f4-b055fa770f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438818296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3438818296
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2734305609
Short name T281
Test name
Test status
Simulation time 128595791 ps
CPU time 3.13 seconds
Started Aug 05 05:41:53 PM PDT 24
Finished Aug 05 05:41:56 PM PDT 24
Peak memory 199908 kb
Host smart-0b2072ea-ddef-4084-b63a-53275f3ee6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734305609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2734305609
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.3748338485
Short name T11
Test name
Test status
Simulation time 50320237294 ps
CPU time 1839.06 seconds
Started Aug 05 05:41:42 PM PDT 24
Finished Aug 05 06:12:22 PM PDT 24
Peak memory 771920 kb
Host smart-322ae957-ea61-4a6b-a2af-0144ea593371
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748338485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3748338485
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.4116019712
Short name T270
Test name
Test status
Simulation time 321046405 ps
CPU time 16.97 seconds
Started Aug 05 05:41:55 PM PDT 24
Finished Aug 05 05:42:12 PM PDT 24
Peak memory 199964 kb
Host smart-15a72977-844b-4732-9c18-6bfe3f3d6b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116019712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.4116019712
Directory /workspace/9.hmac_wipe_secret/latest
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